1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
18 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
20 #pragma GCC diagnostic ignored "-Wpedantic"
22 #include <infiniband/verbs.h>
24 #pragma GCC diagnostic error "-Wpedantic"
27 #include <rte_malloc.h>
28 #include <rte_ethdev_driver.h>
29 #include <rte_ethdev_pci.h>
31 #include <rte_bus_pci.h>
32 #include <rte_common.h>
33 #include <rte_config.h>
34 #include <rte_eal_memconfig.h>
35 #include <rte_kvargs.h>
38 #include "mlx5_utils.h"
39 #include "mlx5_rxtx.h"
40 #include "mlx5_autoconf.h"
41 #include "mlx5_defs.h"
42 #include "mlx5_glue.h"
44 /* Device parameter to enable RX completion queue compression. */
45 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
47 /* Device parameter to configure inline send. */
48 #define MLX5_TXQ_INLINE "txq_inline"
51 * Device parameter to configure the number of TX queues threshold for
52 * enabling inline send.
54 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
56 /* Device parameter to enable multi-packet send WQEs. */
57 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
59 /* Device parameter to include 2 dsegs in the title WQEBB. */
60 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
62 /* Device parameter to limit the size of inlining packet. */
63 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
65 /* Device parameter to enable hardware Tx vector. */
66 #define MLX5_TX_VEC_EN "tx_vec_en"
68 /* Device parameter to enable hardware Rx vector. */
69 #define MLX5_RX_VEC_EN "rx_vec_en"
71 #ifndef HAVE_IBV_MLX5_MOD_MPW
72 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2)
73 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3)
76 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP
77 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4)
80 /** Driver-specific log messages type. */
84 * Retrieve integer value from environment variable.
87 * Environment variable name.
90 * Integer value, 0 if the variable is not set.
93 mlx5_getenv_int(const char *name)
95 const char *val = getenv(name);
103 * Verbs callback to allocate a memory. This function should allocate the space
104 * according to the size provided residing inside a huge page.
105 * Please note that all allocation must respect the alignment from libmlx5
106 * (i.e. currently sysconf(_SC_PAGESIZE)).
109 * The size in bytes of the memory to allocate.
111 * A pointer to the callback data.
114 * Allocated buffer, NULL otherwise and rte_errno is set.
117 mlx5_alloc_verbs_buf(size_t size, void *data)
119 struct priv *priv = data;
121 size_t alignment = sysconf(_SC_PAGESIZE);
122 unsigned int socket = SOCKET_ID_ANY;
124 if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) {
125 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
127 socket = ctrl->socket;
128 } else if (priv->verbs_alloc_ctx.type ==
129 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) {
130 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
132 socket = ctrl->socket;
134 assert(data != NULL);
135 ret = rte_malloc_socket(__func__, size, alignment, socket);
142 * Verbs callback to free a memory.
145 * A pointer to the memory to free.
147 * A pointer to the callback data.
150 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused)
152 assert(data != NULL);
157 * DPDK callback to close the device.
159 * Destroy all queues and objects, free memory.
162 * Pointer to Ethernet device structure.
165 mlx5_dev_close(struct rte_eth_dev *dev)
167 struct priv *priv = dev->data->dev_private;
171 DRV_LOG(DEBUG, "port %u closing device \"%s\"",
173 ((priv->ctx != NULL) ? priv->ctx->device->name : ""));
174 /* In case mlx5_dev_stop() has not been called. */
175 mlx5_dev_interrupt_handler_uninstall(dev);
176 mlx5_traffic_disable(dev);
177 /* Prevent crashes when queues are still in use. */
178 dev->rx_pkt_burst = removed_rx_burst;
179 dev->tx_pkt_burst = removed_tx_burst;
180 if (priv->rxqs != NULL) {
181 /* XXX race condition if mlx5_rx_burst() is still running. */
183 for (i = 0; (i != priv->rxqs_n); ++i)
184 mlx5_rxq_release(dev, i);
188 if (priv->txqs != NULL) {
189 /* XXX race condition if mlx5_tx_burst() is still running. */
191 for (i = 0; (i != priv->txqs_n); ++i)
192 mlx5_txq_release(dev, i);
196 if (priv->pd != NULL) {
197 assert(priv->ctx != NULL);
198 claim_zero(mlx5_glue->dealloc_pd(priv->pd));
199 claim_zero(mlx5_glue->close_device(priv->ctx));
201 assert(priv->ctx == NULL);
202 if (priv->rss_conf.rss_key != NULL)
203 rte_free(priv->rss_conf.rss_key);
204 if (priv->reta_idx != NULL)
205 rte_free(priv->reta_idx);
206 if (priv->primary_socket)
207 mlx5_socket_uninit(dev);
208 ret = mlx5_hrxq_ibv_verify(dev);
210 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
212 ret = mlx5_ind_table_ibv_verify(dev);
214 DRV_LOG(WARNING, "port %u some indirection table still remain",
216 ret = mlx5_rxq_ibv_verify(dev);
218 DRV_LOG(WARNING, "port %u some Verbs Rx queue still remain",
220 ret = mlx5_rxq_verify(dev);
222 DRV_LOG(WARNING, "port %u some Rx queues still remain",
224 ret = mlx5_txq_ibv_verify(dev);
226 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
228 ret = mlx5_txq_verify(dev);
230 DRV_LOG(WARNING, "port %u some Tx queues still remain",
232 ret = mlx5_flow_verify(dev);
234 DRV_LOG(WARNING, "port %u some flows still remain",
236 ret = mlx5_mr_verify(dev);
238 DRV_LOG(WARNING, "port %u some memory region still remain",
240 memset(priv, 0, sizeof(*priv));
243 const struct eth_dev_ops mlx5_dev_ops = {
244 .dev_configure = mlx5_dev_configure,
245 .dev_start = mlx5_dev_start,
246 .dev_stop = mlx5_dev_stop,
247 .dev_set_link_down = mlx5_set_link_down,
248 .dev_set_link_up = mlx5_set_link_up,
249 .dev_close = mlx5_dev_close,
250 .promiscuous_enable = mlx5_promiscuous_enable,
251 .promiscuous_disable = mlx5_promiscuous_disable,
252 .allmulticast_enable = mlx5_allmulticast_enable,
253 .allmulticast_disable = mlx5_allmulticast_disable,
254 .link_update = mlx5_link_update,
255 .stats_get = mlx5_stats_get,
256 .stats_reset = mlx5_stats_reset,
257 .xstats_get = mlx5_xstats_get,
258 .xstats_reset = mlx5_xstats_reset,
259 .xstats_get_names = mlx5_xstats_get_names,
260 .dev_infos_get = mlx5_dev_infos_get,
261 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
262 .vlan_filter_set = mlx5_vlan_filter_set,
263 .rx_queue_setup = mlx5_rx_queue_setup,
264 .tx_queue_setup = mlx5_tx_queue_setup,
265 .rx_queue_release = mlx5_rx_queue_release,
266 .tx_queue_release = mlx5_tx_queue_release,
267 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
268 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
269 .mac_addr_remove = mlx5_mac_addr_remove,
270 .mac_addr_add = mlx5_mac_addr_add,
271 .mac_addr_set = mlx5_mac_addr_set,
272 .mtu_set = mlx5_dev_set_mtu,
273 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
274 .vlan_offload_set = mlx5_vlan_offload_set,
275 .reta_update = mlx5_dev_rss_reta_update,
276 .reta_query = mlx5_dev_rss_reta_query,
277 .rss_hash_update = mlx5_rss_hash_update,
278 .rss_hash_conf_get = mlx5_rss_hash_conf_get,
279 .filter_ctrl = mlx5_dev_filter_ctrl,
280 .rx_descriptor_status = mlx5_rx_descriptor_status,
281 .tx_descriptor_status = mlx5_tx_descriptor_status,
282 .rx_queue_intr_enable = mlx5_rx_intr_enable,
283 .rx_queue_intr_disable = mlx5_rx_intr_disable,
284 .is_removed = mlx5_is_removed,
287 static const struct eth_dev_ops mlx5_dev_sec_ops = {
288 .stats_get = mlx5_stats_get,
289 .stats_reset = mlx5_stats_reset,
290 .xstats_get = mlx5_xstats_get,
291 .xstats_reset = mlx5_xstats_reset,
292 .xstats_get_names = mlx5_xstats_get_names,
293 .dev_infos_get = mlx5_dev_infos_get,
294 .rx_descriptor_status = mlx5_rx_descriptor_status,
295 .tx_descriptor_status = mlx5_tx_descriptor_status,
298 /* Available operators in flow isolated mode. */
299 const struct eth_dev_ops mlx5_dev_ops_isolate = {
300 .dev_configure = mlx5_dev_configure,
301 .dev_start = mlx5_dev_start,
302 .dev_stop = mlx5_dev_stop,
303 .dev_set_link_down = mlx5_set_link_down,
304 .dev_set_link_up = mlx5_set_link_up,
305 .dev_close = mlx5_dev_close,
306 .link_update = mlx5_link_update,
307 .stats_get = mlx5_stats_get,
308 .stats_reset = mlx5_stats_reset,
309 .xstats_get = mlx5_xstats_get,
310 .xstats_reset = mlx5_xstats_reset,
311 .xstats_get_names = mlx5_xstats_get_names,
312 .dev_infos_get = mlx5_dev_infos_get,
313 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
314 .vlan_filter_set = mlx5_vlan_filter_set,
315 .rx_queue_setup = mlx5_rx_queue_setup,
316 .tx_queue_setup = mlx5_tx_queue_setup,
317 .rx_queue_release = mlx5_rx_queue_release,
318 .tx_queue_release = mlx5_tx_queue_release,
319 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
320 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
321 .mac_addr_remove = mlx5_mac_addr_remove,
322 .mac_addr_add = mlx5_mac_addr_add,
323 .mac_addr_set = mlx5_mac_addr_set,
324 .mtu_set = mlx5_dev_set_mtu,
325 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
326 .vlan_offload_set = mlx5_vlan_offload_set,
327 .filter_ctrl = mlx5_dev_filter_ctrl,
328 .rx_descriptor_status = mlx5_rx_descriptor_status,
329 .tx_descriptor_status = mlx5_tx_descriptor_status,
330 .rx_queue_intr_enable = mlx5_rx_intr_enable,
331 .rx_queue_intr_disable = mlx5_rx_intr_disable,
332 .is_removed = mlx5_is_removed,
336 struct rte_pci_addr pci_addr; /* associated PCI address */
337 uint32_t ports; /* physical ports bitfield. */
341 * Get device index in mlx5_dev[] from PCI bus address.
343 * @param[in] pci_addr
344 * PCI bus address to look for.
347 * mlx5_dev[] index on success, -1 on failure.
350 mlx5_dev_idx(struct rte_pci_addr *pci_addr)
355 assert(pci_addr != NULL);
356 for (i = 0; (i != RTE_DIM(mlx5_dev)); ++i) {
357 if ((mlx5_dev[i].pci_addr.domain == pci_addr->domain) &&
358 (mlx5_dev[i].pci_addr.bus == pci_addr->bus) &&
359 (mlx5_dev[i].pci_addr.devid == pci_addr->devid) &&
360 (mlx5_dev[i].pci_addr.function == pci_addr->function))
362 if ((mlx5_dev[i].ports == 0) && (ret == -1))
369 * Verify and store value for device argument.
372 * Key argument to verify.
374 * Value associated with key.
379 * 0 on success, a negative errno value otherwise and rte_errno is set.
382 mlx5_args_check(const char *key, const char *val, void *opaque)
384 struct mlx5_dev_config *config = opaque;
388 tmp = strtoul(val, NULL, 0);
391 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
394 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
395 config->cqe_comp = !!tmp;
396 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
397 config->txq_inline = tmp;
398 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
399 config->txqs_inline = tmp;
400 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
401 config->mps = !!tmp ? config->mps : 0;
402 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
403 config->mpw_hdr_dseg = !!tmp;
404 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
405 config->inline_max_packet_sz = tmp;
406 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
407 config->tx_vec_en = !!tmp;
408 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
409 config->rx_vec_en = !!tmp;
411 DRV_LOG(WARNING, "%s: unknown parameter", key);
419 * Parse device parameters.
422 * Pointer to device configuration structure.
424 * Device arguments structure.
427 * 0 on success, a negative errno value otherwise and rte_errno is set.
430 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
432 const char **params = (const char *[]){
433 MLX5_RXQ_CQE_COMP_EN,
435 MLX5_TXQS_MIN_INLINE,
437 MLX5_TXQ_MPW_HDR_DSEG_EN,
438 MLX5_TXQ_MAX_INLINE_LEN,
443 struct rte_kvargs *kvlist;
449 /* Following UGLY cast is done to pass checkpatch. */
450 kvlist = rte_kvargs_parse(devargs->args, params);
453 /* Process parameters. */
454 for (i = 0; (params[i] != NULL); ++i) {
455 if (rte_kvargs_count(kvlist, params[i])) {
456 ret = rte_kvargs_process(kvlist, params[i],
457 mlx5_args_check, config);
460 rte_kvargs_free(kvlist);
465 rte_kvargs_free(kvlist);
469 static struct rte_pci_driver mlx5_driver;
472 * Reserved UAR address space for TXQ UAR(hw doorbell) mapping, process
473 * local resource used by both primary and secondary to avoid duplicate
475 * The space has to be available on both primary and secondary process,
476 * TXQ UAR maps to this area using fixed mmap w/o double check.
478 static void *uar_base;
481 find_lower_va_bound(const struct rte_memseg *ms, void *arg)
488 *addr = RTE_MIN(*addr, ms->addr);
494 * Reserve UAR address space for primary process.
497 * Pointer to Ethernet device.
500 * 0 on success, a negative errno value otherwise and rte_errno is set.
503 mlx5_uar_init_primary(struct rte_eth_dev *dev)
505 struct priv *priv = dev->data->dev_private;
506 void *addr = (void *)0;
508 if (uar_base) { /* UAR address space mapped. */
509 priv->uar_base = uar_base;
512 /* find out lower bound of hugepage segments */
513 rte_memseg_walk(find_lower_va_bound, &addr);
515 /* keep distance to hugepages to minimize potential conflicts. */
516 addr = RTE_PTR_SUB(addr, MLX5_UAR_OFFSET + MLX5_UAR_SIZE);
517 /* anonymous mmap, no real memory consumption. */
518 addr = mmap(addr, MLX5_UAR_SIZE,
519 PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
520 if (addr == MAP_FAILED) {
522 "port %u failed to reserve UAR address space, please"
523 " adjust MLX5_UAR_SIZE or try --base-virtaddr",
528 /* Accept either same addr or a new addr returned from mmap if target
531 DRV_LOG(INFO, "port %u reserved UAR address space: %p",
532 dev->data->port_id, addr);
533 priv->uar_base = addr; /* for primary and secondary UAR re-mmap. */
534 uar_base = addr; /* process local, don't reserve again. */
539 * Reserve UAR address space for secondary process, align with
543 * Pointer to Ethernet device.
546 * 0 on success, a negative errno value otherwise and rte_errno is set.
549 mlx5_uar_init_secondary(struct rte_eth_dev *dev)
551 struct priv *priv = dev->data->dev_private;
554 assert(priv->uar_base);
555 if (uar_base) { /* already reserved. */
556 assert(uar_base == priv->uar_base);
559 /* anonymous mmap, no real memory consumption. */
560 addr = mmap(priv->uar_base, MLX5_UAR_SIZE,
561 PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
562 if (addr == MAP_FAILED) {
563 DRV_LOG(ERR, "port %u UAR mmap failed: %p size: %llu",
564 dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE);
568 if (priv->uar_base != addr) {
570 "port %u UAR address %p size %llu occupied, please"
571 " adjust MLX5_UAR_OFFSET or try EAL parameter"
573 dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE);
577 uar_base = addr; /* process local, don't reserve again */
578 DRV_LOG(INFO, "port %u reserved UAR address space: %p",
579 dev->data->port_id, addr);
584 * DPDK callback to register a PCI device.
586 * This function creates an Ethernet device for each port of a given
590 * PCI driver structure (mlx5_driver).
592 * PCI device information.
595 * 0 on success, a negative errno value otherwise and rte_errno is set.
598 mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
599 struct rte_pci_device *pci_dev)
601 struct ibv_device **list = NULL;
602 struct ibv_device *ibv_dev;
604 struct ibv_context *attr_ctx = NULL;
605 struct ibv_device_attr_ex device_attr;
607 unsigned int cqe_comp;
608 unsigned int tunnel_en = 0;
611 struct mlx5dv_context attrs_out = {0};
612 #ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT
613 struct ibv_counter_set_description cs_desc;
616 assert(pci_drv == &mlx5_driver);
617 /* Get mlx5_dev[] index. */
618 idx = mlx5_dev_idx(&pci_dev->addr);
620 DRV_LOG(ERR, "this driver cannot support any more adapters");
624 DRV_LOG(DEBUG, "using driver device index %d", idx);
625 /* Save PCI address. */
626 mlx5_dev[idx].pci_addr = pci_dev->addr;
627 list = mlx5_glue->get_device_list(&i);
633 "cannot list devices, is ib_uverbs loaded?");
638 * For each listed device, check related sysfs entry against
639 * the provided PCI ID.
642 struct rte_pci_addr pci_addr;
645 DRV_LOG(DEBUG, "checking device \"%s\"", list[i]->name);
646 if (mlx5_ibv_device_to_pci_addr(list[i], &pci_addr))
648 if ((pci_dev->addr.domain != pci_addr.domain) ||
649 (pci_dev->addr.bus != pci_addr.bus) ||
650 (pci_dev->addr.devid != pci_addr.devid) ||
651 (pci_dev->addr.function != pci_addr.function))
653 DRV_LOG(INFO, "PCI information matches, using device \"%s\"",
655 attr_ctx = mlx5_glue->open_device(list[i]);
660 if (attr_ctx == NULL) {
661 mlx5_glue->free_device_list(list);
665 "cannot access device, is mlx5_ib loaded?");
670 "cannot use device, are drivers up to date?");
675 DRV_LOG(DEBUG, "device opened");
677 * Multi-packet send is supported by ConnectX-4 Lx PF as well
678 * as all ConnectX-5 devices.
680 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
681 attrs_out.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS;
683 mlx5_glue->dv_query_device(attr_ctx, &attrs_out);
684 if (attrs_out.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
685 if (attrs_out.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) {
686 DRV_LOG(DEBUG, "enhanced MPW is supported");
687 mps = MLX5_MPW_ENHANCED;
689 DRV_LOG(DEBUG, "MPW is supported");
693 DRV_LOG(DEBUG, "MPW isn't supported");
694 mps = MLX5_MPW_DISABLED;
696 if (RTE_CACHE_LINE_SIZE == 128 &&
697 !(attrs_out.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP))
701 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
702 if (attrs_out.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) {
703 tunnel_en = ((attrs_out.tunnel_offloads_caps &
704 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) &&
705 (attrs_out.tunnel_offloads_caps &
706 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE));
708 DRV_LOG(DEBUG, "tunnel offloading is %ssupported",
709 tunnel_en ? "" : "not ");
712 "tunnel offloading disabled due to old OFED/rdma-core version");
714 if (mlx5_glue->query_device_ex(attr_ctx, NULL, &device_attr)) {
718 DRV_LOG(INFO, "%u port(s) detected",
719 device_attr.orig_attr.phys_port_cnt);
720 for (i = 0; i < device_attr.orig_attr.phys_port_cnt; i++) {
721 char name[RTE_ETH_NAME_MAX_LEN];
723 uint32_t port = i + 1; /* ports are indexed from one */
724 uint32_t test = (1 << i);
725 struct ibv_context *ctx = NULL;
726 struct ibv_port_attr port_attr;
727 struct ibv_pd *pd = NULL;
728 struct priv *priv = NULL;
729 struct rte_eth_dev *eth_dev = NULL;
730 struct ibv_device_attr_ex device_attr_ex;
731 struct ether_addr mac;
732 struct mlx5_dev_config config = {
733 .cqe_comp = cqe_comp,
735 .tunnel_en = tunnel_en,
739 .txq_inline = MLX5_ARG_UNSET,
740 .txqs_inline = MLX5_ARG_UNSET,
741 .inline_max_packet_sz = MLX5_ARG_UNSET,
744 len = snprintf(name, sizeof(name), PCI_PRI_FMT,
745 pci_dev->addr.domain, pci_dev->addr.bus,
746 pci_dev->addr.devid, pci_dev->addr.function);
747 if (device_attr.orig_attr.phys_port_cnt > 1)
748 snprintf(name + len, sizeof(name), " port %u", i);
749 mlx5_dev[idx].ports |= test;
750 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
751 eth_dev = rte_eth_dev_attach_secondary(name);
752 if (eth_dev == NULL) {
753 DRV_LOG(ERR, "can not attach rte ethdev");
758 eth_dev->device = &pci_dev->device;
759 eth_dev->dev_ops = &mlx5_dev_sec_ops;
760 err = mlx5_uar_init_secondary(eth_dev);
763 /* Receive command fd from primary process */
764 err = mlx5_socket_connect(eth_dev);
767 /* Remap UAR for Tx queues. */
768 err = mlx5_tx_uar_remap(eth_dev, err);
772 * Ethdev pointer is still required as input since
773 * the primary device is not accessible from the
776 eth_dev->rx_pkt_burst =
777 mlx5_select_rx_function(eth_dev);
778 eth_dev->tx_pkt_burst =
779 mlx5_select_tx_function(eth_dev);
782 DRV_LOG(DEBUG, "using port %u (%08" PRIx32 ")", port, test);
783 ctx = mlx5_glue->open_device(ibv_dev);
788 /* Check port status. */
789 err = mlx5_glue->query_port(ctx, port, &port_attr);
791 DRV_LOG(ERR, "port query failed: %s", strerror(err));
794 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
796 "port %d is not configured in Ethernet mode",
801 if (port_attr.state != IBV_PORT_ACTIVE)
802 DRV_LOG(DEBUG, "port %d is not active: \"%s\" (%d)",
804 mlx5_glue->port_state_str(port_attr.state),
806 /* Allocate protection domain. */
807 pd = mlx5_glue->alloc_pd(ctx);
809 DRV_LOG(ERR, "PD allocation failure");
813 mlx5_dev[idx].ports |= test;
814 /* from rte_ethdev.c */
815 priv = rte_zmalloc("ethdev private structure",
817 RTE_CACHE_LINE_SIZE);
819 DRV_LOG(ERR, "priv allocation failure");
824 strncpy(priv->ibdev_path, priv->ctx->device->ibdev_path,
825 sizeof(priv->ibdev_path));
826 priv->device_attr = device_attr;
829 priv->mtu = ETHER_MTU;
830 err = mlx5_args(&config, pci_dev->device.devargs);
832 DRV_LOG(ERR, "failed to process device arguments: %s",
836 if (mlx5_glue->query_device_ex(ctx, NULL, &device_attr_ex)) {
837 DRV_LOG(ERR, "ibv_query_device_ex() failed");
841 config.hw_csum = !!(device_attr_ex.device_cap_flags_ex &
842 IBV_DEVICE_RAW_IP_CSUM);
843 DRV_LOG(DEBUG, "checksum offloading is %ssupported",
844 (config.hw_csum ? "" : "not "));
845 #ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT
846 config.flow_counter_en = !!(device_attr.max_counter_sets);
847 mlx5_glue->describe_counter_set(ctx, 0, &cs_desc);
849 "counter type = %d, num of cs = %ld, attributes = %d",
850 cs_desc.counter_type, cs_desc.num_of_cs,
853 config.ind_table_max_size =
854 device_attr_ex.rss_caps.max_rwq_indirection_table_size;
855 /* Remove this check once DPDK supports larger/variable
856 * indirection tables. */
857 if (config.ind_table_max_size >
858 (unsigned int)ETH_RSS_RETA_SIZE_512)
859 config.ind_table_max_size = ETH_RSS_RETA_SIZE_512;
860 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u",
861 config.ind_table_max_size);
862 config.hw_vlan_strip = !!(device_attr_ex.raw_packet_caps &
863 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
864 DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
865 (config.hw_vlan_strip ? "" : "not "));
867 config.hw_fcs_strip = !!(device_attr_ex.raw_packet_caps &
868 IBV_RAW_PACKET_CAP_SCATTER_FCS);
869 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported",
870 (config.hw_fcs_strip ? "" : "not "));
872 #ifdef HAVE_IBV_WQ_FLAG_RX_END_PADDING
873 config.hw_padding = !!device_attr_ex.rx_pad_end_addr_align;
876 "hardware Rx end alignment padding is %ssupported",
877 (config.hw_padding ? "" : "not "));
878 config.tso = ((device_attr_ex.tso_caps.max_tso > 0) &&
879 (device_attr_ex.tso_caps.supported_qpts &
880 (1 << IBV_QPT_RAW_PACKET)));
882 config.tso_max_payload_sz =
883 device_attr_ex.tso_caps.max_tso;
884 if (config.mps && !mps) {
886 "multi-packet send not supported on this device"
887 " (" MLX5_TXQ_MPW_EN ")");
891 DRV_LOG(INFO, "%s MPS is %s",
892 config.mps == MLX5_MPW_ENHANCED ? "enhanced " : "",
893 config.mps != MLX5_MPW_DISABLED ? "enabled" :
895 if (config.cqe_comp && !cqe_comp) {
896 DRV_LOG(WARNING, "Rx CQE compression isn't supported");
899 eth_dev = rte_eth_dev_allocate(name);
900 if (eth_dev == NULL) {
901 DRV_LOG(ERR, "can not allocate rte ethdev");
905 eth_dev->data->dev_private = priv;
907 eth_dev->data->mac_addrs = priv->mac;
908 eth_dev->device = &pci_dev->device;
909 rte_eth_copy_pci_info(eth_dev, pci_dev);
910 eth_dev->device->driver = &mlx5_driver.driver;
911 err = mlx5_uar_init_primary(eth_dev);
914 /* Configure the first MAC address by default. */
915 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) {
917 "port %u cannot get MAC address, is mlx5_en"
918 " loaded? (errno: %s)",
919 eth_dev->data->port_id, strerror(errno));
924 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x",
925 eth_dev->data->port_id,
926 mac.addr_bytes[0], mac.addr_bytes[1],
927 mac.addr_bytes[2], mac.addr_bytes[3],
928 mac.addr_bytes[4], mac.addr_bytes[5]);
931 char ifname[IF_NAMESIZE];
933 if (mlx5_get_ifname(eth_dev, &ifname) == 0)
934 DRV_LOG(DEBUG, "port %u ifname is \"%s\"",
935 eth_dev->data->port_id, ifname);
937 DRV_LOG(DEBUG, "port %u ifname is unknown",
938 eth_dev->data->port_id);
941 /* Get actual MTU if possible. */
942 err = mlx5_get_mtu(eth_dev, &priv->mtu);
945 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id,
948 * Initialize burst functions to prevent crashes before link-up.
950 eth_dev->rx_pkt_burst = removed_rx_burst;
951 eth_dev->tx_pkt_burst = removed_tx_burst;
952 eth_dev->dev_ops = &mlx5_dev_ops;
953 /* Register MAC address. */
954 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
955 TAILQ_INIT(&priv->flows);
956 TAILQ_INIT(&priv->ctrl_flows);
957 /* Hint libmlx5 to use PMD allocator for data plane resources */
958 struct mlx5dv_ctx_allocators alctr = {
959 .alloc = &mlx5_alloc_verbs_buf,
960 .free = &mlx5_free_verbs_buf,
963 mlx5_glue->dv_set_context_attr(ctx,
964 MLX5DV_CTX_ATTR_BUF_ALLOCATORS,
965 (void *)((uintptr_t)&alctr));
966 /* Bring Ethernet device up. */
967 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up",
968 eth_dev->data->port_id);
969 mlx5_set_link_up(eth_dev);
970 /* Store device configuration on private structure. */
971 priv->config = config;
977 claim_zero(mlx5_glue->dealloc_pd(pd));
979 claim_zero(mlx5_glue->close_device(ctx));
983 * XXX if something went wrong in the loop above, there is a resource
984 * leak (ctx, pd, priv, dpdk ethdev) but we can do nothing about it as
985 * long as the dpdk does not provide a way to deallocate a ethdev and a
986 * way to enumerate the registered ethdevs to free the previous ones.
988 /* no port found, complain */
989 if (!mlx5_dev[idx].ports) {
995 claim_zero(mlx5_glue->close_device(attr_ctx));
997 mlx5_glue->free_device_list(list);
1005 static const struct rte_pci_id mlx5_pci_id_map[] = {
1007 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1008 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
1011 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1012 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
1015 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1016 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
1019 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1020 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
1023 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1024 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
1027 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1028 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
1031 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1032 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
1035 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1036 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
1043 static struct rte_pci_driver mlx5_driver = {
1045 .name = MLX5_DRIVER_NAME
1047 .id_table = mlx5_pci_id_map,
1048 .probe = mlx5_pci_probe,
1049 .drv_flags = RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV,
1052 #ifdef RTE_LIBRTE_MLX5_DLOPEN_DEPS
1055 * Suffix RTE_EAL_PMD_PATH with "-glue".
1057 * This function performs a sanity check on RTE_EAL_PMD_PATH before
1058 * suffixing its last component.
1061 * Output buffer, should be large enough otherwise NULL is returned.
1066 * Pointer to @p buf or @p NULL in case suffix cannot be appended.
1069 mlx5_glue_path(char *buf, size_t size)
1071 static const char *const bad[] = { "/", ".", "..", NULL };
1072 const char *path = RTE_EAL_PMD_PATH;
1073 size_t len = strlen(path);
1077 while (len && path[len - 1] == '/')
1079 for (off = len; off && path[off - 1] != '/'; --off)
1081 for (i = 0; bad[i]; ++i)
1082 if (!strncmp(path + off, bad[i], (int)(len - off)))
1084 i = snprintf(buf, size, "%.*s-glue", (int)len, path);
1085 if (i == -1 || (size_t)i >= size)
1090 "unable to append \"-glue\" to last component of"
1091 " RTE_EAL_PMD_PATH (\"" RTE_EAL_PMD_PATH "\"),"
1092 " please re-configure DPDK");
1097 * Initialization routine for run-time dependency on rdma-core.
1100 mlx5_glue_init(void)
1102 char glue_path[sizeof(RTE_EAL_PMD_PATH) - 1 + sizeof("-glue")];
1103 const char *path[] = {
1105 * A basic security check is necessary before trusting
1106 * MLX5_GLUE_PATH, which may override RTE_EAL_PMD_PATH.
1108 (geteuid() == getuid() && getegid() == getgid() ?
1109 getenv("MLX5_GLUE_PATH") : NULL),
1111 * When RTE_EAL_PMD_PATH is set, use its glue-suffixed
1112 * variant, otherwise let dlopen() look up libraries on its
1115 (*RTE_EAL_PMD_PATH ?
1116 mlx5_glue_path(glue_path, sizeof(glue_path)) : ""),
1119 void *handle = NULL;
1123 while (!handle && i != RTE_DIM(path)) {
1132 end = strpbrk(path[i], ":;");
1134 end = path[i] + strlen(path[i]);
1135 len = end - path[i];
1140 ret = snprintf(name, sizeof(name), "%.*s%s" MLX5_GLUE,
1142 (!len || *(end - 1) == '/') ? "" : "/");
1145 if (sizeof(name) != (size_t)ret + 1)
1147 DRV_LOG(DEBUG, "looking for rdma-core glue as \"%s\"",
1149 handle = dlopen(name, RTLD_LAZY);
1160 DRV_LOG(WARNING, "cannot load glue library: %s", dlmsg);
1163 sym = dlsym(handle, "mlx5_glue");
1164 if (!sym || !*sym) {
1168 DRV_LOG(ERR, "cannot resolve glue symbol: %s", dlmsg);
1177 "cannot initialize PMD due to missing run-time dependency on"
1178 " rdma-core libraries (libibverbs, libmlx5)");
1185 * Driver initialization routine.
1187 RTE_INIT(rte_mlx5_pmd_init);
1189 rte_mlx5_pmd_init(void)
1191 /* Build the static table for ptype conversion. */
1192 mlx5_set_ptype_table();
1194 * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use
1195 * huge pages. Calling ibv_fork_init() during init allows
1196 * applications to use fork() safely for purposes other than
1197 * using this PMD, which is not supported in forked processes.
1199 setenv("RDMAV_HUGEPAGES_SAFE", "1", 1);
1200 /* Match the size of Rx completion entry to the size of a cacheline. */
1201 if (RTE_CACHE_LINE_SIZE == 128)
1202 setenv("MLX5_CQE_SIZE", "128", 0);
1203 #ifdef RTE_LIBRTE_MLX5_DLOPEN_DEPS
1204 if (mlx5_glue_init())
1209 /* Glue structure must not contain any NULL pointers. */
1213 for (i = 0; i != sizeof(*mlx5_glue) / sizeof(void *); ++i)
1214 assert(((const void *const *)mlx5_glue)[i]);
1217 if (strcmp(mlx5_glue->version, MLX5_GLUE_VERSION)) {
1219 "rdma-core glue \"%s\" mismatch: \"%s\" is required",
1220 mlx5_glue->version, MLX5_GLUE_VERSION);
1223 mlx5_glue->fork_init();
1224 rte_pci_register(&mlx5_driver);
1227 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
1228 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
1229 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");
1231 /** Initialize driver log type. */
1232 RTE_INIT(vdev_netvsc_init_log)
1234 mlx5_logtype = rte_log_register("pmd.net.mlx5");
1235 if (mlx5_logtype >= 0)
1236 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE);