drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <stdint.h>
  10 #include <stdlib.h>
  11 #include <errno.h>
  12
  13 #include <rte_malloc.h>
  14 #include <ethdev_driver.h>
  15 #include <rte_pci.h>
  16 #include <rte_bus_pci.h>
  17 #include <rte_common.h>
  18 #include <rte_kvargs.h>
  19 #include <rte_rwlock.h>
  20 #include <rte_spinlock.h>
  21 #include <rte_string_fns.h>
  22 #include <rte_eal_paging.h>
  23 #include <rte_alarm.h>
  24 #include <rte_cycles.h>
  25
  26 #include <mlx5_glue.h>
  27 #include <mlx5_devx_cmds.h>
  28 #include <mlx5_common.h>
  29 #include <mlx5_common_os.h>
  30 #include <mlx5_common_mp.h>
  31 #include <mlx5_malloc.h>
  32
  33 #include "mlx5_defs.h"
  34 #include "mlx5.h"
  35 #include "mlx5_utils.h"
  36 #include "mlx5_rxtx.h"
  37 #include "mlx5_rx.h"
  38 #include "mlx5_tx.h"
  39 #include "mlx5_autoconf.h"
  40 #include "mlx5_flow.h"
  41 #include "mlx5_flow_os.h"
  42 #include "rte_pmd_mlx5.h"
  43
  44 #define MLX5_ETH_DRIVER_NAME mlx5_eth
  45
  46 /* Driver type key for new device global syntax. */
  47 #define MLX5_DRIVER_KEY "driver"
  48
  49 /* Device parameter to enable RX completion queue compression. */
  50 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  51
  52 /* Device parameter to enable padding Rx packet to cacheline size. */
  53 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
  54
  55 /* Device parameter to enable Multi-Packet Rx queue. */
  56 #define MLX5_RX_MPRQ_EN "mprq_en"
  57
  58 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
  59 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
  60
  61 /* Device parameter to configure log 2 of the stride size for MPRQ. */
  62 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
  63
  64 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
  65 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
  66
  67 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
  68 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
  69
  70 /* Device parameter to configure inline send. Deprecated, ignored.*/
  71 #define MLX5_TXQ_INLINE "txq_inline"
  72
  73 /* Device parameter to limit packet size to inline with ordinary SEND. */
  74 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
  75
  76 /* Device parameter to configure minimal data size to inline. */
  77 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
  78
  79 /* Device parameter to limit packet size to inline with Enhanced MPW. */
  80 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
  81
  82 /*
  83  * Device parameter to configure the number of TX queues threshold for
  84  * enabling inline send.
  85  */
  86 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  87
  88 /*
  89  * Device parameter to configure the number of TX queues threshold for
  90  * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
  91  */
  92 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
  93
  94 /* Device parameter to enable multi-packet send WQEs. */
  95 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
  96
  97 /*
  98  * Device parameter to force doorbell register mapping
  99  * to non-cahed region eliminating the extra write memory barrier.
 100  */
 101 #define MLX5_TX_DB_NC "tx_db_nc"
 102
 103 /*
 104  * Device parameter to include 2 dsegs in the title WQEBB.
 105  * Deprecated, ignored.
 106  */
 107 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
 108
 109 /*
 110  * Device parameter to limit the size of inlining packet.
 111  * Deprecated, ignored.
 112  */
 113 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
 114
 115 /*
 116  * Device parameter to enable Tx scheduling on timestamps
 117  * and specify the packet pacing granularity in nanoseconds.
 118  */
 119 #define MLX5_TX_PP "tx_pp"
 120
 121 /*
 122  * Device parameter to specify skew in nanoseconds on Tx datapath,
 123  * it represents the time between SQ start WQE processing and
 124  * appearing actual packet data on the wire.
 125  */
 126 #define MLX5_TX_SKEW "tx_skew"
 127
 128 /*
 129  * Device parameter to enable hardware Tx vector.
 130  * Deprecated, ignored (no vectorized Tx routines anymore).
 131  */
 132 #define MLX5_TX_VEC_EN "tx_vec_en"
 133
 134 /* Device parameter to enable hardware Rx vector. */
 135 #define MLX5_RX_VEC_EN "rx_vec_en"
 136
 137 /* Allow L3 VXLAN flow creation. */
 138 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
 139
 140 /* Activate DV E-Switch flow steering. */
 141 #define MLX5_DV_ESW_EN "dv_esw_en"
 142
 143 /* Activate DV flow steering. */
 144 #define MLX5_DV_FLOW_EN "dv_flow_en"
 145
 146 /* Enable extensive flow metadata support. */
 147 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
 148
 149 /* Device parameter to let the user manage the lacp traffic of bonded device */
 150 #define MLX5_LACP_BY_USER "lacp_by_user"
 151
 152 /* Activate Netlink support in VF mode. */
 153 #define MLX5_VF_NL_EN "vf_nl_en"
 154
 155 /* Enable extending memsegs when creating a MR. */
 156 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
 157
 158 /* Select port representors to instantiate. */
 159 #define MLX5_REPRESENTOR "representor"
 160
 161 /* Device parameter to configure the maximum number of dump files per queue. */
 162 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
 163
 164 /* Configure timeout of LRO session (in microseconds). */
 165 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
 166
 167 /*
 168  * Device parameter to configure the total data buffer size for a single
 169  * hairpin queue (logarithm value).
 170  */
 171 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
 172
 173 /* Flow memory reclaim mode. */
 174 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
 175
 176 /* The default memory allocator used in PMD. */
 177 #define MLX5_SYS_MEM_EN "sys_mem_en"
 178 /* Decap will be used or not. */
 179 #define MLX5_DECAP_EN "decap_en"
 180
 181 /* Device parameter to configure allow or prevent duplicate rules pattern. */
 182 #define MLX5_ALLOW_DUPLICATE_PATTERN "allow_duplicate_pattern"
 183
 184 /* Device parameter to configure implicit registration of mempool memory. */
 185 #define MLX5_MR_MEMPOOL_REG_EN "mr_mempool_reg_en"
 186
 187 /* Device parameter to configure the delay drop when creating Rxqs. */
 188 #define MLX5_DELAY_DROP "delay_drop"
 189
 190 /* Shared memory between primary and secondary processes. */
 191 struct mlx5_shared_data *mlx5_shared_data;
 192
 193 /** Driver-specific log messages type. */
 194 int mlx5_logtype;
 195
 196 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
 197                                                 LIST_HEAD_INITIALIZER();
 198 static pthread_mutex_t mlx5_dev_ctx_list_mutex;
 199 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
 200 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
 201         [MLX5_IPOOL_DECAP_ENCAP] = {
 202                 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
 203                 .trunk_size = 64,
 204                 .grow_trunk = 3,
 205                 .grow_shift = 2,
 206                 .need_lock = 1,
 207                 .release_mem_en = 1,
 208                 .malloc = mlx5_malloc,
 209                 .free = mlx5_free,
 210                 .type = "mlx5_encap_decap_ipool",
 211         },
 212         [MLX5_IPOOL_PUSH_VLAN] = {
 213                 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
 214                 .trunk_size = 64,
 215                 .grow_trunk = 3,
 216                 .grow_shift = 2,
 217                 .need_lock = 1,
 218                 .release_mem_en = 1,
 219                 .malloc = mlx5_malloc,
 220                 .free = mlx5_free,
 221                 .type = "mlx5_push_vlan_ipool",
 222         },
 223         [MLX5_IPOOL_TAG] = {
 224                 .size = sizeof(struct mlx5_flow_dv_tag_resource),
 225                 .trunk_size = 64,
 226                 .grow_trunk = 3,
 227                 .grow_shift = 2,
 228                 .need_lock = 1,
 229                 .release_mem_en = 0,
 230                 .per_core_cache = (1 << 16),
 231                 .malloc = mlx5_malloc,
 232                 .free = mlx5_free,
 233                 .type = "mlx5_tag_ipool",
 234         },
 235         [MLX5_IPOOL_PORT_ID] = {
 236                 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
 237                 .trunk_size = 64,
 238                 .grow_trunk = 3,
 239                 .grow_shift = 2,
 240                 .need_lock = 1,
 241                 .release_mem_en = 1,
 242                 .malloc = mlx5_malloc,
 243                 .free = mlx5_free,
 244                 .type = "mlx5_port_id_ipool",
 245         },
 246         [MLX5_IPOOL_JUMP] = {
 247                 .size = sizeof(struct mlx5_flow_tbl_data_entry),
 248                 .trunk_size = 64,
 249                 .grow_trunk = 3,
 250                 .grow_shift = 2,
 251                 .need_lock = 1,
 252                 .release_mem_en = 1,
 253                 .malloc = mlx5_malloc,
 254                 .free = mlx5_free,
 255                 .type = "mlx5_jump_ipool",
 256         },
 257         [MLX5_IPOOL_SAMPLE] = {
 258                 .size = sizeof(struct mlx5_flow_dv_sample_resource),
 259                 .trunk_size = 64,
 260                 .grow_trunk = 3,
 261                 .grow_shift = 2,
 262                 .need_lock = 1,
 263                 .release_mem_en = 1,
 264                 .malloc = mlx5_malloc,
 265                 .free = mlx5_free,
 266                 .type = "mlx5_sample_ipool",
 267         },
 268         [MLX5_IPOOL_DEST_ARRAY] = {
 269                 .size = sizeof(struct mlx5_flow_dv_dest_array_resource),
 270                 .trunk_size = 64,
 271                 .grow_trunk = 3,
 272                 .grow_shift = 2,
 273                 .need_lock = 1,
 274                 .release_mem_en = 1,
 275                 .malloc = mlx5_malloc,
 276                 .free = mlx5_free,
 277                 .type = "mlx5_dest_array_ipool",
 278         },
 279         [MLX5_IPOOL_TUNNEL_ID] = {
 280                 .size = sizeof(struct mlx5_flow_tunnel),
 281                 .trunk_size = MLX5_MAX_TUNNELS,
 282                 .need_lock = 1,
 283                 .release_mem_en = 1,
 284                 .type = "mlx5_tunnel_offload",
 285         },
 286         [MLX5_IPOOL_TNL_TBL_ID] = {
 287                 .size = 0,
 288                 .need_lock = 1,
 289                 .type = "mlx5_flow_tnl_tbl_ipool",
 290         },
 291 #endif
 292         [MLX5_IPOOL_MTR] = {
 293                 /**
 294                  * The ipool index should grow continually from small to big,
 295                  * for meter idx, so not set grow_trunk to avoid meter index
 296                  * not jump continually.
 297                  */
 298                 .size = sizeof(struct mlx5_legacy_flow_meter),
 299                 .trunk_size = 64,
 300                 .need_lock = 1,
 301                 .release_mem_en = 1,
 302                 .malloc = mlx5_malloc,
 303                 .free = mlx5_free,
 304                 .type = "mlx5_meter_ipool",
 305         },
 306         [MLX5_IPOOL_MCP] = {
 307                 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
 308                 .trunk_size = 64,
 309                 .grow_trunk = 3,
 310                 .grow_shift = 2,
 311                 .need_lock = 1,
 312                 .release_mem_en = 1,
 313                 .malloc = mlx5_malloc,
 314                 .free = mlx5_free,
 315                 .type = "mlx5_mcp_ipool",
 316         },
 317         [MLX5_IPOOL_HRXQ] = {
 318                 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
 319                 .trunk_size = 64,
 320                 .grow_trunk = 3,
 321                 .grow_shift = 2,
 322                 .need_lock = 1,
 323                 .release_mem_en = 1,
 324                 .malloc = mlx5_malloc,
 325                 .free = mlx5_free,
 326                 .type = "mlx5_hrxq_ipool",
 327         },
 328         [MLX5_IPOOL_MLX5_FLOW] = {
 329                 /*
 330                  * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
 331                  * It set in run time according to PCI function configuration.
 332                  */
 333                 .size = 0,
 334                 .trunk_size = 64,
 335                 .grow_trunk = 3,
 336                 .grow_shift = 2,
 337                 .need_lock = 1,
 338                 .release_mem_en = 0,
 339                 .per_core_cache = 1 << 19,
 340                 .malloc = mlx5_malloc,
 341                 .free = mlx5_free,
 342                 .type = "mlx5_flow_handle_ipool",
 343         },
 344         [MLX5_IPOOL_RTE_FLOW] = {
 345                 .size = sizeof(struct rte_flow),
 346                 .trunk_size = 4096,
 347                 .need_lock = 1,
 348                 .release_mem_en = 1,
 349                 .malloc = mlx5_malloc,
 350                 .free = mlx5_free,
 351                 .type = "rte_flow_ipool",
 352         },
 353         [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID] = {
 354                 .size = 0,
 355                 .need_lock = 1,
 356                 .type = "mlx5_flow_rss_id_ipool",
 357         },
 358         [MLX5_IPOOL_RSS_SHARED_ACTIONS] = {
 359                 .size = sizeof(struct mlx5_shared_action_rss),
 360                 .trunk_size = 64,
 361                 .grow_trunk = 3,
 362                 .grow_shift = 2,
 363                 .need_lock = 1,
 364                 .release_mem_en = 1,
 365                 .malloc = mlx5_malloc,
 366                 .free = mlx5_free,
 367                 .type = "mlx5_shared_action_rss",
 368         },
 369         [MLX5_IPOOL_MTR_POLICY] = {
 370                 /**
 371                  * The ipool index should grow continually from small to big,
 372                  * for policy idx, so not set grow_trunk to avoid policy index
 373                  * not jump continually.
 374                  */
 375                 .size = sizeof(struct mlx5_flow_meter_sub_policy),
 376                 .trunk_size = 64,
 377                 .need_lock = 1,
 378                 .release_mem_en = 1,
 379                 .malloc = mlx5_malloc,
 380                 .free = mlx5_free,
 381                 .type = "mlx5_meter_policy_ipool",
 382         },
 383 };
 384
 385 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
 386 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
 387
 388 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 1024
 389
 390 /**
 391  * Decide whether representor ID is a HPF(host PF) port on BF2.
 392  *
 393  * @param dev
 394  *   Pointer to Ethernet device structure.
 395  *
 396  * @return
 397  *   Non-zero if HPF, otherwise 0.
 398  */
 399 bool
 400 mlx5_is_hpf(struct rte_eth_dev *dev)
 401 {
 402         struct mlx5_priv *priv = dev->data->dev_private;
 403         uint16_t repr = MLX5_REPRESENTOR_REPR(priv->representor_id);
 404         int type = MLX5_REPRESENTOR_TYPE(priv->representor_id);
 405
 406         return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_VF &&
 407                MLX5_REPRESENTOR_REPR(-1) == repr;
 408 }
 409
 410 /**
 411  * Decide whether representor ID is a SF port representor.
 412  *
 413  * @param dev
 414  *   Pointer to Ethernet device structure.
 415  *
 416  * @return
 417  *   Non-zero if HPF, otherwise 0.
 418  */
 419 bool
 420 mlx5_is_sf_repr(struct rte_eth_dev *dev)
 421 {
 422         struct mlx5_priv *priv = dev->data->dev_private;
 423         int type = MLX5_REPRESENTOR_TYPE(priv->representor_id);
 424
 425         return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_SF;
 426 }
 427
 428 /**
 429  * Initialize the ASO aging management structure.
 430  *
 431  * @param[in] sh
 432  *   Pointer to mlx5_dev_ctx_shared object to free
 433  *
 434  * @return
 435  *   0 on success, a negative errno value otherwise and rte_errno is set.
 436  */
 437 int
 438 mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh)
 439 {
 440         int err;
 441
 442         if (sh->aso_age_mng)
 443                 return 0;
 444         sh->aso_age_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->aso_age_mng),
 445                                       RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 446         if (!sh->aso_age_mng) {
 447                 DRV_LOG(ERR, "aso_age_mng allocation was failed.");
 448                 rte_errno = ENOMEM;
 449                 return -ENOMEM;
 450         }
 451         err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_FLOW_HIT);
 452         if (err) {
 453                 mlx5_free(sh->aso_age_mng);
 454                 return -1;
 455         }
 456         rte_rwlock_init(&sh->aso_age_mng->resize_rwl);
 457         rte_spinlock_init(&sh->aso_age_mng->free_sl);
 458         LIST_INIT(&sh->aso_age_mng->free);
 459         return 0;
 460 }
 461
 462 /**
 463  * Close and release all the resources of the ASO aging management structure.
 464  *
 465  * @param[in] sh
 466  *   Pointer to mlx5_dev_ctx_shared object to free.
 467  */
 468 static void
 469 mlx5_flow_aso_age_mng_close(struct mlx5_dev_ctx_shared *sh)
 470 {
 471         int i, j;
 472
 473         mlx5_aso_flow_hit_queue_poll_stop(sh);
 474         mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_FLOW_HIT);
 475         if (sh->aso_age_mng->pools) {
 476                 struct mlx5_aso_age_pool *pool;
 477
 478                 for (i = 0; i < sh->aso_age_mng->next; ++i) {
 479                         pool = sh->aso_age_mng->pools[i];
 480                         claim_zero(mlx5_devx_cmd_destroy
 481                                                 (pool->flow_hit_aso_obj));
 482                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j)
 483                                 if (pool->actions[j].dr_action)
 484                                         claim_zero
 485                                             (mlx5_flow_os_destroy_flow_action
 486                                               (pool->actions[j].dr_action));
 487                         mlx5_free(pool);
 488                 }
 489                 mlx5_free(sh->aso_age_mng->pools);
 490         }
 491         mlx5_free(sh->aso_age_mng);
 492 }
 493
 494 /**
 495  * Initialize the shared aging list information per port.
 496  *
 497  * @param[in] sh
 498  *   Pointer to mlx5_dev_ctx_shared object.
 499  */
 500 static void
 501 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
 502 {
 503         uint32_t i;
 504         struct mlx5_age_info *age_info;
 505
 506         for (i = 0; i < sh->max_port; i++) {
 507                 age_info = &sh->port[i].age_info;
 508                 age_info->flags = 0;
 509                 TAILQ_INIT(&age_info->aged_counters);
 510                 LIST_INIT(&age_info->aged_aso);
 511                 rte_spinlock_init(&age_info->aged_sl);
 512                 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
 513         }
 514 }
 515
 516 /**
 517  * DV flow counter mode detect and config.
 518  *
 519  * @param dev
 520  *   Pointer to rte_eth_dev structure.
 521  *
 522  */
 523 void
 524 mlx5_flow_counter_mode_config(struct rte_eth_dev *dev __rte_unused)
 525 {
 526 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 527         struct mlx5_priv *priv = dev->data->dev_private;
 528         struct mlx5_dev_ctx_shared *sh = priv->sh;
 529         struct mlx5_hca_attr *hca_attr = &sh->cdev->config.hca_attr;
 530         bool fallback;
 531
 532 #ifndef HAVE_IBV_DEVX_ASYNC
 533         fallback = true;
 534 #else
 535         fallback = false;
 536         if (!sh->cdev->config.devx || !sh->config.dv_flow_en ||
 537             !hca_attr->flow_counters_dump ||
 538             !(hca_attr->flow_counter_bulk_alloc_bitmap & 0x4) ||
 539             (mlx5_flow_dv_discover_counter_offset_support(dev) == -ENOTSUP))
 540                 fallback = true;
 541 #endif
 542         if (fallback)
 543                 DRV_LOG(INFO, "Use fall-back DV counter management. Flow "
 544                         "counter dump:%d, bulk_alloc_bitmap:0x%hhx.",
 545                         hca_attr->flow_counters_dump,
 546                         hca_attr->flow_counter_bulk_alloc_bitmap);
 547         /* Initialize fallback mode only on the port initializes sh. */
 548         if (sh->refcnt == 1)
 549                 sh->cmng.counter_fallback = fallback;
 550         else if (fallback != sh->cmng.counter_fallback)
 551                 DRV_LOG(WARNING, "Port %d in sh has different fallback mode "
 552                         "with others:%d.", PORT_ID(priv), fallback);
 553 #endif
 554 }
 555
 556 /**
 557  * Initialize the counters management structure.
 558  *
 559  * @param[in] sh
 560  *   Pointer to mlx5_dev_ctx_shared object to free
 561  */
 562 static void
 563 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
 564 {
 565         int i;
 566
 567         memset(&sh->cmng, 0, sizeof(sh->cmng));
 568         TAILQ_INIT(&sh->cmng.flow_counters);
 569         sh->cmng.min_id = MLX5_CNT_BATCH_OFFSET;
 570         sh->cmng.max_id = -1;
 571         sh->cmng.last_pool_idx = POOL_IDX_INVALID;
 572         rte_spinlock_init(&sh->cmng.pool_update_sl);
 573         for (i = 0; i < MLX5_COUNTER_TYPE_MAX; i++) {
 574                 TAILQ_INIT(&sh->cmng.counters[i]);
 575                 rte_spinlock_init(&sh->cmng.csl[i]);
 576         }
 577 }
 578
 579 /**
 580  * Destroy all the resources allocated for a counter memory management.
 581  *
 582  * @param[in] mng
 583  *   Pointer to the memory management structure.
 584  */
 585 static void
 586 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
 587 {
 588         uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
 589
 590         LIST_REMOVE(mng, next);
 591         mlx5_os_wrapped_mkey_destroy(&mng->wm);
 592         mlx5_free(mem);
 593 }
 594
 595 /**
 596  * Close and release all the resources of the counters management.
 597  *
 598  * @param[in] sh
 599  *   Pointer to mlx5_dev_ctx_shared object to free.
 600  */
 601 static void
 602 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
 603 {
 604         struct mlx5_counter_stats_mem_mng *mng;
 605         int i, j;
 606         int retries = 1024;
 607
 608         rte_errno = 0;
 609         while (--retries) {
 610                 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
 611                 if (rte_errno != EINPROGRESS)
 612                         break;
 613                 rte_pause();
 614         }
 615
 616         if (sh->cmng.pools) {
 617                 struct mlx5_flow_counter_pool *pool;
 618                 uint16_t n_valid = sh->cmng.n_valid;
 619                 bool fallback = sh->cmng.counter_fallback;
 620
 621                 for (i = 0; i < n_valid; ++i) {
 622                         pool = sh->cmng.pools[i];
 623                         if (!fallback && pool->min_dcs)
 624                                 claim_zero(mlx5_devx_cmd_destroy
 625                                                                (pool->min_dcs));
 626                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
 627                                 struct mlx5_flow_counter *cnt =
 628                                                 MLX5_POOL_GET_CNT(pool, j);
 629
 630                                 if (cnt->action)
 631                                         claim_zero
 632                                          (mlx5_flow_os_destroy_flow_action
 633                                           (cnt->action));
 634                                 if (fallback && MLX5_POOL_GET_CNT
 635                                     (pool, j)->dcs_when_free)
 636                                         claim_zero(mlx5_devx_cmd_destroy
 637                                                    (cnt->dcs_when_free));
 638                         }
 639                         mlx5_free(pool);
 640                 }
 641                 mlx5_free(sh->cmng.pools);
 642         }
 643         mng = LIST_FIRST(&sh->cmng.mem_mngs);
 644         while (mng) {
 645                 mlx5_flow_destroy_counter_stat_mem_mng(mng);
 646                 mng = LIST_FIRST(&sh->cmng.mem_mngs);
 647         }
 648         memset(&sh->cmng, 0, sizeof(sh->cmng));
 649 }
 650
 651 /**
 652  * Initialize the aso flow meters management structure.
 653  *
 654  * @param[in] sh
 655  *   Pointer to mlx5_dev_ctx_shared object to free
 656  */
 657 int
 658 mlx5_aso_flow_mtrs_mng_init(struct mlx5_dev_ctx_shared *sh)
 659 {
 660         if (!sh->mtrmng) {
 661                 sh->mtrmng = mlx5_malloc(MLX5_MEM_ZERO,
 662                         sizeof(*sh->mtrmng),
 663                         RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 664                 if (!sh->mtrmng) {
 665                         DRV_LOG(ERR,
 666                         "meter management allocation was failed.");
 667                         rte_errno = ENOMEM;
 668                         return -ENOMEM;
 669                 }
 670                 if (sh->meter_aso_en) {
 671                         rte_spinlock_init(&sh->mtrmng->pools_mng.mtrsl);
 672                         rte_rwlock_init(&sh->mtrmng->pools_mng.resize_mtrwl);
 673                         LIST_INIT(&sh->mtrmng->pools_mng.meters);
 674                 }
 675                 sh->mtrmng->def_policy_id = MLX5_INVALID_POLICY_ID;
 676         }
 677         return 0;
 678 }
 679
 680 /**
 681  * Close and release all the resources of
 682  * the ASO flow meter management structure.
 683  *
 684  * @param[in] sh
 685  *   Pointer to mlx5_dev_ctx_shared object to free.
 686  */
 687 static void
 688 mlx5_aso_flow_mtrs_mng_close(struct mlx5_dev_ctx_shared *sh)
 689 {
 690         struct mlx5_aso_mtr_pool *mtr_pool;
 691         struct mlx5_flow_mtr_mng *mtrmng = sh->mtrmng;
 692         uint32_t idx;
 693 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
 694         struct mlx5_aso_mtr *aso_mtr;
 695         int i;
 696 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
 697
 698         if (sh->meter_aso_en) {
 699                 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_POLICER);
 700                 idx = mtrmng->pools_mng.n_valid;
 701                 while (idx--) {
 702                         mtr_pool = mtrmng->pools_mng.pools[idx];
 703 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
 704                         for (i = 0; i < MLX5_ASO_MTRS_PER_POOL; i++) {
 705                                 aso_mtr = &mtr_pool->mtrs[i];
 706                                 if (aso_mtr->fm.meter_action)
 707                                         claim_zero
 708                                         (mlx5_glue->destroy_flow_action
 709                                         (aso_mtr->fm.meter_action));
 710                         }
 711 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
 712                         claim_zero(mlx5_devx_cmd_destroy
 713                                                 (mtr_pool->devx_obj));
 714                         mtrmng->pools_mng.n_valid--;
 715                         mlx5_free(mtr_pool);
 716                 }
 717                 mlx5_free(sh->mtrmng->pools_mng.pools);
 718         }
 719         mlx5_free(sh->mtrmng);
 720         sh->mtrmng = NULL;
 721 }
 722
 723 /* Send FLOW_AGED event if needed. */
 724 void
 725 mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh)
 726 {
 727         struct mlx5_age_info *age_info;
 728         uint32_t i;
 729
 730         for (i = 0; i < sh->max_port; i++) {
 731                 age_info = &sh->port[i].age_info;
 732                 if (!MLX5_AGE_GET(age_info, MLX5_AGE_EVENT_NEW))
 733                         continue;
 734                 MLX5_AGE_UNSET(age_info, MLX5_AGE_EVENT_NEW);
 735                 if (MLX5_AGE_GET(age_info, MLX5_AGE_TRIGGER)) {
 736                         MLX5_AGE_UNSET(age_info, MLX5_AGE_TRIGGER);
 737                         rte_eth_dev_callback_process
 738                                 (&rte_eth_devices[sh->port[i].devx_ih_port_id],
 739                                 RTE_ETH_EVENT_FLOW_AGED, NULL);
 740                 }
 741         }
 742 }
 743
 744 /*
 745  * Initialize the ASO connection tracking structure.
 746  *
 747  * @param[in] sh
 748  *   Pointer to mlx5_dev_ctx_shared object.
 749  *
 750  * @return
 751  *   0 on success, a negative errno value otherwise and rte_errno is set.
 752  */
 753 int
 754 mlx5_flow_aso_ct_mng_init(struct mlx5_dev_ctx_shared *sh)
 755 {
 756         int err;
 757
 758         if (sh->ct_mng)
 759                 return 0;
 760         sh->ct_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->ct_mng),
 761                                  RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 762         if (!sh->ct_mng) {
 763                 DRV_LOG(ERR, "ASO CT management allocation failed.");
 764                 rte_errno = ENOMEM;
 765                 return -rte_errno;
 766         }
 767         err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_CONNECTION_TRACKING);
 768         if (err) {
 769                 mlx5_free(sh->ct_mng);
 770                 /* rte_errno should be extracted from the failure. */
 771                 rte_errno = EINVAL;
 772                 return -rte_errno;
 773         }
 774         rte_spinlock_init(&sh->ct_mng->ct_sl);
 775         rte_rwlock_init(&sh->ct_mng->resize_rwl);
 776         LIST_INIT(&sh->ct_mng->free_cts);
 777         return 0;
 778 }
 779
 780 /*
 781  * Close and release all the resources of the
 782  * ASO connection tracking management structure.
 783  *
 784  * @param[in] sh
 785  *   Pointer to mlx5_dev_ctx_shared object to free.
 786  */
 787 static void
 788 mlx5_flow_aso_ct_mng_close(struct mlx5_dev_ctx_shared *sh)
 789 {
 790         struct mlx5_aso_ct_pools_mng *mng = sh->ct_mng;
 791         struct mlx5_aso_ct_pool *ct_pool;
 792         struct mlx5_aso_ct_action *ct;
 793         uint32_t idx;
 794         uint32_t val;
 795         uint32_t cnt;
 796         int i;
 797
 798         mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_CONNECTION_TRACKING);
 799         idx = mng->next;
 800         while (idx--) {
 801                 cnt = 0;
 802                 ct_pool = mng->pools[idx];
 803                 for (i = 0; i < MLX5_ASO_CT_ACTIONS_PER_POOL; i++) {
 804                         ct = &ct_pool->actions[i];
 805                         val = __atomic_fetch_sub(&ct->refcnt, 1,
 806                                                  __ATOMIC_RELAXED);
 807                         MLX5_ASSERT(val == 1);
 808                         if (val > 1)
 809                                 cnt++;
 810 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
 811                         if (ct->dr_action_orig)
 812                                 claim_zero(mlx5_glue->destroy_flow_action
 813                                                         (ct->dr_action_orig));
 814                         if (ct->dr_action_rply)
 815                                 claim_zero(mlx5_glue->destroy_flow_action
 816                                                         (ct->dr_action_rply));
 817 #endif
 818                 }
 819                 claim_zero(mlx5_devx_cmd_destroy(ct_pool->devx_obj));
 820                 if (cnt) {
 821                         DRV_LOG(DEBUG, "%u ASO CT objects are being used in the pool %u",
 822                                 cnt, i);
 823                 }
 824                 mlx5_free(ct_pool);
 825                 /* in case of failure. */
 826                 mng->next--;
 827         }
 828         mlx5_free(mng->pools);
 829         mlx5_free(mng);
 830         /* Management structure must be cleared to 0s during allocation. */
 831         sh->ct_mng = NULL;
 832 }
 833
 834 /**
 835  * Initialize the flow resources' indexed mempool.
 836  *
 837  * @param[in] sh
 838  *   Pointer to mlx5_dev_ctx_shared object.
 839  */
 840 static void
 841 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh)
 842 {
 843         uint8_t i;
 844         struct mlx5_indexed_pool_config cfg;
 845
 846         for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
 847                 cfg = mlx5_ipool_cfg[i];
 848                 switch (i) {
 849                 default:
 850                         break;
 851                 /*
 852                  * Set MLX5_IPOOL_MLX5_FLOW ipool size
 853                  * according to PCI function flow configuration.
 854                  */
 855                 case MLX5_IPOOL_MLX5_FLOW:
 856                         cfg.size = sh->config.dv_flow_en ?
 857                                 sizeof(struct mlx5_flow_handle) :
 858                                 MLX5_FLOW_HANDLE_VERBS_SIZE;
 859                         break;
 860                 }
 861                 if (sh->config.reclaim_mode) {
 862                         cfg.release_mem_en = 1;
 863                         cfg.per_core_cache = 0;
 864                 } else {
 865                         cfg.release_mem_en = 0;
 866                 }
 867                 sh->ipool[i] = mlx5_ipool_create(&cfg);
 868         }
 869 }
 870
 871
 872 /**
 873  * Release the flow resources' indexed mempool.
 874  *
 875  * @param[in] sh
 876  *   Pointer to mlx5_dev_ctx_shared object.
 877  */
 878 static void
 879 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
 880 {
 881         uint8_t i;
 882
 883         for (i = 0; i < MLX5_IPOOL_MAX; ++i)
 884                 mlx5_ipool_destroy(sh->ipool[i]);
 885         for (i = 0; i < MLX5_MAX_MODIFY_NUM; ++i)
 886                 if (sh->mdh_ipools[i])
 887                         mlx5_ipool_destroy(sh->mdh_ipools[i]);
 888 }
 889
 890 /*
 891  * Check if dynamic flex parser for eCPRI already exists.
 892  *
 893  * @param dev
 894  *   Pointer to Ethernet device structure.
 895  *
 896  * @return
 897  *   true on exists, false on not.
 898  */
 899 bool
 900 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
 901 {
 902         struct mlx5_priv *priv = dev->data->dev_private;
 903         struct mlx5_ecpri_parser_profile *prf = &priv->sh->ecpri_parser;
 904
 905         return !!prf->obj;
 906 }
 907
 908 /*
 909  * Allocation of a flex parser for eCPRI. Once created, this parser related
 910  * resources will be held until the device is closed.
 911  *
 912  * @param dev
 913  *   Pointer to Ethernet device structure.
 914  *
 915  * @return
 916  *   0 on success, a negative errno value otherwise and rte_errno is set.
 917  */
 918 int
 919 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
 920 {
 921         struct mlx5_priv *priv = dev->data->dev_private;
 922         struct mlx5_ecpri_parser_profile *prf = &priv->sh->ecpri_parser;
 923         struct mlx5_devx_graph_node_attr node = {
 924                 .modify_field_select = 0,
 925         };
 926         uint32_t ids[8];
 927         int ret;
 928
 929         if (!priv->sh->cdev->config.hca_attr.parse_graph_flex_node) {
 930                 DRV_LOG(ERR, "Dynamic flex parser is not supported "
 931                         "for device %s.", priv->dev_data->name);
 932                 return -ENOTSUP;
 933         }
 934         node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED;
 935         /* 8 bytes now: 4B common header + 4B message body header. */
 936         node.header_length_base_value = 0x8;
 937         /* After MAC layer: Ether / VLAN. */
 938         node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC;
 939         /* Type of compared condition should be 0xAEFE in the L2 layer. */
 940         node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI;
 941         /* Sample #0: type in common header. */
 942         node.sample[0].flow_match_sample_en = 1;
 943         /* Fixed offset. */
 944         node.sample[0].flow_match_sample_offset_mode = 0x0;
 945         /* Only the 2nd byte will be used. */
 946         node.sample[0].flow_match_sample_field_base_offset = 0x0;
 947         /* Sample #1: message payload. */
 948         node.sample[1].flow_match_sample_en = 1;
 949         /* Fixed offset. */
 950         node.sample[1].flow_match_sample_offset_mode = 0x0;
 951         /*
 952          * Only the first two bytes will be used right now, and its offset will
 953          * start after the common header that with the length of a DW(u32).
 954          */
 955         node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);
 956         prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->cdev->ctx, &node);
 957         if (!prf->obj) {
 958                 DRV_LOG(ERR, "Failed to create flex parser node object.");
 959                 return (rte_errno == 0) ? -ENODEV : -rte_errno;
 960         }
 961         prf->num = 2;
 962         ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num);
 963         if (ret) {
 964                 DRV_LOG(ERR, "Failed to query sample IDs.");
 965                 return (rte_errno == 0) ? -ENODEV : -rte_errno;
 966         }
 967         prf->offset[0] = 0x0;
 968         prf->offset[1] = sizeof(uint32_t);
 969         prf->ids[0] = ids[0];
 970         prf->ids[1] = ids[1];
 971         return 0;
 972 }
 973
 974 /*
 975  * Destroy the flex parser node, including the parser itself, input / output
 976  * arcs and DW samples. Resources could be reused then.
 977  *
 978  * @param dev
 979  *   Pointer to Ethernet device structure.
 980  */
 981 static void
 982 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
 983 {
 984         struct mlx5_priv *priv = dev->data->dev_private;
 985         struct mlx5_ecpri_parser_profile *prf = &priv->sh->ecpri_parser;
 986
 987         if (prf->obj)
 988                 mlx5_devx_cmd_destroy(prf->obj);
 989         prf->obj = NULL;
 990 }
 991
 992 uint32_t
 993 mlx5_get_supported_sw_parsing_offloads(const struct mlx5_hca_attr *attr)
 994 {
 995         uint32_t sw_parsing_offloads = 0;
 996
 997         if (attr->swp) {
 998                 sw_parsing_offloads |= MLX5_SW_PARSING_CAP;
 999                 if (attr->swp_csum)
1000                         sw_parsing_offloads |= MLX5_SW_PARSING_CSUM_CAP;
1001
1002                 if (attr->swp_lso)
1003                         sw_parsing_offloads |= MLX5_SW_PARSING_TSO_CAP;
1004         }
1005         return sw_parsing_offloads;
1006 }
1007
1008 uint32_t
1009 mlx5_get_supported_tunneling_offloads(const struct mlx5_hca_attr *attr)
1010 {
1011         uint32_t tn_offloads = 0;
1012
1013         if (attr->tunnel_stateless_vxlan)
1014                 tn_offloads |= MLX5_TUNNELED_OFFLOADS_VXLAN_CAP;
1015         if (attr->tunnel_stateless_gre)
1016                 tn_offloads |= MLX5_TUNNELED_OFFLOADS_GRE_CAP;
1017         if (attr->tunnel_stateless_geneve_rx)
1018                 tn_offloads |= MLX5_TUNNELED_OFFLOADS_GENEVE_CAP;
1019         return tn_offloads;
1020 }
1021
1022 /* Fill all fields of UAR structure. */
1023 static int
1024 mlx5_rxtx_uars_prepare(struct mlx5_dev_ctx_shared *sh)
1025 {
1026         int ret;
1027
1028         ret = mlx5_devx_uar_prepare(sh->cdev, &sh->tx_uar);
1029         if (ret) {
1030                 DRV_LOG(ERR, "Failed to prepare Tx DevX UAR.");
1031                 return -rte_errno;
1032         }
1033         MLX5_ASSERT(sh->tx_uar.obj);
1034         MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->tx_uar.obj));
1035         ret = mlx5_devx_uar_prepare(sh->cdev, &sh->rx_uar);
1036         if (ret) {
1037                 DRV_LOG(ERR, "Failed to prepare Rx DevX UAR.");
1038                 mlx5_devx_uar_release(&sh->tx_uar);
1039                 return -rte_errno;
1040         }
1041         MLX5_ASSERT(sh->rx_uar.obj);
1042         MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->rx_uar.obj));
1043         return 0;
1044 }
1045
1046 static void
1047 mlx5_rxtx_uars_release(struct mlx5_dev_ctx_shared *sh)
1048 {
1049         mlx5_devx_uar_release(&sh->rx_uar);
1050         mlx5_devx_uar_release(&sh->tx_uar);
1051 }
1052
1053 /**
1054  * rte_mempool_walk() callback to unregister Rx mempools.
1055  * It used when implicit mempool registration is disabled.
1056  *
1057  * @param mp
1058  *   The mempool being walked.
1059  * @param arg
1060  *   Pointer to the device shared context.
1061  */
1062 static void
1063 mlx5_dev_ctx_shared_rx_mempool_unregister_cb(struct rte_mempool *mp, void *arg)
1064 {
1065         struct mlx5_dev_ctx_shared *sh = arg;
1066
1067         mlx5_dev_mempool_unregister(sh->cdev, mp);
1068 }
1069
1070 /**
1071  * Callback used when implicit mempool registration is disabled
1072  * in order to track Rx mempool destruction.
1073  *
1074  * @param event
1075  *   Mempool life cycle event.
1076  * @param mp
1077  *   An Rx mempool registered explicitly when the port is started.
1078  * @param arg
1079  *   Pointer to a device shared context.
1080  */
1081 static void
1082 mlx5_dev_ctx_shared_rx_mempool_event_cb(enum rte_mempool_event event,
1083                                         struct rte_mempool *mp, void *arg)
1084 {
1085         struct mlx5_dev_ctx_shared *sh = arg;
1086
1087         if (event == RTE_MEMPOOL_EVENT_DESTROY)
1088                 mlx5_dev_mempool_unregister(sh->cdev, mp);
1089 }
1090
1091 int
1092 mlx5_dev_ctx_shared_mempool_subscribe(struct rte_eth_dev *dev)
1093 {
1094         struct mlx5_priv *priv = dev->data->dev_private;
1095         struct mlx5_dev_ctx_shared *sh = priv->sh;
1096         int ret;
1097
1098         /* Check if we only need to track Rx mempool destruction. */
1099         if (!sh->cdev->config.mr_mempool_reg_en) {
1100                 ret = rte_mempool_event_callback_register
1101                                 (mlx5_dev_ctx_shared_rx_mempool_event_cb, sh);
1102                 return ret == 0 || rte_errno == EEXIST ? 0 : ret;
1103         }
1104         return mlx5_dev_mempool_subscribe(sh->cdev);
1105 }
1106
1107 /**
1108  * Set up multiple TISs with different affinities according to
1109  * number of bonding ports
1110  *
1111  * @param priv
1112  * Pointer of shared context.
1113  *
1114  * @return
1115  * Zero on success, -1 otherwise.
1116  */
1117 static int
1118 mlx5_setup_tis(struct mlx5_dev_ctx_shared *sh)
1119 {
1120         int i;
1121         struct mlx5_devx_lag_context lag_ctx = { 0 };
1122         struct mlx5_devx_tis_attr tis_attr = { 0 };
1123
1124         tis_attr.transport_domain = sh->td->id;
1125         if (sh->bond.n_port) {
1126                 if (!mlx5_devx_cmd_query_lag(sh->cdev->ctx, &lag_ctx)) {
1127                         sh->lag.tx_remap_affinity[0] =
1128                                 lag_ctx.tx_remap_affinity_1;
1129                         sh->lag.tx_remap_affinity[1] =
1130                                 lag_ctx.tx_remap_affinity_2;
1131                         sh->lag.affinity_mode = lag_ctx.port_select_mode;
1132                 } else {
1133                         DRV_LOG(ERR, "Failed to query lag affinity.");
1134                         return -1;
1135                 }
1136                 if (sh->lag.affinity_mode == MLX5_LAG_MODE_TIS) {
1137                         for (i = 0; i < sh->bond.n_port; i++) {
1138                                 tis_attr.lag_tx_port_affinity =
1139                                         MLX5_IFC_LAG_MAP_TIS_AFFINITY(i,
1140                                                         sh->bond.n_port);
1141                                 sh->tis[i] = mlx5_devx_cmd_create_tis(sh->cdev->ctx,
1142                                                 &tis_attr);
1143                                 if (!sh->tis[i]) {
1144                                         DRV_LOG(ERR, "Failed to TIS %d/%d for bonding device"
1145                                                 " %s.", i, sh->bond.n_port,
1146                                                 sh->ibdev_name);
1147                                         return -1;
1148                                 }
1149                         }
1150                         DRV_LOG(DEBUG, "LAG number of ports : %d, affinity_1 & 2 : pf%d & %d.\n",
1151                                 sh->bond.n_port, lag_ctx.tx_remap_affinity_1,
1152                                 lag_ctx.tx_remap_affinity_2);
1153                         return 0;
1154                 }
1155                 if (sh->lag.affinity_mode == MLX5_LAG_MODE_HASH)
1156                         DRV_LOG(INFO, "Device %s enabled HW hash based LAG.",
1157                                         sh->ibdev_name);
1158         }
1159         tis_attr.lag_tx_port_affinity = 0;
1160         sh->tis[0] = mlx5_devx_cmd_create_tis(sh->cdev->ctx, &tis_attr);
1161         if (!sh->tis[0]) {
1162                 DRV_LOG(ERR, "Failed to TIS 0 for bonding device"
1163                         " %s.", sh->ibdev_name);
1164                 return -1;
1165         }
1166         return 0;
1167 }
1168
1169 /**
1170  * Verify and store value for share device argument.
1171  *
1172  * @param[in] key
1173  *   Key argument to verify.
1174  * @param[in] val
1175  *   Value associated with key.
1176  * @param opaque
1177  *   User data.
1178  *
1179  * @return
1180  *   0 on success, a negative errno value otherwise and rte_errno is set.
1181  */
1182 static int
1183 mlx5_dev_args_check_handler(const char *key, const char *val, void *opaque)
1184 {
1185         struct mlx5_sh_config *config = opaque;
1186         signed long tmp;
1187
1188         errno = 0;
1189         tmp = strtol(val, NULL, 0);
1190         if (errno) {
1191                 rte_errno = errno;
1192                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1193                 return -rte_errno;
1194         }
1195         if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
1196                 /* Negative values are acceptable for some keys only. */
1197                 rte_errno = EINVAL;
1198                 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
1199                 return -rte_errno;
1200         }
1201         if (strcmp(MLX5_TX_PP, key) == 0) {
1202                 unsigned long mod = tmp >= 0 ? tmp : -tmp;
1203
1204                 if (!mod) {
1205                         DRV_LOG(ERR, "Zero Tx packet pacing parameter.");
1206                         rte_errno = EINVAL;
1207                         return -rte_errno;
1208                 }
1209                 config->tx_pp = tmp;
1210         } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
1211                 config->tx_skew = tmp;
1212         } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1213                 config->l3_vxlan_en = !!tmp;
1214         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1215                 config->vf_nl_en = !!tmp;
1216         } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1217                 config->dv_esw_en = !!tmp;
1218         } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1219                 config->dv_flow_en = !!tmp;
1220         } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1221                 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1222                     tmp != MLX5_XMETA_MODE_META16 &&
1223                     tmp != MLX5_XMETA_MODE_META32 &&
1224                     tmp != MLX5_XMETA_MODE_MISS_INFO) {
1225                         DRV_LOG(ERR, "Invalid extensive metadata parameter.");
1226                         rte_errno = EINVAL;
1227                         return -rte_errno;
1228                 }
1229                 if (tmp != MLX5_XMETA_MODE_MISS_INFO)
1230                         config->dv_xmeta_en = tmp;
1231                 else
1232                         config->dv_miss_info = 1;
1233         } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
1234                 config->lacp_by_user = !!tmp;
1235         } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1236                 if (tmp != MLX5_RCM_NONE &&
1237                     tmp != MLX5_RCM_LIGHT &&
1238                     tmp != MLX5_RCM_AGGR) {
1239                         DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1240                         rte_errno = EINVAL;
1241                         return -rte_errno;
1242                 }
1243                 config->reclaim_mode = tmp;
1244         } else if (strcmp(MLX5_DECAP_EN, key) == 0) {
1245                 config->decap_en = !!tmp;
1246         } else if (strcmp(MLX5_ALLOW_DUPLICATE_PATTERN, key) == 0) {
1247                 config->allow_duplicate_pattern = !!tmp;
1248         }
1249         return 0;
1250 }
1251
1252 /**
1253  * Parse user device parameters and adjust them according to device
1254  * capabilities.
1255  *
1256  * @param sh
1257  *   Pointer to shared device context.
1258  * @param devargs
1259  *   Device arguments structure.
1260  * @param config
1261  *   Pointer to shared device configuration structure.
1262  *
1263  * @return
1264  *   0 on success, a negative errno value otherwise and rte_errno is set.
1265  */
1266 static int
1267 mlx5_shared_dev_ctx_args_config(struct mlx5_dev_ctx_shared *sh,
1268                                 struct rte_devargs *devargs,
1269                                 struct mlx5_sh_config *config)
1270 {
1271         struct rte_kvargs *kvlist;
1272         int ret = 0;
1273
1274         /* Default configuration. */
1275         memset(config, 0, sizeof(*config));
1276         config->vf_nl_en = 1;
1277         config->dv_esw_en = 1;
1278         config->dv_flow_en = 1;
1279         config->decap_en = 1;
1280         config->allow_duplicate_pattern = 1;
1281         /* Parse device parameters. */
1282         if (devargs != NULL) {
1283                 kvlist = rte_kvargs_parse(devargs->args, NULL);
1284                 if (kvlist == NULL) {
1285                         DRV_LOG(ERR,
1286                                 "Failed to parse shared device arguments.");
1287                         rte_errno = EINVAL;
1288                         return -rte_errno;
1289                 }
1290                 /* Process parameters. */
1291                 ret = rte_kvargs_process(kvlist, NULL,
1292                                          mlx5_dev_args_check_handler, config);
1293                 rte_kvargs_free(kvlist);
1294                 if (ret) {
1295                         DRV_LOG(ERR, "Failed to process device arguments: %s",
1296                                 strerror(rte_errno));
1297                         return -rte_errno;
1298                 }
1299         }
1300         /* Adjust parameters according to device capabilities. */
1301         if (config->dv_flow_en && !sh->dev_cap.dv_flow_en) {
1302                 DRV_LOG(WARNING, "DV flow is not supported.");
1303                 config->dv_flow_en = 0;
1304         }
1305         if (config->dv_esw_en && !sh->dev_cap.dv_esw_en) {
1306                 DRV_LOG(DEBUG, "E-Switch DV flow is not supported.");
1307                 config->dv_esw_en = 0;
1308         }
1309         if (config->dv_miss_info && config->dv_esw_en)
1310                 config->dv_xmeta_en = MLX5_XMETA_MODE_META16;
1311         if (!config->dv_esw_en &&
1312             config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1313                 DRV_LOG(WARNING,
1314                         "Metadata mode %u is not supported (no E-Switch).",
1315                         config->dv_xmeta_en);
1316                 config->dv_xmeta_en = MLX5_XMETA_MODE_LEGACY;
1317         }
1318         if (config->tx_pp && !sh->dev_cap.txpp_en) {
1319                 DRV_LOG(ERR, "Packet pacing is not supported.");
1320                 rte_errno = ENODEV;
1321                 return -rte_errno;
1322         }
1323         if (!config->tx_pp && config->tx_skew) {
1324                 DRV_LOG(WARNING,
1325                         "\"tx_skew\" doesn't affect without \"tx_pp\".");
1326         }
1327         /*
1328          * If HW has bug working with tunnel packet decapsulation and scatter
1329          * FCS, and decapsulation is needed, clear the hw_fcs_strip bit.
1330          * Then RTE_ETH_RX_OFFLOAD_KEEP_CRC bit will not be set anymore.
1331          */
1332         if (sh->dev_cap.scatter_fcs_w_decap_disable && sh->config.decap_en)
1333                 config->hw_fcs_strip = 0;
1334         else
1335                 config->hw_fcs_strip = sh->dev_cap.hw_fcs_strip;
1336         DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported",
1337                 (config->hw_fcs_strip ? "" : "not "));
1338         DRV_LOG(DEBUG, "\"tx_pp\" is %d.", config->tx_pp);
1339         DRV_LOG(DEBUG, "\"tx_skew\" is %d.", config->tx_skew);
1340         DRV_LOG(DEBUG, "\"reclaim_mode\" is %u.", config->reclaim_mode);
1341         DRV_LOG(DEBUG, "\"dv_esw_en\" is %u.", config->dv_esw_en);
1342         DRV_LOG(DEBUG, "\"dv_flow_en\" is %u.", config->dv_flow_en);
1343         DRV_LOG(DEBUG, "\"dv_xmeta_en\" is %u.", config->dv_xmeta_en);
1344         DRV_LOG(DEBUG, "\"dv_miss_info\" is %u.", config->dv_miss_info);
1345         DRV_LOG(DEBUG, "\"l3_vxlan_en\" is %u.", config->l3_vxlan_en);
1346         DRV_LOG(DEBUG, "\"vf_nl_en\" is %u.", config->vf_nl_en);
1347         DRV_LOG(DEBUG, "\"lacp_by_user\" is %u.", config->lacp_by_user);
1348         DRV_LOG(DEBUG, "\"decap_en\" is %u.", config->decap_en);
1349         DRV_LOG(DEBUG, "\"allow_duplicate_pattern\" is %u.",
1350                 config->allow_duplicate_pattern);
1351         return 0;
1352 }
1353
1354 /**
1355  * Configure realtime timestamp format.
1356  *
1357  * @param sh
1358  *   Pointer to mlx5_dev_ctx_shared object.
1359  * @param hca_attr
1360  *   Pointer to DevX HCA capabilities structure.
1361  */
1362 void
1363 mlx5_rt_timestamp_config(struct mlx5_dev_ctx_shared *sh,
1364                          struct mlx5_hca_attr *hca_attr)
1365 {
1366         uint32_t dw_cnt = MLX5_ST_SZ_DW(register_mtutc);
1367         uint32_t reg[dw_cnt];
1368         int ret = ENOTSUP;
1369
1370         if (hca_attr->access_register_user)
1371                 ret = mlx5_devx_cmd_register_read(sh->cdev->ctx,
1372                                                   MLX5_REGISTER_ID_MTUTC, 0,
1373                                                   reg, dw_cnt);
1374         if (!ret) {
1375                 uint32_t ts_mode;
1376
1377                 /* MTUTC register is read successfully. */
1378                 ts_mode = MLX5_GET(register_mtutc, reg, time_stamp_mode);
1379                 if (ts_mode == MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME)
1380                         sh->dev_cap.rt_timestamp = 1;
1381         } else {
1382                 /* Kernel does not support register reading. */
1383                 if (hca_attr->dev_freq_khz == (NS_PER_S / MS_PER_S))
1384                         sh->dev_cap.rt_timestamp = 1;
1385         }
1386 }
1387
1388 /**
1389  * Allocate shared device context. If there is multiport device the
1390  * master and representors will share this context, if there is single
1391  * port dedicated device, the context will be used by only given
1392  * port due to unification.
1393  *
1394  * Routine first searches the context for the specified device name,
1395  * if found the shared context assumed and reference counter is incremented.
1396  * If no context found the new one is created and initialized with specified
1397  * device context and parameters.
1398  *
1399  * @param[in] spawn
1400  *   Pointer to the device attributes (name, port, etc).
1401  *
1402  * @return
1403  *   Pointer to mlx5_dev_ctx_shared object on success,
1404  *   otherwise NULL and rte_errno is set.
1405  */
1406 struct mlx5_dev_ctx_shared *
1407 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn)
1408 {
1409         struct mlx5_dev_ctx_shared *sh;
1410         int err = 0;
1411         uint32_t i;
1412
1413         MLX5_ASSERT(spawn);
1414         /* Secondary process should not create the shared context. */
1415         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1416         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1417         /* Search for IB context by device name. */
1418         LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
1419                 if (!strcmp(sh->ibdev_name, spawn->phys_dev_name)) {
1420                         sh->refcnt++;
1421                         goto exit;
1422                 }
1423         }
1424         /* No device found, we have to create new shared context. */
1425         MLX5_ASSERT(spawn->max_port);
1426         sh = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
1427                          sizeof(struct mlx5_dev_ctx_shared) +
1428                          spawn->max_port * sizeof(struct mlx5_dev_shared_port),
1429                          RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
1430         if (!sh) {
1431                 DRV_LOG(ERR, "Shared context allocation failure.");
1432                 rte_errno = ENOMEM;
1433                 goto exit;
1434         }
1435         pthread_mutex_init(&sh->txpp.mutex, NULL);
1436         sh->numa_node = spawn->cdev->dev->numa_node;
1437         sh->cdev = spawn->cdev;
1438         sh->esw_mode = !!(spawn->info.master || spawn->info.representor);
1439         if (spawn->bond_info)
1440                 sh->bond = *spawn->bond_info;
1441         err = mlx5_os_capabilities_prepare(sh);
1442         if (err) {
1443                 DRV_LOG(ERR, "Fail to configure device capabilities.");
1444                 goto error;
1445         }
1446         err = mlx5_shared_dev_ctx_args_config(sh, sh->cdev->dev->devargs,
1447                                               &sh->config);
1448         if (err) {
1449                 DRV_LOG(ERR, "Failed to process device configure: %s",
1450                         strerror(rte_errno));
1451                 goto error;
1452         }
1453         sh->refcnt = 1;
1454         sh->max_port = spawn->max_port;
1455         strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->cdev->ctx),
1456                 sizeof(sh->ibdev_name) - 1);
1457         strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->cdev->ctx),
1458                 sizeof(sh->ibdev_path) - 1);
1459         /*
1460          * Setting port_id to max unallowed value means there is no interrupt
1461          * subhandler installed for the given port index i.
1462          */
1463         for (i = 0; i < sh->max_port; i++) {
1464                 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
1465                 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
1466         }
1467         if (sh->cdev->config.devx) {
1468                 sh->td = mlx5_devx_cmd_create_td(sh->cdev->ctx);
1469                 if (!sh->td) {
1470                         DRV_LOG(ERR, "TD allocation failure");
1471                         rte_errno = ENOMEM;
1472                         goto error;
1473                 }
1474                 if (mlx5_setup_tis(sh)) {
1475                         DRV_LOG(ERR, "TIS allocation failure");
1476                         rte_errno = ENOMEM;
1477                         goto error;
1478                 }
1479                 err = mlx5_rxtx_uars_prepare(sh);
1480                 if (err)
1481                         goto error;
1482 #ifndef RTE_ARCH_64
1483         } else {
1484                 /* Initialize UAR access locks for 32bit implementations. */
1485                 rte_spinlock_init(&sh->uar_lock_cq);
1486                 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
1487                         rte_spinlock_init(&sh->uar_lock[i]);
1488 #endif
1489         }
1490         mlx5_os_dev_shared_handler_install(sh);
1491         if (LIST_EMPTY(&mlx5_dev_ctx_list)) {
1492                 err = mlx5_flow_os_init_workspace_once();
1493                 if (err)
1494                         goto error;
1495         }
1496         mlx5_flow_aging_init(sh);
1497         mlx5_flow_counters_mng_init(sh);
1498         mlx5_flow_ipool_create(sh);
1499         /* Add context to the global device list. */
1500         LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
1501         rte_spinlock_init(&sh->geneve_tlv_opt_sl);
1502 exit:
1503         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1504         return sh;
1505 error:
1506         err = rte_errno;
1507         pthread_mutex_destroy(&sh->txpp.mutex);
1508         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1509         MLX5_ASSERT(sh);
1510         mlx5_rxtx_uars_release(sh);
1511         i = 0;
1512         do {
1513                 if (sh->tis[i])
1514                         claim_zero(mlx5_devx_cmd_destroy(sh->tis[i]));
1515         } while (++i < (uint32_t)sh->bond.n_port);
1516         if (sh->td)
1517                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1518         mlx5_free(sh);
1519         rte_errno = err;
1520         return NULL;
1521 }
1522
1523 /**
1524  * Free shared IB device context. Decrement counter and if zero free
1525  * all allocated resources and close handles.
1526  *
1527  * @param[in] sh
1528  *   Pointer to mlx5_dev_ctx_shared object to free
1529  */
1530 void
1531 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
1532 {
1533         int ret;
1534         int i = 0;
1535
1536         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1537 #ifdef RTE_LIBRTE_MLX5_DEBUG
1538         /* Check the object presence in the list. */
1539         struct mlx5_dev_ctx_shared *lctx;
1540
1541         LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
1542                 if (lctx == sh)
1543                         break;
1544         MLX5_ASSERT(lctx);
1545         if (lctx != sh) {
1546                 DRV_LOG(ERR, "Freeing non-existing shared IB context");
1547                 goto exit;
1548         }
1549 #endif
1550         MLX5_ASSERT(sh);
1551         MLX5_ASSERT(sh->refcnt);
1552         /* Secondary process should not free the shared context. */
1553         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1554         if (--sh->refcnt)
1555                 goto exit;
1556         /* Stop watching for mempool events and unregister all mempools. */
1557         if (!sh->cdev->config.mr_mempool_reg_en) {
1558                 ret = rte_mempool_event_callback_unregister
1559                                 (mlx5_dev_ctx_shared_rx_mempool_event_cb, sh);
1560                 if (ret == 0)
1561                         rte_mempool_walk
1562                              (mlx5_dev_ctx_shared_rx_mempool_unregister_cb, sh);
1563         }
1564         /* Remove context from the global device list. */
1565         LIST_REMOVE(sh, next);
1566         /* Release resources on the last device removal. */
1567         if (LIST_EMPTY(&mlx5_dev_ctx_list)) {
1568                 mlx5_os_net_cleanup();
1569                 mlx5_flow_os_release_workspace();
1570         }
1571         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1572         if (sh->flex_parsers_dv) {
1573                 mlx5_list_destroy(sh->flex_parsers_dv);
1574                 sh->flex_parsers_dv = NULL;
1575         }
1576         /*
1577          *  Ensure there is no async event handler installed.
1578          *  Only primary process handles async device events.
1579          **/
1580         mlx5_flow_counters_mng_close(sh);
1581         if (sh->ct_mng)
1582                 mlx5_flow_aso_ct_mng_close(sh);
1583         if (sh->aso_age_mng) {
1584                 mlx5_flow_aso_age_mng_close(sh);
1585                 sh->aso_age_mng = NULL;
1586         }
1587         if (sh->mtrmng)
1588                 mlx5_aso_flow_mtrs_mng_close(sh);
1589         mlx5_flow_ipool_destroy(sh);
1590         mlx5_os_dev_shared_handler_uninstall(sh);
1591         mlx5_rxtx_uars_release(sh);
1592         do {
1593                 if (sh->tis[i])
1594                         claim_zero(mlx5_devx_cmd_destroy(sh->tis[i]));
1595         } while (++i < sh->bond.n_port);
1596         if (sh->td)
1597                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1598         MLX5_ASSERT(sh->geneve_tlv_option_resource == NULL);
1599         pthread_mutex_destroy(&sh->txpp.mutex);
1600         mlx5_free(sh);
1601         return;
1602 exit:
1603         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1604 }
1605
1606 /**
1607  * Destroy table hash list.
1608  *
1609  * @param[in] priv
1610  *   Pointer to the private device data structure.
1611  */
1612 void
1613 mlx5_free_table_hash_list(struct mlx5_priv *priv)
1614 {
1615         struct mlx5_dev_ctx_shared *sh = priv->sh;
1616
1617         if (!sh->flow_tbls)
1618                 return;
1619         mlx5_hlist_destroy(sh->flow_tbls);
1620         sh->flow_tbls = NULL;
1621 }
1622
1623 /**
1624  * Initialize flow table hash list and create the root tables entry
1625  * for each domain.
1626  *
1627  * @param[in] priv
1628  *   Pointer to the private device data structure.
1629  *
1630  * @return
1631  *   Zero on success, positive error code otherwise.
1632  */
1633 int
1634 mlx5_alloc_table_hash_list(struct mlx5_priv *priv __rte_unused)
1635 {
1636         int err = 0;
1637         /* Tables are only used in DV and DR modes. */
1638 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
1639         struct mlx5_dev_ctx_shared *sh = priv->sh;
1640         char s[MLX5_NAME_SIZE];
1641
1642         MLX5_ASSERT(sh);
1643         snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1644         sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE,
1645                                           false, true, sh,
1646                                           flow_dv_tbl_create_cb,
1647                                           flow_dv_tbl_match_cb,
1648                                           flow_dv_tbl_remove_cb,
1649                                           flow_dv_tbl_clone_cb,
1650                                           flow_dv_tbl_clone_free_cb);
1651         if (!sh->flow_tbls) {
1652                 DRV_LOG(ERR, "flow tables with hash creation failed.");
1653                 err = ENOMEM;
1654                 return err;
1655         }
1656 #ifndef HAVE_MLX5DV_DR
1657         struct rte_flow_error error;
1658         struct rte_eth_dev *dev = &rte_eth_devices[priv->dev_data->port_id];
1659
1660         /*
1661          * In case we have not DR support, the zero tables should be created
1662          * because DV expect to see them even if they cannot be created by
1663          * RDMA-CORE.
1664          */
1665         if (!flow_dv_tbl_resource_get(dev, 0, 0, 0, 0,
1666                 NULL, 0, 1, 0, &error) ||
1667             !flow_dv_tbl_resource_get(dev, 0, 1, 0, 0,
1668                 NULL, 0, 1, 0, &error) ||
1669             !flow_dv_tbl_resource_get(dev, 0, 0, 1, 0,
1670                 NULL, 0, 1, 0, &error)) {
1671                 err = ENOMEM;
1672                 goto error;
1673         }
1674         return err;
1675 error:
1676         mlx5_free_table_hash_list(priv);
1677 #endif /* HAVE_MLX5DV_DR */
1678 #endif
1679         return err;
1680 }
1681
1682 /**
1683  * Retrieve integer value from environment variable.
1684  *
1685  * @param[in] name
1686  *   Environment variable name.
1687  *
1688  * @return
1689  *   Integer value, 0 if the variable is not set.
1690  */
1691 int
1692 mlx5_getenv_int(const char *name)
1693 {
1694         const char *val = getenv(name);
1695
1696         if (val == NULL)
1697                 return 0;
1698         return atoi(val);
1699 }
1700
1701 /**
1702  * DPDK callback to add udp tunnel port
1703  *
1704  * @param[in] dev
1705  *   A pointer to eth_dev
1706  * @param[in] udp_tunnel
1707  *   A pointer to udp tunnel
1708  *
1709  * @return
1710  *   0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1711  */
1712 int
1713 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1714                          struct rte_eth_udp_tunnel *udp_tunnel)
1715 {
1716         MLX5_ASSERT(udp_tunnel != NULL);
1717         if (udp_tunnel->prot_type == RTE_ETH_TUNNEL_TYPE_VXLAN &&
1718             udp_tunnel->udp_port == 4789)
1719                 return 0;
1720         if (udp_tunnel->prot_type == RTE_ETH_TUNNEL_TYPE_VXLAN_GPE &&
1721             udp_tunnel->udp_port == 4790)
1722                 return 0;
1723         return -ENOTSUP;
1724 }
1725
1726 /**
1727  * Initialize process private data structure.
1728  *
1729  * @param dev
1730  *   Pointer to Ethernet device structure.
1731  *
1732  * @return
1733  *   0 on success, a negative errno value otherwise and rte_errno is set.
1734  */
1735 int
1736 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1737 {
1738         struct mlx5_priv *priv = dev->data->dev_private;
1739         struct mlx5_proc_priv *ppriv;
1740         size_t ppriv_size;
1741
1742         mlx5_proc_priv_uninit(dev);
1743         /*
1744          * UAR register table follows the process private structure. BlueFlame
1745          * registers for Tx queues are stored in the table.
1746          */
1747         ppriv_size = sizeof(struct mlx5_proc_priv) +
1748                      priv->txqs_n * sizeof(struct mlx5_uar_data);
1749         ppriv = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, ppriv_size,
1750                             RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1751         if (!ppriv) {
1752                 rte_errno = ENOMEM;
1753                 return -rte_errno;
1754         }
1755         ppriv->uar_table_sz = priv->txqs_n;
1756         dev->process_private = ppriv;
1757         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
1758                 priv->sh->pppriv = ppriv;
1759         return 0;
1760 }
1761
1762 /**
1763  * Un-initialize process private data structure.
1764  *
1765  * @param dev
1766  *   Pointer to Ethernet device structure.
1767  */
1768 void
1769 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1770 {
1771         if (!dev->process_private)
1772                 return;
1773         mlx5_free(dev->process_private);
1774         dev->process_private = NULL;
1775 }
1776
1777 /**
1778  * DPDK callback to close the device.
1779  *
1780  * Destroy all queues and objects, free memory.
1781  *
1782  * @param dev
1783  *   Pointer to Ethernet device structure.
1784  */
1785 int
1786 mlx5_dev_close(struct rte_eth_dev *dev)
1787 {
1788         struct mlx5_priv *priv = dev->data->dev_private;
1789         unsigned int i;
1790         int ret;
1791
1792         if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1793                 /* Check if process_private released. */
1794                 if (!dev->process_private)
1795                         return 0;
1796                 mlx5_tx_uar_uninit_secondary(dev);
1797                 mlx5_proc_priv_uninit(dev);
1798                 rte_eth_dev_release_port(dev);
1799                 return 0;
1800         }
1801         if (!priv->sh)
1802                 return 0;
1803         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1804                 dev->data->port_id,
1805                 ((priv->sh->cdev->ctx != NULL) ?
1806                 mlx5_os_get_ctx_device_name(priv->sh->cdev->ctx) : ""));
1807         /*
1808          * If default mreg copy action is removed at the stop stage,
1809          * the search will return none and nothing will be done anymore.
1810          */
1811         mlx5_flow_stop_default(dev);
1812         mlx5_traffic_disable(dev);
1813         /*
1814          * If all the flows are already flushed in the device stop stage,
1815          * then this will return directly without any action.
1816          */
1817         mlx5_flow_list_flush(dev, MLX5_FLOW_TYPE_GEN, true);
1818         mlx5_action_handle_flush(dev);
1819         mlx5_flow_meter_flush(dev, NULL);
1820         /* Prevent crashes when queues are still in use. */
1821         dev->rx_pkt_burst = rte_eth_pkt_burst_dummy;
1822         dev->tx_pkt_burst = rte_eth_pkt_burst_dummy;
1823         rte_wmb();
1824         /* Disable datapath on secondary process. */
1825         mlx5_mp_os_req_stop_rxtx(dev);
1826         /* Free the eCPRI flex parser resource. */
1827         mlx5_flex_parser_ecpri_release(dev);
1828         mlx5_flex_item_port_cleanup(dev);
1829         if (priv->rxq_privs != NULL) {
1830                 /* XXX race condition if mlx5_rx_burst() is still running. */
1831                 rte_delay_us_sleep(1000);
1832                 for (i = 0; (i != priv->rxqs_n); ++i)
1833                         mlx5_rxq_release(dev, i);
1834                 priv->rxqs_n = 0;
1835                 mlx5_free(priv->rxq_privs);
1836                 priv->rxq_privs = NULL;
1837         }
1838         if (priv->txqs != NULL) {
1839                 /* XXX race condition if mlx5_tx_burst() is still running. */
1840                 rte_delay_us_sleep(1000);
1841                 for (i = 0; (i != priv->txqs_n); ++i)
1842                         mlx5_txq_release(dev, i);
1843                 priv->txqs_n = 0;
1844                 priv->txqs = NULL;
1845         }
1846         mlx5_proc_priv_uninit(dev);
1847         if (priv->q_counters) {
1848                 mlx5_devx_cmd_destroy(priv->q_counters);
1849                 priv->q_counters = NULL;
1850         }
1851         if (priv->drop_queue.hrxq)
1852                 mlx5_drop_action_destroy(dev);
1853         if (priv->mreg_cp_tbl)
1854                 mlx5_hlist_destroy(priv->mreg_cp_tbl);
1855         mlx5_mprq_free_mp(dev);
1856         mlx5_os_free_shared_dr(priv);
1857         if (priv->rss_conf.rss_key != NULL)
1858                 mlx5_free(priv->rss_conf.rss_key);
1859         if (priv->reta_idx != NULL)
1860                 mlx5_free(priv->reta_idx);
1861         if (priv->sh->dev_cap.vf)
1862                 mlx5_os_mac_addr_flush(dev);
1863         if (priv->nl_socket_route >= 0)
1864                 close(priv->nl_socket_route);
1865         if (priv->nl_socket_rdma >= 0)
1866                 close(priv->nl_socket_rdma);
1867         if (priv->vmwa_context)
1868                 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1869         ret = mlx5_hrxq_verify(dev);
1870         if (ret)
1871                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1872                         dev->data->port_id);
1873         ret = mlx5_ind_table_obj_verify(dev);
1874         if (ret)
1875                 DRV_LOG(WARNING, "port %u some indirection table still remain",
1876                         dev->data->port_id);
1877         ret = mlx5_rxq_obj_verify(dev);
1878         if (ret)
1879                 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1880                         dev->data->port_id);
1881         ret = mlx5_rxq_verify(dev);
1882         if (ret)
1883                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1884                         dev->data->port_id);
1885         ret = mlx5_txq_obj_verify(dev);
1886         if (ret)
1887                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1888                         dev->data->port_id);
1889         ret = mlx5_txq_verify(dev);
1890         if (ret)
1891                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1892                         dev->data->port_id);
1893         ret = mlx5_flow_verify(dev);
1894         if (ret)
1895                 DRV_LOG(WARNING, "port %u some flows still remain",
1896                         dev->data->port_id);
1897         if (priv->hrxqs)
1898                 mlx5_list_destroy(priv->hrxqs);
1899         /*
1900          * Free the shared context in last turn, because the cleanup
1901          * routines above may use some shared fields, like
1902          * mlx5_os_mac_addr_flush() uses ibdev_path for retrieving
1903          * ifindex if Netlink fails.
1904          */
1905         mlx5_free_shared_dev_ctx(priv->sh);
1906         if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1907                 unsigned int c = 0;
1908                 uint16_t port_id;
1909
1910                 MLX5_ETH_FOREACH_DEV(port_id, dev->device) {
1911                         struct mlx5_priv *opriv =
1912                                 rte_eth_devices[port_id].data->dev_private;
1913
1914                         if (!opriv ||
1915                             opriv->domain_id != priv->domain_id ||
1916                             &rte_eth_devices[port_id] == dev)
1917                                 continue;
1918                         ++c;
1919                         break;
1920                 }
1921                 if (!c)
1922                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1923         }
1924         memset(priv, 0, sizeof(*priv));
1925         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1926         /*
1927          * Reset mac_addrs to NULL such that it is not freed as part of
1928          * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1929          * it is freed when dev_private is freed.
1930          */
1931         dev->data->mac_addrs = NULL;
1932         return 0;
1933 }
1934
1935 const struct eth_dev_ops mlx5_dev_ops = {
1936         .dev_configure = mlx5_dev_configure,
1937         .dev_start = mlx5_dev_start,
1938         .dev_stop = mlx5_dev_stop,
1939         .dev_set_link_down = mlx5_set_link_down,
1940         .dev_set_link_up = mlx5_set_link_up,
1941         .dev_close = mlx5_dev_close,
1942         .promiscuous_enable = mlx5_promiscuous_enable,
1943         .promiscuous_disable = mlx5_promiscuous_disable,
1944         .allmulticast_enable = mlx5_allmulticast_enable,
1945         .allmulticast_disable = mlx5_allmulticast_disable,
1946         .link_update = mlx5_link_update,
1947         .stats_get = mlx5_stats_get,
1948         .stats_reset = mlx5_stats_reset,
1949         .xstats_get = mlx5_xstats_get,
1950         .xstats_reset = mlx5_xstats_reset,
1951         .xstats_get_names = mlx5_xstats_get_names,
1952         .fw_version_get = mlx5_fw_version_get,
1953         .dev_infos_get = mlx5_dev_infos_get,
1954         .representor_info_get = mlx5_representor_info_get,
1955         .read_clock = mlx5_txpp_read_clock,
1956         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1957         .vlan_filter_set = mlx5_vlan_filter_set,
1958         .rx_queue_setup = mlx5_rx_queue_setup,
1959         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1960         .tx_queue_setup = mlx5_tx_queue_setup,
1961         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1962         .rx_queue_release = mlx5_rx_queue_release,
1963         .tx_queue_release = mlx5_tx_queue_release,
1964         .rx_queue_start = mlx5_rx_queue_start,
1965         .rx_queue_stop = mlx5_rx_queue_stop,
1966         .tx_queue_start = mlx5_tx_queue_start,
1967         .tx_queue_stop = mlx5_tx_queue_stop,
1968         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1969         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1970         .mac_addr_remove = mlx5_mac_addr_remove,
1971         .mac_addr_add = mlx5_mac_addr_add,
1972         .mac_addr_set = mlx5_mac_addr_set,
1973         .set_mc_addr_list = mlx5_set_mc_addr_list,
1974         .mtu_set = mlx5_dev_set_mtu,
1975         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1976         .vlan_offload_set = mlx5_vlan_offload_set,
1977         .reta_update = mlx5_dev_rss_reta_update,
1978         .reta_query = mlx5_dev_rss_reta_query,
1979         .rss_hash_update = mlx5_rss_hash_update,
1980         .rss_hash_conf_get = mlx5_rss_hash_conf_get,
1981         .flow_ops_get = mlx5_flow_ops_get,
1982         .rxq_info_get = mlx5_rxq_info_get,
1983         .txq_info_get = mlx5_txq_info_get,
1984         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1985         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1986         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1987         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1988         .is_removed = mlx5_is_removed,
1989         .udp_tunnel_port_add  = mlx5_udp_tunnel_port_add,
1990         .get_module_info = mlx5_get_module_info,
1991         .get_module_eeprom = mlx5_get_module_eeprom,
1992         .hairpin_cap_get = mlx5_hairpin_cap_get,
1993         .mtr_ops_get = mlx5_flow_meter_ops_get,
1994         .hairpin_bind = mlx5_hairpin_bind,
1995         .hairpin_unbind = mlx5_hairpin_unbind,
1996         .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1997         .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1998         .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1999         .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
2000         .get_monitor_addr = mlx5_get_monitor_addr,
2001 };
2002
2003 /* Available operations from secondary process. */
2004 const struct eth_dev_ops mlx5_dev_sec_ops = {
2005         .stats_get = mlx5_stats_get,
2006         .stats_reset = mlx5_stats_reset,
2007         .xstats_get = mlx5_xstats_get,
2008         .xstats_reset = mlx5_xstats_reset,
2009         .xstats_get_names = mlx5_xstats_get_names,
2010         .fw_version_get = mlx5_fw_version_get,
2011         .dev_infos_get = mlx5_dev_infos_get,
2012         .representor_info_get = mlx5_representor_info_get,
2013         .read_clock = mlx5_txpp_read_clock,
2014         .rx_queue_start = mlx5_rx_queue_start,
2015         .rx_queue_stop = mlx5_rx_queue_stop,
2016         .tx_queue_start = mlx5_tx_queue_start,
2017         .tx_queue_stop = mlx5_tx_queue_stop,
2018         .rxq_info_get = mlx5_rxq_info_get,
2019         .txq_info_get = mlx5_txq_info_get,
2020         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
2021         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
2022         .get_module_info = mlx5_get_module_info,
2023         .get_module_eeprom = mlx5_get_module_eeprom,
2024 };
2025
2026 /* Available operations in flow isolated mode. */
2027 const struct eth_dev_ops mlx5_dev_ops_isolate = {
2028         .dev_configure = mlx5_dev_configure,
2029         .dev_start = mlx5_dev_start,
2030         .dev_stop = mlx5_dev_stop,
2031         .dev_set_link_down = mlx5_set_link_down,
2032         .dev_set_link_up = mlx5_set_link_up,
2033         .dev_close = mlx5_dev_close,
2034         .promiscuous_enable = mlx5_promiscuous_enable,
2035         .promiscuous_disable = mlx5_promiscuous_disable,
2036         .allmulticast_enable = mlx5_allmulticast_enable,
2037         .allmulticast_disable = mlx5_allmulticast_disable,
2038         .link_update = mlx5_link_update,
2039         .stats_get = mlx5_stats_get,
2040         .stats_reset = mlx5_stats_reset,
2041         .xstats_get = mlx5_xstats_get,
2042         .xstats_reset = mlx5_xstats_reset,
2043         .xstats_get_names = mlx5_xstats_get_names,
2044         .fw_version_get = mlx5_fw_version_get,
2045         .dev_infos_get = mlx5_dev_infos_get,
2046         .representor_info_get = mlx5_representor_info_get,
2047         .read_clock = mlx5_txpp_read_clock,
2048         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
2049         .vlan_filter_set = mlx5_vlan_filter_set,
2050         .rx_queue_setup = mlx5_rx_queue_setup,
2051         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
2052         .tx_queue_setup = mlx5_tx_queue_setup,
2053         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
2054         .rx_queue_release = mlx5_rx_queue_release,
2055         .tx_queue_release = mlx5_tx_queue_release,
2056         .rx_queue_start = mlx5_rx_queue_start,
2057         .rx_queue_stop = mlx5_rx_queue_stop,
2058         .tx_queue_start = mlx5_tx_queue_start,
2059         .tx_queue_stop = mlx5_tx_queue_stop,
2060         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
2061         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
2062         .mac_addr_remove = mlx5_mac_addr_remove,
2063         .mac_addr_add = mlx5_mac_addr_add,
2064         .mac_addr_set = mlx5_mac_addr_set,
2065         .set_mc_addr_list = mlx5_set_mc_addr_list,
2066         .mtu_set = mlx5_dev_set_mtu,
2067         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
2068         .vlan_offload_set = mlx5_vlan_offload_set,
2069         .flow_ops_get = mlx5_flow_ops_get,
2070         .rxq_info_get = mlx5_rxq_info_get,
2071         .txq_info_get = mlx5_txq_info_get,
2072         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
2073         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
2074         .rx_queue_intr_enable = mlx5_rx_intr_enable,
2075         .rx_queue_intr_disable = mlx5_rx_intr_disable,
2076         .is_removed = mlx5_is_removed,
2077         .get_module_info = mlx5_get_module_info,
2078         .get_module_eeprom = mlx5_get_module_eeprom,
2079         .hairpin_cap_get = mlx5_hairpin_cap_get,
2080         .mtr_ops_get = mlx5_flow_meter_ops_get,
2081         .hairpin_bind = mlx5_hairpin_bind,
2082         .hairpin_unbind = mlx5_hairpin_unbind,
2083         .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
2084         .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
2085         .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
2086         .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
2087         .get_monitor_addr = mlx5_get_monitor_addr,
2088 };
2089
2090 /**
2091  * Verify and store value for device argument.
2092  *
2093  * @param[in] key
2094  *   Key argument to verify.
2095  * @param[in] val
2096  *   Value associated with key.
2097  * @param opaque
2098  *   User data.
2099  *
2100  * @return
2101  *   0 on success, a negative errno value otherwise and rte_errno is set.
2102  */
2103 static int
2104 mlx5_port_args_check_handler(const char *key, const char *val, void *opaque)
2105 {
2106         struct mlx5_port_config *config = opaque;
2107         signed long tmp;
2108
2109         /* No-op, port representors are processed in mlx5_dev_spawn(). */
2110         if (!strcmp(MLX5_DRIVER_KEY, key) || !strcmp(MLX5_REPRESENTOR, key) ||
2111             !strcmp(MLX5_SYS_MEM_EN, key) || !strcmp(MLX5_TX_DB_NC, key) ||
2112             !strcmp(MLX5_MR_MEMPOOL_REG_EN, key) || !strcmp(MLX5_TX_PP, key) ||
2113             !strcmp(MLX5_MR_EXT_MEMSEG_EN, key) || !strcmp(MLX5_TX_SKEW, key) ||
2114             !strcmp(MLX5_RECLAIM_MEM, key) || !strcmp(MLX5_DECAP_EN, key) ||
2115             !strcmp(MLX5_ALLOW_DUPLICATE_PATTERN, key) ||
2116             !strcmp(MLX5_L3_VXLAN_EN, key) || !strcmp(MLX5_VF_NL_EN, key) ||
2117             !strcmp(MLX5_DV_ESW_EN, key) || !strcmp(MLX5_DV_FLOW_EN, key) ||
2118             !strcmp(MLX5_DV_XMETA_EN, key) || !strcmp(MLX5_LACP_BY_USER, key))
2119                 return 0;
2120         errno = 0;
2121         tmp = strtol(val, NULL, 0);
2122         if (errno) {
2123                 rte_errno = errno;
2124                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
2125                 return -rte_errno;
2126         }
2127         if (tmp < 0) {
2128                 /* Negative values are acceptable for some keys only. */
2129                 rte_errno = EINVAL;
2130                 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
2131                 return -rte_errno;
2132         }
2133         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
2134                 if (tmp > MLX5_CQE_RESP_FORMAT_L34H_STRIDX) {
2135                         DRV_LOG(ERR, "invalid CQE compression "
2136                                      "format parameter");
2137                         rte_errno = EINVAL;
2138                         return -rte_errno;
2139                 }
2140                 config->cqe_comp = !!tmp;
2141                 config->cqe_comp_fmt = tmp;
2142         } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
2143                 config->hw_padding = !!tmp;
2144         } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
2145                 config->mprq.enabled = !!tmp;
2146         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
2147                 config->mprq.log_stride_num = tmp;
2148         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
2149                 config->mprq.log_stride_size = tmp;
2150         } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
2151                 config->mprq.max_memcpy_len = tmp;
2152         } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
2153                 config->mprq.min_rxqs_num = tmp;
2154         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
2155                 DRV_LOG(WARNING, "%s: deprecated parameter,"
2156                                  " converted to txq_inline_max", key);
2157                 config->txq_inline_max = tmp;
2158         } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
2159                 config->txq_inline_max = tmp;
2160         } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
2161                 config->txq_inline_min = tmp;
2162         } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
2163                 config->txq_inline_mpw = tmp;
2164         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
2165                 config->txqs_inline = tmp;
2166         } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
2167                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
2168         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
2169                 config->mps = !!tmp;
2170         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
2171                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
2172         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
2173                 DRV_LOG(WARNING, "%s: deprecated parameter,"
2174                                  " converted to txq_inline_mpw", key);
2175                 config->txq_inline_mpw = tmp;
2176         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
2177                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
2178         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
2179                 config->rx_vec_en = !!tmp;
2180         } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
2181                 config->max_dump_files_num = tmp;
2182         } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
2183                 config->lro_timeout = tmp;
2184         } else if (strcmp(RTE_DEVARGS_KEY_CLASS, key) == 0) {
2185                 DRV_LOG(DEBUG, "class argument is %s.", val);
2186         } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
2187                 config->log_hp_size = tmp;
2188         } else if (strcmp(MLX5_DELAY_DROP, key) == 0) {
2189                 config->std_delay_drop = !!(tmp & MLX5_DELAY_DROP_STANDARD);
2190                 config->hp_delay_drop = !!(tmp & MLX5_DELAY_DROP_HAIRPIN);
2191         } else {
2192                 DRV_LOG(WARNING,
2193                         "%s: unknown parameter, maybe it's for another class.",
2194                         key);
2195         }
2196         return 0;
2197 }
2198
2199 /**
2200  * Parse user port parameters and adjust them according to device capabilities.
2201  *
2202  * @param priv
2203  *   Pointer to shared device context.
2204  * @param devargs
2205  *   Device arguments structure.
2206  * @param config
2207  *   Pointer to port configuration structure.
2208  *
2209  * @return
2210  *   0 on success, a negative errno value otherwise and rte_errno is set.
2211  */
2212 int
2213 mlx5_port_args_config(struct mlx5_priv *priv, struct rte_devargs *devargs,
2214                       struct mlx5_port_config *config)
2215 {
2216         struct rte_kvargs *kvlist;
2217         struct mlx5_hca_attr *hca_attr = &priv->sh->cdev->config.hca_attr;
2218         struct mlx5_dev_cap *dev_cap = &priv->sh->dev_cap;
2219         bool devx = priv->sh->cdev->config.devx;
2220         int ret = 0;
2221
2222         /* Default configuration. */
2223         memset(config, 0, sizeof(*config));
2224         config->mps = MLX5_ARG_UNSET;
2225         config->cqe_comp = 1;
2226         config->rx_vec_en = 1;
2227         config->txq_inline_max = MLX5_ARG_UNSET;
2228         config->txq_inline_min = MLX5_ARG_UNSET;
2229         config->txq_inline_mpw = MLX5_ARG_UNSET;
2230         config->txqs_inline = MLX5_ARG_UNSET;
2231         config->mprq.max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN;
2232         config->mprq.min_rxqs_num = MLX5_MPRQ_MIN_RXQS;
2233         config->mprq.log_stride_num = MLX5_MPRQ_DEFAULT_LOG_STRIDE_NUM;
2234         config->log_hp_size = MLX5_ARG_UNSET;
2235         config->std_delay_drop = 0;
2236         config->hp_delay_drop = 0;
2237         /* Parse device parameters. */
2238         if (devargs != NULL) {
2239                 kvlist = rte_kvargs_parse(devargs->args, NULL);
2240                 if (kvlist == NULL) {
2241                         DRV_LOG(ERR,
2242                                 "Failed to parse device arguments.");
2243                         rte_errno = EINVAL;
2244                         return -rte_errno;
2245                 }
2246                 /* Process parameters. */
2247                 ret = rte_kvargs_process(kvlist, NULL,
2248                                          mlx5_port_args_check_handler, config);
2249                 rte_kvargs_free(kvlist);
2250                 if (ret) {
2251                         DRV_LOG(ERR, "Failed to process port arguments: %s",
2252                                 strerror(rte_errno));
2253                         return -rte_errno;
2254                 }
2255         }
2256         /* Adjust parameters according to device capabilities. */
2257         if (config->hw_padding && !dev_cap->hw_padding) {
2258                 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported.");
2259                 config->hw_padding = 0;
2260         } else if (config->hw_padding) {
2261                 DRV_LOG(DEBUG, "Rx end alignment padding is enabled.");
2262         }
2263         /*
2264          * MPW is disabled by default, while the Enhanced MPW is enabled
2265          * by default.
2266          */
2267         if (config->mps == MLX5_ARG_UNSET)
2268                 config->mps = (dev_cap->mps == MLX5_MPW_ENHANCED) ?
2269                               MLX5_MPW_ENHANCED : MLX5_MPW_DISABLED;
2270         else
2271                 config->mps = config->mps ? dev_cap->mps : MLX5_MPW_DISABLED;
2272         DRV_LOG(INFO, "%sMPS is %s",
2273                 config->mps == MLX5_MPW_ENHANCED ? "enhanced " :
2274                 config->mps == MLX5_MPW ? "legacy " : "",
2275                 config->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled");
2276         /* LRO is supported only when DV flow enabled. */
2277         if (dev_cap->lro_supported && !priv->sh->config.dv_flow_en)
2278                 dev_cap->lro_supported = 0;
2279         if (dev_cap->lro_supported) {
2280                 /*
2281                  * If LRO timeout is not configured by application,
2282                  * use the minimal supported value.
2283                  */
2284                 if (!config->lro_timeout)
2285                         config->lro_timeout =
2286                                        hca_attr->lro_timer_supported_periods[0];
2287                 DRV_LOG(DEBUG, "LRO session timeout set to %d usec.",
2288                         config->lro_timeout);
2289         }
2290         if (config->cqe_comp && !dev_cap->cqe_comp) {
2291                 DRV_LOG(WARNING, "Rx CQE 128B compression is not supported.");
2292                 config->cqe_comp = 0;
2293         }
2294         if (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_FTAG_STRIDX &&
2295             (!devx || !hca_attr->mini_cqe_resp_flow_tag)) {
2296                 DRV_LOG(WARNING,
2297                         "Flow Tag CQE compression format isn't supported.");
2298                 config->cqe_comp = 0;
2299         }
2300         if (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_L34H_STRIDX &&
2301             (!devx || !hca_attr->mini_cqe_resp_l3_l4_tag)) {
2302                 DRV_LOG(WARNING,
2303                         "L3/L4 Header CQE compression format isn't supported.");
2304                 config->cqe_comp = 0;
2305         }
2306         DRV_LOG(DEBUG, "Rx CQE compression is %ssupported.",
2307                 config->cqe_comp ? "" : "not ");
2308         if ((config->std_delay_drop || config->hp_delay_drop) &&
2309             !dev_cap->rq_delay_drop_en) {
2310                 config->std_delay_drop = 0;
2311                 config->hp_delay_drop = 0;
2312                 DRV_LOG(WARNING, "dev_port-%u: Rxq delay drop isn't supported.",
2313                         priv->dev_port);
2314         }
2315         if (config->mprq.enabled && !priv->sh->dev_cap.mprq.enabled) {
2316                 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported.");
2317                 config->mprq.enabled = 0;
2318         }
2319         if (config->max_dump_files_num == 0)
2320                 config->max_dump_files_num = 128;
2321         /* Detect minimal data bytes to inline. */
2322         mlx5_set_min_inline(priv);
2323         DRV_LOG(DEBUG, "VLAN insertion in WQE is %ssupported.",
2324                 config->hw_vlan_insert ? "" : "not ");
2325         DRV_LOG(DEBUG, "\"rxq_pkt_pad_en\" is %u.", config->hw_padding);
2326         DRV_LOG(DEBUG, "\"rxq_cqe_comp_en\" is %u.", config->cqe_comp);
2327         DRV_LOG(DEBUG, "\"cqe_comp_fmt\" is %u.", config->cqe_comp_fmt);
2328         DRV_LOG(DEBUG, "\"rx_vec_en\" is %u.", config->rx_vec_en);
2329         DRV_LOG(DEBUG, "Standard \"delay_drop\" is %u.",
2330                 config->std_delay_drop);
2331         DRV_LOG(DEBUG, "Hairpin \"delay_drop\" is %u.", config->hp_delay_drop);
2332         DRV_LOG(DEBUG, "\"max_dump_files_num\" is %u.",
2333                 config->max_dump_files_num);
2334         DRV_LOG(DEBUG, "\"log_hp_size\" is %u.", config->log_hp_size);
2335         DRV_LOG(DEBUG, "\"mprq_en\" is %u.", config->mprq.enabled);
2336         DRV_LOG(DEBUG, "\"mprq_log_stride_num\" is %u.",
2337                 config->mprq.log_stride_num);
2338         DRV_LOG(DEBUG, "\"mprq_log_stride_size\" is %u.",
2339                 config->mprq.log_stride_size);
2340         DRV_LOG(DEBUG, "\"mprq_max_memcpy_len\" is %u.",
2341                 config->mprq.max_memcpy_len);
2342         DRV_LOG(DEBUG, "\"rxqs_min_mprq\" is %u.", config->mprq.min_rxqs_num);
2343         DRV_LOG(DEBUG, "\"lro_timeout_usec\" is %u.", config->lro_timeout);
2344         DRV_LOG(DEBUG, "\"txq_mpw_en\" is %d.", config->mps);
2345         DRV_LOG(DEBUG, "\"txqs_min_inline\" is %d.", config->txqs_inline);
2346         DRV_LOG(DEBUG, "\"txq_inline_min\" is %d.", config->txq_inline_min);
2347         DRV_LOG(DEBUG, "\"txq_inline_max\" is %d.", config->txq_inline_max);
2348         DRV_LOG(DEBUG, "\"txq_inline_mpw\" is %d.", config->txq_inline_mpw);
2349         return 0;
2350 }
2351
2352 /**
2353  * Check sibling device configurations when probing again.
2354  *
2355  * Sibling devices sharing infiniband device context should have compatible
2356  * configurations. This regards representors and bonding device.
2357  *
2358  * @param cdev
2359  *   Pointer to mlx5 device structure.
2360  *
2361  * @return
2362  *   0 on success, a negative errno value otherwise and rte_errno is set.
2363  */
2364 int
2365 mlx5_probe_again_args_validate(struct mlx5_common_device *cdev)
2366 {
2367         struct mlx5_dev_ctx_shared *sh = NULL;
2368         struct mlx5_sh_config *config;
2369         int ret;
2370
2371         /* Secondary process should not handle devargs. */
2372         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2373                 return 0;
2374         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
2375         /* Search for IB context by common device pointer. */
2376         LIST_FOREACH(sh, &mlx5_dev_ctx_list, next)
2377                 if (sh->cdev == cdev)
2378                         break;
2379         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
2380         /* There is sh for this device -> it isn't probe again. */
2381         if (sh == NULL)
2382                 return 0;
2383         config = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
2384                              sizeof(struct mlx5_sh_config),
2385                              RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
2386         if (config == NULL) {
2387                 rte_errno = -ENOMEM;
2388                 return -rte_errno;
2389         }
2390         /*
2391          * Creates a temporary IB context configure structure according to new
2392          * devargs attached in probing again.
2393          */
2394         ret = mlx5_shared_dev_ctx_args_config(sh, sh->cdev->dev->devargs,
2395                                               config);
2396         if (ret) {
2397                 DRV_LOG(ERR, "Failed to process device configure: %s",
2398                         strerror(rte_errno));
2399                 mlx5_free(config);
2400                 return ret;
2401         }
2402         /*
2403          * Checks the match between the temporary structure and the existing
2404          * IB context structure.
2405          */
2406         if (sh->config.dv_flow_en ^ config->dv_flow_en) {
2407                 DRV_LOG(ERR, "\"dv_flow_en\" "
2408                         "configuration mismatch for shared %s context.",
2409                         sh->ibdev_name);
2410                 goto error;
2411         }
2412         if ((sh->config.dv_xmeta_en ^ config->dv_xmeta_en) ||
2413             (sh->config.dv_miss_info ^ config->dv_miss_info)) {
2414                 DRV_LOG(ERR, "\"dv_xmeta_en\" "
2415                         "configuration mismatch for shared %s context.",
2416                         sh->ibdev_name);
2417                 goto error;
2418         }
2419         if (sh->config.dv_esw_en ^ config->dv_esw_en) {
2420                 DRV_LOG(ERR, "\"dv_esw_en\" "
2421                         "configuration mismatch for shared %s context.",
2422                         sh->ibdev_name);
2423                 goto error;
2424         }
2425         if (sh->config.reclaim_mode ^ config->reclaim_mode) {
2426                 DRV_LOG(ERR, "\"reclaim_mode\" "
2427                         "configuration mismatch for shared %s context.",
2428                         sh->ibdev_name);
2429                 goto error;
2430         }
2431         if (sh->config.allow_duplicate_pattern ^
2432             config->allow_duplicate_pattern) {
2433                 DRV_LOG(ERR, "\"allow_duplicate_pattern\" "
2434                         "configuration mismatch for shared %s context.",
2435                         sh->ibdev_name);
2436                 goto error;
2437         }
2438         if (sh->config.l3_vxlan_en ^ config->l3_vxlan_en) {
2439                 DRV_LOG(ERR, "\"l3_vxlan_en\" "
2440                         "configuration mismatch for shared %s context.",
2441                         sh->ibdev_name);
2442                 goto error;
2443         }
2444         if (sh->config.decap_en ^ config->decap_en) {
2445                 DRV_LOG(ERR, "\"decap_en\" "
2446                         "configuration mismatch for shared %s context.",
2447                         sh->ibdev_name);
2448                 goto error;
2449         }
2450         if (sh->config.lacp_by_user ^ config->lacp_by_user) {
2451                 DRV_LOG(ERR, "\"lacp_by_user\" "
2452                         "configuration mismatch for shared %s context.",
2453                         sh->ibdev_name);
2454                 goto error;
2455         }
2456         if (sh->config.tx_pp ^ config->tx_pp) {
2457                 DRV_LOG(ERR, "\"tx_pp\" "
2458                         "configuration mismatch for shared %s context.",
2459                         sh->ibdev_name);
2460                 goto error;
2461         }
2462         if (sh->config.tx_skew ^ config->tx_skew) {
2463                 DRV_LOG(ERR, "\"tx_skew\" "
2464                         "configuration mismatch for shared %s context.",
2465                         sh->ibdev_name);
2466                 goto error;
2467         }
2468         mlx5_free(config);
2469         return 0;
2470 error:
2471         mlx5_free(config);
2472         rte_errno = EINVAL;
2473         return -rte_errno;
2474 }
2475
2476 /**
2477  * Configures the minimal amount of data to inline into WQE
2478  * while sending packets.
2479  *
2480  * - the txq_inline_min has the maximal priority, if this
2481  *   key is specified in devargs
2482  * - if DevX is enabled the inline mode is queried from the
2483  *   device (HCA attributes and NIC vport context if needed).
2484  * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
2485  *   and none (0 bytes) for other NICs
2486  *
2487  * @param priv
2488  *   Pointer to the private device data structure.
2489  */
2490 void
2491 mlx5_set_min_inline(struct mlx5_priv *priv)
2492 {
2493         struct mlx5_hca_attr *hca_attr = &priv->sh->cdev->config.hca_attr;
2494         struct mlx5_port_config *config = &priv->config;
2495
2496         if (config->txq_inline_min != MLX5_ARG_UNSET) {
2497                 /* Application defines size of inlined data explicitly. */
2498                 if (priv->pci_dev != NULL) {
2499                         switch (priv->pci_dev->id.device_id) {
2500                         case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2501                         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2502                                 if (config->txq_inline_min <
2503                                                (int)MLX5_INLINE_HSIZE_L2) {
2504                                         DRV_LOG(DEBUG,
2505                                                 "txq_inline_mix aligned to minimal ConnectX-4 required value %d",
2506                                                 (int)MLX5_INLINE_HSIZE_L2);
2507                                         config->txq_inline_min =
2508                                                         MLX5_INLINE_HSIZE_L2;
2509                                 }
2510                                 break;
2511                         }
2512                 }
2513                 goto exit;
2514         }
2515         if (hca_attr->eth_net_offloads) {
2516                 /* We have DevX enabled, inline mode queried successfully. */
2517                 switch (hca_attr->wqe_inline_mode) {
2518                 case MLX5_CAP_INLINE_MODE_L2:
2519                         /* outer L2 header must be inlined. */
2520                         config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2521                         goto exit;
2522                 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
2523                         /* No inline data are required by NIC. */
2524                         config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2525                         config->hw_vlan_insert =
2526                                 hca_attr->wqe_vlan_insert;
2527                         DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
2528                         goto exit;
2529                 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
2530                         /* inline mode is defined by NIC vport context. */
2531                         if (!hca_attr->eth_virt)
2532                                 break;
2533                         switch (hca_attr->vport_inline_mode) {
2534                         case MLX5_INLINE_MODE_NONE:
2535                                 config->txq_inline_min =
2536                                         MLX5_INLINE_HSIZE_NONE;
2537                                 goto exit;
2538                         case MLX5_INLINE_MODE_L2:
2539                                 config->txq_inline_min =
2540                                         MLX5_INLINE_HSIZE_L2;
2541                                 goto exit;
2542                         case MLX5_INLINE_MODE_IP:
2543                                 config->txq_inline_min =
2544                                         MLX5_INLINE_HSIZE_L3;
2545                                 goto exit;
2546                         case MLX5_INLINE_MODE_TCP_UDP:
2547                                 config->txq_inline_min =
2548                                         MLX5_INLINE_HSIZE_L4;
2549                                 goto exit;
2550                         case MLX5_INLINE_MODE_INNER_L2:
2551                                 config->txq_inline_min =
2552                                         MLX5_INLINE_HSIZE_INNER_L2;
2553                                 goto exit;
2554                         case MLX5_INLINE_MODE_INNER_IP:
2555                                 config->txq_inline_min =
2556                                         MLX5_INLINE_HSIZE_INNER_L3;
2557                                 goto exit;
2558                         case MLX5_INLINE_MODE_INNER_TCP_UDP:
2559                                 config->txq_inline_min =
2560                                         MLX5_INLINE_HSIZE_INNER_L4;
2561                                 goto exit;
2562                         }
2563                 }
2564         }
2565         if (priv->pci_dev == NULL) {
2566                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2567                 goto exit;
2568         }
2569         /*
2570          * We get here if we are unable to deduce
2571          * inline data size with DevX. Try PCI ID
2572          * to determine old NICs.
2573          */
2574         switch (priv->pci_dev->id.device_id) {
2575         case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2576         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2577         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
2578         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
2579                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2580                 config->hw_vlan_insert = 0;
2581                 break;
2582         case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
2583         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
2584         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
2585         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
2586                 /*
2587                  * These NICs support VLAN insertion from WQE and
2588                  * report the wqe_vlan_insert flag. But there is the bug
2589                  * and PFC control may be broken, so disable feature.
2590                  */
2591                 config->hw_vlan_insert = 0;
2592                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2593                 break;
2594         default:
2595                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2596                 break;
2597         }
2598 exit:
2599         DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
2600 }
2601
2602 /**
2603  * Configures the metadata mask fields in the shared context.
2604  *
2605  * @param [in] dev
2606  *   Pointer to Ethernet device.
2607  */
2608 void
2609 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
2610 {
2611         struct mlx5_priv *priv = dev->data->dev_private;
2612         struct mlx5_dev_ctx_shared *sh = priv->sh;
2613         uint32_t meta, mark, reg_c0;
2614
2615         reg_c0 = ~priv->vport_meta_mask;
2616         switch (sh->config.dv_xmeta_en) {
2617         case MLX5_XMETA_MODE_LEGACY:
2618                 meta = UINT32_MAX;
2619                 mark = MLX5_FLOW_MARK_MASK;
2620                 break;
2621         case MLX5_XMETA_MODE_META16:
2622                 meta = reg_c0 >> rte_bsf32(reg_c0);
2623                 mark = MLX5_FLOW_MARK_MASK;
2624                 break;
2625         case MLX5_XMETA_MODE_META32:
2626                 meta = UINT32_MAX;
2627                 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
2628                 break;
2629         default:
2630                 meta = 0;
2631                 mark = 0;
2632                 MLX5_ASSERT(false);
2633                 break;
2634         }
2635         if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
2636                 DRV_LOG(WARNING, "metadata MARK mask mismatch %08X:%08X",
2637                                  sh->dv_mark_mask, mark);
2638         else
2639                 sh->dv_mark_mask = mark;
2640         if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
2641                 DRV_LOG(WARNING, "metadata META mask mismatch %08X:%08X",
2642                                  sh->dv_meta_mask, meta);
2643         else
2644                 sh->dv_meta_mask = meta;
2645         if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
2646                 DRV_LOG(WARNING, "metadata reg_c0 mask mismatch %08X:%08X",
2647                                  sh->dv_meta_mask, reg_c0);
2648         else
2649                 sh->dv_regc0_mask = reg_c0;
2650         DRV_LOG(DEBUG, "metadata mode %u", sh->config.dv_xmeta_en);
2651         DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
2652         DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
2653         DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
2654 }
2655
2656 int
2657 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
2658 {
2659         static const char *const dynf_names[] = {
2660                 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
2661                 RTE_MBUF_DYNFLAG_METADATA_NAME,
2662                 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
2663         };
2664         unsigned int i;
2665
2666         if (n < RTE_DIM(dynf_names))
2667                 return -ENOMEM;
2668         for (i = 0; i < RTE_DIM(dynf_names); i++) {
2669                 if (names[i] == NULL)
2670                         return -EINVAL;
2671                 strcpy(names[i], dynf_names[i]);
2672         }
2673         return RTE_DIM(dynf_names);
2674 }
2675
2676 /**
2677  * Look for the ethernet device belonging to mlx5 driver.
2678  *
2679  * @param[in] port_id
2680  *   port_id to start looking for device.
2681  * @param[in] odev
2682  *   Pointer to the hint device. When device is being probed
2683  *   the its siblings (master and preceding representors might
2684  *   not have assigned driver yet (because the mlx5_os_pci_probe()
2685  *   is not completed yet, for this case match on hint
2686  *   device may be used to detect sibling device.
2687  *
2688  * @return
2689  *   port_id of found device, RTE_MAX_ETHPORT if not found.
2690  */
2691 uint16_t
2692 mlx5_eth_find_next(uint16_t port_id, struct rte_device *odev)
2693 {
2694         while (port_id < RTE_MAX_ETHPORTS) {
2695                 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
2696
2697                 if (dev->state != RTE_ETH_DEV_UNUSED &&
2698                     dev->device &&
2699                     (dev->device == odev ||
2700                      (dev->device->driver &&
2701                      dev->device->driver->name &&
2702                      ((strcmp(dev->device->driver->name,
2703                               MLX5_PCI_DRIVER_NAME) == 0) ||
2704                       (strcmp(dev->device->driver->name,
2705                               MLX5_AUXILIARY_DRIVER_NAME) == 0)))))
2706                         break;
2707                 port_id++;
2708         }
2709         if (port_id >= RTE_MAX_ETHPORTS)
2710                 return RTE_MAX_ETHPORTS;
2711         return port_id;
2712 }
2713
2714 /**
2715  * Callback to remove a device.
2716  *
2717  * This function removes all Ethernet devices belong to a given device.
2718  *
2719  * @param[in] cdev
2720  *   Pointer to the generic device.
2721  *
2722  * @return
2723  *   0 on success, the function cannot fail.
2724  */
2725 int
2726 mlx5_net_remove(struct mlx5_common_device *cdev)
2727 {
2728         uint16_t port_id;
2729         int ret = 0;
2730
2731         RTE_ETH_FOREACH_DEV_OF(port_id, cdev->dev) {
2732                 /*
2733                  * mlx5_dev_close() is not registered to secondary process,
2734                  * call the close function explicitly for secondary process.
2735                  */
2736                 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
2737                         ret |= mlx5_dev_close(&rte_eth_devices[port_id]);
2738                 else
2739                         ret |= rte_eth_dev_close(port_id);
2740         }
2741         return ret == 0 ? 0 : -EIO;
2742 }
2743
2744 static const struct rte_pci_id mlx5_pci_id_map[] = {
2745         {
2746                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2747                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
2748         },
2749         {
2750                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2751                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
2752         },
2753         {
2754                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2755                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
2756         },
2757         {
2758                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2759                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
2760         },
2761         {
2762                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2763                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
2764         },
2765         {
2766                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2767                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
2768         },
2769         {
2770                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2771                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
2772         },
2773         {
2774                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2775                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
2776         },
2777         {
2778                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2779                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
2780         },
2781         {
2782                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2783                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
2784         },
2785         {
2786                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2787                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
2788         },
2789         {
2790                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2791                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
2792         },
2793         {
2794                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2795                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
2796         },
2797         {
2798                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2799                                 PCI_DEVICE_ID_MELLANOX_CONNECTXVF)
2800         },
2801         {
2802                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2803                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
2804         },
2805         {
2806                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2807                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
2808         },
2809         {
2810                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2811                                 PCI_DEVICE_ID_MELLANOX_CONNECTX7)
2812         },
2813         {
2814                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2815                                 PCI_DEVICE_ID_MELLANOX_CONNECTX7BF)
2816         },
2817         {
2818                 .vendor_id = 0
2819         }
2820 };
2821
2822 static struct mlx5_class_driver mlx5_net_driver = {
2823         .drv_class = MLX5_CLASS_ETH,
2824         .name = RTE_STR(MLX5_ETH_DRIVER_NAME),
2825         .id_table = mlx5_pci_id_map,
2826         .probe = mlx5_os_net_probe,
2827         .remove = mlx5_net_remove,
2828         .probe_again = 1,
2829         .intr_lsc = 1,
2830         .intr_rmv = 1,
2831 };
2832
2833 /* Initialize driver log type. */
2834 RTE_LOG_REGISTER_DEFAULT(mlx5_logtype, NOTICE)
2835
2836 /**
2837  * Driver initialization routine.
2838  */
2839 RTE_INIT(rte_mlx5_pmd_init)
2840 {
2841         pthread_mutex_init(&mlx5_dev_ctx_list_mutex, NULL);
2842         mlx5_common_init();
2843         /* Build the static tables for Verbs conversion. */
2844         mlx5_set_ptype_table();
2845         mlx5_set_cksum_table();
2846         mlx5_set_swp_types_table();
2847         if (mlx5_glue)
2848                 mlx5_class_driver_register(&mlx5_net_driver);
2849 }
2850
2851 RTE_PMD_EXPORT_NAME(MLX5_ETH_DRIVER_NAME, __COUNTER__);
2852 RTE_PMD_REGISTER_PCI_TABLE(MLX5_ETH_DRIVER_NAME, mlx5_pci_id_map);
2853 RTE_PMD_REGISTER_KMOD_DEP(MLX5_ETH_DRIVER_NAME, "* ib_uverbs & mlx5_core & mlx5_ib");