1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
13 #include <rte_malloc.h>
14 #include <ethdev_driver.h>
16 #include <rte_bus_pci.h>
17 #include <rte_common.h>
18 #include <rte_kvargs.h>
19 #include <rte_rwlock.h>
20 #include <rte_spinlock.h>
21 #include <rte_string_fns.h>
22 #include <rte_alarm.h>
23 #include <rte_cycles.h>
25 #include <mlx5_glue.h>
26 #include <mlx5_devx_cmds.h>
27 #include <mlx5_common.h>
28 #include <mlx5_common_os.h>
29 #include <mlx5_common_mp.h>
30 #include <mlx5_malloc.h>
32 #include "mlx5_defs.h"
34 #include "mlx5_utils.h"
35 #include "mlx5_rxtx.h"
38 #include "mlx5_autoconf.h"
40 #include "mlx5_flow.h"
41 #include "mlx5_flow_os.h"
42 #include "rte_pmd_mlx5.h"
44 #define MLX5_ETH_DRIVER_NAME mlx5_eth
46 /* Device parameter to enable RX completion queue compression. */
47 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
49 /* Device parameter to enable padding Rx packet to cacheline size. */
50 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
52 /* Device parameter to enable Multi-Packet Rx queue. */
53 #define MLX5_RX_MPRQ_EN "mprq_en"
55 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
56 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
58 /* Device parameter to configure log 2 of the stride size for MPRQ. */
59 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
61 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
62 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
64 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
65 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
67 /* Device parameter to configure inline send. Deprecated, ignored.*/
68 #define MLX5_TXQ_INLINE "txq_inline"
70 /* Device parameter to limit packet size to inline with ordinary SEND. */
71 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
73 /* Device parameter to configure minimal data size to inline. */
74 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
76 /* Device parameter to limit packet size to inline with Enhanced MPW. */
77 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
80 * Device parameter to configure the number of TX queues threshold for
81 * enabling inline send.
83 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
86 * Device parameter to configure the number of TX queues threshold for
87 * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
89 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
91 /* Device parameter to enable multi-packet send WQEs. */
92 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
95 * Device parameter to force doorbell register mapping
96 * to non-cahed region eliminating the extra write memory barrier.
98 #define MLX5_TX_DB_NC "tx_db_nc"
101 * Device parameter to include 2 dsegs in the title WQEBB.
102 * Deprecated, ignored.
104 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
107 * Device parameter to limit the size of inlining packet.
108 * Deprecated, ignored.
110 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
113 * Device parameter to enable Tx scheduling on timestamps
114 * and specify the packet pacing granularity in nanoseconds.
116 #define MLX5_TX_PP "tx_pp"
119 * Device parameter to specify skew in nanoseconds on Tx datapath,
120 * it represents the time between SQ start WQE processing and
121 * appearing actual packet data on the wire.
123 #define MLX5_TX_SKEW "tx_skew"
126 * Device parameter to enable hardware Tx vector.
127 * Deprecated, ignored (no vectorized Tx routines anymore).
129 #define MLX5_TX_VEC_EN "tx_vec_en"
131 /* Device parameter to enable hardware Rx vector. */
132 #define MLX5_RX_VEC_EN "rx_vec_en"
134 /* Allow L3 VXLAN flow creation. */
135 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
137 /* Activate DV E-Switch flow steering. */
138 #define MLX5_DV_ESW_EN "dv_esw_en"
140 /* Activate DV flow steering. */
141 #define MLX5_DV_FLOW_EN "dv_flow_en"
143 /* Enable extensive flow metadata support. */
144 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
146 /* Device parameter to let the user manage the lacp traffic of bonded device */
147 #define MLX5_LACP_BY_USER "lacp_by_user"
149 /* Activate Netlink support in VF mode. */
150 #define MLX5_VF_NL_EN "vf_nl_en"
152 /* Enable extending memsegs when creating a MR. */
153 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
155 /* Select port representors to instantiate. */
156 #define MLX5_REPRESENTOR "representor"
158 /* Device parameter to configure the maximum number of dump files per queue. */
159 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
161 /* Configure timeout of LRO session (in microseconds). */
162 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
165 * Device parameter to configure the total data buffer size for a single
166 * hairpin queue (logarithm value).
168 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
170 /* Flow memory reclaim mode. */
171 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
173 /* The default memory allocator used in PMD. */
174 #define MLX5_SYS_MEM_EN "sys_mem_en"
175 /* Decap will be used or not. */
176 #define MLX5_DECAP_EN "decap_en"
178 /* Device parameter to configure allow or prevent duplicate rules pattern. */
179 #define MLX5_ALLOW_DUPLICATE_PATTERN "allow_duplicate_pattern"
181 /* Shared memory between primary and secondary processes. */
182 struct mlx5_shared_data *mlx5_shared_data;
184 /** Driver-specific log messages type. */
187 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
188 LIST_HEAD_INITIALIZER();
189 static pthread_mutex_t mlx5_dev_ctx_list_mutex;
190 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
191 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
192 [MLX5_IPOOL_DECAP_ENCAP] = {
193 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
199 .malloc = mlx5_malloc,
201 .type = "mlx5_encap_decap_ipool",
203 [MLX5_IPOOL_PUSH_VLAN] = {
204 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
210 .malloc = mlx5_malloc,
212 .type = "mlx5_push_vlan_ipool",
215 .size = sizeof(struct mlx5_flow_dv_tag_resource),
221 .per_core_cache = (1 << 16),
222 .malloc = mlx5_malloc,
224 .type = "mlx5_tag_ipool",
226 [MLX5_IPOOL_PORT_ID] = {
227 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
233 .malloc = mlx5_malloc,
235 .type = "mlx5_port_id_ipool",
237 [MLX5_IPOOL_JUMP] = {
238 .size = sizeof(struct mlx5_flow_tbl_data_entry),
244 .malloc = mlx5_malloc,
246 .type = "mlx5_jump_ipool",
248 [MLX5_IPOOL_SAMPLE] = {
249 .size = sizeof(struct mlx5_flow_dv_sample_resource),
255 .malloc = mlx5_malloc,
257 .type = "mlx5_sample_ipool",
259 [MLX5_IPOOL_DEST_ARRAY] = {
260 .size = sizeof(struct mlx5_flow_dv_dest_array_resource),
266 .malloc = mlx5_malloc,
268 .type = "mlx5_dest_array_ipool",
270 [MLX5_IPOOL_TUNNEL_ID] = {
271 .size = sizeof(struct mlx5_flow_tunnel),
272 .trunk_size = MLX5_MAX_TUNNELS,
275 .type = "mlx5_tunnel_offload",
277 [MLX5_IPOOL_TNL_TBL_ID] = {
280 .type = "mlx5_flow_tnl_tbl_ipool",
285 * The ipool index should grow continually from small to big,
286 * for meter idx, so not set grow_trunk to avoid meter index
287 * not jump continually.
289 .size = sizeof(struct mlx5_legacy_flow_meter),
293 .malloc = mlx5_malloc,
295 .type = "mlx5_meter_ipool",
298 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
304 .malloc = mlx5_malloc,
306 .type = "mlx5_mcp_ipool",
308 [MLX5_IPOOL_HRXQ] = {
309 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
315 .malloc = mlx5_malloc,
317 .type = "mlx5_hrxq_ipool",
319 [MLX5_IPOOL_MLX5_FLOW] = {
321 * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
322 * It set in run time according to PCI function configuration.
330 .per_core_cache = 1 << 19,
331 .malloc = mlx5_malloc,
333 .type = "mlx5_flow_handle_ipool",
335 [MLX5_IPOOL_RTE_FLOW] = {
336 .size = sizeof(struct rte_flow),
340 .malloc = mlx5_malloc,
342 .type = "rte_flow_ipool",
344 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID] = {
347 .type = "mlx5_flow_rss_id_ipool",
349 [MLX5_IPOOL_RSS_SHARED_ACTIONS] = {
350 .size = sizeof(struct mlx5_shared_action_rss),
356 .malloc = mlx5_malloc,
358 .type = "mlx5_shared_action_rss",
360 [MLX5_IPOOL_MTR_POLICY] = {
362 * The ipool index should grow continually from small to big,
363 * for policy idx, so not set grow_trunk to avoid policy index
364 * not jump continually.
366 .size = sizeof(struct mlx5_flow_meter_sub_policy),
370 .malloc = mlx5_malloc,
372 .type = "mlx5_meter_policy_ipool",
377 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
378 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
380 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 1024
383 * Decide whether representor ID is a HPF(host PF) port on BF2.
386 * Pointer to Ethernet device structure.
389 * Non-zero if HPF, otherwise 0.
392 mlx5_is_hpf(struct rte_eth_dev *dev)
394 struct mlx5_priv *priv = dev->data->dev_private;
395 uint16_t repr = MLX5_REPRESENTOR_REPR(priv->representor_id);
396 int type = MLX5_REPRESENTOR_TYPE(priv->representor_id);
398 return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_VF &&
399 MLX5_REPRESENTOR_REPR(-1) == repr;
403 * Decide whether representor ID is a SF port representor.
406 * Pointer to Ethernet device structure.
409 * Non-zero if HPF, otherwise 0.
412 mlx5_is_sf_repr(struct rte_eth_dev *dev)
414 struct mlx5_priv *priv = dev->data->dev_private;
415 int type = MLX5_REPRESENTOR_TYPE(priv->representor_id);
417 return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_SF;
421 * Initialize the ASO aging management structure.
424 * Pointer to mlx5_dev_ctx_shared object to free
427 * 0 on success, a negative errno value otherwise and rte_errno is set.
430 mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh)
436 sh->aso_age_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->aso_age_mng),
437 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
438 if (!sh->aso_age_mng) {
439 DRV_LOG(ERR, "aso_age_mng allocation was failed.");
443 err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_FLOW_HIT);
445 mlx5_free(sh->aso_age_mng);
448 rte_spinlock_init(&sh->aso_age_mng->resize_sl);
449 rte_spinlock_init(&sh->aso_age_mng->free_sl);
450 LIST_INIT(&sh->aso_age_mng->free);
455 * Close and release all the resources of the ASO aging management structure.
458 * Pointer to mlx5_dev_ctx_shared object to free.
461 mlx5_flow_aso_age_mng_close(struct mlx5_dev_ctx_shared *sh)
465 mlx5_aso_flow_hit_queue_poll_stop(sh);
466 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_FLOW_HIT);
467 if (sh->aso_age_mng->pools) {
468 struct mlx5_aso_age_pool *pool;
470 for (i = 0; i < sh->aso_age_mng->next; ++i) {
471 pool = sh->aso_age_mng->pools[i];
472 claim_zero(mlx5_devx_cmd_destroy
473 (pool->flow_hit_aso_obj));
474 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j)
475 if (pool->actions[j].dr_action)
477 (mlx5_flow_os_destroy_flow_action
478 (pool->actions[j].dr_action));
481 mlx5_free(sh->aso_age_mng->pools);
483 mlx5_free(sh->aso_age_mng);
487 * Initialize the shared aging list information per port.
490 * Pointer to mlx5_dev_ctx_shared object.
493 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
496 struct mlx5_age_info *age_info;
498 for (i = 0; i < sh->max_port; i++) {
499 age_info = &sh->port[i].age_info;
501 TAILQ_INIT(&age_info->aged_counters);
502 LIST_INIT(&age_info->aged_aso);
503 rte_spinlock_init(&age_info->aged_sl);
504 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
509 * Initialize the counters management structure.
512 * Pointer to mlx5_dev_ctx_shared object to free
515 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
519 memset(&sh->cmng, 0, sizeof(sh->cmng));
520 TAILQ_INIT(&sh->cmng.flow_counters);
521 sh->cmng.min_id = MLX5_CNT_BATCH_OFFSET;
522 sh->cmng.max_id = -1;
523 sh->cmng.last_pool_idx = POOL_IDX_INVALID;
524 rte_spinlock_init(&sh->cmng.pool_update_sl);
525 for (i = 0; i < MLX5_COUNTER_TYPE_MAX; i++) {
526 TAILQ_INIT(&sh->cmng.counters[i]);
527 rte_spinlock_init(&sh->cmng.csl[i]);
532 * Destroy all the resources allocated for a counter memory management.
535 * Pointer to the memory management structure.
538 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
540 uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
542 LIST_REMOVE(mng, next);
543 claim_zero(mlx5_devx_cmd_destroy(mng->dm));
544 claim_zero(mlx5_os_umem_dereg(mng->umem));
549 * Close and release all the resources of the counters management.
552 * Pointer to mlx5_dev_ctx_shared object to free.
555 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
557 struct mlx5_counter_stats_mem_mng *mng;
563 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
564 if (rte_errno != EINPROGRESS)
569 if (sh->cmng.pools) {
570 struct mlx5_flow_counter_pool *pool;
571 uint16_t n_valid = sh->cmng.n_valid;
572 bool fallback = sh->cmng.counter_fallback;
574 for (i = 0; i < n_valid; ++i) {
575 pool = sh->cmng.pools[i];
576 if (!fallback && pool->min_dcs)
577 claim_zero(mlx5_devx_cmd_destroy
579 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
580 struct mlx5_flow_counter *cnt =
581 MLX5_POOL_GET_CNT(pool, j);
585 (mlx5_flow_os_destroy_flow_action
587 if (fallback && MLX5_POOL_GET_CNT
588 (pool, j)->dcs_when_free)
589 claim_zero(mlx5_devx_cmd_destroy
590 (cnt->dcs_when_free));
594 mlx5_free(sh->cmng.pools);
596 mng = LIST_FIRST(&sh->cmng.mem_mngs);
598 mlx5_flow_destroy_counter_stat_mem_mng(mng);
599 mng = LIST_FIRST(&sh->cmng.mem_mngs);
601 memset(&sh->cmng, 0, sizeof(sh->cmng));
605 * Initialize the aso flow meters management structure.
608 * Pointer to mlx5_dev_ctx_shared object to free
611 mlx5_aso_flow_mtrs_mng_init(struct mlx5_dev_ctx_shared *sh)
614 sh->mtrmng = mlx5_malloc(MLX5_MEM_ZERO,
616 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
619 "meter management allocation was failed.");
623 if (sh->meter_aso_en) {
624 rte_spinlock_init(&sh->mtrmng->pools_mng.mtrsl);
625 LIST_INIT(&sh->mtrmng->pools_mng.meters);
627 sh->mtrmng->def_policy_id = MLX5_INVALID_POLICY_ID;
633 * Close and release all the resources of
634 * the ASO flow meter management structure.
637 * Pointer to mlx5_dev_ctx_shared object to free.
640 mlx5_aso_flow_mtrs_mng_close(struct mlx5_dev_ctx_shared *sh)
642 struct mlx5_aso_mtr_pool *mtr_pool;
643 struct mlx5_flow_mtr_mng *mtrmng = sh->mtrmng;
645 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
646 struct mlx5_aso_mtr *aso_mtr;
648 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
650 if (sh->meter_aso_en) {
651 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_POLICER);
652 idx = mtrmng->pools_mng.n_valid;
654 mtr_pool = mtrmng->pools_mng.pools[idx];
655 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
656 for (i = 0; i < MLX5_ASO_MTRS_PER_POOL; i++) {
657 aso_mtr = &mtr_pool->mtrs[i];
658 if (aso_mtr->fm.meter_action)
660 (mlx5_glue->destroy_flow_action
661 (aso_mtr->fm.meter_action));
663 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
664 claim_zero(mlx5_devx_cmd_destroy
665 (mtr_pool->devx_obj));
666 mtrmng->pools_mng.n_valid--;
669 mlx5_free(sh->mtrmng->pools_mng.pools);
671 mlx5_free(sh->mtrmng);
675 /* Send FLOW_AGED event if needed. */
677 mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh)
679 struct mlx5_age_info *age_info;
682 for (i = 0; i < sh->max_port; i++) {
683 age_info = &sh->port[i].age_info;
684 if (!MLX5_AGE_GET(age_info, MLX5_AGE_EVENT_NEW))
686 MLX5_AGE_UNSET(age_info, MLX5_AGE_EVENT_NEW);
687 if (MLX5_AGE_GET(age_info, MLX5_AGE_TRIGGER)) {
688 MLX5_AGE_UNSET(age_info, MLX5_AGE_TRIGGER);
689 rte_eth_dev_callback_process
690 (&rte_eth_devices[sh->port[i].devx_ih_port_id],
691 RTE_ETH_EVENT_FLOW_AGED, NULL);
697 * Initialize the ASO connection tracking structure.
700 * Pointer to mlx5_dev_ctx_shared object.
703 * 0 on success, a negative errno value otherwise and rte_errno is set.
706 mlx5_flow_aso_ct_mng_init(struct mlx5_dev_ctx_shared *sh)
712 sh->ct_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->ct_mng),
713 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
715 DRV_LOG(ERR, "ASO CT management allocation failed.");
719 err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_CONNECTION_TRACKING);
721 mlx5_free(sh->ct_mng);
722 /* rte_errno should be extracted from the failure. */
726 rte_spinlock_init(&sh->ct_mng->ct_sl);
727 rte_rwlock_init(&sh->ct_mng->resize_rwl);
728 LIST_INIT(&sh->ct_mng->free_cts);
733 * Close and release all the resources of the
734 * ASO connection tracking management structure.
737 * Pointer to mlx5_dev_ctx_shared object to free.
740 mlx5_flow_aso_ct_mng_close(struct mlx5_dev_ctx_shared *sh)
742 struct mlx5_aso_ct_pools_mng *mng = sh->ct_mng;
743 struct mlx5_aso_ct_pool *ct_pool;
744 struct mlx5_aso_ct_action *ct;
750 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_CONNECTION_TRACKING);
754 ct_pool = mng->pools[idx];
755 for (i = 0; i < MLX5_ASO_CT_ACTIONS_PER_POOL; i++) {
756 ct = &ct_pool->actions[i];
757 val = __atomic_fetch_sub(&ct->refcnt, 1,
759 MLX5_ASSERT(val == 1);
762 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
763 if (ct->dr_action_orig)
764 claim_zero(mlx5_glue->destroy_flow_action
765 (ct->dr_action_orig));
766 if (ct->dr_action_rply)
767 claim_zero(mlx5_glue->destroy_flow_action
768 (ct->dr_action_rply));
771 claim_zero(mlx5_devx_cmd_destroy(ct_pool->devx_obj));
773 DRV_LOG(DEBUG, "%u ASO CT objects are being used in the pool %u",
777 /* in case of failure. */
780 mlx5_free(mng->pools);
782 /* Management structure must be cleared to 0s during allocation. */
787 * Initialize the flow resources' indexed mempool.
790 * Pointer to mlx5_dev_ctx_shared object.
792 * Pointer to user dev config.
795 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
796 const struct mlx5_dev_config *config)
799 struct mlx5_indexed_pool_config cfg;
801 for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
802 cfg = mlx5_ipool_cfg[i];
807 * Set MLX5_IPOOL_MLX5_FLOW ipool size
808 * according to PCI function flow configuration.
810 case MLX5_IPOOL_MLX5_FLOW:
811 cfg.size = config->dv_flow_en ?
812 sizeof(struct mlx5_flow_handle) :
813 MLX5_FLOW_HANDLE_VERBS_SIZE;
816 if (config->reclaim_mode) {
817 cfg.release_mem_en = 1;
818 cfg.per_core_cache = 0;
820 cfg.release_mem_en = 0;
822 sh->ipool[i] = mlx5_ipool_create(&cfg);
828 * Release the flow resources' indexed mempool.
831 * Pointer to mlx5_dev_ctx_shared object.
834 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
838 for (i = 0; i < MLX5_IPOOL_MAX; ++i)
839 mlx5_ipool_destroy(sh->ipool[i]);
840 for (i = 0; i < MLX5_MAX_MODIFY_NUM; ++i)
841 if (sh->mdh_ipools[i])
842 mlx5_ipool_destroy(sh->mdh_ipools[i]);
846 * Check if dynamic flex parser for eCPRI already exists.
849 * Pointer to Ethernet device structure.
852 * true on exists, false on not.
855 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
857 struct mlx5_priv *priv = dev->data->dev_private;
858 struct mlx5_flex_parser_profiles *prf =
859 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
865 * Allocation of a flex parser for eCPRI. Once created, this parser related
866 * resources will be held until the device is closed.
869 * Pointer to Ethernet device structure.
872 * 0 on success, a negative errno value otherwise and rte_errno is set.
875 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
877 struct mlx5_priv *priv = dev->data->dev_private;
878 struct mlx5_flex_parser_profiles *prf =
879 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
880 struct mlx5_devx_graph_node_attr node = {
881 .modify_field_select = 0,
886 if (!priv->config.hca_attr.parse_graph_flex_node) {
887 DRV_LOG(ERR, "Dynamic flex parser is not supported "
888 "for device %s.", priv->dev_data->name);
891 node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED;
892 /* 8 bytes now: 4B common header + 4B message body header. */
893 node.header_length_base_value = 0x8;
894 /* After MAC layer: Ether / VLAN. */
895 node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC;
896 /* Type of compared condition should be 0xAEFE in the L2 layer. */
897 node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI;
898 /* Sample #0: type in common header. */
899 node.sample[0].flow_match_sample_en = 1;
901 node.sample[0].flow_match_sample_offset_mode = 0x0;
902 /* Only the 2nd byte will be used. */
903 node.sample[0].flow_match_sample_field_base_offset = 0x0;
904 /* Sample #1: message payload. */
905 node.sample[1].flow_match_sample_en = 1;
907 node.sample[1].flow_match_sample_offset_mode = 0x0;
909 * Only the first two bytes will be used right now, and its offset will
910 * start after the common header that with the length of a DW(u32).
912 node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);
913 prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->ctx, &node);
915 DRV_LOG(ERR, "Failed to create flex parser node object.");
916 return (rte_errno == 0) ? -ENODEV : -rte_errno;
919 ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num);
921 DRV_LOG(ERR, "Failed to query sample IDs.");
922 return (rte_errno == 0) ? -ENODEV : -rte_errno;
924 prf->offset[0] = 0x0;
925 prf->offset[1] = sizeof(uint32_t);
926 prf->ids[0] = ids[0];
927 prf->ids[1] = ids[1];
932 * Destroy the flex parser node, including the parser itself, input / output
933 * arcs and DW samples. Resources could be reused then.
936 * Pointer to Ethernet device structure.
939 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
941 struct mlx5_priv *priv = dev->data->dev_private;
942 struct mlx5_flex_parser_profiles *prf =
943 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
946 mlx5_devx_cmd_destroy(prf->obj);
951 * Allocate Rx and Tx UARs in robust fashion.
952 * This routine handles the following UAR allocation issues:
954 * - tries to allocate the UAR with the most appropriate memory
955 * mapping type from the ones supported by the host
957 * - tries to allocate the UAR with non-NULL base address
958 * OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as
959 * UAR base address if UAR was not the first object in the UAR page.
960 * It caused the PMD failure and we should try to get another UAR
961 * till we get the first one with non-NULL base address returned.
964 mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh,
965 const struct mlx5_dev_config *config)
967 uint32_t uar_mapping, retry;
971 for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
972 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
973 /* Control the mapping type according to the settings. */
974 uar_mapping = (config->dbnc == MLX5_TXDB_NCACHED) ?
975 MLX5DV_UAR_ALLOC_TYPE_NC :
976 MLX5DV_UAR_ALLOC_TYPE_BF;
978 RTE_SET_USED(config);
980 * It seems we have no way to control the memory mapping type
981 * for the UAR, the default "Write-Combining" type is supposed.
982 * The UAR initialization on queue creation queries the
983 * actual mapping type done by Verbs/kernel and setups the
984 * PMD datapath accordingly.
988 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->ctx, uar_mapping);
989 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
991 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
992 if (config->dbnc == MLX5_TXDB_CACHED ||
993 config->dbnc == MLX5_TXDB_HEURISTIC)
994 DRV_LOG(WARNING, "Devarg tx_db_nc setting "
995 "is not supported by DevX");
997 * In some environments like virtual machine
998 * the Write Combining mapped might be not supported
999 * and UAR allocation fails. We try "Non-Cached"
1000 * mapping for the case. The tx_burst routines take
1001 * the UAR mapping type into account on UAR setup
1002 * on queue creation.
1004 DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (BF)");
1005 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
1006 sh->tx_uar = mlx5_glue->devx_alloc_uar
1007 (sh->ctx, uar_mapping);
1008 } else if (!sh->tx_uar &&
1009 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_NC) {
1010 if (config->dbnc == MLX5_TXDB_NCACHED)
1011 DRV_LOG(WARNING, "Devarg tx_db_nc settings "
1012 "is not supported by DevX");
1014 * If Verbs/kernel does not support "Non-Cached"
1015 * try the "Write-Combining".
1017 DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (NC)");
1018 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_BF;
1019 sh->tx_uar = mlx5_glue->devx_alloc_uar
1020 (sh->ctx, uar_mapping);
1024 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (BF/NC)");
1028 base_addr = mlx5_os_get_devx_uar_base_addr(sh->tx_uar);
1032 * The UARs are allocated by rdma_core within the
1033 * IB device context, on context closure all UARs
1034 * will be freed, should be no memory/object leakage.
1036 DRV_LOG(DEBUG, "Retrying to allocate Tx DevX UAR");
1039 /* Check whether we finally succeeded with valid UAR allocation. */
1041 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (NULL base)");
1045 for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
1047 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
1048 (sh->ctx, uar_mapping);
1049 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
1050 if (!sh->devx_rx_uar &&
1051 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
1053 * Rx UAR is used to control interrupts only,
1054 * should be no datapath noticeable impact,
1055 * can try "Non-Cached" mapping safely.
1057 DRV_LOG(DEBUG, "Failed to allocate Rx DevX UAR (BF)");
1058 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
1059 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
1060 (sh->ctx, uar_mapping);
1063 if (!sh->devx_rx_uar) {
1064 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (BF/NC)");
1068 base_addr = mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar);
1072 * The UARs are allocated by rdma_core within the
1073 * IB device context, on context closure all UARs
1074 * will be freed, should be no memory/object leakage.
1076 DRV_LOG(DEBUG, "Retrying to allocate Rx DevX UAR");
1077 sh->devx_rx_uar = NULL;
1079 /* Check whether we finally succeeded with valid UAR allocation. */
1080 if (!sh->devx_rx_uar) {
1081 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (NULL base)");
1089 * Allocate shared device context. If there is multiport device the
1090 * master and representors will share this context, if there is single
1091 * port dedicated device, the context will be used by only given
1092 * port due to unification.
1094 * Routine first searches the context for the specified device name,
1095 * if found the shared context assumed and reference counter is incremented.
1096 * If no context found the new one is created and initialized with specified
1097 * device context and parameters.
1100 * Pointer to the device attributes (name, port, etc).
1102 * Pointer to device configuration structure.
1105 * Pointer to mlx5_dev_ctx_shared object on success,
1106 * otherwise NULL and rte_errno is set.
1108 struct mlx5_dev_ctx_shared *
1109 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
1110 const struct mlx5_dev_config *config)
1112 struct mlx5_dev_ctx_shared *sh;
1115 struct mlx5_devx_tis_attr tis_attr = { 0 };
1118 /* Secondary process should not create the shared context. */
1119 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1120 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1121 /* Search for IB context by device name. */
1122 LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
1123 if (!strcmp(sh->ibdev_name,
1124 mlx5_os_get_dev_device_name(spawn->phys_dev))) {
1129 /* No device found, we have to create new shared context. */
1130 MLX5_ASSERT(spawn->max_port);
1131 sh = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
1132 sizeof(struct mlx5_dev_ctx_shared) +
1134 sizeof(struct mlx5_dev_shared_port),
1135 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
1137 DRV_LOG(ERR, "shared context allocation failure");
1141 sh->numa_node = spawn->numa_node;
1142 if (spawn->bond_info)
1143 sh->bond = *spawn->bond_info;
1144 err = mlx5_os_open_device(spawn, config, sh);
1147 err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
1149 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
1153 sh->max_port = spawn->max_port;
1154 sh->reclaim_mode = config->reclaim_mode;
1155 strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
1156 sizeof(sh->ibdev_name) - 1);
1157 strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
1158 sizeof(sh->ibdev_path) - 1);
1160 * Setting port_id to max unallowed value means
1161 * there is no interrupt subhandler installed for
1162 * the given port index i.
1164 for (i = 0; i < sh->max_port; i++) {
1165 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
1166 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
1168 sh->pd = mlx5_os_alloc_pd(sh->ctx);
1169 if (sh->pd == NULL) {
1170 DRV_LOG(ERR, "PD allocation failure");
1175 err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
1177 DRV_LOG(ERR, "Fail to extract pdn from PD");
1180 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
1182 DRV_LOG(ERR, "TD allocation failure");
1186 tis_attr.transport_domain = sh->td->id;
1187 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
1189 DRV_LOG(ERR, "TIS allocation failure");
1193 err = mlx5_alloc_rxtx_uars(sh, config);
1196 MLX5_ASSERT(sh->tx_uar);
1197 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->tx_uar));
1199 MLX5_ASSERT(sh->devx_rx_uar);
1200 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar));
1203 /* Initialize UAR access locks for 32bit implementations. */
1204 rte_spinlock_init(&sh->uar_lock_cq);
1205 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
1206 rte_spinlock_init(&sh->uar_lock[i]);
1209 * Once the device is added to the list of memory event
1210 * callback, its global MR cache table cannot be expanded
1211 * on the fly because of deadlock. If it overflows, lookup
1212 * should be done by searching MR list linearly, which is slow.
1214 * At this point the device is not added to the memory
1215 * event list yet, context is just being created.
1217 err = mlx5_mr_btree_init(&sh->share_cache.cache,
1218 MLX5_MR_BTREE_CACHE_N * 2,
1224 mlx5_os_set_reg_mr_cb(&sh->share_cache.reg_mr_cb,
1225 &sh->share_cache.dereg_mr_cb);
1226 mlx5_os_dev_shared_handler_install(sh);
1227 sh->cnt_id_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_DWORD);
1228 if (!sh->cnt_id_tbl) {
1232 if (LIST_EMPTY(&mlx5_dev_ctx_list)) {
1233 err = mlx5_flow_os_init_workspace_once();
1237 mlx5_flow_aging_init(sh);
1238 mlx5_flow_counters_mng_init(sh);
1239 mlx5_flow_ipool_create(sh, config);
1240 /* Add device to memory callback list. */
1241 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1242 LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
1244 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1245 /* Add context to the global device list. */
1246 LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
1247 rte_spinlock_init(&sh->geneve_tlv_opt_sl);
1249 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1252 pthread_mutex_destroy(&sh->txpp.mutex);
1253 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1256 mlx5_l3t_destroy(sh->cnt_id_tbl);
1257 if (sh->share_cache.cache.table)
1258 mlx5_mr_btree_free(&sh->share_cache.cache);
1260 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1262 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1263 if (sh->devx_rx_uar)
1264 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1266 mlx5_glue->devx_free_uar(sh->tx_uar);
1268 claim_zero(mlx5_os_dealloc_pd(sh->pd));
1270 claim_zero(mlx5_glue->close_device(sh->ctx));
1272 MLX5_ASSERT(err > 0);
1278 * Free shared IB device context. Decrement counter and if zero free
1279 * all allocated resources and close handles.
1282 * Pointer to mlx5_dev_ctx_shared object to free
1285 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
1287 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1288 #ifdef RTE_LIBRTE_MLX5_DEBUG
1289 /* Check the object presence in the list. */
1290 struct mlx5_dev_ctx_shared *lctx;
1292 LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
1297 DRV_LOG(ERR, "Freeing non-existing shared IB context");
1302 MLX5_ASSERT(sh->refcnt);
1303 /* Secondary process should not free the shared context. */
1304 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1307 /* Remove from memory callback device list. */
1308 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1309 LIST_REMOVE(sh, mem_event_cb);
1310 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1311 /* Release created Memory Regions. */
1312 mlx5_mr_release_cache(&sh->share_cache);
1313 /* Remove context from the global device list. */
1314 LIST_REMOVE(sh, next);
1315 /* Release flow workspaces objects on the last device. */
1316 if (LIST_EMPTY(&mlx5_dev_ctx_list))
1317 mlx5_flow_os_release_workspace();
1318 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1320 * Ensure there is no async event handler installed.
1321 * Only primary process handles async device events.
1323 mlx5_flow_counters_mng_close(sh);
1324 if (sh->aso_age_mng) {
1325 mlx5_flow_aso_age_mng_close(sh);
1326 sh->aso_age_mng = NULL;
1329 mlx5_aso_flow_mtrs_mng_close(sh);
1330 mlx5_flow_ipool_destroy(sh);
1331 mlx5_os_dev_shared_handler_uninstall(sh);
1332 if (sh->cnt_id_tbl) {
1333 mlx5_l3t_destroy(sh->cnt_id_tbl);
1334 sh->cnt_id_tbl = NULL;
1337 mlx5_glue->devx_free_uar(sh->tx_uar);
1341 claim_zero(mlx5_os_dealloc_pd(sh->pd));
1343 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1345 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1346 if (sh->devx_rx_uar)
1347 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1349 claim_zero(mlx5_glue->close_device(sh->ctx));
1350 MLX5_ASSERT(sh->geneve_tlv_option_resource == NULL);
1351 pthread_mutex_destroy(&sh->txpp.mutex);
1355 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1359 * Destroy table hash list.
1362 * Pointer to the private device data structure.
1365 mlx5_free_table_hash_list(struct mlx5_priv *priv)
1367 struct mlx5_dev_ctx_shared *sh = priv->sh;
1371 mlx5_hlist_destroy(sh->flow_tbls);
1375 * Initialize flow table hash list and create the root tables entry
1379 * Pointer to the private device data structure.
1382 * Zero on success, positive error code otherwise.
1385 mlx5_alloc_table_hash_list(struct mlx5_priv *priv __rte_unused)
1388 /* Tables are only used in DV and DR modes. */
1389 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
1390 struct mlx5_dev_ctx_shared *sh = priv->sh;
1391 char s[MLX5_NAME_SIZE];
1394 snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1395 sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE,
1397 flow_dv_tbl_create_cb,
1398 flow_dv_tbl_match_cb,
1399 flow_dv_tbl_remove_cb,
1400 flow_dv_tbl_clone_cb,
1401 flow_dv_tbl_clone_free_cb);
1402 if (!sh->flow_tbls) {
1403 DRV_LOG(ERR, "flow tables with hash creation failed.");
1407 #ifndef HAVE_MLX5DV_DR
1408 struct rte_flow_error error;
1409 struct rte_eth_dev *dev = &rte_eth_devices[priv->dev_data->port_id];
1412 * In case we have not DR support, the zero tables should be created
1413 * because DV expect to see them even if they cannot be created by
1416 if (!flow_dv_tbl_resource_get(dev, 0, 0, 0, 0,
1417 NULL, 0, 1, 0, &error) ||
1418 !flow_dv_tbl_resource_get(dev, 0, 1, 0, 0,
1419 NULL, 0, 1, 0, &error) ||
1420 !flow_dv_tbl_resource_get(dev, 0, 0, 1, 0,
1421 NULL, 0, 1, 0, &error)) {
1427 mlx5_free_table_hash_list(priv);
1428 #endif /* HAVE_MLX5DV_DR */
1434 * Retrieve integer value from environment variable.
1437 * Environment variable name.
1440 * Integer value, 0 if the variable is not set.
1443 mlx5_getenv_int(const char *name)
1445 const char *val = getenv(name);
1453 * DPDK callback to add udp tunnel port
1456 * A pointer to eth_dev
1457 * @param[in] udp_tunnel
1458 * A pointer to udp tunnel
1461 * 0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1464 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1465 struct rte_eth_udp_tunnel *udp_tunnel)
1467 MLX5_ASSERT(udp_tunnel != NULL);
1468 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1469 udp_tunnel->udp_port == 4789)
1471 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1472 udp_tunnel->udp_port == 4790)
1478 * Initialize process private data structure.
1481 * Pointer to Ethernet device structure.
1484 * 0 on success, a negative errno value otherwise and rte_errno is set.
1487 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1489 struct mlx5_priv *priv = dev->data->dev_private;
1490 struct mlx5_proc_priv *ppriv;
1493 mlx5_proc_priv_uninit(dev);
1495 * UAR register table follows the process private structure. BlueFlame
1496 * registers for Tx queues are stored in the table.
1499 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1500 ppriv = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, ppriv_size,
1501 RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1506 ppriv->uar_table_sz = priv->txqs_n;
1507 dev->process_private = ppriv;
1512 * Un-initialize process private data structure.
1515 * Pointer to Ethernet device structure.
1518 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1520 if (!dev->process_private)
1522 mlx5_free(dev->process_private);
1523 dev->process_private = NULL;
1527 * DPDK callback to close the device.
1529 * Destroy all queues and objects, free memory.
1532 * Pointer to Ethernet device structure.
1535 mlx5_dev_close(struct rte_eth_dev *dev)
1537 struct mlx5_priv *priv = dev->data->dev_private;
1541 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1542 /* Check if process_private released. */
1543 if (!dev->process_private)
1545 mlx5_tx_uar_uninit_secondary(dev);
1546 mlx5_proc_priv_uninit(dev);
1547 rte_eth_dev_release_port(dev);
1552 DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1554 ((priv->sh->ctx != NULL) ?
1555 mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
1557 * If default mreg copy action is removed at the stop stage,
1558 * the search will return none and nothing will be done anymore.
1560 mlx5_flow_stop_default(dev);
1561 mlx5_traffic_disable(dev);
1563 * If all the flows are already flushed in the device stop stage,
1564 * then this will return directly without any action.
1566 mlx5_flow_list_flush(dev, MLX5_FLOW_TYPE_GEN, true);
1567 mlx5_action_handle_flush(dev);
1568 mlx5_flow_meter_flush(dev, NULL);
1569 /* Prevent crashes when queues are still in use. */
1570 dev->rx_pkt_burst = removed_rx_burst;
1571 dev->tx_pkt_burst = removed_tx_burst;
1573 /* Disable datapath on secondary process. */
1574 mlx5_mp_os_req_stop_rxtx(dev);
1575 /* Free the eCPRI flex parser resource. */
1576 mlx5_flex_parser_ecpri_release(dev);
1577 if (priv->rxqs != NULL) {
1578 /* XXX race condition if mlx5_rx_burst() is still running. */
1579 rte_delay_us_sleep(1000);
1580 for (i = 0; (i != priv->rxqs_n); ++i)
1581 mlx5_rxq_release(dev, i);
1585 if (priv->representor) {
1586 /* Each representor has a dedicated interrupts handler */
1587 mlx5_free(dev->intr_handle);
1588 dev->intr_handle = NULL;
1590 if (priv->txqs != NULL) {
1591 /* XXX race condition if mlx5_tx_burst() is still running. */
1592 rte_delay_us_sleep(1000);
1593 for (i = 0; (i != priv->txqs_n); ++i)
1594 mlx5_txq_release(dev, i);
1598 mlx5_proc_priv_uninit(dev);
1599 if (priv->q_counters) {
1600 mlx5_devx_cmd_destroy(priv->q_counters);
1601 priv->q_counters = NULL;
1603 if (priv->drop_queue.hrxq)
1604 mlx5_drop_action_destroy(dev);
1605 if (priv->mreg_cp_tbl)
1606 mlx5_hlist_destroy(priv->mreg_cp_tbl);
1607 mlx5_mprq_free_mp(dev);
1608 if (priv->sh->ct_mng)
1609 mlx5_flow_aso_ct_mng_close(priv->sh);
1610 mlx5_os_free_shared_dr(priv);
1611 if (priv->rss_conf.rss_key != NULL)
1612 mlx5_free(priv->rss_conf.rss_key);
1613 if (priv->reta_idx != NULL)
1614 mlx5_free(priv->reta_idx);
1615 if (priv->config.vf)
1616 mlx5_os_mac_addr_flush(dev);
1617 if (priv->nl_socket_route >= 0)
1618 close(priv->nl_socket_route);
1619 if (priv->nl_socket_rdma >= 0)
1620 close(priv->nl_socket_rdma);
1621 if (priv->vmwa_context)
1622 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1623 ret = mlx5_hrxq_verify(dev);
1625 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1626 dev->data->port_id);
1627 ret = mlx5_ind_table_obj_verify(dev);
1629 DRV_LOG(WARNING, "port %u some indirection table still remain",
1630 dev->data->port_id);
1631 ret = mlx5_rxq_obj_verify(dev);
1633 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1634 dev->data->port_id);
1635 ret = mlx5_rxq_verify(dev);
1637 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1638 dev->data->port_id);
1639 ret = mlx5_txq_obj_verify(dev);
1641 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1642 dev->data->port_id);
1643 ret = mlx5_txq_verify(dev);
1645 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1646 dev->data->port_id);
1647 ret = mlx5_flow_verify(dev);
1649 DRV_LOG(WARNING, "port %u some flows still remain",
1650 dev->data->port_id);
1652 mlx5_list_destroy(priv->hrxqs);
1654 * Free the shared context in last turn, because the cleanup
1655 * routines above may use some shared fields, like
1656 * mlx5_os_mac_addr_flush() uses ibdev_path for retrieveing
1657 * ifindex if Netlink fails.
1659 mlx5_free_shared_dev_ctx(priv->sh);
1660 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1664 MLX5_ETH_FOREACH_DEV(port_id, dev->device) {
1665 struct mlx5_priv *opriv =
1666 rte_eth_devices[port_id].data->dev_private;
1669 opriv->domain_id != priv->domain_id ||
1670 &rte_eth_devices[port_id] == dev)
1676 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1678 memset(priv, 0, sizeof(*priv));
1679 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1681 * Reset mac_addrs to NULL such that it is not freed as part of
1682 * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1683 * it is freed when dev_private is freed.
1685 dev->data->mac_addrs = NULL;
1689 const struct eth_dev_ops mlx5_dev_ops = {
1690 .dev_configure = mlx5_dev_configure,
1691 .dev_start = mlx5_dev_start,
1692 .dev_stop = mlx5_dev_stop,
1693 .dev_set_link_down = mlx5_set_link_down,
1694 .dev_set_link_up = mlx5_set_link_up,
1695 .dev_close = mlx5_dev_close,
1696 .promiscuous_enable = mlx5_promiscuous_enable,
1697 .promiscuous_disable = mlx5_promiscuous_disable,
1698 .allmulticast_enable = mlx5_allmulticast_enable,
1699 .allmulticast_disable = mlx5_allmulticast_disable,
1700 .link_update = mlx5_link_update,
1701 .stats_get = mlx5_stats_get,
1702 .stats_reset = mlx5_stats_reset,
1703 .xstats_get = mlx5_xstats_get,
1704 .xstats_reset = mlx5_xstats_reset,
1705 .xstats_get_names = mlx5_xstats_get_names,
1706 .fw_version_get = mlx5_fw_version_get,
1707 .dev_infos_get = mlx5_dev_infos_get,
1708 .representor_info_get = mlx5_representor_info_get,
1709 .read_clock = mlx5_txpp_read_clock,
1710 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1711 .vlan_filter_set = mlx5_vlan_filter_set,
1712 .rx_queue_setup = mlx5_rx_queue_setup,
1713 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1714 .tx_queue_setup = mlx5_tx_queue_setup,
1715 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1716 .rx_queue_release = mlx5_rx_queue_release,
1717 .tx_queue_release = mlx5_tx_queue_release,
1718 .rx_queue_start = mlx5_rx_queue_start,
1719 .rx_queue_stop = mlx5_rx_queue_stop,
1720 .tx_queue_start = mlx5_tx_queue_start,
1721 .tx_queue_stop = mlx5_tx_queue_stop,
1722 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1723 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1724 .mac_addr_remove = mlx5_mac_addr_remove,
1725 .mac_addr_add = mlx5_mac_addr_add,
1726 .mac_addr_set = mlx5_mac_addr_set,
1727 .set_mc_addr_list = mlx5_set_mc_addr_list,
1728 .mtu_set = mlx5_dev_set_mtu,
1729 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1730 .vlan_offload_set = mlx5_vlan_offload_set,
1731 .reta_update = mlx5_dev_rss_reta_update,
1732 .reta_query = mlx5_dev_rss_reta_query,
1733 .rss_hash_update = mlx5_rss_hash_update,
1734 .rss_hash_conf_get = mlx5_rss_hash_conf_get,
1735 .flow_ops_get = mlx5_flow_ops_get,
1736 .rxq_info_get = mlx5_rxq_info_get,
1737 .txq_info_get = mlx5_txq_info_get,
1738 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1739 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1740 .rx_queue_intr_enable = mlx5_rx_intr_enable,
1741 .rx_queue_intr_disable = mlx5_rx_intr_disable,
1742 .is_removed = mlx5_is_removed,
1743 .udp_tunnel_port_add = mlx5_udp_tunnel_port_add,
1744 .get_module_info = mlx5_get_module_info,
1745 .get_module_eeprom = mlx5_get_module_eeprom,
1746 .hairpin_cap_get = mlx5_hairpin_cap_get,
1747 .mtr_ops_get = mlx5_flow_meter_ops_get,
1748 .hairpin_bind = mlx5_hairpin_bind,
1749 .hairpin_unbind = mlx5_hairpin_unbind,
1750 .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1751 .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1752 .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1753 .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1754 .get_monitor_addr = mlx5_get_monitor_addr,
1757 /* Available operations from secondary process. */
1758 const struct eth_dev_ops mlx5_dev_sec_ops = {
1759 .stats_get = mlx5_stats_get,
1760 .stats_reset = mlx5_stats_reset,
1761 .xstats_get = mlx5_xstats_get,
1762 .xstats_reset = mlx5_xstats_reset,
1763 .xstats_get_names = mlx5_xstats_get_names,
1764 .fw_version_get = mlx5_fw_version_get,
1765 .dev_infos_get = mlx5_dev_infos_get,
1766 .representor_info_get = mlx5_representor_info_get,
1767 .read_clock = mlx5_txpp_read_clock,
1768 .rx_queue_start = mlx5_rx_queue_start,
1769 .rx_queue_stop = mlx5_rx_queue_stop,
1770 .tx_queue_start = mlx5_tx_queue_start,
1771 .tx_queue_stop = mlx5_tx_queue_stop,
1772 .rxq_info_get = mlx5_rxq_info_get,
1773 .txq_info_get = mlx5_txq_info_get,
1774 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1775 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1776 .get_module_info = mlx5_get_module_info,
1777 .get_module_eeprom = mlx5_get_module_eeprom,
1780 /* Available operations in flow isolated mode. */
1781 const struct eth_dev_ops mlx5_dev_ops_isolate = {
1782 .dev_configure = mlx5_dev_configure,
1783 .dev_start = mlx5_dev_start,
1784 .dev_stop = mlx5_dev_stop,
1785 .dev_set_link_down = mlx5_set_link_down,
1786 .dev_set_link_up = mlx5_set_link_up,
1787 .dev_close = mlx5_dev_close,
1788 .promiscuous_enable = mlx5_promiscuous_enable,
1789 .promiscuous_disable = mlx5_promiscuous_disable,
1790 .allmulticast_enable = mlx5_allmulticast_enable,
1791 .allmulticast_disable = mlx5_allmulticast_disable,
1792 .link_update = mlx5_link_update,
1793 .stats_get = mlx5_stats_get,
1794 .stats_reset = mlx5_stats_reset,
1795 .xstats_get = mlx5_xstats_get,
1796 .xstats_reset = mlx5_xstats_reset,
1797 .xstats_get_names = mlx5_xstats_get_names,
1798 .fw_version_get = mlx5_fw_version_get,
1799 .dev_infos_get = mlx5_dev_infos_get,
1800 .representor_info_get = mlx5_representor_info_get,
1801 .read_clock = mlx5_txpp_read_clock,
1802 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1803 .vlan_filter_set = mlx5_vlan_filter_set,
1804 .rx_queue_setup = mlx5_rx_queue_setup,
1805 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1806 .tx_queue_setup = mlx5_tx_queue_setup,
1807 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1808 .rx_queue_release = mlx5_rx_queue_release,
1809 .tx_queue_release = mlx5_tx_queue_release,
1810 .rx_queue_start = mlx5_rx_queue_start,
1811 .rx_queue_stop = mlx5_rx_queue_stop,
1812 .tx_queue_start = mlx5_tx_queue_start,
1813 .tx_queue_stop = mlx5_tx_queue_stop,
1814 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1815 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1816 .mac_addr_remove = mlx5_mac_addr_remove,
1817 .mac_addr_add = mlx5_mac_addr_add,
1818 .mac_addr_set = mlx5_mac_addr_set,
1819 .set_mc_addr_list = mlx5_set_mc_addr_list,
1820 .mtu_set = mlx5_dev_set_mtu,
1821 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1822 .vlan_offload_set = mlx5_vlan_offload_set,
1823 .flow_ops_get = mlx5_flow_ops_get,
1824 .rxq_info_get = mlx5_rxq_info_get,
1825 .txq_info_get = mlx5_txq_info_get,
1826 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1827 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1828 .rx_queue_intr_enable = mlx5_rx_intr_enable,
1829 .rx_queue_intr_disable = mlx5_rx_intr_disable,
1830 .is_removed = mlx5_is_removed,
1831 .get_module_info = mlx5_get_module_info,
1832 .get_module_eeprom = mlx5_get_module_eeprom,
1833 .hairpin_cap_get = mlx5_hairpin_cap_get,
1834 .mtr_ops_get = mlx5_flow_meter_ops_get,
1835 .hairpin_bind = mlx5_hairpin_bind,
1836 .hairpin_unbind = mlx5_hairpin_unbind,
1837 .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1838 .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1839 .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1840 .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1841 .get_monitor_addr = mlx5_get_monitor_addr,
1845 * Verify and store value for device argument.
1848 * Key argument to verify.
1850 * Value associated with key.
1855 * 0 on success, a negative errno value otherwise and rte_errno is set.
1858 mlx5_args_check(const char *key, const char *val, void *opaque)
1860 struct mlx5_dev_config *config = opaque;
1864 /* No-op, port representors are processed in mlx5_dev_spawn(). */
1865 if (!strcmp(MLX5_REPRESENTOR, key))
1868 tmp = strtol(val, NULL, 0);
1871 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1874 if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
1875 /* Negative values are acceptable for some keys only. */
1877 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
1880 mod = tmp >= 0 ? tmp : -tmp;
1881 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1882 if (tmp > MLX5_CQE_RESP_FORMAT_L34H_STRIDX) {
1883 DRV_LOG(ERR, "invalid CQE compression "
1884 "format parameter");
1888 config->cqe_comp = !!tmp;
1889 config->cqe_comp_fmt = tmp;
1890 } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1891 config->hw_padding = !!tmp;
1892 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1893 config->mprq.enabled = !!tmp;
1894 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1895 config->mprq.stride_num_n = tmp;
1896 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1897 config->mprq.stride_size_n = tmp;
1898 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1899 config->mprq.max_memcpy_len = tmp;
1900 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1901 config->mprq.min_rxqs_num = tmp;
1902 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1903 DRV_LOG(WARNING, "%s: deprecated parameter,"
1904 " converted to txq_inline_max", key);
1905 config->txq_inline_max = tmp;
1906 } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1907 config->txq_inline_max = tmp;
1908 } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1909 config->txq_inline_min = tmp;
1910 } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1911 config->txq_inline_mpw = tmp;
1912 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1913 config->txqs_inline = tmp;
1914 } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1915 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1916 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1917 config->mps = !!tmp;
1918 } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1919 if (tmp != MLX5_TXDB_CACHED &&
1920 tmp != MLX5_TXDB_NCACHED &&
1921 tmp != MLX5_TXDB_HEURISTIC) {
1922 DRV_LOG(ERR, "invalid Tx doorbell "
1923 "mapping parameter");
1928 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1929 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1930 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1931 DRV_LOG(WARNING, "%s: deprecated parameter,"
1932 " converted to txq_inline_mpw", key);
1933 config->txq_inline_mpw = tmp;
1934 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1935 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1936 } else if (strcmp(MLX5_TX_PP, key) == 0) {
1938 DRV_LOG(ERR, "Zero Tx packet pacing parameter");
1942 config->tx_pp = tmp;
1943 } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
1944 config->tx_skew = tmp;
1945 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1946 config->rx_vec_en = !!tmp;
1947 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1948 config->l3_vxlan_en = !!tmp;
1949 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1950 config->vf_nl_en = !!tmp;
1951 } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1952 config->dv_esw_en = !!tmp;
1953 } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1954 config->dv_flow_en = !!tmp;
1955 } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1956 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1957 tmp != MLX5_XMETA_MODE_META16 &&
1958 tmp != MLX5_XMETA_MODE_META32 &&
1959 tmp != MLX5_XMETA_MODE_MISS_INFO) {
1960 DRV_LOG(ERR, "invalid extensive "
1961 "metadata parameter");
1965 if (tmp != MLX5_XMETA_MODE_MISS_INFO)
1966 config->dv_xmeta_en = tmp;
1968 config->dv_miss_info = 1;
1969 } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
1970 config->lacp_by_user = !!tmp;
1971 } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1972 config->mr_ext_memseg_en = !!tmp;
1973 } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1974 config->max_dump_files_num = tmp;
1975 } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1976 config->lro.timeout = tmp;
1977 } else if (strcmp(RTE_DEVARGS_KEY_CLASS, key) == 0) {
1978 DRV_LOG(DEBUG, "class argument is %s.", val);
1979 } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1980 config->log_hp_size = tmp;
1981 } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1982 if (tmp != MLX5_RCM_NONE &&
1983 tmp != MLX5_RCM_LIGHT &&
1984 tmp != MLX5_RCM_AGGR) {
1985 DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1989 config->reclaim_mode = tmp;
1990 } else if (strcmp(MLX5_SYS_MEM_EN, key) == 0) {
1991 config->sys_mem_en = !!tmp;
1992 } else if (strcmp(MLX5_DECAP_EN, key) == 0) {
1993 config->decap_en = !!tmp;
1994 } else if (strcmp(MLX5_ALLOW_DUPLICATE_PATTERN, key) == 0) {
1995 config->allow_duplicate_pattern = !!tmp;
1997 DRV_LOG(WARNING, "%s: unknown parameter", key);
2005 * Parse device parameters.
2008 * Pointer to device configuration structure.
2010 * Device arguments structure.
2013 * 0 on success, a negative errno value otherwise and rte_errno is set.
2016 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
2018 const char **params = (const char *[]){
2019 MLX5_RXQ_CQE_COMP_EN,
2020 MLX5_RXQ_PKT_PAD_EN,
2022 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
2023 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
2024 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
2027 MLX5_TXQ_INLINE_MIN,
2028 MLX5_TXQ_INLINE_MAX,
2029 MLX5_TXQ_INLINE_MPW,
2030 MLX5_TXQS_MIN_INLINE,
2033 MLX5_TXQ_MPW_HDR_DSEG_EN,
2034 MLX5_TXQ_MAX_INLINE_LEN,
2046 MLX5_MR_EXT_MEMSEG_EN,
2048 MLX5_MAX_DUMP_FILES_NUM,
2049 MLX5_LRO_TIMEOUT_USEC,
2050 RTE_DEVARGS_KEY_CLASS,
2055 MLX5_ALLOW_DUPLICATE_PATTERN,
2058 struct rte_kvargs *kvlist;
2062 if (devargs == NULL)
2064 /* Following UGLY cast is done to pass checkpatch. */
2065 kvlist = rte_kvargs_parse(devargs->args, params);
2066 if (kvlist == NULL) {
2070 /* Process parameters. */
2071 for (i = 0; (params[i] != NULL); ++i) {
2072 if (rte_kvargs_count(kvlist, params[i])) {
2073 ret = rte_kvargs_process(kvlist, params[i],
2074 mlx5_args_check, config);
2077 rte_kvargs_free(kvlist);
2082 rte_kvargs_free(kvlist);
2087 * Configures the minimal amount of data to inline into WQE
2088 * while sending packets.
2090 * - the txq_inline_min has the maximal priority, if this
2091 * key is specified in devargs
2092 * - if DevX is enabled the inline mode is queried from the
2093 * device (HCA attributes and NIC vport context if needed).
2094 * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
2095 * and none (0 bytes) for other NICs
2098 * Verbs device parameters (name, port, switch_info) to spawn.
2100 * Device configuration parameters.
2103 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
2104 struct mlx5_dev_config *config)
2106 if (config->txq_inline_min != MLX5_ARG_UNSET) {
2107 /* Application defines size of inlined data explicitly. */
2108 if (spawn->pci_dev != NULL) {
2109 switch (spawn->pci_dev->id.device_id) {
2110 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2111 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2112 if (config->txq_inline_min <
2113 (int)MLX5_INLINE_HSIZE_L2) {
2115 "txq_inline_mix aligned to minimal ConnectX-4 required value %d",
2116 (int)MLX5_INLINE_HSIZE_L2);
2117 config->txq_inline_min =
2118 MLX5_INLINE_HSIZE_L2;
2125 if (config->hca_attr.eth_net_offloads) {
2126 /* We have DevX enabled, inline mode queried successfully. */
2127 switch (config->hca_attr.wqe_inline_mode) {
2128 case MLX5_CAP_INLINE_MODE_L2:
2129 /* outer L2 header must be inlined. */
2130 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2132 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
2133 /* No inline data are required by NIC. */
2134 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2135 config->hw_vlan_insert =
2136 config->hca_attr.wqe_vlan_insert;
2137 DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
2139 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
2140 /* inline mode is defined by NIC vport context. */
2141 if (!config->hca_attr.eth_virt)
2143 switch (config->hca_attr.vport_inline_mode) {
2144 case MLX5_INLINE_MODE_NONE:
2145 config->txq_inline_min =
2146 MLX5_INLINE_HSIZE_NONE;
2148 case MLX5_INLINE_MODE_L2:
2149 config->txq_inline_min =
2150 MLX5_INLINE_HSIZE_L2;
2152 case MLX5_INLINE_MODE_IP:
2153 config->txq_inline_min =
2154 MLX5_INLINE_HSIZE_L3;
2156 case MLX5_INLINE_MODE_TCP_UDP:
2157 config->txq_inline_min =
2158 MLX5_INLINE_HSIZE_L4;
2160 case MLX5_INLINE_MODE_INNER_L2:
2161 config->txq_inline_min =
2162 MLX5_INLINE_HSIZE_INNER_L2;
2164 case MLX5_INLINE_MODE_INNER_IP:
2165 config->txq_inline_min =
2166 MLX5_INLINE_HSIZE_INNER_L3;
2168 case MLX5_INLINE_MODE_INNER_TCP_UDP:
2169 config->txq_inline_min =
2170 MLX5_INLINE_HSIZE_INNER_L4;
2175 if (spawn->pci_dev == NULL) {
2176 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2180 * We get here if we are unable to deduce
2181 * inline data size with DevX. Try PCI ID
2182 * to determine old NICs.
2184 switch (spawn->pci_dev->id.device_id) {
2185 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2186 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2187 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
2188 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
2189 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2190 config->hw_vlan_insert = 0;
2192 case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
2193 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
2194 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
2195 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
2197 * These NICs support VLAN insertion from WQE and
2198 * report the wqe_vlan_insert flag. But there is the bug
2199 * and PFC control may be broken, so disable feature.
2201 config->hw_vlan_insert = 0;
2202 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2205 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2209 DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
2213 * Configures the metadata mask fields in the shared context.
2216 * Pointer to Ethernet device.
2219 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
2221 struct mlx5_priv *priv = dev->data->dev_private;
2222 struct mlx5_dev_ctx_shared *sh = priv->sh;
2223 uint32_t meta, mark, reg_c0;
2225 reg_c0 = ~priv->vport_meta_mask;
2226 switch (priv->config.dv_xmeta_en) {
2227 case MLX5_XMETA_MODE_LEGACY:
2229 mark = MLX5_FLOW_MARK_MASK;
2231 case MLX5_XMETA_MODE_META16:
2232 meta = reg_c0 >> rte_bsf32(reg_c0);
2233 mark = MLX5_FLOW_MARK_MASK;
2235 case MLX5_XMETA_MODE_META32:
2237 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
2245 if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
2246 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
2247 sh->dv_mark_mask, mark);
2249 sh->dv_mark_mask = mark;
2250 if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
2251 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
2252 sh->dv_meta_mask, meta);
2254 sh->dv_meta_mask = meta;
2255 if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
2256 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
2257 sh->dv_meta_mask, reg_c0);
2259 sh->dv_regc0_mask = reg_c0;
2260 DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
2261 DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
2262 DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
2263 DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
2267 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
2269 static const char *const dynf_names[] = {
2270 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
2271 RTE_MBUF_DYNFLAG_METADATA_NAME,
2272 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
2276 if (n < RTE_DIM(dynf_names))
2278 for (i = 0; i < RTE_DIM(dynf_names); i++) {
2279 if (names[i] == NULL)
2281 strcpy(names[i], dynf_names[i]);
2283 return RTE_DIM(dynf_names);
2287 * Comparison callback to sort device data.
2289 * This is meant to be used with qsort().
2292 * Pointer to pointer to first data object.
2294 * Pointer to pointer to second data object.
2297 * 0 if both objects are equal, less than 0 if the first argument is less
2298 * than the second, greater than 0 otherwise.
2301 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
2302 struct mlx5_dev_config *config,
2303 struct rte_device *dpdk_dev)
2305 struct mlx5_dev_ctx_shared *sh = priv->sh;
2306 struct mlx5_dev_config *sh_conf = NULL;
2310 /* Nothing to compare for the single/first device. */
2311 if (sh->refcnt == 1)
2313 /* Find the device with shared context. */
2314 MLX5_ETH_FOREACH_DEV(port_id, dpdk_dev) {
2315 struct mlx5_priv *opriv =
2316 rte_eth_devices[port_id].data->dev_private;
2318 if (opriv && opriv != priv && opriv->sh == sh) {
2319 sh_conf = &opriv->config;
2325 if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
2326 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
2327 " for shared %s context", sh->ibdev_name);
2331 if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
2332 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
2333 " for shared %s context", sh->ibdev_name);
2341 * Look for the ethernet device belonging to mlx5 driver.
2343 * @param[in] port_id
2344 * port_id to start looking for device.
2346 * Pointer to the hint device. When device is being probed
2347 * the its siblings (master and preceding representors might
2348 * not have assigned driver yet (because the mlx5_os_pci_probe()
2349 * is not completed yet, for this case match on hint
2350 * device may be used to detect sibling device.
2353 * port_id of found device, RTE_MAX_ETHPORT if not found.
2356 mlx5_eth_find_next(uint16_t port_id, struct rte_device *odev)
2358 while (port_id < RTE_MAX_ETHPORTS) {
2359 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
2361 if (dev->state != RTE_ETH_DEV_UNUSED &&
2363 (dev->device == odev ||
2364 (dev->device->driver &&
2365 dev->device->driver->name &&
2366 ((strcmp(dev->device->driver->name,
2367 MLX5_PCI_DRIVER_NAME) == 0) ||
2368 (strcmp(dev->device->driver->name,
2369 MLX5_AUXILIARY_DRIVER_NAME) == 0)))))
2373 if (port_id >= RTE_MAX_ETHPORTS)
2374 return RTE_MAX_ETHPORTS;
2379 * Callback to remove a device.
2381 * This function removes all Ethernet devices belong to a given device.
2384 * Pointer to the generic device.
2387 * 0 on success, the function cannot fail.
2390 mlx5_net_remove(struct rte_device *dev)
2395 RTE_ETH_FOREACH_DEV_OF(port_id, dev) {
2397 * mlx5_dev_close() is not registered to secondary process,
2398 * call the close function explicitly for secondary process.
2400 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
2401 ret |= mlx5_dev_close(&rte_eth_devices[port_id]);
2403 ret |= rte_eth_dev_close(port_id);
2405 return ret == 0 ? 0 : -EIO;
2408 static const struct rte_pci_id mlx5_pci_id_map[] = {
2410 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2411 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
2414 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2415 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
2418 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2419 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
2422 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2423 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
2426 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2427 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
2430 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2431 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
2434 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2435 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
2438 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2439 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
2442 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2443 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
2446 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2447 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
2450 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2451 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
2454 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2455 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
2458 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2459 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
2462 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2463 PCI_DEVICE_ID_MELLANOX_CONNECTXVF)
2466 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2467 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
2470 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2471 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
2474 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2475 PCI_DEVICE_ID_MELLANOX_CONNECTX7)
2478 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2479 PCI_DEVICE_ID_MELLANOX_CONNECTX7BF)
2486 static struct mlx5_class_driver mlx5_net_driver = {
2487 .drv_class = MLX5_CLASS_ETH,
2488 .name = RTE_STR(MLX5_ETH_DRIVER_NAME),
2489 .id_table = mlx5_pci_id_map,
2490 .probe = mlx5_os_net_probe,
2491 .remove = mlx5_net_remove,
2492 .dma_map = mlx5_net_dma_map,
2493 .dma_unmap = mlx5_net_dma_unmap,
2499 /* Initialize driver log type. */
2500 RTE_LOG_REGISTER_DEFAULT(mlx5_logtype, NOTICE)
2503 * Driver initialization routine.
2505 RTE_INIT(rte_mlx5_pmd_init)
2507 pthread_mutex_init(&mlx5_dev_ctx_list_mutex, NULL);
2509 /* Build the static tables for Verbs conversion. */
2510 mlx5_set_ptype_table();
2511 mlx5_set_cksum_table();
2512 mlx5_set_swp_types_table();
2514 mlx5_class_driver_register(&mlx5_net_driver);
2517 RTE_PMD_EXPORT_NAME(MLX5_ETH_DRIVER_NAME, __COUNTER__);
2518 RTE_PMD_REGISTER_PCI_TABLE(MLX5_ETH_DRIVER_NAME, mlx5_pci_id_map);
2519 RTE_PMD_REGISTER_KMOD_DEP(MLX5_ETH_DRIVER_NAME, "* ib_uverbs & mlx5_core & mlx5_ib");