1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
13 #include <rte_malloc.h>
14 #include <ethdev_driver.h>
16 #include <rte_bus_pci.h>
17 #include <rte_common.h>
18 #include <rte_kvargs.h>
19 #include <rte_rwlock.h>
20 #include <rte_spinlock.h>
21 #include <rte_string_fns.h>
22 #include <rte_eal_paging.h>
23 #include <rte_alarm.h>
24 #include <rte_cycles.h>
26 #include <mlx5_glue.h>
27 #include <mlx5_devx_cmds.h>
28 #include <mlx5_common.h>
29 #include <mlx5_common_os.h>
30 #include <mlx5_common_mp.h>
31 #include <mlx5_malloc.h>
33 #include "mlx5_defs.h"
35 #include "mlx5_utils.h"
36 #include "mlx5_rxtx.h"
39 #include "mlx5_autoconf.h"
40 #include "mlx5_flow.h"
41 #include "mlx5_flow_os.h"
42 #include "rte_pmd_mlx5.h"
44 #define MLX5_ETH_DRIVER_NAME mlx5_eth
46 /* Driver type key for new device global syntax. */
47 #define MLX5_DRIVER_KEY "driver"
49 /* Device parameter to enable RX completion queue compression. */
50 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
52 /* Device parameter to enable padding Rx packet to cacheline size. */
53 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
55 /* Device parameter to enable Multi-Packet Rx queue. */
56 #define MLX5_RX_MPRQ_EN "mprq_en"
58 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
59 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
61 /* Device parameter to configure log 2 of the stride size for MPRQ. */
62 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
64 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
65 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
67 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
68 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
70 /* Device parameter to configure inline send. Deprecated, ignored.*/
71 #define MLX5_TXQ_INLINE "txq_inline"
73 /* Device parameter to limit packet size to inline with ordinary SEND. */
74 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
76 /* Device parameter to configure minimal data size to inline. */
77 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
79 /* Device parameter to limit packet size to inline with Enhanced MPW. */
80 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
83 * Device parameter to configure the number of TX queues threshold for
84 * enabling inline send.
86 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
89 * Device parameter to configure the number of TX queues threshold for
90 * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
92 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
94 /* Device parameter to enable multi-packet send WQEs. */
95 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
98 * Device parameter to force doorbell register mapping
99 * to non-cahed region eliminating the extra write memory barrier.
101 #define MLX5_TX_DB_NC "tx_db_nc"
104 * Device parameter to include 2 dsegs in the title WQEBB.
105 * Deprecated, ignored.
107 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
110 * Device parameter to limit the size of inlining packet.
111 * Deprecated, ignored.
113 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
116 * Device parameter to enable Tx scheduling on timestamps
117 * and specify the packet pacing granularity in nanoseconds.
119 #define MLX5_TX_PP "tx_pp"
122 * Device parameter to specify skew in nanoseconds on Tx datapath,
123 * it represents the time between SQ start WQE processing and
124 * appearing actual packet data on the wire.
126 #define MLX5_TX_SKEW "tx_skew"
129 * Device parameter to enable hardware Tx vector.
130 * Deprecated, ignored (no vectorized Tx routines anymore).
132 #define MLX5_TX_VEC_EN "tx_vec_en"
134 /* Device parameter to enable hardware Rx vector. */
135 #define MLX5_RX_VEC_EN "rx_vec_en"
137 /* Allow L3 VXLAN flow creation. */
138 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
140 /* Activate DV E-Switch flow steering. */
141 #define MLX5_DV_ESW_EN "dv_esw_en"
143 /* Activate DV flow steering. */
144 #define MLX5_DV_FLOW_EN "dv_flow_en"
146 /* Enable extensive flow metadata support. */
147 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
149 /* Device parameter to let the user manage the lacp traffic of bonded device */
150 #define MLX5_LACP_BY_USER "lacp_by_user"
152 /* Activate Netlink support in VF mode. */
153 #define MLX5_VF_NL_EN "vf_nl_en"
155 /* Enable extending memsegs when creating a MR. */
156 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
158 /* Select port representors to instantiate. */
159 #define MLX5_REPRESENTOR "representor"
161 /* Device parameter to configure the maximum number of dump files per queue. */
162 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
164 /* Configure timeout of LRO session (in microseconds). */
165 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
168 * Device parameter to configure the total data buffer size for a single
169 * hairpin queue (logarithm value).
171 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
173 /* Flow memory reclaim mode. */
174 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
176 /* The default memory allocator used in PMD. */
177 #define MLX5_SYS_MEM_EN "sys_mem_en"
178 /* Decap will be used or not. */
179 #define MLX5_DECAP_EN "decap_en"
181 /* Device parameter to configure allow or prevent duplicate rules pattern. */
182 #define MLX5_ALLOW_DUPLICATE_PATTERN "allow_duplicate_pattern"
184 /* Device parameter to configure implicit registration of mempool memory. */
185 #define MLX5_MR_MEMPOOL_REG_EN "mr_mempool_reg_en"
187 /* Device parameter to configure the delay drop when creating Rxqs. */
188 #define MLX5_DELAY_DROP "delay_drop"
190 /* Shared memory between primary and secondary processes. */
191 struct mlx5_shared_data *mlx5_shared_data;
193 /** Driver-specific log messages type. */
196 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
197 LIST_HEAD_INITIALIZER();
198 static pthread_mutex_t mlx5_dev_ctx_list_mutex;
199 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
200 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
201 [MLX5_IPOOL_DECAP_ENCAP] = {
202 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
208 .malloc = mlx5_malloc,
210 .type = "mlx5_encap_decap_ipool",
212 [MLX5_IPOOL_PUSH_VLAN] = {
213 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
219 .malloc = mlx5_malloc,
221 .type = "mlx5_push_vlan_ipool",
224 .size = sizeof(struct mlx5_flow_dv_tag_resource),
230 .per_core_cache = (1 << 16),
231 .malloc = mlx5_malloc,
233 .type = "mlx5_tag_ipool",
235 [MLX5_IPOOL_PORT_ID] = {
236 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
242 .malloc = mlx5_malloc,
244 .type = "mlx5_port_id_ipool",
246 [MLX5_IPOOL_JUMP] = {
247 .size = sizeof(struct mlx5_flow_tbl_data_entry),
253 .malloc = mlx5_malloc,
255 .type = "mlx5_jump_ipool",
257 [MLX5_IPOOL_SAMPLE] = {
258 .size = sizeof(struct mlx5_flow_dv_sample_resource),
264 .malloc = mlx5_malloc,
266 .type = "mlx5_sample_ipool",
268 [MLX5_IPOOL_DEST_ARRAY] = {
269 .size = sizeof(struct mlx5_flow_dv_dest_array_resource),
275 .malloc = mlx5_malloc,
277 .type = "mlx5_dest_array_ipool",
279 [MLX5_IPOOL_TUNNEL_ID] = {
280 .size = sizeof(struct mlx5_flow_tunnel),
281 .trunk_size = MLX5_MAX_TUNNELS,
284 .type = "mlx5_tunnel_offload",
286 [MLX5_IPOOL_TNL_TBL_ID] = {
289 .type = "mlx5_flow_tnl_tbl_ipool",
294 * The ipool index should grow continually from small to big,
295 * for meter idx, so not set grow_trunk to avoid meter index
296 * not jump continually.
298 .size = sizeof(struct mlx5_legacy_flow_meter),
302 .malloc = mlx5_malloc,
304 .type = "mlx5_meter_ipool",
307 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
313 .malloc = mlx5_malloc,
315 .type = "mlx5_mcp_ipool",
317 [MLX5_IPOOL_HRXQ] = {
318 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
324 .malloc = mlx5_malloc,
326 .type = "mlx5_hrxq_ipool",
328 [MLX5_IPOOL_MLX5_FLOW] = {
330 * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
331 * It set in run time according to PCI function configuration.
339 .per_core_cache = 1 << 19,
340 .malloc = mlx5_malloc,
342 .type = "mlx5_flow_handle_ipool",
344 [MLX5_IPOOL_RTE_FLOW] = {
345 .size = sizeof(struct rte_flow),
349 .malloc = mlx5_malloc,
351 .type = "rte_flow_ipool",
353 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID] = {
356 .type = "mlx5_flow_rss_id_ipool",
358 [MLX5_IPOOL_RSS_SHARED_ACTIONS] = {
359 .size = sizeof(struct mlx5_shared_action_rss),
365 .malloc = mlx5_malloc,
367 .type = "mlx5_shared_action_rss",
369 [MLX5_IPOOL_MTR_POLICY] = {
371 * The ipool index should grow continually from small to big,
372 * for policy idx, so not set grow_trunk to avoid policy index
373 * not jump continually.
375 .size = sizeof(struct mlx5_flow_meter_sub_policy),
379 .malloc = mlx5_malloc,
381 .type = "mlx5_meter_policy_ipool",
385 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
386 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
388 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 1024
391 * Decide whether representor ID is a HPF(host PF) port on BF2.
394 * Pointer to Ethernet device structure.
397 * Non-zero if HPF, otherwise 0.
400 mlx5_is_hpf(struct rte_eth_dev *dev)
402 struct mlx5_priv *priv = dev->data->dev_private;
403 uint16_t repr = MLX5_REPRESENTOR_REPR(priv->representor_id);
404 int type = MLX5_REPRESENTOR_TYPE(priv->representor_id);
406 return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_VF &&
407 MLX5_REPRESENTOR_REPR(-1) == repr;
411 * Decide whether representor ID is a SF port representor.
414 * Pointer to Ethernet device structure.
417 * Non-zero if HPF, otherwise 0.
420 mlx5_is_sf_repr(struct rte_eth_dev *dev)
422 struct mlx5_priv *priv = dev->data->dev_private;
423 int type = MLX5_REPRESENTOR_TYPE(priv->representor_id);
425 return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_SF;
429 * Initialize the ASO aging management structure.
432 * Pointer to mlx5_dev_ctx_shared object to free
435 * 0 on success, a negative errno value otherwise and rte_errno is set.
438 mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh)
444 sh->aso_age_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->aso_age_mng),
445 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
446 if (!sh->aso_age_mng) {
447 DRV_LOG(ERR, "aso_age_mng allocation was failed.");
451 err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_FLOW_HIT);
453 mlx5_free(sh->aso_age_mng);
456 rte_rwlock_init(&sh->aso_age_mng->resize_rwl);
457 rte_spinlock_init(&sh->aso_age_mng->free_sl);
458 LIST_INIT(&sh->aso_age_mng->free);
463 * Close and release all the resources of the ASO aging management structure.
466 * Pointer to mlx5_dev_ctx_shared object to free.
469 mlx5_flow_aso_age_mng_close(struct mlx5_dev_ctx_shared *sh)
473 mlx5_aso_flow_hit_queue_poll_stop(sh);
474 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_FLOW_HIT);
475 if (sh->aso_age_mng->pools) {
476 struct mlx5_aso_age_pool *pool;
478 for (i = 0; i < sh->aso_age_mng->next; ++i) {
479 pool = sh->aso_age_mng->pools[i];
480 claim_zero(mlx5_devx_cmd_destroy
481 (pool->flow_hit_aso_obj));
482 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j)
483 if (pool->actions[j].dr_action)
485 (mlx5_flow_os_destroy_flow_action
486 (pool->actions[j].dr_action));
489 mlx5_free(sh->aso_age_mng->pools);
491 mlx5_free(sh->aso_age_mng);
495 * Initialize the shared aging list information per port.
498 * Pointer to mlx5_dev_ctx_shared object.
501 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
504 struct mlx5_age_info *age_info;
506 for (i = 0; i < sh->max_port; i++) {
507 age_info = &sh->port[i].age_info;
509 TAILQ_INIT(&age_info->aged_counters);
510 LIST_INIT(&age_info->aged_aso);
511 rte_spinlock_init(&age_info->aged_sl);
512 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
517 * Initialize the counters management structure.
520 * Pointer to mlx5_dev_ctx_shared object to free
523 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
527 memset(&sh->cmng, 0, sizeof(sh->cmng));
528 TAILQ_INIT(&sh->cmng.flow_counters);
529 sh->cmng.min_id = MLX5_CNT_BATCH_OFFSET;
530 sh->cmng.max_id = -1;
531 sh->cmng.last_pool_idx = POOL_IDX_INVALID;
532 rte_spinlock_init(&sh->cmng.pool_update_sl);
533 for (i = 0; i < MLX5_COUNTER_TYPE_MAX; i++) {
534 TAILQ_INIT(&sh->cmng.counters[i]);
535 rte_spinlock_init(&sh->cmng.csl[i]);
540 * Destroy all the resources allocated for a counter memory management.
543 * Pointer to the memory management structure.
546 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
548 uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
550 LIST_REMOVE(mng, next);
551 mlx5_os_wrapped_mkey_destroy(&mng->wm);
556 * Close and release all the resources of the counters management.
559 * Pointer to mlx5_dev_ctx_shared object to free.
562 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
564 struct mlx5_counter_stats_mem_mng *mng;
570 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
571 if (rte_errno != EINPROGRESS)
576 if (sh->cmng.pools) {
577 struct mlx5_flow_counter_pool *pool;
578 uint16_t n_valid = sh->cmng.n_valid;
579 bool fallback = sh->cmng.counter_fallback;
581 for (i = 0; i < n_valid; ++i) {
582 pool = sh->cmng.pools[i];
583 if (!fallback && pool->min_dcs)
584 claim_zero(mlx5_devx_cmd_destroy
586 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
587 struct mlx5_flow_counter *cnt =
588 MLX5_POOL_GET_CNT(pool, j);
592 (mlx5_flow_os_destroy_flow_action
594 if (fallback && MLX5_POOL_GET_CNT
595 (pool, j)->dcs_when_free)
596 claim_zero(mlx5_devx_cmd_destroy
597 (cnt->dcs_when_free));
601 mlx5_free(sh->cmng.pools);
603 mng = LIST_FIRST(&sh->cmng.mem_mngs);
605 mlx5_flow_destroy_counter_stat_mem_mng(mng);
606 mng = LIST_FIRST(&sh->cmng.mem_mngs);
608 memset(&sh->cmng, 0, sizeof(sh->cmng));
612 * Initialize the aso flow meters management structure.
615 * Pointer to mlx5_dev_ctx_shared object to free
618 mlx5_aso_flow_mtrs_mng_init(struct mlx5_dev_ctx_shared *sh)
621 sh->mtrmng = mlx5_malloc(MLX5_MEM_ZERO,
623 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
626 "meter management allocation was failed.");
630 if (sh->meter_aso_en) {
631 rte_spinlock_init(&sh->mtrmng->pools_mng.mtrsl);
632 rte_rwlock_init(&sh->mtrmng->pools_mng.resize_mtrwl);
633 LIST_INIT(&sh->mtrmng->pools_mng.meters);
635 sh->mtrmng->def_policy_id = MLX5_INVALID_POLICY_ID;
641 * Close and release all the resources of
642 * the ASO flow meter management structure.
645 * Pointer to mlx5_dev_ctx_shared object to free.
648 mlx5_aso_flow_mtrs_mng_close(struct mlx5_dev_ctx_shared *sh)
650 struct mlx5_aso_mtr_pool *mtr_pool;
651 struct mlx5_flow_mtr_mng *mtrmng = sh->mtrmng;
653 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
654 struct mlx5_aso_mtr *aso_mtr;
656 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
658 if (sh->meter_aso_en) {
659 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_POLICER);
660 idx = mtrmng->pools_mng.n_valid;
662 mtr_pool = mtrmng->pools_mng.pools[idx];
663 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
664 for (i = 0; i < MLX5_ASO_MTRS_PER_POOL; i++) {
665 aso_mtr = &mtr_pool->mtrs[i];
666 if (aso_mtr->fm.meter_action)
668 (mlx5_glue->destroy_flow_action
669 (aso_mtr->fm.meter_action));
671 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
672 claim_zero(mlx5_devx_cmd_destroy
673 (mtr_pool->devx_obj));
674 mtrmng->pools_mng.n_valid--;
677 mlx5_free(sh->mtrmng->pools_mng.pools);
679 mlx5_free(sh->mtrmng);
683 /* Send FLOW_AGED event if needed. */
685 mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh)
687 struct mlx5_age_info *age_info;
690 for (i = 0; i < sh->max_port; i++) {
691 age_info = &sh->port[i].age_info;
692 if (!MLX5_AGE_GET(age_info, MLX5_AGE_EVENT_NEW))
694 MLX5_AGE_UNSET(age_info, MLX5_AGE_EVENT_NEW);
695 if (MLX5_AGE_GET(age_info, MLX5_AGE_TRIGGER)) {
696 MLX5_AGE_UNSET(age_info, MLX5_AGE_TRIGGER);
697 rte_eth_dev_callback_process
698 (&rte_eth_devices[sh->port[i].devx_ih_port_id],
699 RTE_ETH_EVENT_FLOW_AGED, NULL);
705 * Initialize the ASO connection tracking structure.
708 * Pointer to mlx5_dev_ctx_shared object.
711 * 0 on success, a negative errno value otherwise and rte_errno is set.
714 mlx5_flow_aso_ct_mng_init(struct mlx5_dev_ctx_shared *sh)
720 sh->ct_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->ct_mng),
721 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
723 DRV_LOG(ERR, "ASO CT management allocation failed.");
727 err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_CONNECTION_TRACKING);
729 mlx5_free(sh->ct_mng);
730 /* rte_errno should be extracted from the failure. */
734 rte_spinlock_init(&sh->ct_mng->ct_sl);
735 rte_rwlock_init(&sh->ct_mng->resize_rwl);
736 LIST_INIT(&sh->ct_mng->free_cts);
741 * Close and release all the resources of the
742 * ASO connection tracking management structure.
745 * Pointer to mlx5_dev_ctx_shared object to free.
748 mlx5_flow_aso_ct_mng_close(struct mlx5_dev_ctx_shared *sh)
750 struct mlx5_aso_ct_pools_mng *mng = sh->ct_mng;
751 struct mlx5_aso_ct_pool *ct_pool;
752 struct mlx5_aso_ct_action *ct;
758 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_CONNECTION_TRACKING);
762 ct_pool = mng->pools[idx];
763 for (i = 0; i < MLX5_ASO_CT_ACTIONS_PER_POOL; i++) {
764 ct = &ct_pool->actions[i];
765 val = __atomic_fetch_sub(&ct->refcnt, 1,
767 MLX5_ASSERT(val == 1);
770 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
771 if (ct->dr_action_orig)
772 claim_zero(mlx5_glue->destroy_flow_action
773 (ct->dr_action_orig));
774 if (ct->dr_action_rply)
775 claim_zero(mlx5_glue->destroy_flow_action
776 (ct->dr_action_rply));
779 claim_zero(mlx5_devx_cmd_destroy(ct_pool->devx_obj));
781 DRV_LOG(DEBUG, "%u ASO CT objects are being used in the pool %u",
785 /* in case of failure. */
788 mlx5_free(mng->pools);
790 /* Management structure must be cleared to 0s during allocation. */
795 * Initialize the flow resources' indexed mempool.
798 * Pointer to mlx5_dev_ctx_shared object.
800 * Pointer to user dev config.
803 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
804 const struct mlx5_dev_config *config)
807 struct mlx5_indexed_pool_config cfg;
809 for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
810 cfg = mlx5_ipool_cfg[i];
815 * Set MLX5_IPOOL_MLX5_FLOW ipool size
816 * according to PCI function flow configuration.
818 case MLX5_IPOOL_MLX5_FLOW:
819 cfg.size = config->dv_flow_en ?
820 sizeof(struct mlx5_flow_handle) :
821 MLX5_FLOW_HANDLE_VERBS_SIZE;
824 if (config->reclaim_mode) {
825 cfg.release_mem_en = 1;
826 cfg.per_core_cache = 0;
828 cfg.release_mem_en = 0;
830 sh->ipool[i] = mlx5_ipool_create(&cfg);
836 * Release the flow resources' indexed mempool.
839 * Pointer to mlx5_dev_ctx_shared object.
842 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
846 for (i = 0; i < MLX5_IPOOL_MAX; ++i)
847 mlx5_ipool_destroy(sh->ipool[i]);
848 for (i = 0; i < MLX5_MAX_MODIFY_NUM; ++i)
849 if (sh->mdh_ipools[i])
850 mlx5_ipool_destroy(sh->mdh_ipools[i]);
854 * Check if dynamic flex parser for eCPRI already exists.
857 * Pointer to Ethernet device structure.
860 * true on exists, false on not.
863 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
865 struct mlx5_priv *priv = dev->data->dev_private;
866 struct mlx5_ecpri_parser_profile *prf = &priv->sh->ecpri_parser;
872 * Allocation of a flex parser for eCPRI. Once created, this parser related
873 * resources will be held until the device is closed.
876 * Pointer to Ethernet device structure.
879 * 0 on success, a negative errno value otherwise and rte_errno is set.
882 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
884 struct mlx5_priv *priv = dev->data->dev_private;
885 struct mlx5_ecpri_parser_profile *prf = &priv->sh->ecpri_parser;
886 struct mlx5_devx_graph_node_attr node = {
887 .modify_field_select = 0,
892 if (!priv->config.hca_attr.parse_graph_flex_node) {
893 DRV_LOG(ERR, "Dynamic flex parser is not supported "
894 "for device %s.", priv->dev_data->name);
897 node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED;
898 /* 8 bytes now: 4B common header + 4B message body header. */
899 node.header_length_base_value = 0x8;
900 /* After MAC layer: Ether / VLAN. */
901 node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC;
902 /* Type of compared condition should be 0xAEFE in the L2 layer. */
903 node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI;
904 /* Sample #0: type in common header. */
905 node.sample[0].flow_match_sample_en = 1;
907 node.sample[0].flow_match_sample_offset_mode = 0x0;
908 /* Only the 2nd byte will be used. */
909 node.sample[0].flow_match_sample_field_base_offset = 0x0;
910 /* Sample #1: message payload. */
911 node.sample[1].flow_match_sample_en = 1;
913 node.sample[1].flow_match_sample_offset_mode = 0x0;
915 * Only the first two bytes will be used right now, and its offset will
916 * start after the common header that with the length of a DW(u32).
918 node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);
919 prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->cdev->ctx, &node);
921 DRV_LOG(ERR, "Failed to create flex parser node object.");
922 return (rte_errno == 0) ? -ENODEV : -rte_errno;
925 ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num);
927 DRV_LOG(ERR, "Failed to query sample IDs.");
928 return (rte_errno == 0) ? -ENODEV : -rte_errno;
930 prf->offset[0] = 0x0;
931 prf->offset[1] = sizeof(uint32_t);
932 prf->ids[0] = ids[0];
933 prf->ids[1] = ids[1];
938 * Destroy the flex parser node, including the parser itself, input / output
939 * arcs and DW samples. Resources could be reused then.
942 * Pointer to Ethernet device structure.
945 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
947 struct mlx5_priv *priv = dev->data->dev_private;
948 struct mlx5_ecpri_parser_profile *prf = &priv->sh->ecpri_parser;
951 mlx5_devx_cmd_destroy(prf->obj);
956 mlx5_get_supported_sw_parsing_offloads(const struct mlx5_hca_attr *attr)
958 uint32_t sw_parsing_offloads = 0;
961 sw_parsing_offloads |= MLX5_SW_PARSING_CAP;
963 sw_parsing_offloads |= MLX5_SW_PARSING_CSUM_CAP;
966 sw_parsing_offloads |= MLX5_SW_PARSING_TSO_CAP;
968 return sw_parsing_offloads;
972 mlx5_get_supported_tunneling_offloads(const struct mlx5_hca_attr *attr)
974 uint32_t tn_offloads = 0;
976 if (attr->tunnel_stateless_vxlan)
977 tn_offloads |= MLX5_TUNNELED_OFFLOADS_VXLAN_CAP;
978 if (attr->tunnel_stateless_gre)
979 tn_offloads |= MLX5_TUNNELED_OFFLOADS_GRE_CAP;
980 if (attr->tunnel_stateless_geneve_rx)
981 tn_offloads |= MLX5_TUNNELED_OFFLOADS_GENEVE_CAP;
985 /* Fill all fields of UAR structure. */
987 mlx5_rxtx_uars_prepare(struct mlx5_dev_ctx_shared *sh)
991 ret = mlx5_devx_uar_prepare(sh->cdev, &sh->tx_uar);
993 DRV_LOG(ERR, "Failed to prepare Tx DevX UAR.");
996 MLX5_ASSERT(sh->tx_uar.obj);
997 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->tx_uar.obj));
998 ret = mlx5_devx_uar_prepare(sh->cdev, &sh->rx_uar);
1000 DRV_LOG(ERR, "Failed to prepare Rx DevX UAR.");
1001 mlx5_devx_uar_release(&sh->tx_uar);
1004 MLX5_ASSERT(sh->rx_uar.obj);
1005 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->rx_uar.obj));
1010 mlx5_rxtx_uars_release(struct mlx5_dev_ctx_shared *sh)
1012 mlx5_devx_uar_release(&sh->rx_uar);
1013 mlx5_devx_uar_release(&sh->tx_uar);
1017 * rte_mempool_walk() callback to unregister Rx mempools.
1018 * It used when implicit mempool registration is disabled.
1021 * The mempool being walked.
1023 * Pointer to the device shared context.
1026 mlx5_dev_ctx_shared_rx_mempool_unregister_cb(struct rte_mempool *mp, void *arg)
1028 struct mlx5_dev_ctx_shared *sh = arg;
1030 mlx5_dev_mempool_unregister(sh->cdev, mp);
1034 * Callback used when implicit mempool registration is disabled
1035 * in order to track Rx mempool destruction.
1038 * Mempool life cycle event.
1040 * An Rx mempool registered explicitly when the port is started.
1042 * Pointer to a device shared context.
1045 mlx5_dev_ctx_shared_rx_mempool_event_cb(enum rte_mempool_event event,
1046 struct rte_mempool *mp, void *arg)
1048 struct mlx5_dev_ctx_shared *sh = arg;
1050 if (event == RTE_MEMPOOL_EVENT_DESTROY)
1051 mlx5_dev_mempool_unregister(sh->cdev, mp);
1055 mlx5_dev_ctx_shared_mempool_subscribe(struct rte_eth_dev *dev)
1057 struct mlx5_priv *priv = dev->data->dev_private;
1058 struct mlx5_dev_ctx_shared *sh = priv->sh;
1061 /* Check if we only need to track Rx mempool destruction. */
1062 if (!sh->cdev->config.mr_mempool_reg_en) {
1063 ret = rte_mempool_event_callback_register
1064 (mlx5_dev_ctx_shared_rx_mempool_event_cb, sh);
1065 return ret == 0 || rte_errno == EEXIST ? 0 : ret;
1067 return mlx5_dev_mempool_subscribe(sh->cdev);
1071 * Set up multiple TISs with different affinities according to
1072 * number of bonding ports
1075 * Pointer of shared context.
1078 * Zero on success, -1 otherwise.
1081 mlx5_setup_tis(struct mlx5_dev_ctx_shared *sh)
1084 struct mlx5_devx_lag_context lag_ctx = { 0 };
1085 struct mlx5_devx_tis_attr tis_attr = { 0 };
1087 tis_attr.transport_domain = sh->td->id;
1088 if (sh->bond.n_port) {
1089 if (!mlx5_devx_cmd_query_lag(sh->cdev->ctx, &lag_ctx)) {
1090 sh->lag.tx_remap_affinity[0] =
1091 lag_ctx.tx_remap_affinity_1;
1092 sh->lag.tx_remap_affinity[1] =
1093 lag_ctx.tx_remap_affinity_2;
1094 sh->lag.affinity_mode = lag_ctx.port_select_mode;
1096 DRV_LOG(ERR, "Failed to query lag affinity.");
1099 if (sh->lag.affinity_mode == MLX5_LAG_MODE_TIS) {
1100 for (i = 0; i < sh->bond.n_port; i++) {
1101 tis_attr.lag_tx_port_affinity =
1102 MLX5_IFC_LAG_MAP_TIS_AFFINITY(i,
1104 sh->tis[i] = mlx5_devx_cmd_create_tis(sh->cdev->ctx,
1107 DRV_LOG(ERR, "Failed to TIS %d/%d for bonding device"
1108 " %s.", i, sh->bond.n_port,
1113 DRV_LOG(DEBUG, "LAG number of ports : %d, affinity_1 & 2 : pf%d & %d.\n",
1114 sh->bond.n_port, lag_ctx.tx_remap_affinity_1,
1115 lag_ctx.tx_remap_affinity_2);
1118 if (sh->lag.affinity_mode == MLX5_LAG_MODE_HASH)
1119 DRV_LOG(INFO, "Device %s enabled HW hash based LAG.",
1122 tis_attr.lag_tx_port_affinity = 0;
1123 sh->tis[0] = mlx5_devx_cmd_create_tis(sh->cdev->ctx, &tis_attr);
1125 DRV_LOG(ERR, "Failed to TIS 0 for bonding device"
1126 " %s.", sh->ibdev_name);
1133 * Allocate shared device context. If there is multiport device the
1134 * master and representors will share this context, if there is single
1135 * port dedicated device, the context will be used by only given
1136 * port due to unification.
1138 * Routine first searches the context for the specified device name,
1139 * if found the shared context assumed and reference counter is incremented.
1140 * If no context found the new one is created and initialized with specified
1141 * device context and parameters.
1144 * Pointer to the device attributes (name, port, etc).
1146 * Pointer to device configuration structure.
1149 * Pointer to mlx5_dev_ctx_shared object on success,
1150 * otherwise NULL and rte_errno is set.
1152 struct mlx5_dev_ctx_shared *
1153 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
1154 const struct mlx5_dev_config *config)
1156 struct mlx5_dev_ctx_shared *sh;
1161 /* Secondary process should not create the shared context. */
1162 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1163 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1164 /* Search for IB context by device name. */
1165 LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
1166 if (!strcmp(sh->ibdev_name, spawn->phys_dev_name)) {
1171 /* No device found, we have to create new shared context. */
1172 MLX5_ASSERT(spawn->max_port);
1173 sh = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
1174 sizeof(struct mlx5_dev_ctx_shared) +
1176 sizeof(struct mlx5_dev_shared_port),
1177 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
1179 DRV_LOG(ERR, "shared context allocation failure");
1183 pthread_mutex_init(&sh->txpp.mutex, NULL);
1184 sh->numa_node = spawn->cdev->dev->numa_node;
1185 sh->cdev = spawn->cdev;
1186 sh->devx = sh->cdev->config.devx;
1187 if (spawn->bond_info)
1188 sh->bond = *spawn->bond_info;
1189 err = mlx5_os_get_dev_attr(sh->cdev, &sh->device_attr);
1191 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
1195 sh->max_port = spawn->max_port;
1196 sh->reclaim_mode = config->reclaim_mode;
1197 strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->cdev->ctx),
1198 sizeof(sh->ibdev_name) - 1);
1199 strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->cdev->ctx),
1200 sizeof(sh->ibdev_path) - 1);
1202 * Setting port_id to max unallowed value means
1203 * there is no interrupt subhandler installed for
1204 * the given port index i.
1206 for (i = 0; i < sh->max_port; i++) {
1207 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
1208 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
1211 sh->td = mlx5_devx_cmd_create_td(sh->cdev->ctx);
1213 DRV_LOG(ERR, "TD allocation failure");
1217 if (mlx5_setup_tis(sh)) {
1218 DRV_LOG(ERR, "TIS allocation failure");
1222 err = mlx5_rxtx_uars_prepare(sh);
1227 /* Initialize UAR access locks for 32bit implementations. */
1228 rte_spinlock_init(&sh->uar_lock_cq);
1229 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
1230 rte_spinlock_init(&sh->uar_lock[i]);
1233 mlx5_os_dev_shared_handler_install(sh);
1234 if (LIST_EMPTY(&mlx5_dev_ctx_list)) {
1235 err = mlx5_flow_os_init_workspace_once();
1239 mlx5_flow_aging_init(sh);
1240 mlx5_flow_counters_mng_init(sh);
1241 mlx5_flow_ipool_create(sh, config);
1242 /* Add context to the global device list. */
1243 LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
1244 rte_spinlock_init(&sh->geneve_tlv_opt_sl);
1246 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1249 pthread_mutex_destroy(&sh->txpp.mutex);
1250 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1253 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1257 claim_zero(mlx5_devx_cmd_destroy(sh->tis[i]));
1258 } while (++i < (uint32_t)sh->bond.n_port);
1259 mlx5_rxtx_uars_release(sh);
1261 MLX5_ASSERT(err > 0);
1267 * Free shared IB device context. Decrement counter and if zero free
1268 * all allocated resources and close handles.
1271 * Pointer to mlx5_dev_ctx_shared object to free
1274 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
1279 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1280 #ifdef RTE_LIBRTE_MLX5_DEBUG
1281 /* Check the object presence in the list. */
1282 struct mlx5_dev_ctx_shared *lctx;
1284 LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
1289 DRV_LOG(ERR, "Freeing non-existing shared IB context");
1294 MLX5_ASSERT(sh->refcnt);
1295 /* Secondary process should not free the shared context. */
1296 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1299 /* Stop watching for mempool events and unregister all mempools. */
1300 if (!sh->cdev->config.mr_mempool_reg_en) {
1301 ret = rte_mempool_event_callback_unregister
1302 (mlx5_dev_ctx_shared_rx_mempool_event_cb, sh);
1305 (mlx5_dev_ctx_shared_rx_mempool_unregister_cb, sh);
1307 /* Remove context from the global device list. */
1308 LIST_REMOVE(sh, next);
1309 /* Release resources on the last device removal. */
1310 if (LIST_EMPTY(&mlx5_dev_ctx_list)) {
1311 mlx5_os_net_cleanup();
1312 mlx5_flow_os_release_workspace();
1314 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1315 if (sh->flex_parsers_dv) {
1316 mlx5_list_destroy(sh->flex_parsers_dv);
1317 sh->flex_parsers_dv = NULL;
1320 * Ensure there is no async event handler installed.
1321 * Only primary process handles async device events.
1323 mlx5_flow_counters_mng_close(sh);
1324 if (sh->aso_age_mng) {
1325 mlx5_flow_aso_age_mng_close(sh);
1326 sh->aso_age_mng = NULL;
1329 mlx5_aso_flow_mtrs_mng_close(sh);
1330 mlx5_flow_ipool_destroy(sh);
1331 mlx5_os_dev_shared_handler_uninstall(sh);
1332 mlx5_rxtx_uars_release(sh);
1335 claim_zero(mlx5_devx_cmd_destroy(sh->tis[i]));
1336 } while (++i < sh->bond.n_port);
1338 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1339 MLX5_ASSERT(sh->geneve_tlv_option_resource == NULL);
1340 pthread_mutex_destroy(&sh->txpp.mutex);
1344 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1348 * Destroy table hash list.
1351 * Pointer to the private device data structure.
1354 mlx5_free_table_hash_list(struct mlx5_priv *priv)
1356 struct mlx5_dev_ctx_shared *sh = priv->sh;
1360 mlx5_hlist_destroy(sh->flow_tbls);
1361 sh->flow_tbls = NULL;
1365 * Initialize flow table hash list and create the root tables entry
1369 * Pointer to the private device data structure.
1372 * Zero on success, positive error code otherwise.
1375 mlx5_alloc_table_hash_list(struct mlx5_priv *priv __rte_unused)
1378 /* Tables are only used in DV and DR modes. */
1379 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
1380 struct mlx5_dev_ctx_shared *sh = priv->sh;
1381 char s[MLX5_NAME_SIZE];
1384 snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1385 sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE,
1387 flow_dv_tbl_create_cb,
1388 flow_dv_tbl_match_cb,
1389 flow_dv_tbl_remove_cb,
1390 flow_dv_tbl_clone_cb,
1391 flow_dv_tbl_clone_free_cb);
1392 if (!sh->flow_tbls) {
1393 DRV_LOG(ERR, "flow tables with hash creation failed.");
1397 #ifndef HAVE_MLX5DV_DR
1398 struct rte_flow_error error;
1399 struct rte_eth_dev *dev = &rte_eth_devices[priv->dev_data->port_id];
1402 * In case we have not DR support, the zero tables should be created
1403 * because DV expect to see them even if they cannot be created by
1406 if (!flow_dv_tbl_resource_get(dev, 0, 0, 0, 0,
1407 NULL, 0, 1, 0, &error) ||
1408 !flow_dv_tbl_resource_get(dev, 0, 1, 0, 0,
1409 NULL, 0, 1, 0, &error) ||
1410 !flow_dv_tbl_resource_get(dev, 0, 0, 1, 0,
1411 NULL, 0, 1, 0, &error)) {
1417 mlx5_free_table_hash_list(priv);
1418 #endif /* HAVE_MLX5DV_DR */
1424 * Retrieve integer value from environment variable.
1427 * Environment variable name.
1430 * Integer value, 0 if the variable is not set.
1433 mlx5_getenv_int(const char *name)
1435 const char *val = getenv(name);
1443 * DPDK callback to add udp tunnel port
1446 * A pointer to eth_dev
1447 * @param[in] udp_tunnel
1448 * A pointer to udp tunnel
1451 * 0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1454 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1455 struct rte_eth_udp_tunnel *udp_tunnel)
1457 MLX5_ASSERT(udp_tunnel != NULL);
1458 if (udp_tunnel->prot_type == RTE_ETH_TUNNEL_TYPE_VXLAN &&
1459 udp_tunnel->udp_port == 4789)
1461 if (udp_tunnel->prot_type == RTE_ETH_TUNNEL_TYPE_VXLAN_GPE &&
1462 udp_tunnel->udp_port == 4790)
1468 * Initialize process private data structure.
1471 * Pointer to Ethernet device structure.
1474 * 0 on success, a negative errno value otherwise and rte_errno is set.
1477 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1479 struct mlx5_priv *priv = dev->data->dev_private;
1480 struct mlx5_proc_priv *ppriv;
1483 mlx5_proc_priv_uninit(dev);
1485 * UAR register table follows the process private structure. BlueFlame
1486 * registers for Tx queues are stored in the table.
1488 ppriv_size = sizeof(struct mlx5_proc_priv) +
1489 priv->txqs_n * sizeof(struct mlx5_uar_data);
1490 ppriv = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, ppriv_size,
1491 RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1496 ppriv->uar_table_sz = priv->txqs_n;
1497 dev->process_private = ppriv;
1498 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
1499 priv->sh->pppriv = ppriv;
1504 * Un-initialize process private data structure.
1507 * Pointer to Ethernet device structure.
1510 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1512 if (!dev->process_private)
1514 mlx5_free(dev->process_private);
1515 dev->process_private = NULL;
1519 * DPDK callback to close the device.
1521 * Destroy all queues and objects, free memory.
1524 * Pointer to Ethernet device structure.
1527 mlx5_dev_close(struct rte_eth_dev *dev)
1529 struct mlx5_priv *priv = dev->data->dev_private;
1533 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1534 /* Check if process_private released. */
1535 if (!dev->process_private)
1537 mlx5_tx_uar_uninit_secondary(dev);
1538 mlx5_proc_priv_uninit(dev);
1539 rte_eth_dev_release_port(dev);
1544 DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1546 ((priv->sh->cdev->ctx != NULL) ?
1547 mlx5_os_get_ctx_device_name(priv->sh->cdev->ctx) : ""));
1549 * If default mreg copy action is removed at the stop stage,
1550 * the search will return none and nothing will be done anymore.
1552 mlx5_flow_stop_default(dev);
1553 mlx5_traffic_disable(dev);
1555 * If all the flows are already flushed in the device stop stage,
1556 * then this will return directly without any action.
1558 mlx5_flow_list_flush(dev, MLX5_FLOW_TYPE_GEN, true);
1559 mlx5_action_handle_flush(dev);
1560 mlx5_flow_meter_flush(dev, NULL);
1561 /* Prevent crashes when queues are still in use. */
1562 dev->rx_pkt_burst = removed_rx_burst;
1563 dev->tx_pkt_burst = removed_tx_burst;
1565 /* Disable datapath on secondary process. */
1566 mlx5_mp_os_req_stop_rxtx(dev);
1567 /* Free the eCPRI flex parser resource. */
1568 mlx5_flex_parser_ecpri_release(dev);
1569 mlx5_flex_item_port_cleanup(dev);
1570 if (priv->rxq_privs != NULL) {
1571 /* XXX race condition if mlx5_rx_burst() is still running. */
1572 rte_delay_us_sleep(1000);
1573 for (i = 0; (i != priv->rxqs_n); ++i)
1574 mlx5_rxq_release(dev, i);
1576 mlx5_free(priv->rxq_privs);
1577 priv->rxq_privs = NULL;
1579 if (priv->txqs != NULL) {
1580 /* XXX race condition if mlx5_tx_burst() is still running. */
1581 rte_delay_us_sleep(1000);
1582 for (i = 0; (i != priv->txqs_n); ++i)
1583 mlx5_txq_release(dev, i);
1587 mlx5_proc_priv_uninit(dev);
1588 if (priv->q_counters) {
1589 mlx5_devx_cmd_destroy(priv->q_counters);
1590 priv->q_counters = NULL;
1592 if (priv->drop_queue.hrxq)
1593 mlx5_drop_action_destroy(dev);
1594 if (priv->mreg_cp_tbl)
1595 mlx5_hlist_destroy(priv->mreg_cp_tbl);
1596 mlx5_mprq_free_mp(dev);
1597 if (priv->sh->ct_mng)
1598 mlx5_flow_aso_ct_mng_close(priv->sh);
1599 mlx5_os_free_shared_dr(priv);
1600 if (priv->rss_conf.rss_key != NULL)
1601 mlx5_free(priv->rss_conf.rss_key);
1602 if (priv->reta_idx != NULL)
1603 mlx5_free(priv->reta_idx);
1604 if (priv->config.vf)
1605 mlx5_os_mac_addr_flush(dev);
1606 if (priv->nl_socket_route >= 0)
1607 close(priv->nl_socket_route);
1608 if (priv->nl_socket_rdma >= 0)
1609 close(priv->nl_socket_rdma);
1610 if (priv->vmwa_context)
1611 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1612 ret = mlx5_hrxq_verify(dev);
1614 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1615 dev->data->port_id);
1616 ret = mlx5_ind_table_obj_verify(dev);
1618 DRV_LOG(WARNING, "port %u some indirection table still remain",
1619 dev->data->port_id);
1620 ret = mlx5_rxq_obj_verify(dev);
1622 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1623 dev->data->port_id);
1624 ret = mlx5_rxq_verify(dev);
1626 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1627 dev->data->port_id);
1628 ret = mlx5_txq_obj_verify(dev);
1630 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1631 dev->data->port_id);
1632 ret = mlx5_txq_verify(dev);
1634 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1635 dev->data->port_id);
1636 ret = mlx5_flow_verify(dev);
1638 DRV_LOG(WARNING, "port %u some flows still remain",
1639 dev->data->port_id);
1641 mlx5_list_destroy(priv->hrxqs);
1643 * Free the shared context in last turn, because the cleanup
1644 * routines above may use some shared fields, like
1645 * mlx5_os_mac_addr_flush() uses ibdev_path for retrieveing
1646 * ifindex if Netlink fails.
1648 mlx5_free_shared_dev_ctx(priv->sh);
1649 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1653 MLX5_ETH_FOREACH_DEV(port_id, dev->device) {
1654 struct mlx5_priv *opriv =
1655 rte_eth_devices[port_id].data->dev_private;
1658 opriv->domain_id != priv->domain_id ||
1659 &rte_eth_devices[port_id] == dev)
1665 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1667 memset(priv, 0, sizeof(*priv));
1668 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1670 * Reset mac_addrs to NULL such that it is not freed as part of
1671 * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1672 * it is freed when dev_private is freed.
1674 dev->data->mac_addrs = NULL;
1678 const struct eth_dev_ops mlx5_dev_ops = {
1679 .dev_configure = mlx5_dev_configure,
1680 .dev_start = mlx5_dev_start,
1681 .dev_stop = mlx5_dev_stop,
1682 .dev_set_link_down = mlx5_set_link_down,
1683 .dev_set_link_up = mlx5_set_link_up,
1684 .dev_close = mlx5_dev_close,
1685 .promiscuous_enable = mlx5_promiscuous_enable,
1686 .promiscuous_disable = mlx5_promiscuous_disable,
1687 .allmulticast_enable = mlx5_allmulticast_enable,
1688 .allmulticast_disable = mlx5_allmulticast_disable,
1689 .link_update = mlx5_link_update,
1690 .stats_get = mlx5_stats_get,
1691 .stats_reset = mlx5_stats_reset,
1692 .xstats_get = mlx5_xstats_get,
1693 .xstats_reset = mlx5_xstats_reset,
1694 .xstats_get_names = mlx5_xstats_get_names,
1695 .fw_version_get = mlx5_fw_version_get,
1696 .dev_infos_get = mlx5_dev_infos_get,
1697 .representor_info_get = mlx5_representor_info_get,
1698 .read_clock = mlx5_txpp_read_clock,
1699 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1700 .vlan_filter_set = mlx5_vlan_filter_set,
1701 .rx_queue_setup = mlx5_rx_queue_setup,
1702 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1703 .tx_queue_setup = mlx5_tx_queue_setup,
1704 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1705 .rx_queue_release = mlx5_rx_queue_release,
1706 .tx_queue_release = mlx5_tx_queue_release,
1707 .rx_queue_start = mlx5_rx_queue_start,
1708 .rx_queue_stop = mlx5_rx_queue_stop,
1709 .tx_queue_start = mlx5_tx_queue_start,
1710 .tx_queue_stop = mlx5_tx_queue_stop,
1711 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1712 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1713 .mac_addr_remove = mlx5_mac_addr_remove,
1714 .mac_addr_add = mlx5_mac_addr_add,
1715 .mac_addr_set = mlx5_mac_addr_set,
1716 .set_mc_addr_list = mlx5_set_mc_addr_list,
1717 .mtu_set = mlx5_dev_set_mtu,
1718 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1719 .vlan_offload_set = mlx5_vlan_offload_set,
1720 .reta_update = mlx5_dev_rss_reta_update,
1721 .reta_query = mlx5_dev_rss_reta_query,
1722 .rss_hash_update = mlx5_rss_hash_update,
1723 .rss_hash_conf_get = mlx5_rss_hash_conf_get,
1724 .flow_ops_get = mlx5_flow_ops_get,
1725 .rxq_info_get = mlx5_rxq_info_get,
1726 .txq_info_get = mlx5_txq_info_get,
1727 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1728 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1729 .rx_queue_intr_enable = mlx5_rx_intr_enable,
1730 .rx_queue_intr_disable = mlx5_rx_intr_disable,
1731 .is_removed = mlx5_is_removed,
1732 .udp_tunnel_port_add = mlx5_udp_tunnel_port_add,
1733 .get_module_info = mlx5_get_module_info,
1734 .get_module_eeprom = mlx5_get_module_eeprom,
1735 .hairpin_cap_get = mlx5_hairpin_cap_get,
1736 .mtr_ops_get = mlx5_flow_meter_ops_get,
1737 .hairpin_bind = mlx5_hairpin_bind,
1738 .hairpin_unbind = mlx5_hairpin_unbind,
1739 .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1740 .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1741 .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1742 .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1743 .get_monitor_addr = mlx5_get_monitor_addr,
1746 /* Available operations from secondary process. */
1747 const struct eth_dev_ops mlx5_dev_sec_ops = {
1748 .stats_get = mlx5_stats_get,
1749 .stats_reset = mlx5_stats_reset,
1750 .xstats_get = mlx5_xstats_get,
1751 .xstats_reset = mlx5_xstats_reset,
1752 .xstats_get_names = mlx5_xstats_get_names,
1753 .fw_version_get = mlx5_fw_version_get,
1754 .dev_infos_get = mlx5_dev_infos_get,
1755 .representor_info_get = mlx5_representor_info_get,
1756 .read_clock = mlx5_txpp_read_clock,
1757 .rx_queue_start = mlx5_rx_queue_start,
1758 .rx_queue_stop = mlx5_rx_queue_stop,
1759 .tx_queue_start = mlx5_tx_queue_start,
1760 .tx_queue_stop = mlx5_tx_queue_stop,
1761 .rxq_info_get = mlx5_rxq_info_get,
1762 .txq_info_get = mlx5_txq_info_get,
1763 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1764 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1765 .get_module_info = mlx5_get_module_info,
1766 .get_module_eeprom = mlx5_get_module_eeprom,
1769 /* Available operations in flow isolated mode. */
1770 const struct eth_dev_ops mlx5_dev_ops_isolate = {
1771 .dev_configure = mlx5_dev_configure,
1772 .dev_start = mlx5_dev_start,
1773 .dev_stop = mlx5_dev_stop,
1774 .dev_set_link_down = mlx5_set_link_down,
1775 .dev_set_link_up = mlx5_set_link_up,
1776 .dev_close = mlx5_dev_close,
1777 .promiscuous_enable = mlx5_promiscuous_enable,
1778 .promiscuous_disable = mlx5_promiscuous_disable,
1779 .allmulticast_enable = mlx5_allmulticast_enable,
1780 .allmulticast_disable = mlx5_allmulticast_disable,
1781 .link_update = mlx5_link_update,
1782 .stats_get = mlx5_stats_get,
1783 .stats_reset = mlx5_stats_reset,
1784 .xstats_get = mlx5_xstats_get,
1785 .xstats_reset = mlx5_xstats_reset,
1786 .xstats_get_names = mlx5_xstats_get_names,
1787 .fw_version_get = mlx5_fw_version_get,
1788 .dev_infos_get = mlx5_dev_infos_get,
1789 .representor_info_get = mlx5_representor_info_get,
1790 .read_clock = mlx5_txpp_read_clock,
1791 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1792 .vlan_filter_set = mlx5_vlan_filter_set,
1793 .rx_queue_setup = mlx5_rx_queue_setup,
1794 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1795 .tx_queue_setup = mlx5_tx_queue_setup,
1796 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1797 .rx_queue_release = mlx5_rx_queue_release,
1798 .tx_queue_release = mlx5_tx_queue_release,
1799 .rx_queue_start = mlx5_rx_queue_start,
1800 .rx_queue_stop = mlx5_rx_queue_stop,
1801 .tx_queue_start = mlx5_tx_queue_start,
1802 .tx_queue_stop = mlx5_tx_queue_stop,
1803 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1804 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1805 .mac_addr_remove = mlx5_mac_addr_remove,
1806 .mac_addr_add = mlx5_mac_addr_add,
1807 .mac_addr_set = mlx5_mac_addr_set,
1808 .set_mc_addr_list = mlx5_set_mc_addr_list,
1809 .mtu_set = mlx5_dev_set_mtu,
1810 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1811 .vlan_offload_set = mlx5_vlan_offload_set,
1812 .flow_ops_get = mlx5_flow_ops_get,
1813 .rxq_info_get = mlx5_rxq_info_get,
1814 .txq_info_get = mlx5_txq_info_get,
1815 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1816 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1817 .rx_queue_intr_enable = mlx5_rx_intr_enable,
1818 .rx_queue_intr_disable = mlx5_rx_intr_disable,
1819 .is_removed = mlx5_is_removed,
1820 .get_module_info = mlx5_get_module_info,
1821 .get_module_eeprom = mlx5_get_module_eeprom,
1822 .hairpin_cap_get = mlx5_hairpin_cap_get,
1823 .mtr_ops_get = mlx5_flow_meter_ops_get,
1824 .hairpin_bind = mlx5_hairpin_bind,
1825 .hairpin_unbind = mlx5_hairpin_unbind,
1826 .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1827 .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1828 .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1829 .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1830 .get_monitor_addr = mlx5_get_monitor_addr,
1834 * Verify and store value for device argument.
1837 * Key argument to verify.
1839 * Value associated with key.
1844 * 0 on success, a negative errno value otherwise and rte_errno is set.
1847 mlx5_args_check(const char *key, const char *val, void *opaque)
1849 struct mlx5_dev_config *config = opaque;
1853 /* No-op, port representors are processed in mlx5_dev_spawn(). */
1854 if (!strcmp(MLX5_DRIVER_KEY, key) || !strcmp(MLX5_REPRESENTOR, key) ||
1855 !strcmp(MLX5_SYS_MEM_EN, key) || !strcmp(MLX5_TX_DB_NC, key) ||
1856 !strcmp(MLX5_MR_MEMPOOL_REG_EN, key) ||
1857 !strcmp(MLX5_MR_EXT_MEMSEG_EN, key))
1860 tmp = strtol(val, NULL, 0);
1863 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1866 if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
1867 /* Negative values are acceptable for some keys only. */
1869 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
1872 mod = tmp >= 0 ? tmp : -tmp;
1873 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1874 if (tmp > MLX5_CQE_RESP_FORMAT_L34H_STRIDX) {
1875 DRV_LOG(ERR, "invalid CQE compression "
1876 "format parameter");
1880 config->cqe_comp = !!tmp;
1881 config->cqe_comp_fmt = tmp;
1882 } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1883 config->hw_padding = !!tmp;
1884 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1885 config->mprq.enabled = !!tmp;
1886 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1887 config->mprq.stride_num_n = tmp;
1888 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1889 config->mprq.stride_size_n = tmp;
1890 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1891 config->mprq.max_memcpy_len = tmp;
1892 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1893 config->mprq.min_rxqs_num = tmp;
1894 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1895 DRV_LOG(WARNING, "%s: deprecated parameter,"
1896 " converted to txq_inline_max", key);
1897 config->txq_inline_max = tmp;
1898 } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1899 config->txq_inline_max = tmp;
1900 } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1901 config->txq_inline_min = tmp;
1902 } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1903 config->txq_inline_mpw = tmp;
1904 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1905 config->txqs_inline = tmp;
1906 } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1907 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1908 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1909 config->mps = !!tmp;
1910 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1911 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1912 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1913 DRV_LOG(WARNING, "%s: deprecated parameter,"
1914 " converted to txq_inline_mpw", key);
1915 config->txq_inline_mpw = tmp;
1916 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1917 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1918 } else if (strcmp(MLX5_TX_PP, key) == 0) {
1920 DRV_LOG(ERR, "Zero Tx packet pacing parameter");
1924 config->tx_pp = tmp;
1925 } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
1926 config->tx_skew = tmp;
1927 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1928 config->rx_vec_en = !!tmp;
1929 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1930 config->l3_vxlan_en = !!tmp;
1931 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1932 config->vf_nl_en = !!tmp;
1933 } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1934 config->dv_esw_en = !!tmp;
1935 } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1936 config->dv_flow_en = !!tmp;
1937 } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1938 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1939 tmp != MLX5_XMETA_MODE_META16 &&
1940 tmp != MLX5_XMETA_MODE_META32 &&
1941 tmp != MLX5_XMETA_MODE_MISS_INFO) {
1942 DRV_LOG(ERR, "invalid extensive "
1943 "metadata parameter");
1947 if (tmp != MLX5_XMETA_MODE_MISS_INFO)
1948 config->dv_xmeta_en = tmp;
1950 config->dv_miss_info = 1;
1951 } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
1952 config->lacp_by_user = !!tmp;
1953 } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1954 config->max_dump_files_num = tmp;
1955 } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1956 config->lro.timeout = tmp;
1957 } else if (strcmp(RTE_DEVARGS_KEY_CLASS, key) == 0) {
1958 DRV_LOG(DEBUG, "class argument is %s.", val);
1959 } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1960 config->log_hp_size = tmp;
1961 } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1962 if (tmp != MLX5_RCM_NONE &&
1963 tmp != MLX5_RCM_LIGHT &&
1964 tmp != MLX5_RCM_AGGR) {
1965 DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1969 config->reclaim_mode = tmp;
1970 } else if (strcmp(MLX5_DECAP_EN, key) == 0) {
1971 config->decap_en = !!tmp;
1972 } else if (strcmp(MLX5_ALLOW_DUPLICATE_PATTERN, key) == 0) {
1973 config->allow_duplicate_pattern = !!tmp;
1974 } else if (strcmp(MLX5_DELAY_DROP, key) == 0) {
1975 config->std_delay_drop = tmp & MLX5_DELAY_DROP_STANDARD;
1976 config->hp_delay_drop = tmp & MLX5_DELAY_DROP_HAIRPIN;
1978 DRV_LOG(WARNING, "%s: unknown parameter", key);
1986 * Parse device parameters.
1989 * Pointer to device configuration structure.
1991 * Device arguments structure.
1994 * 0 on success, a negative errno value otherwise and rte_errno is set.
1997 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1999 const char **params = (const char *[]){
2001 MLX5_RXQ_CQE_COMP_EN,
2002 MLX5_RXQ_PKT_PAD_EN,
2004 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
2005 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
2006 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
2009 MLX5_TXQ_INLINE_MIN,
2010 MLX5_TXQ_INLINE_MAX,
2011 MLX5_TXQ_INLINE_MPW,
2012 MLX5_TXQS_MIN_INLINE,
2015 MLX5_TXQ_MPW_HDR_DSEG_EN,
2016 MLX5_TXQ_MAX_INLINE_LEN,
2028 MLX5_MR_EXT_MEMSEG_EN,
2030 MLX5_MAX_DUMP_FILES_NUM,
2031 MLX5_LRO_TIMEOUT_USEC,
2032 RTE_DEVARGS_KEY_CLASS,
2037 MLX5_ALLOW_DUPLICATE_PATTERN,
2038 MLX5_MR_MEMPOOL_REG_EN,
2042 struct rte_kvargs *kvlist;
2046 if (devargs == NULL)
2048 /* Following UGLY cast is done to pass checkpatch. */
2049 kvlist = rte_kvargs_parse(devargs->args, params);
2050 if (kvlist == NULL) {
2054 /* Process parameters. */
2055 for (i = 0; (params[i] != NULL); ++i) {
2056 if (rte_kvargs_count(kvlist, params[i])) {
2057 ret = rte_kvargs_process(kvlist, params[i],
2058 mlx5_args_check, config);
2061 rte_kvargs_free(kvlist);
2066 rte_kvargs_free(kvlist);
2071 * Configures the minimal amount of data to inline into WQE
2072 * while sending packets.
2074 * - the txq_inline_min has the maximal priority, if this
2075 * key is specified in devargs
2076 * - if DevX is enabled the inline mode is queried from the
2077 * device (HCA attributes and NIC vport context if needed).
2078 * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
2079 * and none (0 bytes) for other NICs
2082 * Verbs device parameters (name, port, switch_info) to spawn.
2084 * Device configuration parameters.
2087 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
2088 struct mlx5_dev_config *config)
2090 if (config->txq_inline_min != MLX5_ARG_UNSET) {
2091 /* Application defines size of inlined data explicitly. */
2092 if (spawn->pci_dev != NULL) {
2093 switch (spawn->pci_dev->id.device_id) {
2094 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2095 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2096 if (config->txq_inline_min <
2097 (int)MLX5_INLINE_HSIZE_L2) {
2099 "txq_inline_mix aligned to minimal ConnectX-4 required value %d",
2100 (int)MLX5_INLINE_HSIZE_L2);
2101 config->txq_inline_min =
2102 MLX5_INLINE_HSIZE_L2;
2109 if (config->hca_attr.eth_net_offloads) {
2110 /* We have DevX enabled, inline mode queried successfully. */
2111 switch (config->hca_attr.wqe_inline_mode) {
2112 case MLX5_CAP_INLINE_MODE_L2:
2113 /* outer L2 header must be inlined. */
2114 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2116 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
2117 /* No inline data are required by NIC. */
2118 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2119 config->hw_vlan_insert =
2120 config->hca_attr.wqe_vlan_insert;
2121 DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
2123 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
2124 /* inline mode is defined by NIC vport context. */
2125 if (!config->hca_attr.eth_virt)
2127 switch (config->hca_attr.vport_inline_mode) {
2128 case MLX5_INLINE_MODE_NONE:
2129 config->txq_inline_min =
2130 MLX5_INLINE_HSIZE_NONE;
2132 case MLX5_INLINE_MODE_L2:
2133 config->txq_inline_min =
2134 MLX5_INLINE_HSIZE_L2;
2136 case MLX5_INLINE_MODE_IP:
2137 config->txq_inline_min =
2138 MLX5_INLINE_HSIZE_L3;
2140 case MLX5_INLINE_MODE_TCP_UDP:
2141 config->txq_inline_min =
2142 MLX5_INLINE_HSIZE_L4;
2144 case MLX5_INLINE_MODE_INNER_L2:
2145 config->txq_inline_min =
2146 MLX5_INLINE_HSIZE_INNER_L2;
2148 case MLX5_INLINE_MODE_INNER_IP:
2149 config->txq_inline_min =
2150 MLX5_INLINE_HSIZE_INNER_L3;
2152 case MLX5_INLINE_MODE_INNER_TCP_UDP:
2153 config->txq_inline_min =
2154 MLX5_INLINE_HSIZE_INNER_L4;
2159 if (spawn->pci_dev == NULL) {
2160 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2164 * We get here if we are unable to deduce
2165 * inline data size with DevX. Try PCI ID
2166 * to determine old NICs.
2168 switch (spawn->pci_dev->id.device_id) {
2169 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2170 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2171 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
2172 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
2173 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2174 config->hw_vlan_insert = 0;
2176 case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
2177 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
2178 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
2179 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
2181 * These NICs support VLAN insertion from WQE and
2182 * report the wqe_vlan_insert flag. But there is the bug
2183 * and PFC control may be broken, so disable feature.
2185 config->hw_vlan_insert = 0;
2186 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2189 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2193 DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
2197 * Configures the metadata mask fields in the shared context.
2200 * Pointer to Ethernet device.
2203 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
2205 struct mlx5_priv *priv = dev->data->dev_private;
2206 struct mlx5_dev_ctx_shared *sh = priv->sh;
2207 uint32_t meta, mark, reg_c0;
2209 reg_c0 = ~priv->vport_meta_mask;
2210 switch (priv->config.dv_xmeta_en) {
2211 case MLX5_XMETA_MODE_LEGACY:
2213 mark = MLX5_FLOW_MARK_MASK;
2215 case MLX5_XMETA_MODE_META16:
2216 meta = reg_c0 >> rte_bsf32(reg_c0);
2217 mark = MLX5_FLOW_MARK_MASK;
2219 case MLX5_XMETA_MODE_META32:
2221 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
2229 if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
2230 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
2231 sh->dv_mark_mask, mark);
2233 sh->dv_mark_mask = mark;
2234 if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
2235 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
2236 sh->dv_meta_mask, meta);
2238 sh->dv_meta_mask = meta;
2239 if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
2240 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
2241 sh->dv_meta_mask, reg_c0);
2243 sh->dv_regc0_mask = reg_c0;
2244 DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
2245 DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
2246 DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
2247 DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
2251 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
2253 static const char *const dynf_names[] = {
2254 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
2255 RTE_MBUF_DYNFLAG_METADATA_NAME,
2256 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
2260 if (n < RTE_DIM(dynf_names))
2262 for (i = 0; i < RTE_DIM(dynf_names); i++) {
2263 if (names[i] == NULL)
2265 strcpy(names[i], dynf_names[i]);
2267 return RTE_DIM(dynf_names);
2271 * Comparison callback to sort device data.
2273 * This is meant to be used with qsort().
2276 * Pointer to pointer to first data object.
2278 * Pointer to pointer to second data object.
2281 * 0 if both objects are equal, less than 0 if the first argument is less
2282 * than the second, greater than 0 otherwise.
2285 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
2286 struct mlx5_dev_config *config,
2287 struct rte_device *dpdk_dev)
2289 struct mlx5_dev_ctx_shared *sh = priv->sh;
2290 struct mlx5_dev_config *sh_conf = NULL;
2294 /* Nothing to compare for the single/first device. */
2295 if (sh->refcnt == 1)
2297 /* Find the device with shared context. */
2298 MLX5_ETH_FOREACH_DEV(port_id, dpdk_dev) {
2299 struct mlx5_priv *opriv =
2300 rte_eth_devices[port_id].data->dev_private;
2302 if (opriv && opriv != priv && opriv->sh == sh) {
2303 sh_conf = &opriv->config;
2309 if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
2310 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
2311 " for shared %s context", sh->ibdev_name);
2315 if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
2316 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
2317 " for shared %s context", sh->ibdev_name);
2325 * Look for the ethernet device belonging to mlx5 driver.
2327 * @param[in] port_id
2328 * port_id to start looking for device.
2330 * Pointer to the hint device. When device is being probed
2331 * the its siblings (master and preceding representors might
2332 * not have assigned driver yet (because the mlx5_os_pci_probe()
2333 * is not completed yet, for this case match on hint
2334 * device may be used to detect sibling device.
2337 * port_id of found device, RTE_MAX_ETHPORT if not found.
2340 mlx5_eth_find_next(uint16_t port_id, struct rte_device *odev)
2342 while (port_id < RTE_MAX_ETHPORTS) {
2343 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
2345 if (dev->state != RTE_ETH_DEV_UNUSED &&
2347 (dev->device == odev ||
2348 (dev->device->driver &&
2349 dev->device->driver->name &&
2350 ((strcmp(dev->device->driver->name,
2351 MLX5_PCI_DRIVER_NAME) == 0) ||
2352 (strcmp(dev->device->driver->name,
2353 MLX5_AUXILIARY_DRIVER_NAME) == 0)))))
2357 if (port_id >= RTE_MAX_ETHPORTS)
2358 return RTE_MAX_ETHPORTS;
2363 * Callback to remove a device.
2365 * This function removes all Ethernet devices belong to a given device.
2368 * Pointer to the generic device.
2371 * 0 on success, the function cannot fail.
2374 mlx5_net_remove(struct mlx5_common_device *cdev)
2379 RTE_ETH_FOREACH_DEV_OF(port_id, cdev->dev) {
2381 * mlx5_dev_close() is not registered to secondary process,
2382 * call the close function explicitly for secondary process.
2384 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
2385 ret |= mlx5_dev_close(&rte_eth_devices[port_id]);
2387 ret |= rte_eth_dev_close(port_id);
2389 return ret == 0 ? 0 : -EIO;
2392 static const struct rte_pci_id mlx5_pci_id_map[] = {
2394 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2395 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
2398 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2399 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
2402 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2403 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
2406 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2407 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
2410 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2411 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
2414 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2415 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
2418 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2419 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
2422 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2423 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
2426 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2427 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
2430 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2431 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
2434 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2435 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
2438 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2439 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
2442 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2443 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
2446 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2447 PCI_DEVICE_ID_MELLANOX_CONNECTXVF)
2450 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2451 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
2454 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2455 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
2458 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2459 PCI_DEVICE_ID_MELLANOX_CONNECTX7)
2462 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2463 PCI_DEVICE_ID_MELLANOX_CONNECTX7BF)
2470 static struct mlx5_class_driver mlx5_net_driver = {
2471 .drv_class = MLX5_CLASS_ETH,
2472 .name = RTE_STR(MLX5_ETH_DRIVER_NAME),
2473 .id_table = mlx5_pci_id_map,
2474 .probe = mlx5_os_net_probe,
2475 .remove = mlx5_net_remove,
2481 /* Initialize driver log type. */
2482 RTE_LOG_REGISTER_DEFAULT(mlx5_logtype, NOTICE)
2485 * Driver initialization routine.
2487 RTE_INIT(rte_mlx5_pmd_init)
2489 pthread_mutex_init(&mlx5_dev_ctx_list_mutex, NULL);
2491 /* Build the static tables for Verbs conversion. */
2492 mlx5_set_ptype_table();
2493 mlx5_set_cksum_table();
2494 mlx5_set_swp_types_table();
2496 mlx5_class_driver_register(&mlx5_net_driver);
2499 RTE_PMD_EXPORT_NAME(MLX5_ETH_DRIVER_NAME, __COUNTER__);
2500 RTE_PMD_REGISTER_PCI_TABLE(MLX5_ETH_DRIVER_NAME, mlx5_pci_id_map);
2501 RTE_PMD_REGISTER_KMOD_DEP(MLX5_ETH_DRIVER_NAME, "* ib_uverbs & mlx5_core & mlx5_ib");