drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <stdint.h>
  10 #include <stdlib.h>
  11 #include <errno.h>
  12 #include <net/if.h>
  13 #include <sys/mman.h>
  14 #include <linux/rtnetlink.h>
  15
  16 /* Verbs header. */
  17 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  18 #ifdef PEDANTIC
  19 #pragma GCC diagnostic ignored "-Wpedantic"
  20 #endif
  21 #include <infiniband/verbs.h>
  22 #ifdef PEDANTIC
  23 #pragma GCC diagnostic error "-Wpedantic"
  24 #endif
  25
  26 #include <rte_malloc.h>
  27 #include <rte_ethdev_driver.h>
  28 #include <rte_ethdev_pci.h>
  29 #include <rte_pci.h>
  30 #include <rte_bus_pci.h>
  31 #include <rte_common.h>
  32 #include <rte_kvargs.h>
  33 #include <rte_rwlock.h>
  34 #include <rte_spinlock.h>
  35 #include <rte_string_fns.h>
  36 #include <rte_alarm.h>
  37
  38 #include <mlx5_glue.h>
  39 #include <mlx5_devx_cmds.h>
  40 #include <mlx5_common.h>
  41 #include <mlx5_common_mp.h>
  42
  43 #include "mlx5_defs.h"
  44 #include "mlx5.h"
  45 #include "mlx5_utils.h"
  46 #include "mlx5_rxtx.h"
  47 #include "mlx5_autoconf.h"
  48 #include "mlx5_mr.h"
  49 #include "mlx5_flow.h"
  50 #include "rte_pmd_mlx5.h"
  51
  52 /* Device parameter to enable RX completion queue compression. */
  53 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  54
  55 /* Device parameter to enable RX completion entry padding to 128B. */
  56 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
  57
  58 /* Device parameter to enable padding Rx packet to cacheline size. */
  59 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
  60
  61 /* Device parameter to enable Multi-Packet Rx queue. */
  62 #define MLX5_RX_MPRQ_EN "mprq_en"
  63
  64 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
  65 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
  66
  67 /* Device parameter to configure log 2 of the stride size for MPRQ. */
  68 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
  69
  70 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
  71 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
  72
  73 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
  74 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
  75
  76 /* Device parameter to configure inline send. Deprecated, ignored.*/
  77 #define MLX5_TXQ_INLINE "txq_inline"
  78
  79 /* Device parameter to limit packet size to inline with ordinary SEND. */
  80 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
  81
  82 /* Device parameter to configure minimal data size to inline. */
  83 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
  84
  85 /* Device parameter to limit packet size to inline with Enhanced MPW. */
  86 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
  87
  88 /*
  89  * Device parameter to configure the number of TX queues threshold for
  90  * enabling inline send.
  91  */
  92 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  93
  94 /*
  95  * Device parameter to configure the number of TX queues threshold for
  96  * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
  97  */
  98 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
  99
 100 /* Device parameter to enable multi-packet send WQEs. */
 101 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
 102
 103 /*
 104  * Device parameter to force doorbell register mapping
 105  * to non-cahed region eliminating the extra write memory barrier.
 106  */
 107 #define MLX5_TX_DB_NC "tx_db_nc"
 108
 109 /*
 110  * Device parameter to include 2 dsegs in the title WQEBB.
 111  * Deprecated, ignored.
 112  */
 113 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
 114
 115 /*
 116  * Device parameter to limit the size of inlining packet.
 117  * Deprecated, ignored.
 118  */
 119 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
 120
 121 /*
 122  * Device parameter to enable hardware Tx vector.
 123  * Deprecated, ignored (no vectorized Tx routines anymore).
 124  */
 125 #define MLX5_TX_VEC_EN "tx_vec_en"
 126
 127 /* Device parameter to enable hardware Rx vector. */
 128 #define MLX5_RX_VEC_EN "rx_vec_en"
 129
 130 /* Allow L3 VXLAN flow creation. */
 131 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
 132
 133 /* Activate DV E-Switch flow steering. */
 134 #define MLX5_DV_ESW_EN "dv_esw_en"
 135
 136 /* Activate DV flow steering. */
 137 #define MLX5_DV_FLOW_EN "dv_flow_en"
 138
 139 /* Enable extensive flow metadata support. */
 140 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
 141
 142 /* Activate Netlink support in VF mode. */
 143 #define MLX5_VF_NL_EN "vf_nl_en"
 144
 145 /* Enable extending memsegs when creating a MR. */
 146 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
 147
 148 /* Select port representors to instantiate. */
 149 #define MLX5_REPRESENTOR "representor"
 150
 151 /* Device parameter to configure the maximum number of dump files per queue. */
 152 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
 153
 154 /* Configure timeout of LRO session (in microseconds). */
 155 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
 156
 157 /*
 158  * Device parameter to configure the total data buffer size for a single
 159  * hairpin queue (logarithm value).
 160  */
 161 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
 162
 163 #ifndef HAVE_IBV_MLX5_MOD_MPW
 164 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2)
 165 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3)
 166 #endif
 167
 168 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP
 169 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4)
 170 #endif
 171
 172 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
 173
 174 /* Shared memory between primary and secondary processes. */
 175 struct mlx5_shared_data *mlx5_shared_data;
 176
 177 /* Spinlock for mlx5_shared_data allocation. */
 178 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
 179
 180 /* Process local data for secondary processes. */
 181 static struct mlx5_local_data mlx5_local_data;
 182
 183 /** Driver-specific log messages type. */
 184 int mlx5_logtype;
 185
 186 /** Data associated with devices to spawn. */
 187 struct mlx5_dev_spawn_data {
 188         uint32_t ifindex; /**< Network interface index. */
 189         uint32_t max_port; /**< IB device maximal port index. */
 190         uint32_t ibv_port; /**< IB device physical port index. */
 191         int pf_bond; /**< bonding device PF index. < 0 - no bonding */
 192         struct mlx5_switch_info info; /**< Switch information. */
 193         struct ibv_device *ibv_dev; /**< Associated IB device. */
 194         struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */
 195         struct rte_pci_device *pci_dev; /**< Backend PCI device. */
 196 };
 197
 198 static LIST_HEAD(, mlx5_ibv_shared) mlx5_ibv_list = LIST_HEAD_INITIALIZER();
 199 static pthread_mutex_t mlx5_ibv_list_mutex = PTHREAD_MUTEX_INITIALIZER;
 200
 201 static struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
 202         {
 203                 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
 204                 .trunk_size = 64,
 205                 .grow_trunk = 3,
 206                 .grow_shift = 2,
 207                 .need_lock = 0,
 208                 .release_mem_en = 1,
 209                 .malloc = rte_malloc_socket,
 210                 .free = rte_free,
 211                 .type = "mlx5_encap_decap_ipool",
 212         },
 213 };
 214
 215
 216 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
 217 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
 218
 219 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
 220 #define MLX5_TAGS_HLIST_ARRAY_SIZE 8192
 221
 222 /**
 223  * Allocate ID pool structure.
 224  *
 225  * @param[in] max_id
 226  *   The maximum id can be allocated from the pool.
 227  *
 228  * @return
 229  *   Pointer to pool object, NULL value otherwise.
 230  */
 231 struct mlx5_flow_id_pool *
 232 mlx5_flow_id_pool_alloc(uint32_t max_id)
 233 {
 234         struct mlx5_flow_id_pool *pool;
 235         void *mem;
 236
 237         pool = rte_zmalloc("id pool allocation", sizeof(*pool),
 238                            RTE_CACHE_LINE_SIZE);
 239         if (!pool) {
 240                 DRV_LOG(ERR, "can't allocate id pool");
 241                 rte_errno  = ENOMEM;
 242                 return NULL;
 243         }
 244         mem = rte_zmalloc("", MLX5_FLOW_MIN_ID_POOL_SIZE * sizeof(uint32_t),
 245                           RTE_CACHE_LINE_SIZE);
 246         if (!mem) {
 247                 DRV_LOG(ERR, "can't allocate mem for id pool");
 248                 rte_errno  = ENOMEM;
 249                 goto error;
 250         }
 251         pool->free_arr = mem;
 252         pool->curr = pool->free_arr;
 253         pool->last = pool->free_arr + MLX5_FLOW_MIN_ID_POOL_SIZE;
 254         pool->base_index = 0;
 255         pool->max_id = max_id;
 256         return pool;
 257 error:
 258         rte_free(pool);
 259         return NULL;
 260 }
 261
 262 /**
 263  * Release ID pool structure.
 264  *
 265  * @param[in] pool
 266  *   Pointer to flow id pool object to free.
 267  */
 268 void
 269 mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool)
 270 {
 271         rte_free(pool->free_arr);
 272         rte_free(pool);
 273 }
 274
 275 /**
 276  * Generate ID.
 277  *
 278  * @param[in] pool
 279  *   Pointer to flow id pool.
 280  * @param[out] id
 281  *   The generated ID.
 282  *
 283  * @return
 284  *   0 on success, error value otherwise.
 285  */
 286 uint32_t
 287 mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id)
 288 {
 289         if (pool->curr == pool->free_arr) {
 290                 if (pool->base_index == pool->max_id) {
 291                         rte_errno  = ENOMEM;
 292                         DRV_LOG(ERR, "no free id");
 293                         return -rte_errno;
 294                 }
 295                 *id = ++pool->base_index;
 296                 return 0;
 297         }
 298         *id = *(--pool->curr);
 299         return 0;
 300 }
 301
 302 /**
 303  * Release ID.
 304  *
 305  * @param[in] pool
 306  *   Pointer to flow id pool.
 307  * @param[out] id
 308  *   The generated ID.
 309  *
 310  * @return
 311  *   0 on success, error value otherwise.
 312  */
 313 uint32_t
 314 mlx5_flow_id_release(struct mlx5_flow_id_pool *pool, uint32_t id)
 315 {
 316         uint32_t size;
 317         uint32_t size2;
 318         void *mem;
 319
 320         if (pool->curr == pool->last) {
 321                 size = pool->curr - pool->free_arr;
 322                 size2 = size * MLX5_ID_GENERATION_ARRAY_FACTOR;
 323                 MLX5_ASSERT(size2 > size);
 324                 mem = rte_malloc("", size2 * sizeof(uint32_t), 0);
 325                 if (!mem) {
 326                         DRV_LOG(ERR, "can't allocate mem for id pool");
 327                         rte_errno  = ENOMEM;
 328                         return -rte_errno;
 329                 }
 330                 memcpy(mem, pool->free_arr, size * sizeof(uint32_t));
 331                 rte_free(pool->free_arr);
 332                 pool->free_arr = mem;
 333                 pool->curr = pool->free_arr + size;
 334                 pool->last = pool->free_arr + size2;
 335         }
 336         *pool->curr = id;
 337         pool->curr++;
 338         return 0;
 339 }
 340
 341 /**
 342  * Initialize the counters management structure.
 343  *
 344  * @param[in] sh
 345  *   Pointer to mlx5_ibv_shared object to free
 346  */
 347 static void
 348 mlx5_flow_counters_mng_init(struct mlx5_ibv_shared *sh)
 349 {
 350         uint8_t i;
 351
 352         TAILQ_INIT(&sh->cmng.flow_counters);
 353         for (i = 0; i < RTE_DIM(sh->cmng.ccont); ++i)
 354                 TAILQ_INIT(&sh->cmng.ccont[i].pool_list);
 355 }
 356
 357 /**
 358  * Destroy all the resources allocated for a counter memory management.
 359  *
 360  * @param[in] mng
 361  *   Pointer to the memory management structure.
 362  */
 363 static void
 364 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
 365 {
 366         uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
 367
 368         LIST_REMOVE(mng, next);
 369         claim_zero(mlx5_devx_cmd_destroy(mng->dm));
 370         claim_zero(mlx5_glue->devx_umem_dereg(mng->umem));
 371         rte_free(mem);
 372 }
 373
 374 /**
 375  * Close and release all the resources of the counters management.
 376  *
 377  * @param[in] sh
 378  *   Pointer to mlx5_ibv_shared object to free.
 379  */
 380 static void
 381 mlx5_flow_counters_mng_close(struct mlx5_ibv_shared *sh)
 382 {
 383         struct mlx5_counter_stats_mem_mng *mng;
 384         uint8_t i;
 385         int j;
 386         int retries = 1024;
 387
 388         rte_errno = 0;
 389         while (--retries) {
 390                 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
 391                 if (rte_errno != EINPROGRESS)
 392                         break;
 393                 rte_pause();
 394         }
 395         for (i = 0; i < RTE_DIM(sh->cmng.ccont); ++i) {
 396                 struct mlx5_flow_counter_pool *pool;
 397                 uint32_t batch = !!(i % 2);
 398
 399                 if (!sh->cmng.ccont[i].pools)
 400                         continue;
 401                 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
 402                 while (pool) {
 403                         if (batch) {
 404                                 if (pool->min_dcs)
 405                                         claim_zero
 406                                         (mlx5_devx_cmd_destroy(pool->min_dcs));
 407                         }
 408                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
 409                                 if (pool->counters_raw[j].action)
 410                                         claim_zero
 411                                         (mlx5_glue->destroy_flow_action
 412                                                (pool->counters_raw[j].action));
 413                                 if (!batch && MLX5_GET_POOL_CNT_EXT
 414                                     (pool, j)->dcs)
 415                                         claim_zero(mlx5_devx_cmd_destroy
 416                                                   (MLX5_GET_POOL_CNT_EXT
 417                                                   (pool, j)->dcs));
 418                         }
 419                         TAILQ_REMOVE(&sh->cmng.ccont[i].pool_list, pool,
 420                                      next);
 421                         rte_free(pool);
 422                         pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
 423                 }
 424                 rte_free(sh->cmng.ccont[i].pools);
 425         }
 426         mng = LIST_FIRST(&sh->cmng.mem_mngs);
 427         while (mng) {
 428                 mlx5_flow_destroy_counter_stat_mem_mng(mng);
 429                 mng = LIST_FIRST(&sh->cmng.mem_mngs);
 430         }
 431         memset(&sh->cmng, 0, sizeof(sh->cmng));
 432 }
 433
 434 /**
 435  * Initialize the flow resources' indexed mempool.
 436  *
 437  * @param[in] sh
 438  *   Pointer to mlx5_ibv_shared object.
 439  */
 440 static void
 441 mlx5_flow_ipool_create(struct mlx5_ibv_shared *sh)
 442 {
 443         uint8_t i;
 444
 445         for (i = 0; i < MLX5_IPOOL_MAX; ++i)
 446                 sh->ipool[i] = mlx5_ipool_create(&mlx5_ipool_cfg[i]);
 447 }
 448
 449 /**
 450  * Release the flow resources' indexed mempool.
 451  *
 452  * @param[in] sh
 453  *   Pointer to mlx5_ibv_shared object.
 454  */
 455 static void
 456 mlx5_flow_ipool_destroy(struct mlx5_ibv_shared *sh)
 457 {
 458         uint8_t i;
 459
 460         for (i = 0; i < MLX5_IPOOL_MAX; ++i)
 461                 mlx5_ipool_destroy(sh->ipool[i]);
 462 }
 463
 464 /**
 465  * Extract pdn of PD object using DV API.
 466  *
 467  * @param[in] pd
 468  *   Pointer to the verbs PD object.
 469  * @param[out] pdn
 470  *   Pointer to the PD object number variable.
 471  *
 472  * @return
 473  *   0 on success, error value otherwise.
 474  */
 475 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 476 static int
 477 mlx5_get_pdn(struct ibv_pd *pd __rte_unused, uint32_t *pdn __rte_unused)
 478 {
 479         struct mlx5dv_obj obj;
 480         struct mlx5dv_pd pd_info;
 481         int ret = 0;
 482
 483         obj.pd.in = pd;
 484         obj.pd.out = &pd_info;
 485         ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD);
 486         if (ret) {
 487                 DRV_LOG(DEBUG, "Fail to get PD object info");
 488                 return ret;
 489         }
 490         *pdn = pd_info.pdn;
 491         return 0;
 492 }
 493 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
 494
 495 static int
 496 mlx5_config_doorbell_mapping_env(const struct mlx5_dev_config *config)
 497 {
 498         char *env;
 499         int value;
 500
 501         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 502         /* Get environment variable to store. */
 503         env = getenv(MLX5_SHUT_UP_BF);
 504         value = env ? !!strcmp(env, "0") : MLX5_ARG_UNSET;
 505         if (config->dbnc == MLX5_ARG_UNSET)
 506                 setenv(MLX5_SHUT_UP_BF, MLX5_SHUT_UP_BF_DEFAULT, 1);
 507         else
 508                 setenv(MLX5_SHUT_UP_BF,
 509                        config->dbnc == MLX5_TXDB_NCACHED ? "1" : "0", 1);
 510         return value;
 511 }
 512
 513 static void
 514 mlx5_restore_doorbell_mapping_env(int value)
 515 {
 516         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 517         /* Restore the original environment variable state. */
 518         if (value == MLX5_ARG_UNSET)
 519                 unsetenv(MLX5_SHUT_UP_BF);
 520         else
 521                 setenv(MLX5_SHUT_UP_BF, value ? "1" : "0", 1);
 522 }
 523
 524 /**
 525  * Allocate shared IB device context. If there is multiport device the
 526  * master and representors will share this context, if there is single
 527  * port dedicated IB device, the context will be used by only given
 528  * port due to unification.
 529  *
 530  * Routine first searches the context for the specified IB device name,
 531  * if found the shared context assumed and reference counter is incremented.
 532  * If no context found the new one is created and initialized with specified
 533  * IB device context and parameters.
 534  *
 535  * @param[in] spawn
 536  *   Pointer to the IB device attributes (name, port, etc).
 537  * @param[in] config
 538  *   Pointer to device configuration structure.
 539  *
 540  * @return
 541  *   Pointer to mlx5_ibv_shared object on success,
 542  *   otherwise NULL and rte_errno is set.
 543  */
 544 static struct mlx5_ibv_shared *
 545 mlx5_alloc_shared_ibctx(const struct mlx5_dev_spawn_data *spawn,
 546                         const struct mlx5_dev_config *config)
 547 {
 548         struct mlx5_ibv_shared *sh;
 549         int dbmap_env;
 550         int err = 0;
 551         uint32_t i;
 552 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 553         struct mlx5_devx_tis_attr tis_attr = { 0 };
 554 #endif
 555
 556         MLX5_ASSERT(spawn);
 557         /* Secondary process should not create the shared context. */
 558         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 559         pthread_mutex_lock(&mlx5_ibv_list_mutex);
 560         /* Search for IB context by device name. */
 561         LIST_FOREACH(sh, &mlx5_ibv_list, next) {
 562                 if (!strcmp(sh->ibdev_name, spawn->ibv_dev->name)) {
 563                         sh->refcnt++;
 564                         goto exit;
 565                 }
 566         }
 567         /* No device found, we have to create new shared context. */
 568         MLX5_ASSERT(spawn->max_port);
 569         sh = rte_zmalloc("ethdev shared ib context",
 570                          sizeof(struct mlx5_ibv_shared) +
 571                          spawn->max_port *
 572                          sizeof(struct mlx5_ibv_shared_port),
 573                          RTE_CACHE_LINE_SIZE);
 574         if (!sh) {
 575                 DRV_LOG(ERR, "shared context allocation failure");
 576                 rte_errno  = ENOMEM;
 577                 goto exit;
 578         }
 579         /*
 580          * Configure environment variable "MLX5_BF_SHUT_UP"
 581          * before the device creation. The rdma_core library
 582          * checks the variable at device creation and
 583          * stores the result internally.
 584          */
 585         dbmap_env = mlx5_config_doorbell_mapping_env(config);
 586         /* Try to open IB device with DV first, then usual Verbs. */
 587         errno = 0;
 588         sh->ctx = mlx5_glue->dv_open_device(spawn->ibv_dev);
 589         if (sh->ctx) {
 590                 sh->devx = 1;
 591                 DRV_LOG(DEBUG, "DevX is supported");
 592                 /* The device is created, no need for environment. */
 593                 mlx5_restore_doorbell_mapping_env(dbmap_env);
 594         } else {
 595                 /* The environment variable is still configured. */
 596                 sh->ctx = mlx5_glue->open_device(spawn->ibv_dev);
 597                 err = errno ? errno : ENODEV;
 598                 /*
 599                  * The environment variable is not needed anymore,
 600                  * all device creation attempts are completed.
 601                  */
 602                 mlx5_restore_doorbell_mapping_env(dbmap_env);
 603                 if (!sh->ctx)
 604                         goto error;
 605                 DRV_LOG(DEBUG, "DevX is NOT supported");
 606         }
 607         err = mlx5_glue->query_device_ex(sh->ctx, NULL, &sh->device_attr);
 608         if (err) {
 609                 DRV_LOG(DEBUG, "ibv_query_device_ex() failed");
 610                 goto error;
 611         }
 612         sh->refcnt = 1;
 613         sh->max_port = spawn->max_port;
 614         strncpy(sh->ibdev_name, sh->ctx->device->name,
 615                 sizeof(sh->ibdev_name));
 616         strncpy(sh->ibdev_path, sh->ctx->device->ibdev_path,
 617                 sizeof(sh->ibdev_path));
 618         pthread_mutex_init(&sh->intr_mutex, NULL);
 619         /*
 620          * Setting port_id to max unallowed value means
 621          * there is no interrupt subhandler installed for
 622          * the given port index i.
 623          */
 624         for (i = 0; i < sh->max_port; i++) {
 625                 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
 626                 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
 627         }
 628         sh->pd = mlx5_glue->alloc_pd(sh->ctx);
 629         if (sh->pd == NULL) {
 630                 DRV_LOG(ERR, "PD allocation failure");
 631                 err = ENOMEM;
 632                 goto error;
 633         }
 634 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 635         if (sh->devx) {
 636                 err = mlx5_get_pdn(sh->pd, &sh->pdn);
 637                 if (err) {
 638                         DRV_LOG(ERR, "Fail to extract pdn from PD");
 639                         goto error;
 640                 }
 641                 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
 642                 if (!sh->td) {
 643                         DRV_LOG(ERR, "TD allocation failure");
 644                         err = ENOMEM;
 645                         goto error;
 646                 }
 647                 tis_attr.transport_domain = sh->td->id;
 648                 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
 649                 if (!sh->tis) {
 650                         DRV_LOG(ERR, "TIS allocation failure");
 651                         err = ENOMEM;
 652                         goto error;
 653                 }
 654         }
 655         sh->flow_id_pool = mlx5_flow_id_pool_alloc(UINT32_MAX);
 656         if (!sh->flow_id_pool) {
 657                 DRV_LOG(ERR, "can't create flow id pool");
 658                 err = ENOMEM;
 659                 goto error;
 660         }
 661 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
 662         /*
 663          * Once the device is added to the list of memory event
 664          * callback, its global MR cache table cannot be expanded
 665          * on the fly because of deadlock. If it overflows, lookup
 666          * should be done by searching MR list linearly, which is slow.
 667          *
 668          * At this point the device is not added to the memory
 669          * event list yet, context is just being created.
 670          */
 671         err = mlx5_mr_btree_init(&sh->share_cache.cache,
 672                                  MLX5_MR_BTREE_CACHE_N * 2,
 673                                  spawn->pci_dev->device.numa_node);
 674         if (err) {
 675                 err = rte_errno;
 676                 goto error;
 677         }
 678         mlx5_flow_counters_mng_init(sh);
 679         mlx5_flow_ipool_create(sh);
 680         /* Add device to memory callback list. */
 681         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
 682         LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
 683                          sh, mem_event_cb);
 684         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
 685         /* Add context to the global device list. */
 686         LIST_INSERT_HEAD(&mlx5_ibv_list, sh, next);
 687 exit:
 688         pthread_mutex_unlock(&mlx5_ibv_list_mutex);
 689         return sh;
 690 error:
 691         pthread_mutex_unlock(&mlx5_ibv_list_mutex);
 692         MLX5_ASSERT(sh);
 693         if (sh->tis)
 694                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
 695         if (sh->td)
 696                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
 697         if (sh->pd)
 698                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
 699         if (sh->ctx)
 700                 claim_zero(mlx5_glue->close_device(sh->ctx));
 701         if (sh->flow_id_pool)
 702                 mlx5_flow_id_pool_release(sh->flow_id_pool);
 703         rte_free(sh);
 704         MLX5_ASSERT(err > 0);
 705         rte_errno = err;
 706         return NULL;
 707 }
 708
 709 /**
 710  * Free shared IB device context. Decrement counter and if zero free
 711  * all allocated resources and close handles.
 712  *
 713  * @param[in] sh
 714  *   Pointer to mlx5_ibv_shared object to free
 715  */
 716 static void
 717 mlx5_free_shared_ibctx(struct mlx5_ibv_shared *sh)
 718 {
 719         pthread_mutex_lock(&mlx5_ibv_list_mutex);
 720 #ifdef RTE_LIBRTE_MLX5_DEBUG
 721         /* Check the object presence in the list. */
 722         struct mlx5_ibv_shared *lctx;
 723
 724         LIST_FOREACH(lctx, &mlx5_ibv_list, next)
 725                 if (lctx == sh)
 726                         break;
 727         MLX5_ASSERT(lctx);
 728         if (lctx != sh) {
 729                 DRV_LOG(ERR, "Freeing non-existing shared IB context");
 730                 goto exit;
 731         }
 732 #endif
 733         MLX5_ASSERT(sh);
 734         MLX5_ASSERT(sh->refcnt);
 735         /* Secondary process should not free the shared context. */
 736         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 737         if (--sh->refcnt)
 738                 goto exit;
 739         /* Remove from memory callback device list. */
 740         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
 741         LIST_REMOVE(sh, mem_event_cb);
 742         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
 743         /* Release created Memory Regions. */
 744         mlx5_mr_release_cache(&sh->share_cache);
 745         /* Remove context from the global device list. */
 746         LIST_REMOVE(sh, next);
 747         /*
 748          *  Ensure there is no async event handler installed.
 749          *  Only primary process handles async device events.
 750          **/
 751         mlx5_flow_counters_mng_close(sh);
 752         mlx5_flow_ipool_destroy(sh);
 753         MLX5_ASSERT(!sh->intr_cnt);
 754         if (sh->intr_cnt)
 755                 mlx5_intr_callback_unregister
 756                         (&sh->intr_handle, mlx5_dev_interrupt_handler, sh);
 757 #ifdef HAVE_MLX5_DEVX_ASYNC_SUPPORT
 758         if (sh->devx_intr_cnt) {
 759                 if (sh->intr_handle_devx.fd)
 760                         rte_intr_callback_unregister(&sh->intr_handle_devx,
 761                                           mlx5_dev_interrupt_handler_devx, sh);
 762                 if (sh->devx_comp)
 763                         mlx5dv_devx_destroy_cmd_comp(sh->devx_comp);
 764         }
 765 #endif
 766         pthread_mutex_destroy(&sh->intr_mutex);
 767         if (sh->pd)
 768                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
 769         if (sh->tis)
 770                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
 771         if (sh->td)
 772                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
 773         if (sh->ctx)
 774                 claim_zero(mlx5_glue->close_device(sh->ctx));
 775         if (sh->flow_id_pool)
 776                 mlx5_flow_id_pool_release(sh->flow_id_pool);
 777         rte_free(sh);
 778 exit:
 779         pthread_mutex_unlock(&mlx5_ibv_list_mutex);
 780 }
 781
 782 /**
 783  * Destroy table hash list and all the root entries per domain.
 784  *
 785  * @param[in] priv
 786  *   Pointer to the private device data structure.
 787  */
 788 static void
 789 mlx5_free_table_hash_list(struct mlx5_priv *priv)
 790 {
 791         struct mlx5_ibv_shared *sh = priv->sh;
 792         struct mlx5_flow_tbl_data_entry *tbl_data;
 793         union mlx5_flow_tbl_key table_key = {
 794                 {
 795                         .table_id = 0,
 796                         .reserved = 0,
 797                         .domain = 0,
 798                         .direction = 0,
 799                 }
 800         };
 801         struct mlx5_hlist_entry *pos;
 802
 803         if (!sh->flow_tbls)
 804                 return;
 805         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 806         if (pos) {
 807                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 808                                         entry);
 809                 MLX5_ASSERT(tbl_data);
 810                 mlx5_hlist_remove(sh->flow_tbls, pos);
 811                 rte_free(tbl_data);
 812         }
 813         table_key.direction = 1;
 814         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 815         if (pos) {
 816                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 817                                         entry);
 818                 MLX5_ASSERT(tbl_data);
 819                 mlx5_hlist_remove(sh->flow_tbls, pos);
 820                 rte_free(tbl_data);
 821         }
 822         table_key.direction = 0;
 823         table_key.domain = 1;
 824         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 825         if (pos) {
 826                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 827                                         entry);
 828                 MLX5_ASSERT(tbl_data);
 829                 mlx5_hlist_remove(sh->flow_tbls, pos);
 830                 rte_free(tbl_data);
 831         }
 832         mlx5_hlist_destroy(sh->flow_tbls, NULL, NULL);
 833 }
 834
 835 /**
 836  * Initialize flow table hash list and create the root tables entry
 837  * for each domain.
 838  *
 839  * @param[in] priv
 840  *   Pointer to the private device data structure.
 841  *
 842  * @return
 843  *   Zero on success, positive error code otherwise.
 844  */
 845 static int
 846 mlx5_alloc_table_hash_list(struct mlx5_priv *priv)
 847 {
 848         struct mlx5_ibv_shared *sh = priv->sh;
 849         char s[MLX5_HLIST_NAMESIZE];
 850         int err = 0;
 851
 852         MLX5_ASSERT(sh);
 853         snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
 854         sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE);
 855         if (!sh->flow_tbls) {
 856                 DRV_LOG(ERR, "flow tables with hash creation failed.\n");
 857                 err = ENOMEM;
 858                 return err;
 859         }
 860 #ifndef HAVE_MLX5DV_DR
 861         /*
 862          * In case we have not DR support, the zero tables should be created
 863          * because DV expect to see them even if they cannot be created by
 864          * RDMA-CORE.
 865          */
 866         union mlx5_flow_tbl_key table_key = {
 867                 {
 868                         .table_id = 0,
 869                         .reserved = 0,
 870                         .domain = 0,
 871                         .direction = 0,
 872                 }
 873         };
 874         struct mlx5_flow_tbl_data_entry *tbl_data = rte_zmalloc(NULL,
 875                                                           sizeof(*tbl_data), 0);
 876
 877         if (!tbl_data) {
 878                 err = ENOMEM;
 879                 goto error;
 880         }
 881         tbl_data->entry.key = table_key.v64;
 882         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
 883         if (err)
 884                 goto error;
 885         rte_atomic32_init(&tbl_data->tbl.refcnt);
 886         rte_atomic32_inc(&tbl_data->tbl.refcnt);
 887         table_key.direction = 1;
 888         tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
 889         if (!tbl_data) {
 890                 err = ENOMEM;
 891                 goto error;
 892         }
 893         tbl_data->entry.key = table_key.v64;
 894         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
 895         if (err)
 896                 goto error;
 897         rte_atomic32_init(&tbl_data->tbl.refcnt);
 898         rte_atomic32_inc(&tbl_data->tbl.refcnt);
 899         table_key.direction = 0;
 900         table_key.domain = 1;
 901         tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
 902         if (!tbl_data) {
 903                 err = ENOMEM;
 904                 goto error;
 905         }
 906         tbl_data->entry.key = table_key.v64;
 907         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
 908         if (err)
 909                 goto error;
 910         rte_atomic32_init(&tbl_data->tbl.refcnt);
 911         rte_atomic32_inc(&tbl_data->tbl.refcnt);
 912         return err;
 913 error:
 914         mlx5_free_table_hash_list(priv);
 915 #endif /* HAVE_MLX5DV_DR */
 916         return err;
 917 }
 918
 919 /**
 920  * Initialize DR related data within private structure.
 921  * Routine checks the reference counter and does actual
 922  * resources creation/initialization only if counter is zero.
 923  *
 924  * @param[in] priv
 925  *   Pointer to the private device data structure.
 926  *
 927  * @return
 928  *   Zero on success, positive error code otherwise.
 929  */
 930 static int
 931 mlx5_alloc_shared_dr(struct mlx5_priv *priv)
 932 {
 933         struct mlx5_ibv_shared *sh = priv->sh;
 934         char s[MLX5_HLIST_NAMESIZE];
 935         int err = 0;
 936
 937         if (!sh->flow_tbls)
 938                 err = mlx5_alloc_table_hash_list(priv);
 939         else
 940                 DRV_LOG(DEBUG, "sh->flow_tbls[%p] already created, reuse\n",
 941                         (void *)sh->flow_tbls);
 942         if (err)
 943                 return err;
 944         /* Create tags hash list table. */
 945         snprintf(s, sizeof(s), "%s_tags", sh->ibdev_name);
 946         sh->tag_table = mlx5_hlist_create(s, MLX5_TAGS_HLIST_ARRAY_SIZE);
 947         if (!sh->tag_table) {
 948                 DRV_LOG(ERR, "tags with hash creation failed.\n");
 949                 err = ENOMEM;
 950                 goto error;
 951         }
 952 #ifdef HAVE_MLX5DV_DR
 953         void *domain;
 954
 955         if (sh->dv_refcnt) {
 956                 /* Shared DV/DR structures is already initialized. */
 957                 sh->dv_refcnt++;
 958                 priv->dr_shared = 1;
 959                 return 0;
 960         }
 961         /* Reference counter is zero, we should initialize structures. */
 962         domain = mlx5_glue->dr_create_domain(sh->ctx,
 963                                              MLX5DV_DR_DOMAIN_TYPE_NIC_RX);
 964         if (!domain) {
 965                 DRV_LOG(ERR, "ingress mlx5dv_dr_create_domain failed");
 966                 err = errno;
 967                 goto error;
 968         }
 969         sh->rx_domain = domain;
 970         domain = mlx5_glue->dr_create_domain(sh->ctx,
 971                                              MLX5DV_DR_DOMAIN_TYPE_NIC_TX);
 972         if (!domain) {
 973                 DRV_LOG(ERR, "egress mlx5dv_dr_create_domain failed");
 974                 err = errno;
 975                 goto error;
 976         }
 977         pthread_mutex_init(&sh->dv_mutex, NULL);
 978         sh->tx_domain = domain;
 979 #ifdef HAVE_MLX5DV_DR_ESWITCH
 980         if (priv->config.dv_esw_en) {
 981                 domain  = mlx5_glue->dr_create_domain
 982                         (sh->ctx, MLX5DV_DR_DOMAIN_TYPE_FDB);
 983                 if (!domain) {
 984                         DRV_LOG(ERR, "FDB mlx5dv_dr_create_domain failed");
 985                         err = errno;
 986                         goto error;
 987                 }
 988                 sh->fdb_domain = domain;
 989                 sh->esw_drop_action = mlx5_glue->dr_create_flow_action_drop();
 990         }
 991 #endif
 992         sh->pop_vlan_action = mlx5_glue->dr_create_flow_action_pop_vlan();
 993 #endif /* HAVE_MLX5DV_DR */
 994         sh->dv_refcnt++;
 995         priv->dr_shared = 1;
 996         return 0;
 997 error:
 998         /* Rollback the created objects. */
 999         if (sh->rx_domain) {
1000                 mlx5_glue->dr_destroy_domain(sh->rx_domain);
1001                 sh->rx_domain = NULL;
1002         }
1003         if (sh->tx_domain) {
1004                 mlx5_glue->dr_destroy_domain(sh->tx_domain);
1005                 sh->tx_domain = NULL;
1006         }
1007         if (sh->fdb_domain) {
1008                 mlx5_glue->dr_destroy_domain(sh->fdb_domain);
1009                 sh->fdb_domain = NULL;
1010         }
1011         if (sh->esw_drop_action) {
1012                 mlx5_glue->destroy_flow_action(sh->esw_drop_action);
1013                 sh->esw_drop_action = NULL;
1014         }
1015         if (sh->pop_vlan_action) {
1016                 mlx5_glue->destroy_flow_action(sh->pop_vlan_action);
1017                 sh->pop_vlan_action = NULL;
1018         }
1019         if (sh->tag_table) {
1020                 /* tags should be destroyed with flow before. */
1021                 mlx5_hlist_destroy(sh->tag_table, NULL, NULL);
1022                 sh->tag_table = NULL;
1023         }
1024         mlx5_free_table_hash_list(priv);
1025         return err;
1026 }
1027
1028 /**
1029  * Destroy DR related data within private structure.
1030  *
1031  * @param[in] priv
1032  *   Pointer to the private device data structure.
1033  */
1034 static void
1035 mlx5_free_shared_dr(struct mlx5_priv *priv)
1036 {
1037         struct mlx5_ibv_shared *sh;
1038
1039         if (!priv->dr_shared)
1040                 return;
1041         priv->dr_shared = 0;
1042         sh = priv->sh;
1043         MLX5_ASSERT(sh);
1044 #ifdef HAVE_MLX5DV_DR
1045         MLX5_ASSERT(sh->dv_refcnt);
1046         if (sh->dv_refcnt && --sh->dv_refcnt)
1047                 return;
1048         if (sh->rx_domain) {
1049                 mlx5_glue->dr_destroy_domain(sh->rx_domain);
1050                 sh->rx_domain = NULL;
1051         }
1052         if (sh->tx_domain) {
1053                 mlx5_glue->dr_destroy_domain(sh->tx_domain);
1054                 sh->tx_domain = NULL;
1055         }
1056 #ifdef HAVE_MLX5DV_DR_ESWITCH
1057         if (sh->fdb_domain) {
1058                 mlx5_glue->dr_destroy_domain(sh->fdb_domain);
1059                 sh->fdb_domain = NULL;
1060         }
1061         if (sh->esw_drop_action) {
1062                 mlx5_glue->destroy_flow_action(sh->esw_drop_action);
1063                 sh->esw_drop_action = NULL;
1064         }
1065 #endif
1066         if (sh->pop_vlan_action) {
1067                 mlx5_glue->destroy_flow_action(sh->pop_vlan_action);
1068                 sh->pop_vlan_action = NULL;
1069         }
1070         pthread_mutex_destroy(&sh->dv_mutex);
1071 #endif /* HAVE_MLX5DV_DR */
1072         if (sh->tag_table) {
1073                 /* tags should be destroyed with flow before. */
1074                 mlx5_hlist_destroy(sh->tag_table, NULL, NULL);
1075                 sh->tag_table = NULL;
1076         }
1077         mlx5_free_table_hash_list(priv);
1078 }
1079
1080 /**
1081  * Initialize shared data between primary and secondary process.
1082  *
1083  * A memzone is reserved by primary process and secondary processes attach to
1084  * the memzone.
1085  *
1086  * @return
1087  *   0 on success, a negative errno value otherwise and rte_errno is set.
1088  */
1089 static int
1090 mlx5_init_shared_data(void)
1091 {
1092         const struct rte_memzone *mz;
1093         int ret = 0;
1094
1095         rte_spinlock_lock(&mlx5_shared_data_lock);
1096         if (mlx5_shared_data == NULL) {
1097                 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
1098                         /* Allocate shared memory. */
1099                         mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
1100                                                  sizeof(*mlx5_shared_data),
1101                                                  SOCKET_ID_ANY, 0);
1102                         if (mz == NULL) {
1103                                 DRV_LOG(ERR,
1104                                         "Cannot allocate mlx5 shared data");
1105                                 ret = -rte_errno;
1106                                 goto error;
1107                         }
1108                         mlx5_shared_data = mz->addr;
1109                         memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data));
1110                         rte_spinlock_init(&mlx5_shared_data->lock);
1111                 } else {
1112                         /* Lookup allocated shared memory. */
1113                         mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA);
1114                         if (mz == NULL) {
1115                                 DRV_LOG(ERR,
1116                                         "Cannot attach mlx5 shared data");
1117                                 ret = -rte_errno;
1118                                 goto error;
1119                         }
1120                         mlx5_shared_data = mz->addr;
1121                         memset(&mlx5_local_data, 0, sizeof(mlx5_local_data));
1122                 }
1123         }
1124 error:
1125         rte_spinlock_unlock(&mlx5_shared_data_lock);
1126         return ret;
1127 }
1128
1129 /**
1130  * Retrieve integer value from environment variable.
1131  *
1132  * @param[in] name
1133  *   Environment variable name.
1134  *
1135  * @return
1136  *   Integer value, 0 if the variable is not set.
1137  */
1138 int
1139 mlx5_getenv_int(const char *name)
1140 {
1141         const char *val = getenv(name);
1142
1143         if (val == NULL)
1144                 return 0;
1145         return atoi(val);
1146 }
1147
1148 /**
1149  * Verbs callback to allocate a memory. This function should allocate the space
1150  * according to the size provided residing inside a huge page.
1151  * Please note that all allocation must respect the alignment from libmlx5
1152  * (i.e. currently sysconf(_SC_PAGESIZE)).
1153  *
1154  * @param[in] size
1155  *   The size in bytes of the memory to allocate.
1156  * @param[in] data
1157  *   A pointer to the callback data.
1158  *
1159  * @return
1160  *   Allocated buffer, NULL otherwise and rte_errno is set.
1161  */
1162 static void *
1163 mlx5_alloc_verbs_buf(size_t size, void *data)
1164 {
1165         struct mlx5_priv *priv = data;
1166         void *ret;
1167         size_t alignment = sysconf(_SC_PAGESIZE);
1168         unsigned int socket = SOCKET_ID_ANY;
1169
1170         if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) {
1171                 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
1172
1173                 socket = ctrl->socket;
1174         } else if (priv->verbs_alloc_ctx.type ==
1175                    MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) {
1176                 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
1177
1178                 socket = ctrl->socket;
1179         }
1180         MLX5_ASSERT(data != NULL);
1181         ret = rte_malloc_socket(__func__, size, alignment, socket);
1182         if (!ret && size)
1183                 rte_errno = ENOMEM;
1184         return ret;
1185 }
1186
1187 /**
1188  * Verbs callback to free a memory.
1189  *
1190  * @param[in] ptr
1191  *   A pointer to the memory to free.
1192  * @param[in] data
1193  *   A pointer to the callback data.
1194  */
1195 static void
1196 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused)
1197 {
1198         MLX5_ASSERT(data != NULL);
1199         rte_free(ptr);
1200 }
1201
1202 /**
1203  * DPDK callback to add udp tunnel port
1204  *
1205  * @param[in] dev
1206  *   A pointer to eth_dev
1207  * @param[in] udp_tunnel
1208  *   A pointer to udp tunnel
1209  *
1210  * @return
1211  *   0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1212  */
1213 int
1214 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1215                          struct rte_eth_udp_tunnel *udp_tunnel)
1216 {
1217         MLX5_ASSERT(udp_tunnel != NULL);
1218         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1219             udp_tunnel->udp_port == 4789)
1220                 return 0;
1221         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1222             udp_tunnel->udp_port == 4790)
1223                 return 0;
1224         return -ENOTSUP;
1225 }
1226
1227 /**
1228  * Initialize process private data structure.
1229  *
1230  * @param dev
1231  *   Pointer to Ethernet device structure.
1232  *
1233  * @return
1234  *   0 on success, a negative errno value otherwise and rte_errno is set.
1235  */
1236 int
1237 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1238 {
1239         struct mlx5_priv *priv = dev->data->dev_private;
1240         struct mlx5_proc_priv *ppriv;
1241         size_t ppriv_size;
1242
1243         /*
1244          * UAR register table follows the process private structure. BlueFlame
1245          * registers for Tx queues are stored in the table.
1246          */
1247         ppriv_size =
1248                 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1249         ppriv = rte_malloc_socket("mlx5_proc_priv", ppriv_size,
1250                                   RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1251         if (!ppriv) {
1252                 rte_errno = ENOMEM;
1253                 return -rte_errno;
1254         }
1255         ppriv->uar_table_sz = ppriv_size;
1256         dev->process_private = ppriv;
1257         return 0;
1258 }
1259
1260 /**
1261  * Un-initialize process private data structure.
1262  *
1263  * @param dev
1264  *   Pointer to Ethernet device structure.
1265  */
1266 static void
1267 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1268 {
1269         if (!dev->process_private)
1270                 return;
1271         rte_free(dev->process_private);
1272         dev->process_private = NULL;
1273 }
1274
1275 /**
1276  * DPDK callback to close the device.
1277  *
1278  * Destroy all queues and objects, free memory.
1279  *
1280  * @param dev
1281  *   Pointer to Ethernet device structure.
1282  */
1283 static void
1284 mlx5_dev_close(struct rte_eth_dev *dev)
1285 {
1286         struct mlx5_priv *priv = dev->data->dev_private;
1287         unsigned int i;
1288         int ret;
1289
1290         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1291                 dev->data->port_id,
1292                 ((priv->sh->ctx != NULL) ? priv->sh->ctx->device->name : ""));
1293         /* In case mlx5_dev_stop() has not been called. */
1294         mlx5_dev_interrupt_handler_uninstall(dev);
1295         mlx5_dev_interrupt_handler_devx_uninstall(dev);
1296         /*
1297          * If default mreg copy action is removed at the stop stage,
1298          * the search will return none and nothing will be done anymore.
1299          */
1300         mlx5_flow_stop_default(dev);
1301         mlx5_traffic_disable(dev);
1302         /*
1303          * If all the flows are already flushed in the device stop stage,
1304          * then this will return directly without any action.
1305          */
1306         mlx5_flow_list_flush(dev, &priv->flows, true);
1307         mlx5_flow_meter_flush(dev, NULL);
1308         /* Free the intermediate buffers for flow creation. */
1309         mlx5_flow_free_intermediate(dev);
1310         /* Prevent crashes when queues are still in use. */
1311         dev->rx_pkt_burst = removed_rx_burst;
1312         dev->tx_pkt_burst = removed_tx_burst;
1313         rte_wmb();
1314         /* Disable datapath on secondary process. */
1315         mlx5_mp_req_stop_rxtx(dev);
1316         if (priv->rxqs != NULL) {
1317                 /* XXX race condition if mlx5_rx_burst() is still running. */
1318                 usleep(1000);
1319                 for (i = 0; (i != priv->rxqs_n); ++i)
1320                         mlx5_rxq_release(dev, i);
1321                 priv->rxqs_n = 0;
1322                 priv->rxqs = NULL;
1323         }
1324         if (priv->txqs != NULL) {
1325                 /* XXX race condition if mlx5_tx_burst() is still running. */
1326                 usleep(1000);
1327                 for (i = 0; (i != priv->txqs_n); ++i)
1328                         mlx5_txq_release(dev, i);
1329                 priv->txqs_n = 0;
1330                 priv->txqs = NULL;
1331         }
1332         mlx5_proc_priv_uninit(dev);
1333         if (priv->mreg_cp_tbl)
1334                 mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
1335         mlx5_mprq_free_mp(dev);
1336         mlx5_free_shared_dr(priv);
1337         if (priv->rss_conf.rss_key != NULL)
1338                 rte_free(priv->rss_conf.rss_key);
1339         if (priv->reta_idx != NULL)
1340                 rte_free(priv->reta_idx);
1341         if (priv->config.vf)
1342                 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev),
1343                                        dev->data->mac_addrs,
1344                                        MLX5_MAX_MAC_ADDRESSES, priv->mac_own);
1345         if (priv->nl_socket_route >= 0)
1346                 close(priv->nl_socket_route);
1347         if (priv->nl_socket_rdma >= 0)
1348                 close(priv->nl_socket_rdma);
1349         if (priv->vmwa_context)
1350                 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1351         if (priv->sh) {
1352                 /*
1353                  * Free the shared context in last turn, because the cleanup
1354                  * routines above may use some shared fields, like
1355                  * mlx5_nl_mac_addr_flush() uses ibdev_path for retrieveing
1356                  * ifindex if Netlink fails.
1357                  */
1358                 mlx5_free_shared_ibctx(priv->sh);
1359                 priv->sh = NULL;
1360         }
1361         ret = mlx5_hrxq_verify(dev);
1362         if (ret)
1363                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1364                         dev->data->port_id);
1365         ret = mlx5_ind_table_obj_verify(dev);
1366         if (ret)
1367                 DRV_LOG(WARNING, "port %u some indirection table still remain",
1368                         dev->data->port_id);
1369         ret = mlx5_rxq_obj_verify(dev);
1370         if (ret)
1371                 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1372                         dev->data->port_id);
1373         ret = mlx5_rxq_verify(dev);
1374         if (ret)
1375                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1376                         dev->data->port_id);
1377         ret = mlx5_txq_obj_verify(dev);
1378         if (ret)
1379                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1380                         dev->data->port_id);
1381         ret = mlx5_txq_verify(dev);
1382         if (ret)
1383                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1384                         dev->data->port_id);
1385         ret = mlx5_flow_verify(dev);
1386         if (ret)
1387                 DRV_LOG(WARNING, "port %u some flows still remain",
1388                         dev->data->port_id);
1389         if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1390                 unsigned int c = 0;
1391                 uint16_t port_id;
1392
1393                 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1394                         struct mlx5_priv *opriv =
1395                                 rte_eth_devices[port_id].data->dev_private;
1396
1397                         if (!opriv ||
1398                             opriv->domain_id != priv->domain_id ||
1399                             &rte_eth_devices[port_id] == dev)
1400                                 continue;
1401                         ++c;
1402                         break;
1403                 }
1404                 if (!c)
1405                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1406         }
1407         memset(priv, 0, sizeof(*priv));
1408         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1409         /*
1410          * Reset mac_addrs to NULL such that it is not freed as part of
1411          * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1412          * it is freed when dev_private is freed.
1413          */
1414         dev->data->mac_addrs = NULL;
1415 }
1416
1417 const struct eth_dev_ops mlx5_dev_ops = {
1418         .dev_configure = mlx5_dev_configure,
1419         .dev_start = mlx5_dev_start,
1420         .dev_stop = mlx5_dev_stop,
1421         .dev_set_link_down = mlx5_set_link_down,
1422         .dev_set_link_up = mlx5_set_link_up,
1423         .dev_close = mlx5_dev_close,
1424         .promiscuous_enable = mlx5_promiscuous_enable,
1425         .promiscuous_disable = mlx5_promiscuous_disable,
1426         .allmulticast_enable = mlx5_allmulticast_enable,
1427         .allmulticast_disable = mlx5_allmulticast_disable,
1428         .link_update = mlx5_link_update,
1429         .stats_get = mlx5_stats_get,
1430         .stats_reset = mlx5_stats_reset,
1431         .xstats_get = mlx5_xstats_get,
1432         .xstats_reset = mlx5_xstats_reset,
1433         .xstats_get_names = mlx5_xstats_get_names,
1434         .fw_version_get = mlx5_fw_version_get,
1435         .dev_infos_get = mlx5_dev_infos_get,
1436         .read_clock = mlx5_read_clock,
1437         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1438         .vlan_filter_set = mlx5_vlan_filter_set,
1439         .rx_queue_setup = mlx5_rx_queue_setup,
1440         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1441         .tx_queue_setup = mlx5_tx_queue_setup,
1442         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1443         .rx_queue_release = mlx5_rx_queue_release,
1444         .tx_queue_release = mlx5_tx_queue_release,
1445         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1446         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1447         .mac_addr_remove = mlx5_mac_addr_remove,
1448         .mac_addr_add = mlx5_mac_addr_add,
1449         .mac_addr_set = mlx5_mac_addr_set,
1450         .set_mc_addr_list = mlx5_set_mc_addr_list,
1451         .mtu_set = mlx5_dev_set_mtu,
1452         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1453         .vlan_offload_set = mlx5_vlan_offload_set,
1454         .reta_update = mlx5_dev_rss_reta_update,
1455         .reta_query = mlx5_dev_rss_reta_query,
1456         .rss_hash_update = mlx5_rss_hash_update,
1457         .rss_hash_conf_get = mlx5_rss_hash_conf_get,
1458         .filter_ctrl = mlx5_dev_filter_ctrl,
1459         .rx_descriptor_status = mlx5_rx_descriptor_status,
1460         .tx_descriptor_status = mlx5_tx_descriptor_status,
1461         .rxq_info_get = mlx5_rxq_info_get,
1462         .txq_info_get = mlx5_txq_info_get,
1463         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1464         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1465         .rx_queue_count = mlx5_rx_queue_count,
1466         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1467         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1468         .is_removed = mlx5_is_removed,
1469         .udp_tunnel_port_add  = mlx5_udp_tunnel_port_add,
1470         .get_module_info = mlx5_get_module_info,
1471         .get_module_eeprom = mlx5_get_module_eeprom,
1472         .hairpin_cap_get = mlx5_hairpin_cap_get,
1473         .mtr_ops_get = mlx5_flow_meter_ops_get,
1474 };
1475
1476 /* Available operations from secondary process. */
1477 static const struct eth_dev_ops mlx5_dev_sec_ops = {
1478         .stats_get = mlx5_stats_get,
1479         .stats_reset = mlx5_stats_reset,
1480         .xstats_get = mlx5_xstats_get,
1481         .xstats_reset = mlx5_xstats_reset,
1482         .xstats_get_names = mlx5_xstats_get_names,
1483         .fw_version_get = mlx5_fw_version_get,
1484         .dev_infos_get = mlx5_dev_infos_get,
1485         .rx_descriptor_status = mlx5_rx_descriptor_status,
1486         .tx_descriptor_status = mlx5_tx_descriptor_status,
1487         .rxq_info_get = mlx5_rxq_info_get,
1488         .txq_info_get = mlx5_txq_info_get,
1489         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1490         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1491         .get_module_info = mlx5_get_module_info,
1492         .get_module_eeprom = mlx5_get_module_eeprom,
1493 };
1494
1495 /* Available operations in flow isolated mode. */
1496 const struct eth_dev_ops mlx5_dev_ops_isolate = {
1497         .dev_configure = mlx5_dev_configure,
1498         .dev_start = mlx5_dev_start,
1499         .dev_stop = mlx5_dev_stop,
1500         .dev_set_link_down = mlx5_set_link_down,
1501         .dev_set_link_up = mlx5_set_link_up,
1502         .dev_close = mlx5_dev_close,
1503         .promiscuous_enable = mlx5_promiscuous_enable,
1504         .promiscuous_disable = mlx5_promiscuous_disable,
1505         .allmulticast_enable = mlx5_allmulticast_enable,
1506         .allmulticast_disable = mlx5_allmulticast_disable,
1507         .link_update = mlx5_link_update,
1508         .stats_get = mlx5_stats_get,
1509         .stats_reset = mlx5_stats_reset,
1510         .xstats_get = mlx5_xstats_get,
1511         .xstats_reset = mlx5_xstats_reset,
1512         .xstats_get_names = mlx5_xstats_get_names,
1513         .fw_version_get = mlx5_fw_version_get,
1514         .dev_infos_get = mlx5_dev_infos_get,
1515         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1516         .vlan_filter_set = mlx5_vlan_filter_set,
1517         .rx_queue_setup = mlx5_rx_queue_setup,
1518         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1519         .tx_queue_setup = mlx5_tx_queue_setup,
1520         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1521         .rx_queue_release = mlx5_rx_queue_release,
1522         .tx_queue_release = mlx5_tx_queue_release,
1523         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1524         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1525         .mac_addr_remove = mlx5_mac_addr_remove,
1526         .mac_addr_add = mlx5_mac_addr_add,
1527         .mac_addr_set = mlx5_mac_addr_set,
1528         .set_mc_addr_list = mlx5_set_mc_addr_list,
1529         .mtu_set = mlx5_dev_set_mtu,
1530         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1531         .vlan_offload_set = mlx5_vlan_offload_set,
1532         .filter_ctrl = mlx5_dev_filter_ctrl,
1533         .rx_descriptor_status = mlx5_rx_descriptor_status,
1534         .tx_descriptor_status = mlx5_tx_descriptor_status,
1535         .rxq_info_get = mlx5_rxq_info_get,
1536         .txq_info_get = mlx5_txq_info_get,
1537         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1538         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1539         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1540         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1541         .is_removed = mlx5_is_removed,
1542         .get_module_info = mlx5_get_module_info,
1543         .get_module_eeprom = mlx5_get_module_eeprom,
1544         .hairpin_cap_get = mlx5_hairpin_cap_get,
1545         .mtr_ops_get = mlx5_flow_meter_ops_get,
1546 };
1547
1548 /**
1549  * Verify and store value for device argument.
1550  *
1551  * @param[in] key
1552  *   Key argument to verify.
1553  * @param[in] val
1554  *   Value associated with key.
1555  * @param opaque
1556  *   User data.
1557  *
1558  * @return
1559  *   0 on success, a negative errno value otherwise and rte_errno is set.
1560  */
1561 static int
1562 mlx5_args_check(const char *key, const char *val, void *opaque)
1563 {
1564         struct mlx5_dev_config *config = opaque;
1565         unsigned long tmp;
1566
1567         /* No-op, port representors are processed in mlx5_dev_spawn(). */
1568         if (!strcmp(MLX5_REPRESENTOR, key))
1569                 return 0;
1570         errno = 0;
1571         tmp = strtoul(val, NULL, 0);
1572         if (errno) {
1573                 rte_errno = errno;
1574                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1575                 return -rte_errno;
1576         }
1577         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1578                 config->cqe_comp = !!tmp;
1579         } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
1580                 config->cqe_pad = !!tmp;
1581         } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1582                 config->hw_padding = !!tmp;
1583         } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1584                 config->mprq.enabled = !!tmp;
1585         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1586                 config->mprq.stride_num_n = tmp;
1587         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1588                 config->mprq.stride_size_n = tmp;
1589         } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1590                 config->mprq.max_memcpy_len = tmp;
1591         } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1592                 config->mprq.min_rxqs_num = tmp;
1593         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1594                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1595                                  " converted to txq_inline_max", key);
1596                 config->txq_inline_max = tmp;
1597         } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1598                 config->txq_inline_max = tmp;
1599         } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1600                 config->txq_inline_min = tmp;
1601         } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1602                 config->txq_inline_mpw = tmp;
1603         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1604                 config->txqs_inline = tmp;
1605         } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1606                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1607         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1608                 config->mps = !!tmp;
1609         } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1610                 if (tmp != MLX5_TXDB_CACHED &&
1611                     tmp != MLX5_TXDB_NCACHED &&
1612                     tmp != MLX5_TXDB_HEURISTIC) {
1613                         DRV_LOG(ERR, "invalid Tx doorbell "
1614                                      "mapping parameter");
1615                         rte_errno = EINVAL;
1616                         return -rte_errno;
1617                 }
1618                 config->dbnc = tmp;
1619         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1620                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1621         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1622                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1623                                  " converted to txq_inline_mpw", key);
1624                 config->txq_inline_mpw = tmp;
1625         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1626                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1627         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1628                 config->rx_vec_en = !!tmp;
1629         } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1630                 config->l3_vxlan_en = !!tmp;
1631         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1632                 config->vf_nl_en = !!tmp;
1633         } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1634                 config->dv_esw_en = !!tmp;
1635         } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1636                 config->dv_flow_en = !!tmp;
1637         } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1638                 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1639                     tmp != MLX5_XMETA_MODE_META16 &&
1640                     tmp != MLX5_XMETA_MODE_META32) {
1641                         DRV_LOG(ERR, "invalid extensive "
1642                                      "metadata parameter");
1643                         rte_errno = EINVAL;
1644                         return -rte_errno;
1645                 }
1646                 config->dv_xmeta_en = tmp;
1647         } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1648                 config->mr_ext_memseg_en = !!tmp;
1649         } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1650                 config->max_dump_files_num = tmp;
1651         } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1652                 config->lro.timeout = tmp;
1653         } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1654                 DRV_LOG(DEBUG, "class argument is %s.", val);
1655         } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1656                 config->log_hp_size = tmp;
1657         } else {
1658                 DRV_LOG(WARNING, "%s: unknown parameter", key);
1659                 rte_errno = EINVAL;
1660                 return -rte_errno;
1661         }
1662         return 0;
1663 }
1664
1665 /**
1666  * Parse device parameters.
1667  *
1668  * @param config
1669  *   Pointer to device configuration structure.
1670  * @param devargs
1671  *   Device arguments structure.
1672  *
1673  * @return
1674  *   0 on success, a negative errno value otherwise and rte_errno is set.
1675  */
1676 static int
1677 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1678 {
1679         const char **params = (const char *[]){
1680                 MLX5_RXQ_CQE_COMP_EN,
1681                 MLX5_RXQ_CQE_PAD_EN,
1682                 MLX5_RXQ_PKT_PAD_EN,
1683                 MLX5_RX_MPRQ_EN,
1684                 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1685                 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1686                 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1687                 MLX5_RXQS_MIN_MPRQ,
1688                 MLX5_TXQ_INLINE,
1689                 MLX5_TXQ_INLINE_MIN,
1690                 MLX5_TXQ_INLINE_MAX,
1691                 MLX5_TXQ_INLINE_MPW,
1692                 MLX5_TXQS_MIN_INLINE,
1693                 MLX5_TXQS_MAX_VEC,
1694                 MLX5_TXQ_MPW_EN,
1695                 MLX5_TXQ_MPW_HDR_DSEG_EN,
1696                 MLX5_TXQ_MAX_INLINE_LEN,
1697                 MLX5_TX_DB_NC,
1698                 MLX5_TX_VEC_EN,
1699                 MLX5_RX_VEC_EN,
1700                 MLX5_L3_VXLAN_EN,
1701                 MLX5_VF_NL_EN,
1702                 MLX5_DV_ESW_EN,
1703                 MLX5_DV_FLOW_EN,
1704                 MLX5_DV_XMETA_EN,
1705                 MLX5_MR_EXT_MEMSEG_EN,
1706                 MLX5_REPRESENTOR,
1707                 MLX5_MAX_DUMP_FILES_NUM,
1708                 MLX5_LRO_TIMEOUT_USEC,
1709                 MLX5_CLASS_ARG_NAME,
1710                 MLX5_HP_BUF_SIZE,
1711                 NULL,
1712         };
1713         struct rte_kvargs *kvlist;
1714         int ret = 0;
1715         int i;
1716
1717         if (devargs == NULL)
1718                 return 0;
1719         /* Following UGLY cast is done to pass checkpatch. */
1720         kvlist = rte_kvargs_parse(devargs->args, params);
1721         if (kvlist == NULL) {
1722                 rte_errno = EINVAL;
1723                 return -rte_errno;
1724         }
1725         /* Process parameters. */
1726         for (i = 0; (params[i] != NULL); ++i) {
1727                 if (rte_kvargs_count(kvlist, params[i])) {
1728                         ret = rte_kvargs_process(kvlist, params[i],
1729                                                  mlx5_args_check, config);
1730                         if (ret) {
1731                                 rte_errno = EINVAL;
1732                                 rte_kvargs_free(kvlist);
1733                                 return -rte_errno;
1734                         }
1735                 }
1736         }
1737         rte_kvargs_free(kvlist);
1738         return 0;
1739 }
1740
1741 static struct rte_pci_driver mlx5_driver;
1742
1743 /**
1744  * PMD global initialization.
1745  *
1746  * Independent from individual device, this function initializes global
1747  * per-PMD data structures distinguishing primary and secondary processes.
1748  * Hence, each initialization is called once per a process.
1749  *
1750  * @return
1751  *   0 on success, a negative errno value otherwise and rte_errno is set.
1752  */
1753 static int
1754 mlx5_init_once(void)
1755 {
1756         struct mlx5_shared_data *sd;
1757         struct mlx5_local_data *ld = &mlx5_local_data;
1758         int ret = 0;
1759
1760         if (mlx5_init_shared_data())
1761                 return -rte_errno;
1762         sd = mlx5_shared_data;
1763         MLX5_ASSERT(sd);
1764         rte_spinlock_lock(&sd->lock);
1765         switch (rte_eal_process_type()) {
1766         case RTE_PROC_PRIMARY:
1767                 if (sd->init_done)
1768                         break;
1769                 LIST_INIT(&sd->mem_event_cb_list);
1770                 rte_rwlock_init(&sd->mem_event_rwlock);
1771                 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
1772                                                 mlx5_mr_mem_event_cb, NULL);
1773                 ret = mlx5_mp_init_primary(MLX5_MP_NAME,
1774                                            mlx5_mp_primary_handle);
1775                 if (ret)
1776                         goto out;
1777                 sd->init_done = true;
1778                 break;
1779         case RTE_PROC_SECONDARY:
1780                 if (ld->init_done)
1781                         break;
1782                 ret = mlx5_mp_init_secondary(MLX5_MP_NAME,
1783                                              mlx5_mp_secondary_handle);
1784                 if (ret)
1785                         goto out;
1786                 ++sd->secondary_cnt;
1787                 ld->init_done = true;
1788                 break;
1789         default:
1790                 break;
1791         }
1792 out:
1793         rte_spinlock_unlock(&sd->lock);
1794         return ret;
1795 }
1796
1797 /**
1798  * Configures the minimal amount of data to inline into WQE
1799  * while sending packets.
1800  *
1801  * - the txq_inline_min has the maximal priority, if this
1802  *   key is specified in devargs
1803  * - if DevX is enabled the inline mode is queried from the
1804  *   device (HCA attributes and NIC vport context if needed).
1805  * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1806  *   and none (0 bytes) for other NICs
1807  *
1808  * @param spawn
1809  *   Verbs device parameters (name, port, switch_info) to spawn.
1810  * @param config
1811  *   Device configuration parameters.
1812  */
1813 static void
1814 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1815                     struct mlx5_dev_config *config)
1816 {
1817         if (config->txq_inline_min != MLX5_ARG_UNSET) {
1818                 /* Application defines size of inlined data explicitly. */
1819                 switch (spawn->pci_dev->id.device_id) {
1820                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1821                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1822                         if (config->txq_inline_min <
1823                                        (int)MLX5_INLINE_HSIZE_L2) {
1824                                 DRV_LOG(DEBUG,
1825                                         "txq_inline_mix aligned to minimal"
1826                                         " ConnectX-4 required value %d",
1827                                         (int)MLX5_INLINE_HSIZE_L2);
1828                                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1829                         }
1830                         break;
1831                 }
1832                 goto exit;
1833         }
1834         if (config->hca_attr.eth_net_offloads) {
1835                 /* We have DevX enabled, inline mode queried successfully. */
1836                 switch (config->hca_attr.wqe_inline_mode) {
1837                 case MLX5_CAP_INLINE_MODE_L2:
1838                         /* outer L2 header must be inlined. */
1839                         config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1840                         goto exit;
1841                 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1842                         /* No inline data are required by NIC. */
1843                         config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1844                         config->hw_vlan_insert =
1845                                 config->hca_attr.wqe_vlan_insert;
1846                         DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1847                         goto exit;
1848                 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1849                         /* inline mode is defined by NIC vport context. */
1850                         if (!config->hca_attr.eth_virt)
1851                                 break;
1852                         switch (config->hca_attr.vport_inline_mode) {
1853                         case MLX5_INLINE_MODE_NONE:
1854                                 config->txq_inline_min =
1855                                         MLX5_INLINE_HSIZE_NONE;
1856                                 goto exit;
1857                         case MLX5_INLINE_MODE_L2:
1858                                 config->txq_inline_min =
1859                                         MLX5_INLINE_HSIZE_L2;
1860                                 goto exit;
1861                         case MLX5_INLINE_MODE_IP:
1862                                 config->txq_inline_min =
1863                                         MLX5_INLINE_HSIZE_L3;
1864                                 goto exit;
1865                         case MLX5_INLINE_MODE_TCP_UDP:
1866                                 config->txq_inline_min =
1867                                         MLX5_INLINE_HSIZE_L4;
1868                                 goto exit;
1869                         case MLX5_INLINE_MODE_INNER_L2:
1870                                 config->txq_inline_min =
1871                                         MLX5_INLINE_HSIZE_INNER_L2;
1872                                 goto exit;
1873                         case MLX5_INLINE_MODE_INNER_IP:
1874                                 config->txq_inline_min =
1875                                         MLX5_INLINE_HSIZE_INNER_L3;
1876                                 goto exit;
1877                         case MLX5_INLINE_MODE_INNER_TCP_UDP:
1878                                 config->txq_inline_min =
1879                                         MLX5_INLINE_HSIZE_INNER_L4;
1880                                 goto exit;
1881                         }
1882                 }
1883         }
1884         /*
1885          * We get here if we are unable to deduce
1886          * inline data size with DevX. Try PCI ID
1887          * to determine old NICs.
1888          */
1889         switch (spawn->pci_dev->id.device_id) {
1890         case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1891         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1892         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
1893         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1894                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1895                 config->hw_vlan_insert = 0;
1896                 break;
1897         case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
1898         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1899         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
1900         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1901                 /*
1902                  * These NICs support VLAN insertion from WQE and
1903                  * report the wqe_vlan_insert flag. But there is the bug
1904                  * and PFC control may be broken, so disable feature.
1905                  */
1906                 config->hw_vlan_insert = 0;
1907                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1908                 break;
1909         default:
1910                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1911                 break;
1912         }
1913 exit:
1914         DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
1915 }
1916
1917 /**
1918  * Configures the metadata mask fields in the shared context.
1919  *
1920  * @param [in] dev
1921  *   Pointer to Ethernet device.
1922  */
1923 static void
1924 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
1925 {
1926         struct mlx5_priv *priv = dev->data->dev_private;
1927         struct mlx5_ibv_shared *sh = priv->sh;
1928         uint32_t meta, mark, reg_c0;
1929
1930         reg_c0 = ~priv->vport_meta_mask;
1931         switch (priv->config.dv_xmeta_en) {
1932         case MLX5_XMETA_MODE_LEGACY:
1933                 meta = UINT32_MAX;
1934                 mark = MLX5_FLOW_MARK_MASK;
1935                 break;
1936         case MLX5_XMETA_MODE_META16:
1937                 meta = reg_c0 >> rte_bsf32(reg_c0);
1938                 mark = MLX5_FLOW_MARK_MASK;
1939                 break;
1940         case MLX5_XMETA_MODE_META32:
1941                 meta = UINT32_MAX;
1942                 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
1943                 break;
1944         default:
1945                 meta = 0;
1946                 mark = 0;
1947                 MLX5_ASSERT(false);
1948                 break;
1949         }
1950         if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
1951                 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
1952                                  sh->dv_mark_mask, mark);
1953         else
1954                 sh->dv_mark_mask = mark;
1955         if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
1956                 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
1957                                  sh->dv_meta_mask, meta);
1958         else
1959                 sh->dv_meta_mask = meta;
1960         if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
1961                 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
1962                                  sh->dv_meta_mask, reg_c0);
1963         else
1964                 sh->dv_regc0_mask = reg_c0;
1965         DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
1966         DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
1967         DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
1968         DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
1969 }
1970
1971 /**
1972  * Allocate page of door-bells and register it using DevX API.
1973  *
1974  * @param [in] dev
1975  *   Pointer to Ethernet device.
1976  *
1977  * @return
1978  *   Pointer to new page on success, NULL otherwise.
1979  */
1980 static struct mlx5_devx_dbr_page *
1981 mlx5_alloc_dbr_page(struct rte_eth_dev *dev)
1982 {
1983         struct mlx5_priv *priv = dev->data->dev_private;
1984         struct mlx5_devx_dbr_page *page;
1985
1986         /* Allocate space for door-bell page and management data. */
1987         page = rte_calloc_socket(__func__, 1, sizeof(struct mlx5_devx_dbr_page),
1988                                  RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1989         if (!page) {
1990                 DRV_LOG(ERR, "port %u cannot allocate dbr page",
1991                         dev->data->port_id);
1992                 return NULL;
1993         }
1994         /* Register allocated memory. */
1995         page->umem = mlx5_glue->devx_umem_reg(priv->sh->ctx, page->dbrs,
1996                                               MLX5_DBR_PAGE_SIZE, 0);
1997         if (!page->umem) {
1998                 DRV_LOG(ERR, "port %u cannot umem reg dbr page",
1999                         dev->data->port_id);
2000                 rte_free(page);
2001                 return NULL;
2002         }
2003         return page;
2004 }
2005
2006 /**
2007  * Find the next available door-bell, allocate new page if needed.
2008  *
2009  * @param [in] dev
2010  *   Pointer to Ethernet device.
2011  * @param [out] dbr_page
2012  *   Door-bell page containing the page data.
2013  *
2014  * @return
2015  *   Door-bell address offset on success, a negative error value otherwise.
2016  */
2017 int64_t
2018 mlx5_get_dbr(struct rte_eth_dev *dev, struct mlx5_devx_dbr_page **dbr_page)
2019 {
2020         struct mlx5_priv *priv = dev->data->dev_private;
2021         struct mlx5_devx_dbr_page *page = NULL;
2022         uint32_t i, j;
2023
2024         LIST_FOREACH(page, &priv->dbrpgs, next)
2025                 if (page->dbr_count < MLX5_DBR_PER_PAGE)
2026                         break;
2027         if (!page) { /* No page with free door-bell exists. */
2028                 page = mlx5_alloc_dbr_page(dev);
2029                 if (!page) /* Failed to allocate new page. */
2030                         return (-1);
2031                 LIST_INSERT_HEAD(&priv->dbrpgs, page, next);
2032         }
2033         /* Loop to find bitmap part with clear bit. */
2034         for (i = 0;
2035              i < MLX5_DBR_BITMAP_SIZE && page->dbr_bitmap[i] == UINT64_MAX;
2036              i++)
2037                 ; /* Empty. */
2038         /* Find the first clear bit. */
2039         j = rte_bsf64(~page->dbr_bitmap[i]);
2040         MLX5_ASSERT(i < (MLX5_DBR_PER_PAGE / 64));
2041         page->dbr_bitmap[i] |= (1 << j);
2042         page->dbr_count++;
2043         *dbr_page = page;
2044         return (((i * 64) + j) * sizeof(uint64_t));
2045 }
2046
2047 /**
2048  * Release a door-bell record.
2049  *
2050  * @param [in] dev
2051  *   Pointer to Ethernet device.
2052  * @param [in] umem_id
2053  *   UMEM ID of page containing the door-bell record to release.
2054  * @param [in] offset
2055  *   Offset of door-bell record in page.
2056  *
2057  * @return
2058  *   0 on success, a negative error value otherwise.
2059  */
2060 int32_t
2061 mlx5_release_dbr(struct rte_eth_dev *dev, uint32_t umem_id, uint64_t offset)
2062 {
2063         struct mlx5_priv *priv = dev->data->dev_private;
2064         struct mlx5_devx_dbr_page *page = NULL;
2065         int ret = 0;
2066
2067         LIST_FOREACH(page, &priv->dbrpgs, next)
2068                 /* Find the page this address belongs to. */
2069                 if (page->umem->umem_id == umem_id)
2070                         break;
2071         if (!page)
2072                 return -EINVAL;
2073         page->dbr_count--;
2074         if (!page->dbr_count) {
2075                 /* Page not used, free it and remove from list. */
2076                 LIST_REMOVE(page, next);
2077                 if (page->umem)
2078                         ret = -mlx5_glue->devx_umem_dereg(page->umem);
2079                 rte_free(page);
2080         } else {
2081                 /* Mark in bitmap that this door-bell is not in use. */
2082                 offset /= MLX5_DBR_SIZE;
2083                 int i = offset / 64;
2084                 int j = offset % 64;
2085
2086                 page->dbr_bitmap[i] &= ~(1 << j);
2087         }
2088         return ret;
2089 }
2090
2091 int
2092 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
2093 {
2094         static const char *const dynf_names[] = {
2095                 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
2096                 RTE_MBUF_DYNFLAG_METADATA_NAME
2097         };
2098         unsigned int i;
2099
2100         if (n < RTE_DIM(dynf_names))
2101                 return -ENOMEM;
2102         for (i = 0; i < RTE_DIM(dynf_names); i++) {
2103                 if (names[i] == NULL)
2104                         return -EINVAL;
2105                 strcpy(names[i], dynf_names[i]);
2106         }
2107         return RTE_DIM(dynf_names);
2108 }
2109
2110 /**
2111  * Check sibling device configurations.
2112  *
2113  * Sibling devices sharing the Infiniband device context
2114  * should have compatible configurations. This regards
2115  * representors and bonding slaves.
2116  *
2117  * @param priv
2118  *   Private device descriptor.
2119  * @param config
2120  *   Configuration of the device is going to be created.
2121  *
2122  * @return
2123  *   0 on success, EINVAL otherwise
2124  */
2125 static int
2126 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
2127                               struct mlx5_dev_config *config)
2128 {
2129         struct mlx5_ibv_shared *sh = priv->sh;
2130         struct mlx5_dev_config *sh_conf = NULL;
2131         uint16_t port_id;
2132
2133         MLX5_ASSERT(sh);
2134         /* Nothing to compare for the single/first device. */
2135         if (sh->refcnt == 1)
2136                 return 0;
2137         /* Find the device with shared context. */
2138         MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
2139                 struct mlx5_priv *opriv =
2140                         rte_eth_devices[port_id].data->dev_private;
2141
2142                 if (opriv && opriv != priv && opriv->sh == sh) {
2143                         sh_conf = &opriv->config;
2144                         break;
2145                 }
2146         }
2147         if (!sh_conf)
2148                 return 0;
2149         if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
2150                 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
2151                              " for shared %s context", sh->ibdev_name);
2152                 rte_errno = EINVAL;
2153                 return rte_errno;
2154         }
2155         if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
2156                 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
2157                              " for shared %s context", sh->ibdev_name);
2158                 rte_errno = EINVAL;
2159                 return rte_errno;
2160         }
2161         return 0;
2162 }
2163 /**
2164  * Spawn an Ethernet device from Verbs information.
2165  *
2166  * @param dpdk_dev
2167  *   Backing DPDK device.
2168  * @param spawn
2169  *   Verbs device parameters (name, port, switch_info) to spawn.
2170  * @param config
2171  *   Device configuration parameters.
2172  *
2173  * @return
2174  *   A valid Ethernet device object on success, NULL otherwise and rte_errno
2175  *   is set. The following errors are defined:
2176  *
2177  *   EBUSY: device is not supposed to be spawned.
2178  *   EEXIST: device is already spawned
2179  */
2180 static struct rte_eth_dev *
2181 mlx5_dev_spawn(struct rte_device *dpdk_dev,
2182                struct mlx5_dev_spawn_data *spawn,
2183                struct mlx5_dev_config config)
2184 {
2185         const struct mlx5_switch_info *switch_info = &spawn->info;
2186         struct mlx5_ibv_shared *sh = NULL;
2187         struct ibv_port_attr port_attr;
2188         struct mlx5dv_context dv_attr = { .comp_mask = 0 };
2189         struct rte_eth_dev *eth_dev = NULL;
2190         struct mlx5_priv *priv = NULL;
2191         int err = 0;
2192         unsigned int hw_padding = 0;
2193         unsigned int mps;
2194         unsigned int cqe_comp;
2195         unsigned int cqe_pad = 0;
2196         unsigned int tunnel_en = 0;
2197         unsigned int mpls_en = 0;
2198         unsigned int swp = 0;
2199         unsigned int mprq = 0;
2200         unsigned int mprq_min_stride_size_n = 0;
2201         unsigned int mprq_max_stride_size_n = 0;
2202         unsigned int mprq_min_stride_num_n = 0;
2203         unsigned int mprq_max_stride_num_n = 0;
2204         struct rte_ether_addr mac;
2205         char name[RTE_ETH_NAME_MAX_LEN];
2206         int own_domain_id = 0;
2207         uint16_t port_id;
2208         unsigned int i;
2209 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
2210         struct mlx5dv_devx_port devx_port = { .comp_mask = 0 };
2211 #endif
2212
2213         /* Determine if this port representor is supposed to be spawned. */
2214         if (switch_info->representor && dpdk_dev->devargs) {
2215                 struct rte_eth_devargs eth_da;
2216
2217                 err = rte_eth_devargs_parse(dpdk_dev->devargs->args, &eth_da);
2218                 if (err) {
2219                         rte_errno = -err;
2220                         DRV_LOG(ERR, "failed to process device arguments: %s",
2221                                 strerror(rte_errno));
2222                         return NULL;
2223                 }
2224                 for (i = 0; i < eth_da.nb_representor_ports; ++i)
2225                         if (eth_da.representor_ports[i] ==
2226                             (uint16_t)switch_info->port_name)
2227                                 break;
2228                 if (i == eth_da.nb_representor_ports) {
2229                         rte_errno = EBUSY;
2230                         return NULL;
2231                 }
2232         }
2233         /* Build device name. */
2234         if (spawn->pf_bond <  0) {
2235                 /* Single device. */
2236                 if (!switch_info->representor)
2237                         strlcpy(name, dpdk_dev->name, sizeof(name));
2238                 else
2239                         snprintf(name, sizeof(name), "%s_representor_%u",
2240                                  dpdk_dev->name, switch_info->port_name);
2241         } else {
2242                 /* Bonding device. */
2243                 if (!switch_info->representor)
2244                         snprintf(name, sizeof(name), "%s_%s",
2245                                  dpdk_dev->name, spawn->ibv_dev->name);
2246                 else
2247                         snprintf(name, sizeof(name), "%s_%s_representor_%u",
2248                                  dpdk_dev->name, spawn->ibv_dev->name,
2249                                  switch_info->port_name);
2250         }
2251         /* check if the device is already spawned */
2252         if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) {
2253                 rte_errno = EEXIST;
2254                 return NULL;
2255         }
2256         DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name);
2257         if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
2258                 struct mlx5_mp_id mp_id;
2259
2260                 eth_dev = rte_eth_dev_attach_secondary(name);
2261                 if (eth_dev == NULL) {
2262                         DRV_LOG(ERR, "can not attach rte ethdev");
2263                         rte_errno = ENOMEM;
2264                         return NULL;
2265                 }
2266                 eth_dev->device = dpdk_dev;
2267                 eth_dev->dev_ops = &mlx5_dev_sec_ops;
2268                 err = mlx5_proc_priv_init(eth_dev);
2269                 if (err)
2270                         return NULL;
2271                 mp_id.port_id = eth_dev->data->port_id;
2272                 strlcpy(mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN);
2273                 /* Receive command fd from primary process */
2274                 err = mlx5_mp_req_verbs_cmd_fd(&mp_id);
2275                 if (err < 0)
2276                         return NULL;
2277                 /* Remap UAR for Tx queues. */
2278                 err = mlx5_tx_uar_init_secondary(eth_dev, err);
2279                 if (err)
2280                         return NULL;
2281                 /*
2282                  * Ethdev pointer is still required as input since
2283                  * the primary device is not accessible from the
2284                  * secondary process.
2285                  */
2286                 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev);
2287                 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev);
2288                 return eth_dev;
2289         }
2290         /*
2291          * Some parameters ("tx_db_nc" in particularly) are needed in
2292          * advance to create dv/verbs device context. We proceed the
2293          * devargs here to get ones, and later proceed devargs again
2294          * to override some hardware settings.
2295          */
2296         err = mlx5_args(&config, dpdk_dev->devargs);
2297         if (err) {
2298                 err = rte_errno;
2299                 DRV_LOG(ERR, "failed to process device arguments: %s",
2300                         strerror(rte_errno));
2301                 goto error;
2302         }
2303         sh = mlx5_alloc_shared_ibctx(spawn, &config);
2304         if (!sh)
2305                 return NULL;
2306         config.devx = sh->devx;
2307 #ifdef HAVE_MLX5DV_DR_ACTION_DEST_DEVX_TIR
2308         config.dest_tir = 1;
2309 #endif
2310 #ifdef HAVE_IBV_MLX5_MOD_SWP
2311         dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP;
2312 #endif
2313         /*
2314          * Multi-packet send is supported by ConnectX-4 Lx PF as well
2315          * as all ConnectX-5 devices.
2316          */
2317 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
2318         dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS;
2319 #endif
2320 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
2321         dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ;
2322 #endif
2323         mlx5_glue->dv_query_device(sh->ctx, &dv_attr);
2324         if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
2325                 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) {
2326                         DRV_LOG(DEBUG, "enhanced MPW is supported");
2327                         mps = MLX5_MPW_ENHANCED;
2328                 } else {
2329                         DRV_LOG(DEBUG, "MPW is supported");
2330                         mps = MLX5_MPW;
2331                 }
2332         } else {
2333                 DRV_LOG(DEBUG, "MPW isn't supported");
2334                 mps = MLX5_MPW_DISABLED;
2335         }
2336 #ifdef HAVE_IBV_MLX5_MOD_SWP
2337         if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP)
2338                 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads;
2339         DRV_LOG(DEBUG, "SWP support: %u", swp);
2340 #endif
2341         config.swp = !!swp;
2342 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
2343         if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) {
2344                 struct mlx5dv_striding_rq_caps mprq_caps =
2345                         dv_attr.striding_rq_caps;
2346
2347                 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d",
2348                         mprq_caps.min_single_stride_log_num_of_bytes);
2349                 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d",
2350                         mprq_caps.max_single_stride_log_num_of_bytes);
2351                 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d",
2352                         mprq_caps.min_single_wqe_log_num_of_strides);
2353                 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d",
2354                         mprq_caps.max_single_wqe_log_num_of_strides);
2355                 DRV_LOG(DEBUG, "\tsupported_qpts: %d",
2356                         mprq_caps.supported_qpts);
2357                 DRV_LOG(DEBUG, "device supports Multi-Packet RQ");
2358                 mprq = 1;
2359                 mprq_min_stride_size_n =
2360                         mprq_caps.min_single_stride_log_num_of_bytes;
2361                 mprq_max_stride_size_n =
2362                         mprq_caps.max_single_stride_log_num_of_bytes;
2363                 mprq_min_stride_num_n =
2364                         mprq_caps.min_single_wqe_log_num_of_strides;
2365                 mprq_max_stride_num_n =
2366                         mprq_caps.max_single_wqe_log_num_of_strides;
2367         }
2368 #endif
2369         if (RTE_CACHE_LINE_SIZE == 128 &&
2370             !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP))
2371                 cqe_comp = 0;
2372         else
2373                 cqe_comp = 1;
2374         config.cqe_comp = cqe_comp;
2375 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD
2376         /* Whether device supports 128B Rx CQE padding. */
2377         cqe_pad = RTE_CACHE_LINE_SIZE == 128 &&
2378                   (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_PAD);
2379 #endif
2380 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
2381         if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) {
2382                 tunnel_en = ((dv_attr.tunnel_offloads_caps &
2383                               MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) &&
2384                              (dv_attr.tunnel_offloads_caps &
2385                               MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE) &&
2386                              (dv_attr.tunnel_offloads_caps &
2387                               MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE));
2388         }
2389         DRV_LOG(DEBUG, "tunnel offloading is %ssupported",
2390                 tunnel_en ? "" : "not ");
2391 #else
2392         DRV_LOG(WARNING,
2393                 "tunnel offloading disabled due to old OFED/rdma-core version");
2394 #endif
2395         config.tunnel_en = tunnel_en;
2396 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
2397         mpls_en = ((dv_attr.tunnel_offloads_caps &
2398                     MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) &&
2399                    (dv_attr.tunnel_offloads_caps &
2400                     MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP));
2401         DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported",
2402                 mpls_en ? "" : "not ");
2403 #else
2404         DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to"
2405                 " old OFED/rdma-core version or firmware configuration");
2406 #endif
2407         config.mpls_en = mpls_en;
2408         /* Check port status. */
2409         err = mlx5_glue->query_port(sh->ctx, spawn->ibv_port, &port_attr);
2410         if (err) {
2411                 DRV_LOG(ERR, "port query failed: %s", strerror(err));
2412                 goto error;
2413         }
2414         if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
2415                 DRV_LOG(ERR, "port is not configured in Ethernet mode");
2416                 err = EINVAL;
2417                 goto error;
2418         }
2419         if (port_attr.state != IBV_PORT_ACTIVE)
2420                 DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)",
2421                         mlx5_glue->port_state_str(port_attr.state),
2422                         port_attr.state);
2423         /* Allocate private eth device data. */
2424         priv = rte_zmalloc("ethdev private structure",
2425                            sizeof(*priv),
2426                            RTE_CACHE_LINE_SIZE);
2427         if (priv == NULL) {
2428                 DRV_LOG(ERR, "priv allocation failure");
2429                 err = ENOMEM;
2430                 goto error;
2431         }
2432         priv->sh = sh;
2433         priv->ibv_port = spawn->ibv_port;
2434         priv->pci_dev = spawn->pci_dev;
2435         priv->mtu = RTE_ETHER_MTU;
2436         priv->mp_id.port_id = port_id;
2437         strlcpy(priv->mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN);
2438 #ifndef RTE_ARCH_64
2439         /* Initialize UAR access locks for 32bit implementations. */
2440         rte_spinlock_init(&priv->uar_lock_cq);
2441         for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
2442                 rte_spinlock_init(&priv->uar_lock[i]);
2443 #endif
2444         /* Some internal functions rely on Netlink sockets, open them now. */
2445         priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA);
2446         priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE);
2447         priv->representor = !!switch_info->representor;
2448         priv->master = !!switch_info->master;
2449         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
2450         priv->vport_meta_tag = 0;
2451         priv->vport_meta_mask = 0;
2452         priv->pf_bond = spawn->pf_bond;
2453 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
2454         /*
2455          * The DevX port query API is implemented. E-Switch may use
2456          * either vport or reg_c[0] metadata register to match on
2457          * vport index. The engaged part of metadata register is
2458          * defined by mask.
2459          */
2460         if (switch_info->representor || switch_info->master) {
2461                 devx_port.comp_mask = MLX5DV_DEVX_PORT_VPORT |
2462                                       MLX5DV_DEVX_PORT_MATCH_REG_C_0;
2463                 err = mlx5_glue->devx_port_query(sh->ctx, spawn->ibv_port,
2464                                                  &devx_port);
2465                 if (err) {
2466                         DRV_LOG(WARNING,
2467                                 "can't query devx port %d on device %s",
2468                                 spawn->ibv_port, spawn->ibv_dev->name);
2469                         devx_port.comp_mask = 0;
2470                 }
2471         }
2472         if (devx_port.comp_mask & MLX5DV_DEVX_PORT_MATCH_REG_C_0) {
2473                 priv->vport_meta_tag = devx_port.reg_c_0.value;
2474                 priv->vport_meta_mask = devx_port.reg_c_0.mask;
2475                 if (!priv->vport_meta_mask) {
2476                         DRV_LOG(ERR, "vport zero mask for port %d"
2477                                      " on bonding device %s",
2478                                      spawn->ibv_port, spawn->ibv_dev->name);
2479                         err = ENOTSUP;
2480                         goto error;
2481                 }
2482                 if (priv->vport_meta_tag & ~priv->vport_meta_mask) {
2483                         DRV_LOG(ERR, "invalid vport tag for port %d"
2484                                      " on bonding device %s",
2485                                      spawn->ibv_port, spawn->ibv_dev->name);
2486                         err = ENOTSUP;
2487                         goto error;
2488                 }
2489         }
2490         if (devx_port.comp_mask & MLX5DV_DEVX_PORT_VPORT) {
2491                 priv->vport_id = devx_port.vport_num;
2492         } else if (spawn->pf_bond >= 0) {
2493                 DRV_LOG(ERR, "can't deduce vport index for port %d"
2494                              " on bonding device %s",
2495                              spawn->ibv_port, spawn->ibv_dev->name);
2496                 err = ENOTSUP;
2497                 goto error;
2498         } else {
2499                 /* Suppose vport index in compatible way. */
2500                 priv->vport_id = switch_info->representor ?
2501                                  switch_info->port_name + 1 : -1;
2502         }
2503 #else
2504         /*
2505          * Kernel/rdma_core support single E-Switch per PF configurations
2506          * only and vport_id field contains the vport index for
2507          * associated VF, which is deduced from representor port name.
2508          * For example, let's have the IB device port 10, it has
2509          * attached network device eth0, which has port name attribute
2510          * pf0vf2, we can deduce the VF number as 2, and set vport index
2511          * as 3 (2+1). This assigning schema should be changed if the
2512          * multiple E-Switch instances per PF configurations or/and PCI
2513          * subfunctions are added.
2514          */
2515         priv->vport_id = switch_info->representor ?
2516                          switch_info->port_name + 1 : -1;
2517 #endif
2518         /* representor_id field keeps the unmodified VF index. */
2519         priv->representor_id = switch_info->representor ?
2520                                switch_info->port_name : -1;
2521         /*
2522          * Look for sibling devices in order to reuse their switch domain
2523          * if any, otherwise allocate one.
2524          */
2525         MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
2526                 const struct mlx5_priv *opriv =
2527                         rte_eth_devices[port_id].data->dev_private;
2528
2529                 if (!opriv ||
2530                     opriv->sh != priv->sh ||
2531                         opriv->domain_id ==
2532                         RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID)
2533                         continue;
2534                 priv->domain_id = opriv->domain_id;
2535                 break;
2536         }
2537         if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
2538                 err = rte_eth_switch_domain_alloc(&priv->domain_id);
2539                 if (err) {
2540                         err = rte_errno;
2541                         DRV_LOG(ERR, "unable to allocate switch domain: %s",
2542                                 strerror(rte_errno));
2543                         goto error;
2544                 }
2545                 own_domain_id = 1;
2546         }
2547         /* Override some values set by hardware configuration. */
2548         mlx5_args(&config, dpdk_dev->devargs);
2549         err = mlx5_dev_check_sibling_config(priv, &config);
2550         if (err)
2551                 goto error;
2552         config.hw_csum = !!(sh->device_attr.device_cap_flags_ex &
2553                             IBV_DEVICE_RAW_IP_CSUM);
2554         DRV_LOG(DEBUG, "checksum offloading is %ssupported",
2555                 (config.hw_csum ? "" : "not "));
2556 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \
2557         !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
2558         DRV_LOG(DEBUG, "counters are not supported");
2559 #endif
2560 #if !defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_MLX5DV_DR)
2561         if (config.dv_flow_en) {
2562                 DRV_LOG(WARNING, "DV flow is not supported");
2563                 config.dv_flow_en = 0;
2564         }
2565 #endif
2566         config.ind_table_max_size =
2567                 sh->device_attr.rss_caps.max_rwq_indirection_table_size;
2568         /*
2569          * Remove this check once DPDK supports larger/variable
2570          * indirection tables.
2571          */
2572         if (config.ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512)
2573                 config.ind_table_max_size = ETH_RSS_RETA_SIZE_512;
2574         DRV_LOG(DEBUG, "maximum Rx indirection table size is %u",
2575                 config.ind_table_max_size);
2576         config.hw_vlan_strip = !!(sh->device_attr.raw_packet_caps &
2577                                   IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
2578         DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
2579                 (config.hw_vlan_strip ? "" : "not "));
2580         config.hw_fcs_strip = !!(sh->device_attr.raw_packet_caps &
2581                                  IBV_RAW_PACKET_CAP_SCATTER_FCS);
2582         DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported",
2583                 (config.hw_fcs_strip ? "" : "not "));
2584 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING)
2585         hw_padding = !!sh->device_attr.rx_pad_end_addr_align;
2586 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING)
2587         hw_padding = !!(sh->device_attr.device_cap_flags_ex &
2588                         IBV_DEVICE_PCI_WRITE_END_PADDING);
2589 #endif
2590         if (config.hw_padding && !hw_padding) {
2591                 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported");
2592                 config.hw_padding = 0;
2593         } else if (config.hw_padding) {
2594                 DRV_LOG(DEBUG, "Rx end alignment padding is enabled");
2595         }
2596         config.tso = (sh->device_attr.tso_caps.max_tso > 0 &&
2597                       (sh->device_attr.tso_caps.supported_qpts &
2598                        (1 << IBV_QPT_RAW_PACKET)));
2599         if (config.tso)
2600                 config.tso_max_payload_sz = sh->device_attr.tso_caps.max_tso;
2601         /*
2602          * MPW is disabled by default, while the Enhanced MPW is enabled
2603          * by default.
2604          */
2605         if (config.mps == MLX5_ARG_UNSET)
2606                 config.mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED :
2607                                                           MLX5_MPW_DISABLED;
2608         else
2609                 config.mps = config.mps ? mps : MLX5_MPW_DISABLED;
2610         DRV_LOG(INFO, "%sMPS is %s",
2611                 config.mps == MLX5_MPW_ENHANCED ? "enhanced " :
2612                 config.mps == MLX5_MPW ? "legacy " : "",
2613                 config.mps != MLX5_MPW_DISABLED ? "enabled" : "disabled");
2614         if (config.cqe_comp && !cqe_comp) {
2615                 DRV_LOG(WARNING, "Rx CQE compression isn't supported");
2616                 config.cqe_comp = 0;
2617         }
2618         if (config.cqe_pad && !cqe_pad) {
2619                 DRV_LOG(WARNING, "Rx CQE padding isn't supported");
2620                 config.cqe_pad = 0;
2621         } else if (config.cqe_pad) {
2622                 DRV_LOG(INFO, "Rx CQE padding is enabled");
2623         }
2624         if (config.devx) {
2625                 priv->counter_fallback = 0;
2626                 err = mlx5_devx_cmd_query_hca_attr(sh->ctx, &config.hca_attr);
2627                 if (err) {
2628                         err = -err;
2629                         goto error;
2630                 }
2631                 if (!config.hca_attr.flow_counters_dump)
2632                         priv->counter_fallback = 1;
2633 #ifndef HAVE_IBV_DEVX_ASYNC
2634                 priv->counter_fallback = 1;
2635 #endif
2636                 if (priv->counter_fallback)
2637                         DRV_LOG(INFO, "Use fall-back DV counter management");
2638                 /* Check for LRO support. */
2639                 if (config.dest_tir && config.hca_attr.lro_cap &&
2640                     config.dv_flow_en) {
2641                         /* TBD check tunnel lro caps. */
2642                         config.lro.supported = config.hca_attr.lro_cap;
2643                         DRV_LOG(DEBUG, "Device supports LRO");
2644                         /*
2645                          * If LRO timeout is not configured by application,
2646                          * use the minimal supported value.
2647                          */
2648                         if (!config.lro.timeout)
2649                                 config.lro.timeout =
2650                                 config.hca_attr.lro_timer_supported_periods[0];
2651                         DRV_LOG(DEBUG, "LRO session timeout set to %d usec",
2652                                 config.lro.timeout);
2653                 }
2654 #if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_METER)
2655                 if (config.hca_attr.qos.sup && config.hca_attr.qos.srtcm_sup &&
2656                     config.dv_flow_en) {
2657                         uint8_t reg_c_mask =
2658                                 config.hca_attr.qos.flow_meter_reg_c_ids;
2659                         /*
2660                          * Meter needs two REG_C's for color match and pre-sfx
2661                          * flow match. Here get the REG_C for color match.
2662                          * REG_C_0 and REG_C_1 is reserved for metadata feature.
2663                          */
2664                         reg_c_mask &= 0xfc;
2665                         if (__builtin_popcount(reg_c_mask) < 1) {
2666                                 priv->mtr_en = 0;
2667                                 DRV_LOG(WARNING, "No available register for"
2668                                         " meter.");
2669                         } else {
2670                                 priv->mtr_color_reg = ffs(reg_c_mask) - 1 +
2671                                                       REG_C_0;
2672                                 priv->mtr_en = 1;
2673                                 priv->mtr_reg_share =
2674                                       config.hca_attr.qos.flow_meter_reg_share;
2675                                 DRV_LOG(DEBUG, "The REG_C meter uses is %d",
2676                                         priv->mtr_color_reg);
2677                         }
2678                 }
2679 #endif
2680         }
2681         if (config.mprq.enabled && mprq) {
2682                 if (config.mprq.stride_num_n &&
2683                     (config.mprq.stride_num_n > mprq_max_stride_num_n ||
2684                      config.mprq.stride_num_n < mprq_min_stride_num_n)) {
2685                         config.mprq.stride_num_n =
2686                                 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,
2687                                                 mprq_min_stride_num_n),
2688                                         mprq_max_stride_num_n);
2689                         DRV_LOG(WARNING,
2690                                 "the number of strides"
2691                                 " for Multi-Packet RQ is out of range,"
2692                                 " setting default value (%u)",
2693                                 1 << config.mprq.stride_num_n);
2694                 }
2695                 if (config.mprq.stride_size_n &&
2696                     (config.mprq.stride_size_n > mprq_max_stride_size_n ||
2697                      config.mprq.stride_size_n < mprq_min_stride_size_n)) {
2698                         config.mprq.stride_size_n =
2699                                 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_SIZE_N,
2700                                                 mprq_min_stride_size_n),
2701                                         mprq_max_stride_size_n);
2702                         DRV_LOG(WARNING,
2703                                 "the size of a stride"
2704                                 " for Multi-Packet RQ is out of range,"
2705                                 " setting default value (%u)",
2706                                 1 << config.mprq.stride_size_n);
2707                 }
2708                 config.mprq.min_stride_size_n = mprq_min_stride_size_n;
2709                 config.mprq.max_stride_size_n = mprq_max_stride_size_n;
2710         } else if (config.mprq.enabled && !mprq) {
2711                 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported");
2712                 config.mprq.enabled = 0;
2713         }
2714         if (config.max_dump_files_num == 0)
2715                 config.max_dump_files_num = 128;
2716         eth_dev = rte_eth_dev_allocate(name);
2717         if (eth_dev == NULL) {
2718                 DRV_LOG(ERR, "can not allocate rte ethdev");
2719                 err = ENOMEM;
2720                 goto error;
2721         }
2722         /* Flag to call rte_eth_dev_release_port() in rte_eth_dev_close(). */
2723         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2724         if (priv->representor) {
2725                 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR;
2726                 eth_dev->data->representor_id = priv->representor_id;
2727         }
2728         /*
2729          * Store associated network device interface index. This index
2730          * is permanent throughout the lifetime of device. So, we may store
2731          * the ifindex here and use the cached value further.
2732          */
2733         MLX5_ASSERT(spawn->ifindex);
2734         priv->if_index = spawn->ifindex;
2735         eth_dev->data->dev_private = priv;
2736         priv->dev_data = eth_dev->data;
2737         eth_dev->data->mac_addrs = priv->mac;
2738         eth_dev->device = dpdk_dev;
2739         /* Configure the first MAC address by default. */
2740         if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) {
2741                 DRV_LOG(ERR,
2742                         "port %u cannot get MAC address, is mlx5_en"
2743                         " loaded? (errno: %s)",
2744                         eth_dev->data->port_id, strerror(rte_errno));
2745                 err = ENODEV;
2746                 goto error;
2747         }
2748         DRV_LOG(INFO,
2749                 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x",
2750                 eth_dev->data->port_id,
2751                 mac.addr_bytes[0], mac.addr_bytes[1],
2752                 mac.addr_bytes[2], mac.addr_bytes[3],
2753                 mac.addr_bytes[4], mac.addr_bytes[5]);
2754 #ifdef RTE_LIBRTE_MLX5_DEBUG
2755         {
2756                 char ifname[IF_NAMESIZE];
2757
2758                 if (mlx5_get_ifname(eth_dev, &ifname) == 0)
2759                         DRV_LOG(DEBUG, "port %u ifname is \"%s\"",
2760                                 eth_dev->data->port_id, ifname);
2761                 else
2762                         DRV_LOG(DEBUG, "port %u ifname is unknown",
2763                                 eth_dev->data->port_id);
2764         }
2765 #endif
2766         /* Get actual MTU if possible. */
2767         err = mlx5_get_mtu(eth_dev, &priv->mtu);
2768         if (err) {
2769                 err = rte_errno;
2770                 goto error;
2771         }
2772         DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id,
2773                 priv->mtu);
2774         /* Initialize burst functions to prevent crashes before link-up. */
2775         eth_dev->rx_pkt_burst = removed_rx_burst;
2776         eth_dev->tx_pkt_burst = removed_tx_burst;
2777         eth_dev->dev_ops = &mlx5_dev_ops;
2778         /* Register MAC address. */
2779         claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
2780         if (config.vf && config.vf_nl_en)
2781                 mlx5_nl_mac_addr_sync(priv->nl_socket_route,
2782                                       mlx5_ifindex(eth_dev),
2783                                       eth_dev->data->mac_addrs,
2784                                       MLX5_MAX_MAC_ADDRESSES);
2785         TAILQ_INIT(&priv->flows);
2786         TAILQ_INIT(&priv->ctrl_flows);
2787         TAILQ_INIT(&priv->flow_meters);
2788         TAILQ_INIT(&priv->flow_meter_profiles);
2789         /* Hint libmlx5 to use PMD allocator for data plane resources */
2790         struct mlx5dv_ctx_allocators alctr = {
2791                 .alloc = &mlx5_alloc_verbs_buf,
2792                 .free = &mlx5_free_verbs_buf,
2793                 .data = priv,
2794         };
2795         mlx5_glue->dv_set_context_attr(sh->ctx,
2796                                        MLX5DV_CTX_ATTR_BUF_ALLOCATORS,
2797                                        (void *)((uintptr_t)&alctr));
2798         /* Bring Ethernet device up. */
2799         DRV_LOG(DEBUG, "port %u forcing Ethernet interface up",
2800                 eth_dev->data->port_id);
2801         mlx5_set_link_up(eth_dev);
2802         /*
2803          * Even though the interrupt handler is not installed yet,
2804          * interrupts will still trigger on the async_fd from
2805          * Verbs context returned by ibv_open_device().
2806          */
2807         mlx5_link_update(eth_dev, 0);
2808 #ifdef HAVE_MLX5DV_DR_ESWITCH
2809         if (!(config.hca_attr.eswitch_manager && config.dv_flow_en &&
2810               (switch_info->representor || switch_info->master)))
2811                 config.dv_esw_en = 0;
2812 #else
2813         config.dv_esw_en = 0;
2814 #endif
2815         /* Detect minimal data bytes to inline. */
2816         mlx5_set_min_inline(spawn, &config);
2817         /* Store device configuration on private structure. */
2818         priv->config = config;
2819         /* Create context for virtual machine VLAN workaround. */
2820         priv->vmwa_context = mlx5_vlan_vmwa_init(eth_dev, spawn->ifindex);
2821         if (config.dv_flow_en) {
2822                 err = mlx5_alloc_shared_dr(priv);
2823                 if (err)
2824                         goto error;
2825                 /*
2826                  * RSS id is shared with meter flow id. Meter flow id can only
2827                  * use the 24 MSB of the register.
2828                  */
2829                 priv->qrss_id_pool = mlx5_flow_id_pool_alloc(UINT32_MAX >>
2830                                      MLX5_MTR_COLOR_BITS);
2831                 if (!priv->qrss_id_pool) {
2832                         DRV_LOG(ERR, "can't create flow id pool");
2833                         err = ENOMEM;
2834                         goto error;
2835                 }
2836         }
2837         /* Supported Verbs flow priority number detection. */
2838         err = mlx5_flow_discover_priorities(eth_dev);
2839         if (err < 0) {
2840                 err = -err;
2841                 goto error;
2842         }
2843         priv->config.flow_prio = err;
2844         if (!priv->config.dv_esw_en &&
2845             priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
2846                 DRV_LOG(WARNING, "metadata mode %u is not supported "
2847                                  "(no E-Switch)", priv->config.dv_xmeta_en);
2848                 priv->config.dv_xmeta_en = MLX5_XMETA_MODE_LEGACY;
2849         }
2850         mlx5_set_metadata_mask(eth_dev);
2851         if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
2852             !priv->sh->dv_regc0_mask) {
2853                 DRV_LOG(ERR, "metadata mode %u is not supported "
2854                              "(no metadata reg_c[0] is available)",
2855                              priv->config.dv_xmeta_en);
2856                         err = ENOTSUP;
2857                         goto error;
2858         }
2859         /*
2860          * Allocate the buffer for flow creating, just once.
2861          * The allocation must be done before any flow creating.
2862          */
2863         mlx5_flow_alloc_intermediate(eth_dev);
2864         /* Query availibility of metadata reg_c's. */
2865         err = mlx5_flow_discover_mreg_c(eth_dev);
2866         if (err < 0) {
2867                 err = -err;
2868                 goto error;
2869         }
2870         if (!mlx5_flow_ext_mreg_supported(eth_dev)) {
2871                 DRV_LOG(DEBUG,
2872                         "port %u extensive metadata register is not supported",
2873                         eth_dev->data->port_id);
2874                 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
2875                         DRV_LOG(ERR, "metadata mode %u is not supported "
2876                                      "(no metadata registers available)",
2877                                      priv->config.dv_xmeta_en);
2878                         err = ENOTSUP;
2879                         goto error;
2880                 }
2881         }
2882         if (priv->config.dv_flow_en &&
2883             priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
2884             mlx5_flow_ext_mreg_supported(eth_dev) &&
2885             priv->sh->dv_regc0_mask) {
2886                 priv->mreg_cp_tbl = mlx5_hlist_create(MLX5_FLOW_MREG_HNAME,
2887                                                       MLX5_FLOW_MREG_HTABLE_SZ);
2888                 if (!priv->mreg_cp_tbl) {
2889                         err = ENOMEM;
2890                         goto error;
2891                 }
2892         }
2893         return eth_dev;
2894 error:
2895         if (priv) {
2896                 if (priv->mreg_cp_tbl)
2897                         mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
2898                 if (priv->sh)
2899                         mlx5_free_shared_dr(priv);
2900                 if (priv->nl_socket_route >= 0)
2901                         close(priv->nl_socket_route);
2902                 if (priv->nl_socket_rdma >= 0)
2903                         close(priv->nl_socket_rdma);
2904                 if (priv->vmwa_context)
2905                         mlx5_vlan_vmwa_exit(priv->vmwa_context);
2906                 if (priv->qrss_id_pool)
2907                         mlx5_flow_id_pool_release(priv->qrss_id_pool);
2908                 if (own_domain_id)
2909                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
2910                 rte_free(priv);
2911                 if (eth_dev != NULL)
2912                         eth_dev->data->dev_private = NULL;
2913         }
2914         if (eth_dev != NULL) {
2915                 /* mac_addrs must not be freed alone because part of dev_private */
2916                 eth_dev->data->mac_addrs = NULL;
2917                 rte_eth_dev_release_port(eth_dev);
2918         }
2919         if (sh)
2920                 mlx5_free_shared_ibctx(sh);
2921         MLX5_ASSERT(err > 0);
2922         rte_errno = err;
2923         return NULL;
2924 }
2925
2926 /**
2927  * Comparison callback to sort device data.
2928  *
2929  * This is meant to be used with qsort().
2930  *
2931  * @param a[in]
2932  *   Pointer to pointer to first data object.
2933  * @param b[in]
2934  *   Pointer to pointer to second data object.
2935  *
2936  * @return
2937  *   0 if both objects are equal, less than 0 if the first argument is less
2938  *   than the second, greater than 0 otherwise.
2939  */
2940 static int
2941 mlx5_dev_spawn_data_cmp(const void *a, const void *b)
2942 {
2943         const struct mlx5_switch_info *si_a =
2944                 &((const struct mlx5_dev_spawn_data *)a)->info;
2945         const struct mlx5_switch_info *si_b =
2946                 &((const struct mlx5_dev_spawn_data *)b)->info;
2947         int ret;
2948
2949         /* Master device first. */
2950         ret = si_b->master - si_a->master;
2951         if (ret)
2952                 return ret;
2953         /* Then representor devices. */
2954         ret = si_b->representor - si_a->representor;
2955         if (ret)
2956                 return ret;
2957         /* Unidentified devices come last in no specific order. */
2958         if (!si_a->representor)
2959                 return 0;
2960         /* Order representors by name. */
2961         return si_a->port_name - si_b->port_name;
2962 }
2963
2964 /**
2965  * Match PCI information for possible slaves of bonding device.
2966  *
2967  * @param[in] ibv_dev
2968  *   Pointer to Infiniband device structure.
2969  * @param[in] pci_dev
2970  *   Pointer to PCI device structure to match PCI address.
2971  * @param[in] nl_rdma
2972  *   Netlink RDMA group socket handle.
2973  *
2974  * @return
2975  *   negative value if no bonding device found, otherwise
2976  *   positive index of slave PF in bonding.
2977  */
2978 static int
2979 mlx5_device_bond_pci_match(const struct ibv_device *ibv_dev,
2980                            const struct rte_pci_device *pci_dev,
2981                            int nl_rdma)
2982 {
2983         char ifname[IF_NAMESIZE + 1];
2984         unsigned int ifindex;
2985         unsigned int np, i;
2986         FILE *file = NULL;
2987         int pf = -1;
2988
2989         /*
2990          * Try to get master device name. If something goes
2991          * wrong suppose the lack of kernel support and no
2992          * bonding devices.
2993          */
2994         if (nl_rdma < 0)
2995                 return -1;
2996         if (!strstr(ibv_dev->name, "bond"))
2997                 return -1;
2998         np = mlx5_nl_portnum(nl_rdma, ibv_dev->name);
2999         if (!np)
3000                 return -1;
3001         /*
3002          * The Master device might not be on the predefined
3003          * port (not on port index 1, it is not garanted),
3004          * we have to scan all Infiniband device port and
3005          * find master.
3006          */
3007         for (i = 1; i <= np; ++i) {
3008                 /* Check whether Infiniband port is populated. */
3009                 ifindex = mlx5_nl_ifindex(nl_rdma, ibv_dev->name, i);
3010                 if (!ifindex)
3011                         continue;
3012                 if (!if_indextoname(ifindex, ifname))
3013                         continue;
3014                 /* Try to read bonding slave names from sysfs. */
3015                 MKSTR(slaves,
3016                       "/sys/class/net/%s/master/bonding/slaves", ifname);
3017                 file = fopen(slaves, "r");
3018                 if (file)
3019                         break;
3020         }
3021         if (!file)
3022                 return -1;
3023         /* Use safe format to check maximal buffer length. */
3024         MLX5_ASSERT(atol(RTE_STR(IF_NAMESIZE)) == IF_NAMESIZE);
3025         while (fscanf(file, "%" RTE_STR(IF_NAMESIZE) "s", ifname) == 1) {
3026                 char tmp_str[IF_NAMESIZE + 32];
3027                 struct rte_pci_addr pci_addr;
3028                 struct mlx5_switch_info info;
3029
3030                 /* Process slave interface names in the loop. */
3031                 snprintf(tmp_str, sizeof(tmp_str),
3032                          "/sys/class/net/%s", ifname);
3033                 if (mlx5_dev_to_pci_addr(tmp_str, &pci_addr)) {
3034                         DRV_LOG(WARNING, "can not get PCI address"
3035                                          " for netdev \"%s\"", ifname);
3036                         continue;
3037                 }
3038                 if (pci_dev->addr.domain != pci_addr.domain ||
3039                     pci_dev->addr.bus != pci_addr.bus ||
3040                     pci_dev->addr.devid != pci_addr.devid ||
3041                     pci_dev->addr.function != pci_addr.function)
3042                         continue;
3043                 /* Slave interface PCI address match found. */
3044                 fclose(file);
3045                 snprintf(tmp_str, sizeof(tmp_str),
3046                          "/sys/class/net/%s/phys_port_name", ifname);
3047                 file = fopen(tmp_str, "rb");
3048                 if (!file)
3049                         break;
3050                 info.name_type = MLX5_PHYS_PORT_NAME_TYPE_NOTSET;
3051                 if (fscanf(file, "%32s", tmp_str) == 1)
3052                         mlx5_translate_port_name(tmp_str, &info);
3053                 if (info.name_type == MLX5_PHYS_PORT_NAME_TYPE_LEGACY ||
3054                     info.name_type == MLX5_PHYS_PORT_NAME_TYPE_UPLINK)
3055                         pf = info.port_name;
3056                 break;
3057         }
3058         if (file)
3059                 fclose(file);
3060         return pf;
3061 }
3062
3063 /**
3064  * DPDK callback to register a PCI device.
3065  *
3066  * This function spawns Ethernet devices out of a given PCI device.
3067  *
3068  * @param[in] pci_drv
3069  *   PCI driver structure (mlx5_driver).
3070  * @param[in] pci_dev
3071  *   PCI device information.
3072  *
3073  * @return
3074  *   0 on success, a negative errno value otherwise and rte_errno is set.
3075  */
3076 static int
3077 mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3078                struct rte_pci_device *pci_dev)
3079 {
3080         struct ibv_device **ibv_list;
3081         /*
3082          * Number of found IB Devices matching with requested PCI BDF.
3083          * nd != 1 means there are multiple IB devices over the same
3084          * PCI device and we have representors and master.
3085          */
3086         unsigned int nd = 0;
3087         /*
3088          * Number of found IB device Ports. nd = 1 and np = 1..n means
3089          * we have the single multiport IB device, and there may be
3090          * representors attached to some of found ports.
3091          */
3092         unsigned int np = 0;
3093         /*
3094          * Number of DPDK ethernet devices to Spawn - either over
3095          * multiple IB devices or multiple ports of single IB device.
3096          * Actually this is the number of iterations to spawn.
3097          */
3098         unsigned int ns = 0;
3099         /*
3100          * Bonding device
3101          *   < 0 - no bonding device (single one)
3102          *  >= 0 - bonding device (value is slave PF index)
3103          */
3104         int bd = -1;
3105         struct mlx5_dev_spawn_data *list = NULL;
3106         struct mlx5_dev_config dev_config;
3107         int ret;
3108
3109         if (mlx5_class_get(pci_dev->device.devargs) != MLX5_CLASS_NET) {
3110                 DRV_LOG(DEBUG, "Skip probing - should be probed by other mlx5"
3111                         " driver.");
3112                 return 1;
3113         }
3114         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
3115                 mlx5_pmd_socket_init();
3116         ret = mlx5_init_once();
3117         if (ret) {
3118                 DRV_LOG(ERR, "unable to init PMD global data: %s",
3119                         strerror(rte_errno));
3120                 return -rte_errno;
3121         }
3122         MLX5_ASSERT(pci_drv == &mlx5_driver);
3123         errno = 0;
3124         ibv_list = mlx5_glue->get_device_list(&ret);
3125         if (!ibv_list) {
3126                 rte_errno = errno ? errno : ENOSYS;
3127                 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?");
3128                 return -rte_errno;
3129         }
3130         /*
3131          * First scan the list of all Infiniband devices to find
3132          * matching ones, gathering into the list.
3133          */
3134         struct ibv_device *ibv_match[ret + 1];
3135         int nl_route = mlx5_nl_init(NETLINK_ROUTE);
3136         int nl_rdma = mlx5_nl_init(NETLINK_RDMA);
3137         unsigned int i;
3138
3139         while (ret-- > 0) {
3140                 struct rte_pci_addr pci_addr;
3141
3142                 DRV_LOG(DEBUG, "checking device \"%s\"", ibv_list[ret]->name);
3143                 bd = mlx5_device_bond_pci_match
3144                                 (ibv_list[ret], pci_dev, nl_rdma);
3145                 if (bd >= 0) {
3146                         /*
3147                          * Bonding device detected. Only one match is allowed,
3148                          * the bonding is supported over multi-port IB device,
3149                          * there should be no matches on representor PCI
3150                          * functions or non VF LAG bonding devices with
3151                          * specified address.
3152                          */
3153                         if (nd) {
3154                                 DRV_LOG(ERR,
3155                                         "multiple PCI match on bonding device"
3156                                         "\"%s\" found", ibv_list[ret]->name);
3157                                 rte_errno = ENOENT;
3158                                 ret = -rte_errno;
3159                                 goto exit;
3160                         }
3161                         DRV_LOG(INFO, "PCI information matches for"
3162                                       " slave %d bonding device \"%s\"",
3163                                       bd, ibv_list[ret]->name);
3164                         ibv_match[nd++] = ibv_list[ret];
3165                         break;
3166                 }
3167                 if (mlx5_dev_to_pci_addr
3168                         (ibv_list[ret]->ibdev_path, &pci_addr))
3169                         continue;
3170                 if (pci_dev->addr.domain != pci_addr.domain ||
3171                     pci_dev->addr.bus != pci_addr.bus ||
3172                     pci_dev->addr.devid != pci_addr.devid ||
3173                     pci_dev->addr.function != pci_addr.function)
3174                         continue;
3175                 DRV_LOG(INFO, "PCI information matches for device \"%s\"",
3176                         ibv_list[ret]->name);
3177                 ibv_match[nd++] = ibv_list[ret];
3178         }
3179         ibv_match[nd] = NULL;
3180         if (!nd) {
3181                 /* No device matches, just complain and bail out. */
3182                 DRV_LOG(WARNING,
3183                         "no Verbs device matches PCI device " PCI_PRI_FMT ","
3184                         " are kernel drivers loaded?",
3185                         pci_dev->addr.domain, pci_dev->addr.bus,
3186                         pci_dev->addr.devid, pci_dev->addr.function);
3187                 rte_errno = ENOENT;
3188                 ret = -rte_errno;
3189                 goto exit;
3190         }
3191         if (nd == 1) {
3192                 /*
3193                  * Found single matching device may have multiple ports.
3194                  * Each port may be representor, we have to check the port
3195                  * number and check the representors existence.
3196                  */
3197                 if (nl_rdma >= 0)
3198                         np = mlx5_nl_portnum(nl_rdma, ibv_match[0]->name);
3199                 if (!np)
3200                         DRV_LOG(WARNING, "can not get IB device \"%s\""
3201                                          " ports number", ibv_match[0]->name);
3202                 if (bd >= 0 && !np) {
3203                         DRV_LOG(ERR, "can not get ports"
3204                                      " for bonding device");
3205                         rte_errno = ENOENT;
3206                         ret = -rte_errno;
3207                         goto exit;
3208                 }
3209         }
3210 #ifndef HAVE_MLX5DV_DR_DEVX_PORT
3211         if (bd >= 0) {
3212                 /*
3213                  * This may happen if there is VF LAG kernel support and
3214                  * application is compiled with older rdma_core library.
3215                  */
3216                 DRV_LOG(ERR,
3217                         "No kernel/verbs support for VF LAG bonding found.");
3218                 rte_errno = ENOTSUP;
3219                 ret = -rte_errno;
3220                 goto exit;
3221         }
3222 #endif
3223         /*
3224          * Now we can determine the maximal
3225          * amount of devices to be spawned.
3226          */
3227         list = rte_zmalloc("device spawn data",
3228                          sizeof(struct mlx5_dev_spawn_data) *
3229                          (np ? np : nd),
3230                          RTE_CACHE_LINE_SIZE);
3231         if (!list) {
3232                 DRV_LOG(ERR, "spawn data array allocation failure");
3233                 rte_errno = ENOMEM;
3234                 ret = -rte_errno;
3235                 goto exit;
3236         }
3237         if (bd >= 0 || np > 1) {
3238                 /*
3239                  * Single IB device with multiple ports found,
3240                  * it may be E-Switch master device and representors.
3241                  * We have to perform identification trough the ports.
3242                  */
3243                 MLX5_ASSERT(nl_rdma >= 0);
3244                 MLX5_ASSERT(ns == 0);
3245                 MLX5_ASSERT(nd == 1);
3246                 MLX5_ASSERT(np);
3247                 for (i = 1; i <= np; ++i) {
3248                         list[ns].max_port = np;
3249                         list[ns].ibv_port = i;
3250                         list[ns].ibv_dev = ibv_match[0];
3251                         list[ns].eth_dev = NULL;
3252                         list[ns].pci_dev = pci_dev;
3253                         list[ns].pf_bond = bd;
3254                         list[ns].ifindex = mlx5_nl_ifindex
3255                                         (nl_rdma, list[ns].ibv_dev->name, i);
3256                         if (!list[ns].ifindex) {
3257                                 /*
3258                                  * No network interface index found for the
3259                                  * specified port, it means there is no
3260                                  * representor on this port. It's OK,
3261                                  * there can be disabled ports, for example
3262                                  * if sriov_numvfs < sriov_totalvfs.
3263                                  */
3264                                 continue;
3265                         }
3266                         ret = -1;
3267                         if (nl_route >= 0)
3268                                 ret = mlx5_nl_switch_info
3269                                                (nl_route,
3270                                                 list[ns].ifindex,
3271                                                 &list[ns].info);
3272                         if (ret || (!list[ns].info.representor &&
3273                                     !list[ns].info.master)) {
3274                                 /*
3275                                  * We failed to recognize representors with
3276                                  * Netlink, let's try to perform the task
3277                                  * with sysfs.
3278                                  */
3279                                 ret =  mlx5_sysfs_switch_info
3280                                                 (list[ns].ifindex,
3281                                                  &list[ns].info);
3282                         }
3283                         if (!ret && bd >= 0) {
3284                                 switch (list[ns].info.name_type) {
3285                                 case MLX5_PHYS_PORT_NAME_TYPE_UPLINK:
3286                                         if (list[ns].info.port_name == bd)
3287                                                 ns++;
3288                                         break;
3289                                 case MLX5_PHYS_PORT_NAME_TYPE_PFVF:
3290                                         if (list[ns].info.pf_num == bd)
3291                                                 ns++;
3292                                         break;
3293                                 default:
3294                                         break;
3295                                 }
3296                                 continue;
3297                         }
3298                         if (!ret && (list[ns].info.representor ^
3299                                      list[ns].info.master))
3300                                 ns++;
3301                 }
3302                 if (!ns) {
3303                         DRV_LOG(ERR,
3304                                 "unable to recognize master/representors"
3305                                 " on the IB device with multiple ports");
3306                         rte_errno = ENOENT;
3307                         ret = -rte_errno;
3308                         goto exit;
3309                 }
3310         } else {
3311                 /*
3312                  * The existence of several matching entries (nd > 1) means
3313                  * port representors have been instantiated. No existing Verbs
3314                  * call nor sysfs entries can tell them apart, this can only
3315                  * be done through Netlink calls assuming kernel drivers are
3316                  * recent enough to support them.
3317                  *
3318                  * In the event of identification failure through Netlink,
3319                  * try again through sysfs, then:
3320                  *
3321                  * 1. A single IB device matches (nd == 1) with single
3322                  *    port (np=0/1) and is not a representor, assume
3323                  *    no switch support.
3324                  *
3325                  * 2. Otherwise no safe assumptions can be made;
3326                  *    complain louder and bail out.
3327                  */
3328                 np = 1;
3329                 for (i = 0; i != nd; ++i) {
3330                         memset(&list[ns].info, 0, sizeof(list[ns].info));
3331                         list[ns].max_port = 1;
3332                         list[ns].ibv_port = 1;
3333                         list[ns].ibv_dev = ibv_match[i];
3334                         list[ns].eth_dev = NULL;
3335                         list[ns].pci_dev = pci_dev;
3336                         list[ns].pf_bond = -1;
3337                         list[ns].ifindex = 0;
3338                         if (nl_rdma >= 0)
3339                                 list[ns].ifindex = mlx5_nl_ifindex
3340                                         (nl_rdma, list[ns].ibv_dev->name, 1);
3341                         if (!list[ns].ifindex) {
3342                                 char ifname[IF_NAMESIZE];
3343
3344                                 /*
3345                                  * Netlink failed, it may happen with old
3346                                  * ib_core kernel driver (before 4.16).
3347                                  * We can assume there is old driver because
3348                                  * here we are processing single ports IB
3349                                  * devices. Let's try sysfs to retrieve
3350                                  * the ifindex. The method works for
3351                                  * master device only.
3352                                  */
3353                                 if (nd > 1) {
3354                                         /*
3355                                          * Multiple devices found, assume
3356                                          * representors, can not distinguish
3357                                          * master/representor and retrieve
3358                                          * ifindex via sysfs.
3359                                          */
3360                                         continue;
3361                                 }
3362                                 ret = mlx5_get_master_ifname
3363                                         (ibv_match[i]->ibdev_path, &ifname);
3364                                 if (!ret)
3365                                         list[ns].ifindex =
3366                                                 if_nametoindex(ifname);
3367                                 if (!list[ns].ifindex) {
3368                                         /*
3369                                          * No network interface index found
3370                                          * for the specified device, it means
3371                                          * there it is neither representor
3372                                          * nor master.
3373                                          */
3374                                         continue;
3375                                 }
3376                         }
3377                         ret = -1;
3378                         if (nl_route >= 0)
3379                                 ret = mlx5_nl_switch_info
3380                                                (nl_route,
3381                                                 list[ns].ifindex,
3382                                                 &list[ns].info);
3383                         if (ret || (!list[ns].info.representor &&
3384                                     !list[ns].info.master)) {
3385                                 /*
3386                                  * We failed to recognize representors with
3387                                  * Netlink, let's try to perform the task
3388                                  * with sysfs.
3389                                  */
3390                                 ret =  mlx5_sysfs_switch_info
3391                                                 (list[ns].ifindex,
3392                                                  &list[ns].info);
3393                         }
3394                         if (!ret && (list[ns].info.representor ^
3395                                      list[ns].info.master)) {
3396                                 ns++;
3397                         } else if ((nd == 1) &&
3398                                    !list[ns].info.representor &&
3399                                    !list[ns].info.master) {
3400                                 /*
3401                                  * Single IB device with
3402                                  * one physical port and
3403                                  * attached network device.
3404                                  * May be SRIOV is not enabled
3405                                  * or there is no representors.
3406                                  */
3407                                 DRV_LOG(INFO, "no E-Switch support detected");
3408                                 ns++;
3409                                 break;
3410                         }
3411                 }
3412                 if (!ns) {
3413                         DRV_LOG(ERR,
3414                                 "unable to recognize master/representors"
3415                                 " on the multiple IB devices");
3416                         rte_errno = ENOENT;
3417                         ret = -rte_errno;
3418                         goto exit;
3419                 }
3420         }
3421         MLX5_ASSERT(ns);
3422         /*
3423          * Sort list to probe devices in natural order for users convenience
3424          * (i.e. master first, then representors from lowest to highest ID).
3425          */
3426         qsort(list, ns, sizeof(*list), mlx5_dev_spawn_data_cmp);
3427         /* Default configuration. */
3428         dev_config = (struct mlx5_dev_config){
3429                 .hw_padding = 0,
3430                 .mps = MLX5_ARG_UNSET,
3431                 .dbnc = MLX5_ARG_UNSET,
3432                 .rx_vec_en = 1,
3433                 .txq_inline_max = MLX5_ARG_UNSET,
3434                 .txq_inline_min = MLX5_ARG_UNSET,
3435                 .txq_inline_mpw = MLX5_ARG_UNSET,
3436                 .txqs_inline = MLX5_ARG_UNSET,
3437                 .vf_nl_en = 1,
3438                 .mr_ext_memseg_en = 1,
3439                 .mprq = {
3440                         .enabled = 0, /* Disabled by default. */
3441                         .stride_num_n = 0,
3442                         .stride_size_n = 0,
3443                         .max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN,
3444                         .min_rxqs_num = MLX5_MPRQ_MIN_RXQS,
3445                 },
3446                 .dv_esw_en = 1,
3447                 .dv_flow_en = 1,
3448                 .log_hp_size = MLX5_ARG_UNSET,
3449         };
3450         /* Device specific configuration. */
3451         switch (pci_dev->id.device_id) {
3452         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
3453         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
3454         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
3455         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
3456         case PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF:
3457         case PCI_DEVICE_ID_MELLANOX_CONNECTX6VF:
3458         case PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF:
3459                 dev_config.vf = 1;
3460                 break;
3461         default:
3462                 break;
3463         }
3464         for (i = 0; i != ns; ++i) {
3465                 uint32_t restore;
3466
3467                 list[i].eth_dev = mlx5_dev_spawn(&pci_dev->device,
3468                                                  &list[i],
3469                                                  dev_config);
3470                 if (!list[i].eth_dev) {
3471                         if (rte_errno != EBUSY && rte_errno != EEXIST)
3472                                 break;
3473                         /* Device is disabled or already spawned. Ignore it. */
3474                         continue;
3475                 }
3476                 restore = list[i].eth_dev->data->dev_flags;
3477                 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev);
3478                 /* Restore non-PCI flags cleared by the above call. */
3479                 list[i].eth_dev->data->dev_flags |= restore;
3480                 mlx5_dev_interrupt_handler_devx_install(list[i].eth_dev);
3481                 rte_eth_dev_probing_finish(list[i].eth_dev);
3482         }
3483         if (i != ns) {
3484                 DRV_LOG(ERR,
3485                         "probe of PCI device " PCI_PRI_FMT " aborted after"
3486                         " encountering an error: %s",
3487                         pci_dev->addr.domain, pci_dev->addr.bus,
3488                         pci_dev->addr.devid, pci_dev->addr.function,
3489                         strerror(rte_errno));
3490                 ret = -rte_errno;
3491                 /* Roll back. */
3492                 while (i--) {
3493                         if (!list[i].eth_dev)
3494                                 continue;
3495                         mlx5_dev_close(list[i].eth_dev);
3496                         /* mac_addrs must not be freed because in dev_private */
3497                         list[i].eth_dev->data->mac_addrs = NULL;
3498                         claim_zero(rte_eth_dev_release_port(list[i].eth_dev));
3499                 }
3500                 /* Restore original error. */
3501                 rte_errno = -ret;
3502         } else {
3503                 ret = 0;
3504         }
3505 exit:
3506         /*
3507          * Do the routine cleanup:
3508          * - close opened Netlink sockets
3509          * - free allocated spawn data array
3510          * - free the Infiniband device list
3511          */
3512         if (nl_rdma >= 0)
3513                 close(nl_rdma);
3514         if (nl_route >= 0)
3515                 close(nl_route);
3516         if (list)
3517                 rte_free(list);
3518         MLX5_ASSERT(ibv_list);
3519         mlx5_glue->free_device_list(ibv_list);
3520         return ret;
3521 }
3522
3523 /**
3524  * Look for the ethernet device belonging to mlx5 driver.
3525  *
3526  * @param[in] port_id
3527  *   port_id to start looking for device.
3528  * @param[in] pci_dev
3529  *   Pointer to the hint PCI device. When device is being probed
3530  *   the its siblings (master and preceding representors might
3531  *   not have assigned driver yet (because the mlx5_pci_probe()
3532  *   is not completed yet, for this case match on hint PCI
3533  *   device may be used to detect sibling device.
3534  *
3535  * @return
3536  *   port_id of found device, RTE_MAX_ETHPORT if not found.
3537  */
3538 uint16_t
3539 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
3540 {
3541         while (port_id < RTE_MAX_ETHPORTS) {
3542                 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
3543
3544                 if (dev->state != RTE_ETH_DEV_UNUSED &&
3545                     dev->device &&
3546                     (dev->device == &pci_dev->device ||
3547                      (dev->device->driver &&
3548                      dev->device->driver->name &&
3549                      !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
3550                         break;
3551                 port_id++;
3552         }
3553         if (port_id >= RTE_MAX_ETHPORTS)
3554                 return RTE_MAX_ETHPORTS;
3555         return port_id;
3556 }
3557
3558 /**
3559  * DPDK callback to remove a PCI device.
3560  *
3561  * This function removes all Ethernet devices belong to a given PCI device.
3562  *
3563  * @param[in] pci_dev
3564  *   Pointer to the PCI device.
3565  *
3566  * @return
3567  *   0 on success, the function cannot fail.
3568  */
3569 static int
3570 mlx5_pci_remove(struct rte_pci_device *pci_dev)
3571 {
3572         uint16_t port_id;
3573
3574         RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device)
3575                 rte_eth_dev_close(port_id);
3576         return 0;
3577 }
3578
3579 static const struct rte_pci_id mlx5_pci_id_map[] = {
3580         {
3581                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3582                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
3583         },
3584         {
3585                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3586                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
3587         },
3588         {
3589                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3590                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
3591         },
3592         {
3593                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3594                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
3595         },
3596         {
3597                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3598                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
3599         },
3600         {
3601                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3602                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
3603         },
3604         {
3605                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3606                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
3607         },
3608         {
3609                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3610                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
3611         },
3612         {
3613                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3614                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
3615         },
3616         {
3617                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3618                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
3619         },
3620         {
3621                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3622                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
3623         },
3624         {
3625                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3626                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
3627         },
3628         {
3629                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3630                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
3631         },
3632         {
3633                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3634                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF)
3635         },
3636         {
3637                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3638                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
3639         },
3640         {
3641                 .vendor_id = 0
3642         }
3643 };
3644
3645 static struct rte_pci_driver mlx5_driver = {
3646         .driver = {
3647                 .name = MLX5_DRIVER_NAME
3648         },
3649         .id_table = mlx5_pci_id_map,
3650         .probe = mlx5_pci_probe,
3651         .remove = mlx5_pci_remove,
3652         .dma_map = mlx5_dma_map,
3653         .dma_unmap = mlx5_dma_unmap,
3654         .drv_flags = RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV |
3655                      RTE_PCI_DRV_PROBE_AGAIN,
3656 };
3657
3658 /**
3659  * Driver initialization routine.
3660  */
3661 RTE_INIT(rte_mlx5_pmd_init)
3662 {
3663         /* Initialize driver log type. */
3664         mlx5_logtype = rte_log_register("pmd.net.mlx5");
3665         if (mlx5_logtype >= 0)
3666                 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE);
3667
3668         /* Build the static tables for Verbs conversion. */
3669         mlx5_set_ptype_table();
3670         mlx5_set_cksum_table();
3671         mlx5_set_swp_types_table();
3672         if (mlx5_glue)
3673                 rte_pci_register(&mlx5_driver);
3674 }
3675
3676 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
3677 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
3678 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");