1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
13 #include <rte_malloc.h>
14 #include <ethdev_driver.h>
16 #include <rte_bus_pci.h>
17 #include <rte_common.h>
18 #include <rte_kvargs.h>
19 #include <rte_rwlock.h>
20 #include <rte_spinlock.h>
21 #include <rte_string_fns.h>
22 #include <rte_eal_paging.h>
23 #include <rte_alarm.h>
24 #include <rte_cycles.h>
26 #include <mlx5_glue.h>
27 #include <mlx5_devx_cmds.h>
28 #include <mlx5_common.h>
29 #include <mlx5_common_os.h>
30 #include <mlx5_common_mp.h>
31 #include <mlx5_malloc.h>
33 #include "mlx5_defs.h"
35 #include "mlx5_utils.h"
36 #include "mlx5_rxtx.h"
39 #include "mlx5_autoconf.h"
40 #include "mlx5_flow.h"
41 #include "mlx5_flow_os.h"
42 #include "rte_pmd_mlx5.h"
44 #define MLX5_ETH_DRIVER_NAME mlx5_eth
46 /* Driver type key for new device global syntax. */
47 #define MLX5_DRIVER_KEY "driver"
49 /* Device parameter to enable RX completion queue compression. */
50 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
52 /* Device parameter to enable padding Rx packet to cacheline size. */
53 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
55 /* Device parameter to enable Multi-Packet Rx queue. */
56 #define MLX5_RX_MPRQ_EN "mprq_en"
58 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
59 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
61 /* Device parameter to configure log 2 of the stride size for MPRQ. */
62 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
64 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
65 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
67 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
68 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
70 /* Device parameter to configure inline send. Deprecated, ignored.*/
71 #define MLX5_TXQ_INLINE "txq_inline"
73 /* Device parameter to limit packet size to inline with ordinary SEND. */
74 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
76 /* Device parameter to configure minimal data size to inline. */
77 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
79 /* Device parameter to limit packet size to inline with Enhanced MPW. */
80 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
83 * Device parameter to configure the number of TX queues threshold for
84 * enabling inline send.
86 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
89 * Device parameter to configure the number of TX queues threshold for
90 * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
92 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
94 /* Device parameter to enable multi-packet send WQEs. */
95 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
98 * Device parameter to force doorbell register mapping
99 * to non-cahed region eliminating the extra write memory barrier.
101 #define MLX5_TX_DB_NC "tx_db_nc"
104 * Device parameter to include 2 dsegs in the title WQEBB.
105 * Deprecated, ignored.
107 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
110 * Device parameter to limit the size of inlining packet.
111 * Deprecated, ignored.
113 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
116 * Device parameter to enable Tx scheduling on timestamps
117 * and specify the packet pacing granularity in nanoseconds.
119 #define MLX5_TX_PP "tx_pp"
122 * Device parameter to specify skew in nanoseconds on Tx datapath,
123 * it represents the time between SQ start WQE processing and
124 * appearing actual packet data on the wire.
126 #define MLX5_TX_SKEW "tx_skew"
129 * Device parameter to enable hardware Tx vector.
130 * Deprecated, ignored (no vectorized Tx routines anymore).
132 #define MLX5_TX_VEC_EN "tx_vec_en"
134 /* Device parameter to enable hardware Rx vector. */
135 #define MLX5_RX_VEC_EN "rx_vec_en"
137 /* Allow L3 VXLAN flow creation. */
138 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
140 /* Activate DV E-Switch flow steering. */
141 #define MLX5_DV_ESW_EN "dv_esw_en"
143 /* Activate DV flow steering. */
144 #define MLX5_DV_FLOW_EN "dv_flow_en"
146 /* Enable extensive flow metadata support. */
147 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
149 /* Device parameter to let the user manage the lacp traffic of bonded device */
150 #define MLX5_LACP_BY_USER "lacp_by_user"
152 /* Activate Netlink support in VF mode. */
153 #define MLX5_VF_NL_EN "vf_nl_en"
155 /* Enable extending memsegs when creating a MR. */
156 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
158 /* Select port representors to instantiate. */
159 #define MLX5_REPRESENTOR "representor"
161 /* Device parameter to configure the maximum number of dump files per queue. */
162 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
164 /* Configure timeout of LRO session (in microseconds). */
165 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
168 * Device parameter to configure the total data buffer size for a single
169 * hairpin queue (logarithm value).
171 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
173 /* Flow memory reclaim mode. */
174 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
176 /* The default memory allocator used in PMD. */
177 #define MLX5_SYS_MEM_EN "sys_mem_en"
178 /* Decap will be used or not. */
179 #define MLX5_DECAP_EN "decap_en"
181 /* Device parameter to configure allow or prevent duplicate rules pattern. */
182 #define MLX5_ALLOW_DUPLICATE_PATTERN "allow_duplicate_pattern"
184 /* Device parameter to configure implicit registration of mempool memory. */
185 #define MLX5_MR_MEMPOOL_REG_EN "mr_mempool_reg_en"
187 /* Device parameter to configure the delay drop when creating Rxqs. */
188 #define MLX5_DELAY_DROP "delay_drop"
190 /* Shared memory between primary and secondary processes. */
191 struct mlx5_shared_data *mlx5_shared_data;
193 /** Driver-specific log messages type. */
196 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
197 LIST_HEAD_INITIALIZER();
198 static pthread_mutex_t mlx5_dev_ctx_list_mutex;
199 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
200 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
201 [MLX5_IPOOL_DECAP_ENCAP] = {
202 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
208 .malloc = mlx5_malloc,
210 .type = "mlx5_encap_decap_ipool",
212 [MLX5_IPOOL_PUSH_VLAN] = {
213 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
219 .malloc = mlx5_malloc,
221 .type = "mlx5_push_vlan_ipool",
224 .size = sizeof(struct mlx5_flow_dv_tag_resource),
230 .per_core_cache = (1 << 16),
231 .malloc = mlx5_malloc,
233 .type = "mlx5_tag_ipool",
235 [MLX5_IPOOL_PORT_ID] = {
236 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
242 .malloc = mlx5_malloc,
244 .type = "mlx5_port_id_ipool",
246 [MLX5_IPOOL_JUMP] = {
247 .size = sizeof(struct mlx5_flow_tbl_data_entry),
253 .malloc = mlx5_malloc,
255 .type = "mlx5_jump_ipool",
257 [MLX5_IPOOL_SAMPLE] = {
258 .size = sizeof(struct mlx5_flow_dv_sample_resource),
264 .malloc = mlx5_malloc,
266 .type = "mlx5_sample_ipool",
268 [MLX5_IPOOL_DEST_ARRAY] = {
269 .size = sizeof(struct mlx5_flow_dv_dest_array_resource),
275 .malloc = mlx5_malloc,
277 .type = "mlx5_dest_array_ipool",
279 [MLX5_IPOOL_TUNNEL_ID] = {
280 .size = sizeof(struct mlx5_flow_tunnel),
281 .trunk_size = MLX5_MAX_TUNNELS,
284 .type = "mlx5_tunnel_offload",
286 [MLX5_IPOOL_TNL_TBL_ID] = {
289 .type = "mlx5_flow_tnl_tbl_ipool",
294 * The ipool index should grow continually from small to big,
295 * for meter idx, so not set grow_trunk to avoid meter index
296 * not jump continually.
298 .size = sizeof(struct mlx5_legacy_flow_meter),
302 .malloc = mlx5_malloc,
304 .type = "mlx5_meter_ipool",
307 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
313 .malloc = mlx5_malloc,
315 .type = "mlx5_mcp_ipool",
317 [MLX5_IPOOL_HRXQ] = {
318 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
324 .malloc = mlx5_malloc,
326 .type = "mlx5_hrxq_ipool",
328 [MLX5_IPOOL_MLX5_FLOW] = {
330 * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
331 * It set in run time according to PCI function configuration.
339 .per_core_cache = 1 << 19,
340 .malloc = mlx5_malloc,
342 .type = "mlx5_flow_handle_ipool",
344 [MLX5_IPOOL_RTE_FLOW] = {
345 .size = sizeof(struct rte_flow),
349 .malloc = mlx5_malloc,
351 .type = "rte_flow_ipool",
353 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID] = {
356 .type = "mlx5_flow_rss_id_ipool",
358 [MLX5_IPOOL_RSS_SHARED_ACTIONS] = {
359 .size = sizeof(struct mlx5_shared_action_rss),
365 .malloc = mlx5_malloc,
367 .type = "mlx5_shared_action_rss",
369 [MLX5_IPOOL_MTR_POLICY] = {
371 * The ipool index should grow continually from small to big,
372 * for policy idx, so not set grow_trunk to avoid policy index
373 * not jump continually.
375 .size = sizeof(struct mlx5_flow_meter_sub_policy),
379 .malloc = mlx5_malloc,
381 .type = "mlx5_meter_policy_ipool",
385 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
386 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
388 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 1024
391 * Decide whether representor ID is a HPF(host PF) port on BF2.
394 * Pointer to Ethernet device structure.
397 * Non-zero if HPF, otherwise 0.
400 mlx5_is_hpf(struct rte_eth_dev *dev)
402 struct mlx5_priv *priv = dev->data->dev_private;
403 uint16_t repr = MLX5_REPRESENTOR_REPR(priv->representor_id);
404 int type = MLX5_REPRESENTOR_TYPE(priv->representor_id);
406 return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_VF &&
407 MLX5_REPRESENTOR_REPR(-1) == repr;
411 * Decide whether representor ID is a SF port representor.
414 * Pointer to Ethernet device structure.
417 * Non-zero if HPF, otherwise 0.
420 mlx5_is_sf_repr(struct rte_eth_dev *dev)
422 struct mlx5_priv *priv = dev->data->dev_private;
423 int type = MLX5_REPRESENTOR_TYPE(priv->representor_id);
425 return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_SF;
429 * Initialize the ASO aging management structure.
432 * Pointer to mlx5_dev_ctx_shared object to free
435 * 0 on success, a negative errno value otherwise and rte_errno is set.
438 mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh)
444 sh->aso_age_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->aso_age_mng),
445 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
446 if (!sh->aso_age_mng) {
447 DRV_LOG(ERR, "aso_age_mng allocation was failed.");
451 err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_FLOW_HIT);
453 mlx5_free(sh->aso_age_mng);
456 rte_rwlock_init(&sh->aso_age_mng->resize_rwl);
457 rte_spinlock_init(&sh->aso_age_mng->free_sl);
458 LIST_INIT(&sh->aso_age_mng->free);
463 * Close and release all the resources of the ASO aging management structure.
466 * Pointer to mlx5_dev_ctx_shared object to free.
469 mlx5_flow_aso_age_mng_close(struct mlx5_dev_ctx_shared *sh)
473 mlx5_aso_flow_hit_queue_poll_stop(sh);
474 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_FLOW_HIT);
475 if (sh->aso_age_mng->pools) {
476 struct mlx5_aso_age_pool *pool;
478 for (i = 0; i < sh->aso_age_mng->next; ++i) {
479 pool = sh->aso_age_mng->pools[i];
480 claim_zero(mlx5_devx_cmd_destroy
481 (pool->flow_hit_aso_obj));
482 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j)
483 if (pool->actions[j].dr_action)
485 (mlx5_flow_os_destroy_flow_action
486 (pool->actions[j].dr_action));
489 mlx5_free(sh->aso_age_mng->pools);
491 mlx5_free(sh->aso_age_mng);
495 * Initialize the shared aging list information per port.
498 * Pointer to mlx5_dev_ctx_shared object.
501 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
504 struct mlx5_age_info *age_info;
506 for (i = 0; i < sh->max_port; i++) {
507 age_info = &sh->port[i].age_info;
509 TAILQ_INIT(&age_info->aged_counters);
510 LIST_INIT(&age_info->aged_aso);
511 rte_spinlock_init(&age_info->aged_sl);
512 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
517 * Initialize the counters management structure.
520 * Pointer to mlx5_dev_ctx_shared object to free
523 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
527 memset(&sh->cmng, 0, sizeof(sh->cmng));
528 TAILQ_INIT(&sh->cmng.flow_counters);
529 sh->cmng.min_id = MLX5_CNT_BATCH_OFFSET;
530 sh->cmng.max_id = -1;
531 sh->cmng.last_pool_idx = POOL_IDX_INVALID;
532 rte_spinlock_init(&sh->cmng.pool_update_sl);
533 for (i = 0; i < MLX5_COUNTER_TYPE_MAX; i++) {
534 TAILQ_INIT(&sh->cmng.counters[i]);
535 rte_spinlock_init(&sh->cmng.csl[i]);
540 * Destroy all the resources allocated for a counter memory management.
543 * Pointer to the memory management structure.
546 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
548 uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
550 LIST_REMOVE(mng, next);
551 mlx5_os_wrapped_mkey_destroy(&mng->wm);
556 * Close and release all the resources of the counters management.
559 * Pointer to mlx5_dev_ctx_shared object to free.
562 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
564 struct mlx5_counter_stats_mem_mng *mng;
570 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
571 if (rte_errno != EINPROGRESS)
576 if (sh->cmng.pools) {
577 struct mlx5_flow_counter_pool *pool;
578 uint16_t n_valid = sh->cmng.n_valid;
579 bool fallback = sh->cmng.counter_fallback;
581 for (i = 0; i < n_valid; ++i) {
582 pool = sh->cmng.pools[i];
583 if (!fallback && pool->min_dcs)
584 claim_zero(mlx5_devx_cmd_destroy
586 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
587 struct mlx5_flow_counter *cnt =
588 MLX5_POOL_GET_CNT(pool, j);
592 (mlx5_flow_os_destroy_flow_action
594 if (fallback && MLX5_POOL_GET_CNT
595 (pool, j)->dcs_when_free)
596 claim_zero(mlx5_devx_cmd_destroy
597 (cnt->dcs_when_free));
601 mlx5_free(sh->cmng.pools);
603 mng = LIST_FIRST(&sh->cmng.mem_mngs);
605 mlx5_flow_destroy_counter_stat_mem_mng(mng);
606 mng = LIST_FIRST(&sh->cmng.mem_mngs);
608 memset(&sh->cmng, 0, sizeof(sh->cmng));
612 * Initialize the aso flow meters management structure.
615 * Pointer to mlx5_dev_ctx_shared object to free
618 mlx5_aso_flow_mtrs_mng_init(struct mlx5_dev_ctx_shared *sh)
621 sh->mtrmng = mlx5_malloc(MLX5_MEM_ZERO,
623 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
626 "meter management allocation was failed.");
630 if (sh->meter_aso_en) {
631 rte_spinlock_init(&sh->mtrmng->pools_mng.mtrsl);
632 rte_rwlock_init(&sh->mtrmng->pools_mng.resize_mtrwl);
633 LIST_INIT(&sh->mtrmng->pools_mng.meters);
635 sh->mtrmng->def_policy_id = MLX5_INVALID_POLICY_ID;
641 * Close and release all the resources of
642 * the ASO flow meter management structure.
645 * Pointer to mlx5_dev_ctx_shared object to free.
648 mlx5_aso_flow_mtrs_mng_close(struct mlx5_dev_ctx_shared *sh)
650 struct mlx5_aso_mtr_pool *mtr_pool;
651 struct mlx5_flow_mtr_mng *mtrmng = sh->mtrmng;
653 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
654 struct mlx5_aso_mtr *aso_mtr;
656 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
658 if (sh->meter_aso_en) {
659 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_POLICER);
660 idx = mtrmng->pools_mng.n_valid;
662 mtr_pool = mtrmng->pools_mng.pools[idx];
663 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
664 for (i = 0; i < MLX5_ASO_MTRS_PER_POOL; i++) {
665 aso_mtr = &mtr_pool->mtrs[i];
666 if (aso_mtr->fm.meter_action)
668 (mlx5_glue->destroy_flow_action
669 (aso_mtr->fm.meter_action));
671 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
672 claim_zero(mlx5_devx_cmd_destroy
673 (mtr_pool->devx_obj));
674 mtrmng->pools_mng.n_valid--;
677 mlx5_free(sh->mtrmng->pools_mng.pools);
679 mlx5_free(sh->mtrmng);
683 /* Send FLOW_AGED event if needed. */
685 mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh)
687 struct mlx5_age_info *age_info;
690 for (i = 0; i < sh->max_port; i++) {
691 age_info = &sh->port[i].age_info;
692 if (!MLX5_AGE_GET(age_info, MLX5_AGE_EVENT_NEW))
694 MLX5_AGE_UNSET(age_info, MLX5_AGE_EVENT_NEW);
695 if (MLX5_AGE_GET(age_info, MLX5_AGE_TRIGGER)) {
696 MLX5_AGE_UNSET(age_info, MLX5_AGE_TRIGGER);
697 rte_eth_dev_callback_process
698 (&rte_eth_devices[sh->port[i].devx_ih_port_id],
699 RTE_ETH_EVENT_FLOW_AGED, NULL);
705 * Initialize the ASO connection tracking structure.
708 * Pointer to mlx5_dev_ctx_shared object.
711 * 0 on success, a negative errno value otherwise and rte_errno is set.
714 mlx5_flow_aso_ct_mng_init(struct mlx5_dev_ctx_shared *sh)
720 sh->ct_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->ct_mng),
721 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
723 DRV_LOG(ERR, "ASO CT management allocation failed.");
727 err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_CONNECTION_TRACKING);
729 mlx5_free(sh->ct_mng);
730 /* rte_errno should be extracted from the failure. */
734 rte_spinlock_init(&sh->ct_mng->ct_sl);
735 rte_rwlock_init(&sh->ct_mng->resize_rwl);
736 LIST_INIT(&sh->ct_mng->free_cts);
741 * Close and release all the resources of the
742 * ASO connection tracking management structure.
745 * Pointer to mlx5_dev_ctx_shared object to free.
748 mlx5_flow_aso_ct_mng_close(struct mlx5_dev_ctx_shared *sh)
750 struct mlx5_aso_ct_pools_mng *mng = sh->ct_mng;
751 struct mlx5_aso_ct_pool *ct_pool;
752 struct mlx5_aso_ct_action *ct;
758 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_CONNECTION_TRACKING);
762 ct_pool = mng->pools[idx];
763 for (i = 0; i < MLX5_ASO_CT_ACTIONS_PER_POOL; i++) {
764 ct = &ct_pool->actions[i];
765 val = __atomic_fetch_sub(&ct->refcnt, 1,
767 MLX5_ASSERT(val == 1);
770 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
771 if (ct->dr_action_orig)
772 claim_zero(mlx5_glue->destroy_flow_action
773 (ct->dr_action_orig));
774 if (ct->dr_action_rply)
775 claim_zero(mlx5_glue->destroy_flow_action
776 (ct->dr_action_rply));
779 claim_zero(mlx5_devx_cmd_destroy(ct_pool->devx_obj));
781 DRV_LOG(DEBUG, "%u ASO CT objects are being used in the pool %u",
785 /* in case of failure. */
788 mlx5_free(mng->pools);
790 /* Management structure must be cleared to 0s during allocation. */
795 * Initialize the flow resources' indexed mempool.
798 * Pointer to mlx5_dev_ctx_shared object.
800 * Pointer to user dev config.
803 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
804 const struct mlx5_dev_config *config)
807 struct mlx5_indexed_pool_config cfg;
809 for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
810 cfg = mlx5_ipool_cfg[i];
815 * Set MLX5_IPOOL_MLX5_FLOW ipool size
816 * according to PCI function flow configuration.
818 case MLX5_IPOOL_MLX5_FLOW:
819 cfg.size = config->dv_flow_en ?
820 sizeof(struct mlx5_flow_handle) :
821 MLX5_FLOW_HANDLE_VERBS_SIZE;
824 if (config->reclaim_mode) {
825 cfg.release_mem_en = 1;
826 cfg.per_core_cache = 0;
828 cfg.release_mem_en = 0;
830 sh->ipool[i] = mlx5_ipool_create(&cfg);
836 * Release the flow resources' indexed mempool.
839 * Pointer to mlx5_dev_ctx_shared object.
842 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
846 for (i = 0; i < MLX5_IPOOL_MAX; ++i)
847 mlx5_ipool_destroy(sh->ipool[i]);
848 for (i = 0; i < MLX5_MAX_MODIFY_NUM; ++i)
849 if (sh->mdh_ipools[i])
850 mlx5_ipool_destroy(sh->mdh_ipools[i]);
854 * Check if dynamic flex parser for eCPRI already exists.
857 * Pointer to Ethernet device structure.
860 * true on exists, false on not.
863 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
865 struct mlx5_priv *priv = dev->data->dev_private;
866 struct mlx5_ecpri_parser_profile *prf = &priv->sh->ecpri_parser;
872 * Allocation of a flex parser for eCPRI. Once created, this parser related
873 * resources will be held until the device is closed.
876 * Pointer to Ethernet device structure.
879 * 0 on success, a negative errno value otherwise and rte_errno is set.
882 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
884 struct mlx5_priv *priv = dev->data->dev_private;
885 struct mlx5_ecpri_parser_profile *prf = &priv->sh->ecpri_parser;
886 struct mlx5_devx_graph_node_attr node = {
887 .modify_field_select = 0,
892 if (!priv->sh->cdev->config.hca_attr.parse_graph_flex_node) {
893 DRV_LOG(ERR, "Dynamic flex parser is not supported "
894 "for device %s.", priv->dev_data->name);
897 node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED;
898 /* 8 bytes now: 4B common header + 4B message body header. */
899 node.header_length_base_value = 0x8;
900 /* After MAC layer: Ether / VLAN. */
901 node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC;
902 /* Type of compared condition should be 0xAEFE in the L2 layer. */
903 node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI;
904 /* Sample #0: type in common header. */
905 node.sample[0].flow_match_sample_en = 1;
907 node.sample[0].flow_match_sample_offset_mode = 0x0;
908 /* Only the 2nd byte will be used. */
909 node.sample[0].flow_match_sample_field_base_offset = 0x0;
910 /* Sample #1: message payload. */
911 node.sample[1].flow_match_sample_en = 1;
913 node.sample[1].flow_match_sample_offset_mode = 0x0;
915 * Only the first two bytes will be used right now, and its offset will
916 * start after the common header that with the length of a DW(u32).
918 node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);
919 prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->cdev->ctx, &node);
921 DRV_LOG(ERR, "Failed to create flex parser node object.");
922 return (rte_errno == 0) ? -ENODEV : -rte_errno;
925 ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num);
927 DRV_LOG(ERR, "Failed to query sample IDs.");
928 return (rte_errno == 0) ? -ENODEV : -rte_errno;
930 prf->offset[0] = 0x0;
931 prf->offset[1] = sizeof(uint32_t);
932 prf->ids[0] = ids[0];
933 prf->ids[1] = ids[1];
938 * Destroy the flex parser node, including the parser itself, input / output
939 * arcs and DW samples. Resources could be reused then.
942 * Pointer to Ethernet device structure.
945 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
947 struct mlx5_priv *priv = dev->data->dev_private;
948 struct mlx5_ecpri_parser_profile *prf = &priv->sh->ecpri_parser;
951 mlx5_devx_cmd_destroy(prf->obj);
956 mlx5_get_supported_sw_parsing_offloads(const struct mlx5_hca_attr *attr)
958 uint32_t sw_parsing_offloads = 0;
961 sw_parsing_offloads |= MLX5_SW_PARSING_CAP;
963 sw_parsing_offloads |= MLX5_SW_PARSING_CSUM_CAP;
966 sw_parsing_offloads |= MLX5_SW_PARSING_TSO_CAP;
968 return sw_parsing_offloads;
972 mlx5_get_supported_tunneling_offloads(const struct mlx5_hca_attr *attr)
974 uint32_t tn_offloads = 0;
976 if (attr->tunnel_stateless_vxlan)
977 tn_offloads |= MLX5_TUNNELED_OFFLOADS_VXLAN_CAP;
978 if (attr->tunnel_stateless_gre)
979 tn_offloads |= MLX5_TUNNELED_OFFLOADS_GRE_CAP;
980 if (attr->tunnel_stateless_geneve_rx)
981 tn_offloads |= MLX5_TUNNELED_OFFLOADS_GENEVE_CAP;
985 /* Fill all fields of UAR structure. */
987 mlx5_rxtx_uars_prepare(struct mlx5_dev_ctx_shared *sh)
991 ret = mlx5_devx_uar_prepare(sh->cdev, &sh->tx_uar);
993 DRV_LOG(ERR, "Failed to prepare Tx DevX UAR.");
996 MLX5_ASSERT(sh->tx_uar.obj);
997 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->tx_uar.obj));
998 ret = mlx5_devx_uar_prepare(sh->cdev, &sh->rx_uar);
1000 DRV_LOG(ERR, "Failed to prepare Rx DevX UAR.");
1001 mlx5_devx_uar_release(&sh->tx_uar);
1004 MLX5_ASSERT(sh->rx_uar.obj);
1005 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->rx_uar.obj));
1010 mlx5_rxtx_uars_release(struct mlx5_dev_ctx_shared *sh)
1012 mlx5_devx_uar_release(&sh->rx_uar);
1013 mlx5_devx_uar_release(&sh->tx_uar);
1017 * rte_mempool_walk() callback to unregister Rx mempools.
1018 * It used when implicit mempool registration is disabled.
1021 * The mempool being walked.
1023 * Pointer to the device shared context.
1026 mlx5_dev_ctx_shared_rx_mempool_unregister_cb(struct rte_mempool *mp, void *arg)
1028 struct mlx5_dev_ctx_shared *sh = arg;
1030 mlx5_dev_mempool_unregister(sh->cdev, mp);
1034 * Callback used when implicit mempool registration is disabled
1035 * in order to track Rx mempool destruction.
1038 * Mempool life cycle event.
1040 * An Rx mempool registered explicitly when the port is started.
1042 * Pointer to a device shared context.
1045 mlx5_dev_ctx_shared_rx_mempool_event_cb(enum rte_mempool_event event,
1046 struct rte_mempool *mp, void *arg)
1048 struct mlx5_dev_ctx_shared *sh = arg;
1050 if (event == RTE_MEMPOOL_EVENT_DESTROY)
1051 mlx5_dev_mempool_unregister(sh->cdev, mp);
1055 mlx5_dev_ctx_shared_mempool_subscribe(struct rte_eth_dev *dev)
1057 struct mlx5_priv *priv = dev->data->dev_private;
1058 struct mlx5_dev_ctx_shared *sh = priv->sh;
1061 /* Check if we only need to track Rx mempool destruction. */
1062 if (!sh->cdev->config.mr_mempool_reg_en) {
1063 ret = rte_mempool_event_callback_register
1064 (mlx5_dev_ctx_shared_rx_mempool_event_cb, sh);
1065 return ret == 0 || rte_errno == EEXIST ? 0 : ret;
1067 return mlx5_dev_mempool_subscribe(sh->cdev);
1071 * Set up multiple TISs with different affinities according to
1072 * number of bonding ports
1075 * Pointer of shared context.
1078 * Zero on success, -1 otherwise.
1081 mlx5_setup_tis(struct mlx5_dev_ctx_shared *sh)
1084 struct mlx5_devx_lag_context lag_ctx = { 0 };
1085 struct mlx5_devx_tis_attr tis_attr = { 0 };
1087 tis_attr.transport_domain = sh->td->id;
1088 if (sh->bond.n_port) {
1089 if (!mlx5_devx_cmd_query_lag(sh->cdev->ctx, &lag_ctx)) {
1090 sh->lag.tx_remap_affinity[0] =
1091 lag_ctx.tx_remap_affinity_1;
1092 sh->lag.tx_remap_affinity[1] =
1093 lag_ctx.tx_remap_affinity_2;
1094 sh->lag.affinity_mode = lag_ctx.port_select_mode;
1096 DRV_LOG(ERR, "Failed to query lag affinity.");
1099 if (sh->lag.affinity_mode == MLX5_LAG_MODE_TIS) {
1100 for (i = 0; i < sh->bond.n_port; i++) {
1101 tis_attr.lag_tx_port_affinity =
1102 MLX5_IFC_LAG_MAP_TIS_AFFINITY(i,
1104 sh->tis[i] = mlx5_devx_cmd_create_tis(sh->cdev->ctx,
1107 DRV_LOG(ERR, "Failed to TIS %d/%d for bonding device"
1108 " %s.", i, sh->bond.n_port,
1113 DRV_LOG(DEBUG, "LAG number of ports : %d, affinity_1 & 2 : pf%d & %d.\n",
1114 sh->bond.n_port, lag_ctx.tx_remap_affinity_1,
1115 lag_ctx.tx_remap_affinity_2);
1118 if (sh->lag.affinity_mode == MLX5_LAG_MODE_HASH)
1119 DRV_LOG(INFO, "Device %s enabled HW hash based LAG.",
1122 tis_attr.lag_tx_port_affinity = 0;
1123 sh->tis[0] = mlx5_devx_cmd_create_tis(sh->cdev->ctx, &tis_attr);
1125 DRV_LOG(ERR, "Failed to TIS 0 for bonding device"
1126 " %s.", sh->ibdev_name);
1133 * Configure realtime timestamp format.
1136 * Pointer to mlx5_dev_ctx_shared object.
1138 * Device configuration parameters.
1140 * Pointer to DevX HCA capabilities structure.
1143 mlx5_rt_timestamp_config(struct mlx5_dev_ctx_shared *sh,
1144 struct mlx5_dev_config *config,
1145 struct mlx5_hca_attr *hca_attr)
1147 uint32_t dw_cnt = MLX5_ST_SZ_DW(register_mtutc);
1148 uint32_t reg[dw_cnt];
1151 if (hca_attr->access_register_user)
1152 ret = mlx5_devx_cmd_register_read(sh->cdev->ctx,
1153 MLX5_REGISTER_ID_MTUTC, 0,
1158 /* MTUTC register is read successfully. */
1159 ts_mode = MLX5_GET(register_mtutc, reg, time_stamp_mode);
1160 if (ts_mode == MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME)
1161 config->rt_timestamp = 1;
1163 /* Kernel does not support register reading. */
1164 if (hca_attr->dev_freq_khz == (NS_PER_S / MS_PER_S))
1165 config->rt_timestamp = 1;
1170 * Allocate shared device context. If there is multiport device the
1171 * master and representors will share this context, if there is single
1172 * port dedicated device, the context will be used by only given
1173 * port due to unification.
1175 * Routine first searches the context for the specified device name,
1176 * if found the shared context assumed and reference counter is incremented.
1177 * If no context found the new one is created and initialized with specified
1178 * device context and parameters.
1181 * Pointer to the device attributes (name, port, etc).
1183 * Pointer to device configuration structure.
1186 * Pointer to mlx5_dev_ctx_shared object on success,
1187 * otherwise NULL and rte_errno is set.
1189 struct mlx5_dev_ctx_shared *
1190 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
1191 const struct mlx5_dev_config *config)
1193 struct mlx5_dev_ctx_shared *sh;
1198 /* Secondary process should not create the shared context. */
1199 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1200 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1201 /* Search for IB context by device name. */
1202 LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
1203 if (!strcmp(sh->ibdev_name, spawn->phys_dev_name)) {
1208 /* No device found, we have to create new shared context. */
1209 MLX5_ASSERT(spawn->max_port);
1210 sh = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
1211 sizeof(struct mlx5_dev_ctx_shared) +
1212 spawn->max_port * sizeof(struct mlx5_dev_shared_port),
1213 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
1215 DRV_LOG(ERR, "Shared context allocation failure.");
1219 pthread_mutex_init(&sh->txpp.mutex, NULL);
1220 sh->numa_node = spawn->cdev->dev->numa_node;
1221 sh->cdev = spawn->cdev;
1222 if (spawn->bond_info)
1223 sh->bond = *spawn->bond_info;
1224 err = mlx5_os_get_dev_attr(sh->cdev, &sh->device_attr);
1226 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
1230 sh->max_port = spawn->max_port;
1231 sh->reclaim_mode = config->reclaim_mode;
1232 strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->cdev->ctx),
1233 sizeof(sh->ibdev_name) - 1);
1234 strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->cdev->ctx),
1235 sizeof(sh->ibdev_path) - 1);
1237 * Setting port_id to max unallowed value means there is no interrupt
1238 * subhandler installed for the given port index i.
1240 for (i = 0; i < sh->max_port; i++) {
1241 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
1242 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
1244 if (sh->cdev->config.devx) {
1245 sh->td = mlx5_devx_cmd_create_td(sh->cdev->ctx);
1247 DRV_LOG(ERR, "TD allocation failure");
1251 if (mlx5_setup_tis(sh)) {
1252 DRV_LOG(ERR, "TIS allocation failure");
1256 err = mlx5_rxtx_uars_prepare(sh);
1261 /* Initialize UAR access locks for 32bit implementations. */
1262 rte_spinlock_init(&sh->uar_lock_cq);
1263 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
1264 rte_spinlock_init(&sh->uar_lock[i]);
1267 mlx5_os_dev_shared_handler_install(sh);
1268 if (LIST_EMPTY(&mlx5_dev_ctx_list)) {
1269 err = mlx5_flow_os_init_workspace_once();
1273 mlx5_flow_aging_init(sh);
1274 mlx5_flow_counters_mng_init(sh);
1275 mlx5_flow_ipool_create(sh, config);
1276 /* Add context to the global device list. */
1277 LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
1278 rte_spinlock_init(&sh->geneve_tlv_opt_sl);
1280 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1284 pthread_mutex_destroy(&sh->txpp.mutex);
1285 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1287 mlx5_rxtx_uars_release(sh);
1291 claim_zero(mlx5_devx_cmd_destroy(sh->tis[i]));
1292 } while (++i < (uint32_t)sh->bond.n_port);
1294 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1301 * Free shared IB device context. Decrement counter and if zero free
1302 * all allocated resources and close handles.
1305 * Pointer to mlx5_dev_ctx_shared object to free
1308 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
1313 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1314 #ifdef RTE_LIBRTE_MLX5_DEBUG
1315 /* Check the object presence in the list. */
1316 struct mlx5_dev_ctx_shared *lctx;
1318 LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
1323 DRV_LOG(ERR, "Freeing non-existing shared IB context");
1328 MLX5_ASSERT(sh->refcnt);
1329 /* Secondary process should not free the shared context. */
1330 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1333 /* Stop watching for mempool events and unregister all mempools. */
1334 if (!sh->cdev->config.mr_mempool_reg_en) {
1335 ret = rte_mempool_event_callback_unregister
1336 (mlx5_dev_ctx_shared_rx_mempool_event_cb, sh);
1339 (mlx5_dev_ctx_shared_rx_mempool_unregister_cb, sh);
1341 /* Remove context from the global device list. */
1342 LIST_REMOVE(sh, next);
1343 /* Release resources on the last device removal. */
1344 if (LIST_EMPTY(&mlx5_dev_ctx_list)) {
1345 mlx5_os_net_cleanup();
1346 mlx5_flow_os_release_workspace();
1348 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1349 if (sh->flex_parsers_dv) {
1350 mlx5_list_destroy(sh->flex_parsers_dv);
1351 sh->flex_parsers_dv = NULL;
1354 * Ensure there is no async event handler installed.
1355 * Only primary process handles async device events.
1357 mlx5_flow_counters_mng_close(sh);
1359 mlx5_flow_aso_ct_mng_close(sh);
1360 if (sh->aso_age_mng) {
1361 mlx5_flow_aso_age_mng_close(sh);
1362 sh->aso_age_mng = NULL;
1365 mlx5_aso_flow_mtrs_mng_close(sh);
1366 mlx5_flow_ipool_destroy(sh);
1367 mlx5_os_dev_shared_handler_uninstall(sh);
1368 mlx5_rxtx_uars_release(sh);
1371 claim_zero(mlx5_devx_cmd_destroy(sh->tis[i]));
1372 } while (++i < sh->bond.n_port);
1374 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1375 MLX5_ASSERT(sh->geneve_tlv_option_resource == NULL);
1376 pthread_mutex_destroy(&sh->txpp.mutex);
1380 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1384 * Destroy table hash list.
1387 * Pointer to the private device data structure.
1390 mlx5_free_table_hash_list(struct mlx5_priv *priv)
1392 struct mlx5_dev_ctx_shared *sh = priv->sh;
1396 mlx5_hlist_destroy(sh->flow_tbls);
1397 sh->flow_tbls = NULL;
1401 * Initialize flow table hash list and create the root tables entry
1405 * Pointer to the private device data structure.
1408 * Zero on success, positive error code otherwise.
1411 mlx5_alloc_table_hash_list(struct mlx5_priv *priv __rte_unused)
1414 /* Tables are only used in DV and DR modes. */
1415 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
1416 struct mlx5_dev_ctx_shared *sh = priv->sh;
1417 char s[MLX5_NAME_SIZE];
1420 snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1421 sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE,
1423 flow_dv_tbl_create_cb,
1424 flow_dv_tbl_match_cb,
1425 flow_dv_tbl_remove_cb,
1426 flow_dv_tbl_clone_cb,
1427 flow_dv_tbl_clone_free_cb);
1428 if (!sh->flow_tbls) {
1429 DRV_LOG(ERR, "flow tables with hash creation failed.");
1433 #ifndef HAVE_MLX5DV_DR
1434 struct rte_flow_error error;
1435 struct rte_eth_dev *dev = &rte_eth_devices[priv->dev_data->port_id];
1438 * In case we have not DR support, the zero tables should be created
1439 * because DV expect to see them even if they cannot be created by
1442 if (!flow_dv_tbl_resource_get(dev, 0, 0, 0, 0,
1443 NULL, 0, 1, 0, &error) ||
1444 !flow_dv_tbl_resource_get(dev, 0, 1, 0, 0,
1445 NULL, 0, 1, 0, &error) ||
1446 !flow_dv_tbl_resource_get(dev, 0, 0, 1, 0,
1447 NULL, 0, 1, 0, &error)) {
1453 mlx5_free_table_hash_list(priv);
1454 #endif /* HAVE_MLX5DV_DR */
1460 * Retrieve integer value from environment variable.
1463 * Environment variable name.
1466 * Integer value, 0 if the variable is not set.
1469 mlx5_getenv_int(const char *name)
1471 const char *val = getenv(name);
1479 * DPDK callback to add udp tunnel port
1482 * A pointer to eth_dev
1483 * @param[in] udp_tunnel
1484 * A pointer to udp tunnel
1487 * 0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1490 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1491 struct rte_eth_udp_tunnel *udp_tunnel)
1493 MLX5_ASSERT(udp_tunnel != NULL);
1494 if (udp_tunnel->prot_type == RTE_ETH_TUNNEL_TYPE_VXLAN &&
1495 udp_tunnel->udp_port == 4789)
1497 if (udp_tunnel->prot_type == RTE_ETH_TUNNEL_TYPE_VXLAN_GPE &&
1498 udp_tunnel->udp_port == 4790)
1504 * Initialize process private data structure.
1507 * Pointer to Ethernet device structure.
1510 * 0 on success, a negative errno value otherwise and rte_errno is set.
1513 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1515 struct mlx5_priv *priv = dev->data->dev_private;
1516 struct mlx5_proc_priv *ppriv;
1519 mlx5_proc_priv_uninit(dev);
1521 * UAR register table follows the process private structure. BlueFlame
1522 * registers for Tx queues are stored in the table.
1524 ppriv_size = sizeof(struct mlx5_proc_priv) +
1525 priv->txqs_n * sizeof(struct mlx5_uar_data);
1526 ppriv = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, ppriv_size,
1527 RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1532 ppriv->uar_table_sz = priv->txqs_n;
1533 dev->process_private = ppriv;
1534 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
1535 priv->sh->pppriv = ppriv;
1540 * Un-initialize process private data structure.
1543 * Pointer to Ethernet device structure.
1546 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1548 if (!dev->process_private)
1550 mlx5_free(dev->process_private);
1551 dev->process_private = NULL;
1555 * DPDK callback to close the device.
1557 * Destroy all queues and objects, free memory.
1560 * Pointer to Ethernet device structure.
1563 mlx5_dev_close(struct rte_eth_dev *dev)
1565 struct mlx5_priv *priv = dev->data->dev_private;
1569 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1570 /* Check if process_private released. */
1571 if (!dev->process_private)
1573 mlx5_tx_uar_uninit_secondary(dev);
1574 mlx5_proc_priv_uninit(dev);
1575 rte_eth_dev_release_port(dev);
1580 DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1582 ((priv->sh->cdev->ctx != NULL) ?
1583 mlx5_os_get_ctx_device_name(priv->sh->cdev->ctx) : ""));
1585 * If default mreg copy action is removed at the stop stage,
1586 * the search will return none and nothing will be done anymore.
1588 mlx5_flow_stop_default(dev);
1589 mlx5_traffic_disable(dev);
1591 * If all the flows are already flushed in the device stop stage,
1592 * then this will return directly without any action.
1594 mlx5_flow_list_flush(dev, MLX5_FLOW_TYPE_GEN, true);
1595 mlx5_action_handle_flush(dev);
1596 mlx5_flow_meter_flush(dev, NULL);
1597 /* Prevent crashes when queues are still in use. */
1598 dev->rx_pkt_burst = rte_eth_pkt_burst_dummy;
1599 dev->tx_pkt_burst = rte_eth_pkt_burst_dummy;
1601 /* Disable datapath on secondary process. */
1602 mlx5_mp_os_req_stop_rxtx(dev);
1603 /* Free the eCPRI flex parser resource. */
1604 mlx5_flex_parser_ecpri_release(dev);
1605 mlx5_flex_item_port_cleanup(dev);
1606 if (priv->rxq_privs != NULL) {
1607 /* XXX race condition if mlx5_rx_burst() is still running. */
1608 rte_delay_us_sleep(1000);
1609 for (i = 0; (i != priv->rxqs_n); ++i)
1610 mlx5_rxq_release(dev, i);
1612 mlx5_free(priv->rxq_privs);
1613 priv->rxq_privs = NULL;
1615 if (priv->txqs != NULL) {
1616 /* XXX race condition if mlx5_tx_burst() is still running. */
1617 rte_delay_us_sleep(1000);
1618 for (i = 0; (i != priv->txqs_n); ++i)
1619 mlx5_txq_release(dev, i);
1623 mlx5_proc_priv_uninit(dev);
1624 if (priv->q_counters) {
1625 mlx5_devx_cmd_destroy(priv->q_counters);
1626 priv->q_counters = NULL;
1628 if (priv->drop_queue.hrxq)
1629 mlx5_drop_action_destroy(dev);
1630 if (priv->mreg_cp_tbl)
1631 mlx5_hlist_destroy(priv->mreg_cp_tbl);
1632 mlx5_mprq_free_mp(dev);
1633 mlx5_os_free_shared_dr(priv);
1634 if (priv->rss_conf.rss_key != NULL)
1635 mlx5_free(priv->rss_conf.rss_key);
1636 if (priv->reta_idx != NULL)
1637 mlx5_free(priv->reta_idx);
1638 if (priv->config.vf)
1639 mlx5_os_mac_addr_flush(dev);
1640 if (priv->nl_socket_route >= 0)
1641 close(priv->nl_socket_route);
1642 if (priv->nl_socket_rdma >= 0)
1643 close(priv->nl_socket_rdma);
1644 if (priv->vmwa_context)
1645 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1646 ret = mlx5_hrxq_verify(dev);
1648 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1649 dev->data->port_id);
1650 ret = mlx5_ind_table_obj_verify(dev);
1652 DRV_LOG(WARNING, "port %u some indirection table still remain",
1653 dev->data->port_id);
1654 ret = mlx5_rxq_obj_verify(dev);
1656 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1657 dev->data->port_id);
1658 ret = mlx5_rxq_verify(dev);
1660 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1661 dev->data->port_id);
1662 ret = mlx5_txq_obj_verify(dev);
1664 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1665 dev->data->port_id);
1666 ret = mlx5_txq_verify(dev);
1668 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1669 dev->data->port_id);
1670 ret = mlx5_flow_verify(dev);
1672 DRV_LOG(WARNING, "port %u some flows still remain",
1673 dev->data->port_id);
1675 mlx5_list_destroy(priv->hrxqs);
1677 * Free the shared context in last turn, because the cleanup
1678 * routines above may use some shared fields, like
1679 * mlx5_os_mac_addr_flush() uses ibdev_path for retrieving
1680 * ifindex if Netlink fails.
1682 mlx5_free_shared_dev_ctx(priv->sh);
1683 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1687 MLX5_ETH_FOREACH_DEV(port_id, dev->device) {
1688 struct mlx5_priv *opriv =
1689 rte_eth_devices[port_id].data->dev_private;
1692 opriv->domain_id != priv->domain_id ||
1693 &rte_eth_devices[port_id] == dev)
1699 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1701 memset(priv, 0, sizeof(*priv));
1702 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1704 * Reset mac_addrs to NULL such that it is not freed as part of
1705 * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1706 * it is freed when dev_private is freed.
1708 dev->data->mac_addrs = NULL;
1712 const struct eth_dev_ops mlx5_dev_ops = {
1713 .dev_configure = mlx5_dev_configure,
1714 .dev_start = mlx5_dev_start,
1715 .dev_stop = mlx5_dev_stop,
1716 .dev_set_link_down = mlx5_set_link_down,
1717 .dev_set_link_up = mlx5_set_link_up,
1718 .dev_close = mlx5_dev_close,
1719 .promiscuous_enable = mlx5_promiscuous_enable,
1720 .promiscuous_disable = mlx5_promiscuous_disable,
1721 .allmulticast_enable = mlx5_allmulticast_enable,
1722 .allmulticast_disable = mlx5_allmulticast_disable,
1723 .link_update = mlx5_link_update,
1724 .stats_get = mlx5_stats_get,
1725 .stats_reset = mlx5_stats_reset,
1726 .xstats_get = mlx5_xstats_get,
1727 .xstats_reset = mlx5_xstats_reset,
1728 .xstats_get_names = mlx5_xstats_get_names,
1729 .fw_version_get = mlx5_fw_version_get,
1730 .dev_infos_get = mlx5_dev_infos_get,
1731 .representor_info_get = mlx5_representor_info_get,
1732 .read_clock = mlx5_txpp_read_clock,
1733 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1734 .vlan_filter_set = mlx5_vlan_filter_set,
1735 .rx_queue_setup = mlx5_rx_queue_setup,
1736 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1737 .tx_queue_setup = mlx5_tx_queue_setup,
1738 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1739 .rx_queue_release = mlx5_rx_queue_release,
1740 .tx_queue_release = mlx5_tx_queue_release,
1741 .rx_queue_start = mlx5_rx_queue_start,
1742 .rx_queue_stop = mlx5_rx_queue_stop,
1743 .tx_queue_start = mlx5_tx_queue_start,
1744 .tx_queue_stop = mlx5_tx_queue_stop,
1745 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1746 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1747 .mac_addr_remove = mlx5_mac_addr_remove,
1748 .mac_addr_add = mlx5_mac_addr_add,
1749 .mac_addr_set = mlx5_mac_addr_set,
1750 .set_mc_addr_list = mlx5_set_mc_addr_list,
1751 .mtu_set = mlx5_dev_set_mtu,
1752 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1753 .vlan_offload_set = mlx5_vlan_offload_set,
1754 .reta_update = mlx5_dev_rss_reta_update,
1755 .reta_query = mlx5_dev_rss_reta_query,
1756 .rss_hash_update = mlx5_rss_hash_update,
1757 .rss_hash_conf_get = mlx5_rss_hash_conf_get,
1758 .flow_ops_get = mlx5_flow_ops_get,
1759 .rxq_info_get = mlx5_rxq_info_get,
1760 .txq_info_get = mlx5_txq_info_get,
1761 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1762 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1763 .rx_queue_intr_enable = mlx5_rx_intr_enable,
1764 .rx_queue_intr_disable = mlx5_rx_intr_disable,
1765 .is_removed = mlx5_is_removed,
1766 .udp_tunnel_port_add = mlx5_udp_tunnel_port_add,
1767 .get_module_info = mlx5_get_module_info,
1768 .get_module_eeprom = mlx5_get_module_eeprom,
1769 .hairpin_cap_get = mlx5_hairpin_cap_get,
1770 .mtr_ops_get = mlx5_flow_meter_ops_get,
1771 .hairpin_bind = mlx5_hairpin_bind,
1772 .hairpin_unbind = mlx5_hairpin_unbind,
1773 .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1774 .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1775 .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1776 .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1777 .get_monitor_addr = mlx5_get_monitor_addr,
1780 /* Available operations from secondary process. */
1781 const struct eth_dev_ops mlx5_dev_sec_ops = {
1782 .stats_get = mlx5_stats_get,
1783 .stats_reset = mlx5_stats_reset,
1784 .xstats_get = mlx5_xstats_get,
1785 .xstats_reset = mlx5_xstats_reset,
1786 .xstats_get_names = mlx5_xstats_get_names,
1787 .fw_version_get = mlx5_fw_version_get,
1788 .dev_infos_get = mlx5_dev_infos_get,
1789 .representor_info_get = mlx5_representor_info_get,
1790 .read_clock = mlx5_txpp_read_clock,
1791 .rx_queue_start = mlx5_rx_queue_start,
1792 .rx_queue_stop = mlx5_rx_queue_stop,
1793 .tx_queue_start = mlx5_tx_queue_start,
1794 .tx_queue_stop = mlx5_tx_queue_stop,
1795 .rxq_info_get = mlx5_rxq_info_get,
1796 .txq_info_get = mlx5_txq_info_get,
1797 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1798 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1799 .get_module_info = mlx5_get_module_info,
1800 .get_module_eeprom = mlx5_get_module_eeprom,
1803 /* Available operations in flow isolated mode. */
1804 const struct eth_dev_ops mlx5_dev_ops_isolate = {
1805 .dev_configure = mlx5_dev_configure,
1806 .dev_start = mlx5_dev_start,
1807 .dev_stop = mlx5_dev_stop,
1808 .dev_set_link_down = mlx5_set_link_down,
1809 .dev_set_link_up = mlx5_set_link_up,
1810 .dev_close = mlx5_dev_close,
1811 .promiscuous_enable = mlx5_promiscuous_enable,
1812 .promiscuous_disable = mlx5_promiscuous_disable,
1813 .allmulticast_enable = mlx5_allmulticast_enable,
1814 .allmulticast_disable = mlx5_allmulticast_disable,
1815 .link_update = mlx5_link_update,
1816 .stats_get = mlx5_stats_get,
1817 .stats_reset = mlx5_stats_reset,
1818 .xstats_get = mlx5_xstats_get,
1819 .xstats_reset = mlx5_xstats_reset,
1820 .xstats_get_names = mlx5_xstats_get_names,
1821 .fw_version_get = mlx5_fw_version_get,
1822 .dev_infos_get = mlx5_dev_infos_get,
1823 .representor_info_get = mlx5_representor_info_get,
1824 .read_clock = mlx5_txpp_read_clock,
1825 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1826 .vlan_filter_set = mlx5_vlan_filter_set,
1827 .rx_queue_setup = mlx5_rx_queue_setup,
1828 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1829 .tx_queue_setup = mlx5_tx_queue_setup,
1830 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1831 .rx_queue_release = mlx5_rx_queue_release,
1832 .tx_queue_release = mlx5_tx_queue_release,
1833 .rx_queue_start = mlx5_rx_queue_start,
1834 .rx_queue_stop = mlx5_rx_queue_stop,
1835 .tx_queue_start = mlx5_tx_queue_start,
1836 .tx_queue_stop = mlx5_tx_queue_stop,
1837 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1838 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1839 .mac_addr_remove = mlx5_mac_addr_remove,
1840 .mac_addr_add = mlx5_mac_addr_add,
1841 .mac_addr_set = mlx5_mac_addr_set,
1842 .set_mc_addr_list = mlx5_set_mc_addr_list,
1843 .mtu_set = mlx5_dev_set_mtu,
1844 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1845 .vlan_offload_set = mlx5_vlan_offload_set,
1846 .flow_ops_get = mlx5_flow_ops_get,
1847 .rxq_info_get = mlx5_rxq_info_get,
1848 .txq_info_get = mlx5_txq_info_get,
1849 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1850 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1851 .rx_queue_intr_enable = mlx5_rx_intr_enable,
1852 .rx_queue_intr_disable = mlx5_rx_intr_disable,
1853 .is_removed = mlx5_is_removed,
1854 .get_module_info = mlx5_get_module_info,
1855 .get_module_eeprom = mlx5_get_module_eeprom,
1856 .hairpin_cap_get = mlx5_hairpin_cap_get,
1857 .mtr_ops_get = mlx5_flow_meter_ops_get,
1858 .hairpin_bind = mlx5_hairpin_bind,
1859 .hairpin_unbind = mlx5_hairpin_unbind,
1860 .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1861 .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1862 .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1863 .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1864 .get_monitor_addr = mlx5_get_monitor_addr,
1868 * Verify and store value for device argument.
1871 * Key argument to verify.
1873 * Value associated with key.
1878 * 0 on success, a negative errno value otherwise and rte_errno is set.
1881 mlx5_args_check(const char *key, const char *val, void *opaque)
1883 struct mlx5_dev_config *config = opaque;
1887 /* No-op, port representors are processed in mlx5_dev_spawn(). */
1888 if (!strcmp(MLX5_DRIVER_KEY, key) || !strcmp(MLX5_REPRESENTOR, key) ||
1889 !strcmp(MLX5_SYS_MEM_EN, key) || !strcmp(MLX5_TX_DB_NC, key) ||
1890 !strcmp(MLX5_MR_MEMPOOL_REG_EN, key) ||
1891 !strcmp(MLX5_MR_EXT_MEMSEG_EN, key))
1894 tmp = strtol(val, NULL, 0);
1897 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1900 if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
1901 /* Negative values are acceptable for some keys only. */
1903 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
1906 mod = tmp >= 0 ? tmp : -tmp;
1907 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1908 if (tmp > MLX5_CQE_RESP_FORMAT_L34H_STRIDX) {
1909 DRV_LOG(ERR, "invalid CQE compression "
1910 "format parameter");
1914 config->cqe_comp = !!tmp;
1915 config->cqe_comp_fmt = tmp;
1916 } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1917 config->hw_padding = !!tmp;
1918 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1919 config->mprq.enabled = !!tmp;
1920 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1921 config->mprq.log_stride_num = tmp;
1922 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1923 config->mprq.log_stride_size = tmp;
1924 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1925 config->mprq.max_memcpy_len = tmp;
1926 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1927 config->mprq.min_rxqs_num = tmp;
1928 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1929 DRV_LOG(WARNING, "%s: deprecated parameter,"
1930 " converted to txq_inline_max", key);
1931 config->txq_inline_max = tmp;
1932 } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1933 config->txq_inline_max = tmp;
1934 } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1935 config->txq_inline_min = tmp;
1936 } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1937 config->txq_inline_mpw = tmp;
1938 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1939 config->txqs_inline = tmp;
1940 } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1941 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1942 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1943 config->mps = !!tmp;
1944 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1945 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1946 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1947 DRV_LOG(WARNING, "%s: deprecated parameter,"
1948 " converted to txq_inline_mpw", key);
1949 config->txq_inline_mpw = tmp;
1950 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1951 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1952 } else if (strcmp(MLX5_TX_PP, key) == 0) {
1954 DRV_LOG(ERR, "Zero Tx packet pacing parameter");
1958 config->tx_pp = tmp;
1959 } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
1960 config->tx_skew = tmp;
1961 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1962 config->rx_vec_en = !!tmp;
1963 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1964 config->l3_vxlan_en = !!tmp;
1965 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1966 config->vf_nl_en = !!tmp;
1967 } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1968 config->dv_esw_en = !!tmp;
1969 } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1970 config->dv_flow_en = !!tmp;
1971 } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1972 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1973 tmp != MLX5_XMETA_MODE_META16 &&
1974 tmp != MLX5_XMETA_MODE_META32 &&
1975 tmp != MLX5_XMETA_MODE_MISS_INFO) {
1976 DRV_LOG(ERR, "invalid extensive "
1977 "metadata parameter");
1981 if (tmp != MLX5_XMETA_MODE_MISS_INFO)
1982 config->dv_xmeta_en = tmp;
1984 config->dv_miss_info = 1;
1985 } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
1986 config->lacp_by_user = !!tmp;
1987 } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1988 config->max_dump_files_num = tmp;
1989 } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1990 config->lro.timeout = tmp;
1991 } else if (strcmp(RTE_DEVARGS_KEY_CLASS, key) == 0) {
1992 DRV_LOG(DEBUG, "class argument is %s.", val);
1993 } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1994 config->log_hp_size = tmp;
1995 } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1996 if (tmp != MLX5_RCM_NONE &&
1997 tmp != MLX5_RCM_LIGHT &&
1998 tmp != MLX5_RCM_AGGR) {
1999 DRV_LOG(ERR, "Unrecognized %s: \"%s\"", key, val);
2003 config->reclaim_mode = tmp;
2004 } else if (strcmp(MLX5_DECAP_EN, key) == 0) {
2005 config->decap_en = !!tmp;
2006 } else if (strcmp(MLX5_ALLOW_DUPLICATE_PATTERN, key) == 0) {
2007 config->allow_duplicate_pattern = !!tmp;
2008 } else if (strcmp(MLX5_DELAY_DROP, key) == 0) {
2009 config->std_delay_drop = !!(tmp & MLX5_DELAY_DROP_STANDARD);
2010 config->hp_delay_drop = !!(tmp & MLX5_DELAY_DROP_HAIRPIN);
2013 "%s: unknown parameter, maybe it's for another class.",
2020 * Parse device parameters.
2023 * Pointer to device configuration structure.
2025 * Device arguments structure.
2028 * 0 on success, a negative errno value otherwise and rte_errno is set.
2031 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
2033 struct rte_kvargs *kvlist;
2036 if (devargs == NULL)
2038 /* Following UGLY cast is done to pass checkpatch. */
2039 kvlist = rte_kvargs_parse(devargs->args, NULL);
2040 if (kvlist == NULL) {
2044 /* Process parameters. */
2045 ret = rte_kvargs_process(kvlist, NULL, mlx5_args_check, config);
2050 rte_kvargs_free(kvlist);
2055 * Configures the minimal amount of data to inline into WQE
2056 * while sending packets.
2058 * - the txq_inline_min has the maximal priority, if this
2059 * key is specified in devargs
2060 * - if DevX is enabled the inline mode is queried from the
2061 * device (HCA attributes and NIC vport context if needed).
2062 * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
2063 * and none (0 bytes) for other NICs
2066 * Verbs device parameters (name, port, switch_info) to spawn.
2068 * Device configuration parameters.
2071 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
2072 struct mlx5_dev_config *config)
2074 struct mlx5_hca_attr *hca_attr = &spawn->cdev->config.hca_attr;
2076 if (config->txq_inline_min != MLX5_ARG_UNSET) {
2077 /* Application defines size of inlined data explicitly. */
2078 if (spawn->pci_dev != NULL) {
2079 switch (spawn->pci_dev->id.device_id) {
2080 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2081 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2082 if (config->txq_inline_min <
2083 (int)MLX5_INLINE_HSIZE_L2) {
2085 "txq_inline_mix aligned to minimal ConnectX-4 required value %d",
2086 (int)MLX5_INLINE_HSIZE_L2);
2087 config->txq_inline_min =
2088 MLX5_INLINE_HSIZE_L2;
2095 if (hca_attr->eth_net_offloads) {
2096 /* We have DevX enabled, inline mode queried successfully. */
2097 switch (hca_attr->wqe_inline_mode) {
2098 case MLX5_CAP_INLINE_MODE_L2:
2099 /* outer L2 header must be inlined. */
2100 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2102 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
2103 /* No inline data are required by NIC. */
2104 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2105 config->hw_vlan_insert =
2106 hca_attr->wqe_vlan_insert;
2107 DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
2109 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
2110 /* inline mode is defined by NIC vport context. */
2111 if (!hca_attr->eth_virt)
2113 switch (hca_attr->vport_inline_mode) {
2114 case MLX5_INLINE_MODE_NONE:
2115 config->txq_inline_min =
2116 MLX5_INLINE_HSIZE_NONE;
2118 case MLX5_INLINE_MODE_L2:
2119 config->txq_inline_min =
2120 MLX5_INLINE_HSIZE_L2;
2122 case MLX5_INLINE_MODE_IP:
2123 config->txq_inline_min =
2124 MLX5_INLINE_HSIZE_L3;
2126 case MLX5_INLINE_MODE_TCP_UDP:
2127 config->txq_inline_min =
2128 MLX5_INLINE_HSIZE_L4;
2130 case MLX5_INLINE_MODE_INNER_L2:
2131 config->txq_inline_min =
2132 MLX5_INLINE_HSIZE_INNER_L2;
2134 case MLX5_INLINE_MODE_INNER_IP:
2135 config->txq_inline_min =
2136 MLX5_INLINE_HSIZE_INNER_L3;
2138 case MLX5_INLINE_MODE_INNER_TCP_UDP:
2139 config->txq_inline_min =
2140 MLX5_INLINE_HSIZE_INNER_L4;
2145 if (spawn->pci_dev == NULL) {
2146 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2150 * We get here if we are unable to deduce
2151 * inline data size with DevX. Try PCI ID
2152 * to determine old NICs.
2154 switch (spawn->pci_dev->id.device_id) {
2155 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2156 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2157 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
2158 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
2159 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2160 config->hw_vlan_insert = 0;
2162 case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
2163 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
2164 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
2165 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
2167 * These NICs support VLAN insertion from WQE and
2168 * report the wqe_vlan_insert flag. But there is the bug
2169 * and PFC control may be broken, so disable feature.
2171 config->hw_vlan_insert = 0;
2172 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2175 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2179 DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
2183 * Configures the metadata mask fields in the shared context.
2186 * Pointer to Ethernet device.
2189 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
2191 struct mlx5_priv *priv = dev->data->dev_private;
2192 struct mlx5_dev_ctx_shared *sh = priv->sh;
2193 uint32_t meta, mark, reg_c0;
2195 reg_c0 = ~priv->vport_meta_mask;
2196 switch (priv->config.dv_xmeta_en) {
2197 case MLX5_XMETA_MODE_LEGACY:
2199 mark = MLX5_FLOW_MARK_MASK;
2201 case MLX5_XMETA_MODE_META16:
2202 meta = reg_c0 >> rte_bsf32(reg_c0);
2203 mark = MLX5_FLOW_MARK_MASK;
2205 case MLX5_XMETA_MODE_META32:
2207 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
2215 if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
2216 DRV_LOG(WARNING, "metadata MARK mask mismatch %08X:%08X",
2217 sh->dv_mark_mask, mark);
2219 sh->dv_mark_mask = mark;
2220 if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
2221 DRV_LOG(WARNING, "metadata META mask mismatch %08X:%08X",
2222 sh->dv_meta_mask, meta);
2224 sh->dv_meta_mask = meta;
2225 if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
2226 DRV_LOG(WARNING, "metadata reg_c0 mask mismatch %08X:%08X",
2227 sh->dv_meta_mask, reg_c0);
2229 sh->dv_regc0_mask = reg_c0;
2230 DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
2231 DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
2232 DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
2233 DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
2237 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
2239 static const char *const dynf_names[] = {
2240 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
2241 RTE_MBUF_DYNFLAG_METADATA_NAME,
2242 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
2246 if (n < RTE_DIM(dynf_names))
2248 for (i = 0; i < RTE_DIM(dynf_names); i++) {
2249 if (names[i] == NULL)
2251 strcpy(names[i], dynf_names[i]);
2253 return RTE_DIM(dynf_names);
2257 * Check sibling device configurations.
2259 * Sibling devices sharing the Infiniband device context should have compatible
2260 * configurations. This regards representors and bonding device.
2263 * Shared device context.
2265 * Configuration of the device is going to be created.
2267 * Backing DPDK device.
2270 * 0 on success, EINVAL otherwise
2273 mlx5_dev_check_sibling_config(struct mlx5_dev_ctx_shared *sh,
2274 struct mlx5_dev_config *config,
2275 struct rte_device *dpdk_dev)
2277 struct mlx5_dev_config *sh_conf = NULL;
2281 /* Nothing to compare for the single/first device. */
2282 if (sh->refcnt == 1)
2284 /* Find the device with shared context. */
2285 MLX5_ETH_FOREACH_DEV(port_id, dpdk_dev) {
2286 struct mlx5_priv *opriv =
2287 rte_eth_devices[port_id].data->dev_private;
2289 if (opriv && opriv->sh == sh) {
2290 sh_conf = &opriv->config;
2296 if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
2297 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
2298 " for shared %s context", sh->ibdev_name);
2302 if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
2303 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
2304 " for shared %s context", sh->ibdev_name);
2312 * Look for the ethernet device belonging to mlx5 driver.
2314 * @param[in] port_id
2315 * port_id to start looking for device.
2317 * Pointer to the hint device. When device is being probed
2318 * the its siblings (master and preceding representors might
2319 * not have assigned driver yet (because the mlx5_os_pci_probe()
2320 * is not completed yet, for this case match on hint
2321 * device may be used to detect sibling device.
2324 * port_id of found device, RTE_MAX_ETHPORT if not found.
2327 mlx5_eth_find_next(uint16_t port_id, struct rte_device *odev)
2329 while (port_id < RTE_MAX_ETHPORTS) {
2330 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
2332 if (dev->state != RTE_ETH_DEV_UNUSED &&
2334 (dev->device == odev ||
2335 (dev->device->driver &&
2336 dev->device->driver->name &&
2337 ((strcmp(dev->device->driver->name,
2338 MLX5_PCI_DRIVER_NAME) == 0) ||
2339 (strcmp(dev->device->driver->name,
2340 MLX5_AUXILIARY_DRIVER_NAME) == 0)))))
2344 if (port_id >= RTE_MAX_ETHPORTS)
2345 return RTE_MAX_ETHPORTS;
2350 * Callback to remove a device.
2352 * This function removes all Ethernet devices belong to a given device.
2355 * Pointer to the generic device.
2358 * 0 on success, the function cannot fail.
2361 mlx5_net_remove(struct mlx5_common_device *cdev)
2366 RTE_ETH_FOREACH_DEV_OF(port_id, cdev->dev) {
2368 * mlx5_dev_close() is not registered to secondary process,
2369 * call the close function explicitly for secondary process.
2371 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
2372 ret |= mlx5_dev_close(&rte_eth_devices[port_id]);
2374 ret |= rte_eth_dev_close(port_id);
2376 return ret == 0 ? 0 : -EIO;
2379 static const struct rte_pci_id mlx5_pci_id_map[] = {
2381 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2382 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
2385 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2386 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
2389 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2390 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
2393 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2394 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
2397 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2398 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
2401 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2402 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
2405 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2406 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
2409 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2410 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
2413 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2414 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
2417 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2418 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
2421 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2422 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
2425 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2426 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
2429 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2430 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
2433 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2434 PCI_DEVICE_ID_MELLANOX_CONNECTXVF)
2437 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2438 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
2441 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2442 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
2445 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2446 PCI_DEVICE_ID_MELLANOX_CONNECTX7)
2449 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2450 PCI_DEVICE_ID_MELLANOX_CONNECTX7BF)
2457 static struct mlx5_class_driver mlx5_net_driver = {
2458 .drv_class = MLX5_CLASS_ETH,
2459 .name = RTE_STR(MLX5_ETH_DRIVER_NAME),
2460 .id_table = mlx5_pci_id_map,
2461 .probe = mlx5_os_net_probe,
2462 .remove = mlx5_net_remove,
2468 /* Initialize driver log type. */
2469 RTE_LOG_REGISTER_DEFAULT(mlx5_logtype, NOTICE)
2472 * Driver initialization routine.
2474 RTE_INIT(rte_mlx5_pmd_init)
2476 pthread_mutex_init(&mlx5_dev_ctx_list_mutex, NULL);
2478 /* Build the static tables for Verbs conversion. */
2479 mlx5_set_ptype_table();
2480 mlx5_set_cksum_table();
2481 mlx5_set_swp_types_table();
2483 mlx5_class_driver_register(&mlx5_net_driver);
2486 RTE_PMD_EXPORT_NAME(MLX5_ETH_DRIVER_NAME, __COUNTER__);
2487 RTE_PMD_REGISTER_PCI_TABLE(MLX5_ETH_DRIVER_NAME, mlx5_pci_id_map);
2488 RTE_PMD_REGISTER_KMOD_DEP(MLX5_ETH_DRIVER_NAME, "* ib_uverbs & mlx5_core & mlx5_ib");