4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
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12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of 6WIND S.A. nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
46 #pragma GCC diagnostic ignored "-Wpedantic"
48 #include <infiniband/verbs.h>
50 #pragma GCC diagnostic error "-Wpedantic"
53 /* DPDK headers don't like -pedantic. */
55 #pragma GCC diagnostic ignored "-Wpedantic"
57 #include <rte_malloc.h>
58 #include <rte_ethdev.h>
59 #include <rte_ethdev_pci.h>
61 #include <rte_common.h>
62 #include <rte_kvargs.h>
64 #pragma GCC diagnostic error "-Wpedantic"
68 #include "mlx5_utils.h"
69 #include "mlx5_rxtx.h"
70 #include "mlx5_autoconf.h"
71 #include "mlx5_defs.h"
73 /* Device parameter to enable RX completion queue compression. */
74 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
76 /* Device parameter to configure inline send. */
77 #define MLX5_TXQ_INLINE "txq_inline"
80 * Device parameter to configure the number of TX queues threshold for
81 * enabling inline send.
83 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
85 /* Device parameter to enable multi-packet send WQEs. */
86 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
88 /* Device parameter to include 2 dsegs in the title WQEBB. */
89 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
91 /* Device parameter to limit the size of inlining packet. */
92 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
94 /* Device parameter to enable hardware TSO offload. */
95 #define MLX5_TSO "tso"
97 /* Default PMD specific parameter value. */
98 #define MLX5_ARG_UNSET (-1)
106 int inline_max_packet_sz;
110 * Retrieve integer value from environment variable.
113 * Environment variable name.
116 * Integer value, 0 if the variable is not set.
119 mlx5_getenv_int(const char *name)
121 const char *val = getenv(name);
129 * DPDK callback to close the device.
131 * Destroy all queues and objects, free memory.
134 * Pointer to Ethernet device structure.
137 mlx5_dev_close(struct rte_eth_dev *dev)
139 struct priv *priv = mlx5_get_priv(dev);
143 DEBUG("%p: closing device \"%s\"",
145 ((priv->ctx != NULL) ? priv->ctx->device->name : ""));
146 /* In case mlx5_dev_stop() has not been called. */
147 priv_dev_interrupt_handler_uninstall(priv, dev);
148 priv_special_flow_disable_all(priv);
149 priv_mac_addrs_disable(priv);
150 priv_destroy_hash_rxqs(priv);
152 /* Remove flow director elements. */
153 priv_fdir_disable(priv);
154 priv_fdir_delete_filters_list(priv);
156 /* Prevent crashes when queues are still in use. */
157 dev->rx_pkt_burst = removed_rx_burst;
158 dev->tx_pkt_burst = removed_tx_burst;
159 if (priv->rxqs != NULL) {
160 /* XXX race condition if mlx5_rx_burst() is still running. */
162 for (i = 0; (i != priv->rxqs_n); ++i) {
163 struct rxq *rxq = (*priv->rxqs)[i];
164 struct rxq_ctrl *rxq_ctrl;
168 rxq_ctrl = container_of(rxq, struct rxq_ctrl, rxq);
169 (*priv->rxqs)[i] = NULL;
170 rxq_cleanup(rxq_ctrl);
176 if (priv->txqs != NULL) {
177 /* XXX race condition if mlx5_tx_burst() is still running. */
179 for (i = 0; (i != priv->txqs_n); ++i) {
180 struct txq *txq = (*priv->txqs)[i];
181 struct txq_ctrl *txq_ctrl;
185 txq_ctrl = container_of(txq, struct txq_ctrl, txq);
186 (*priv->txqs)[i] = NULL;
187 txq_cleanup(txq_ctrl);
193 if (priv->pd != NULL) {
194 assert(priv->ctx != NULL);
195 claim_zero(ibv_dealloc_pd(priv->pd));
196 claim_zero(ibv_close_device(priv->ctx));
198 assert(priv->ctx == NULL);
199 if (priv->rss_conf != NULL) {
200 for (i = 0; (i != hash_rxq_init_n); ++i)
201 rte_free((*priv->rss_conf)[i]);
202 rte_free(priv->rss_conf);
204 if (priv->reta_idx != NULL)
205 rte_free(priv->reta_idx);
207 memset(priv, 0, sizeof(*priv));
210 static const struct eth_dev_ops mlx5_dev_ops = {
211 .dev_configure = mlx5_dev_configure,
212 .dev_start = mlx5_dev_start,
213 .dev_stop = mlx5_dev_stop,
214 .dev_set_link_down = mlx5_set_link_down,
215 .dev_set_link_up = mlx5_set_link_up,
216 .dev_close = mlx5_dev_close,
217 .promiscuous_enable = mlx5_promiscuous_enable,
218 .promiscuous_disable = mlx5_promiscuous_disable,
219 .allmulticast_enable = mlx5_allmulticast_enable,
220 .allmulticast_disable = mlx5_allmulticast_disable,
221 .link_update = mlx5_link_update,
222 .stats_get = mlx5_stats_get,
223 .stats_reset = mlx5_stats_reset,
224 .xstats_get = mlx5_xstats_get,
225 .xstats_reset = mlx5_xstats_reset,
226 .xstats_get_names = mlx5_xstats_get_names,
227 .dev_infos_get = mlx5_dev_infos_get,
228 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
229 .vlan_filter_set = mlx5_vlan_filter_set,
230 .rx_queue_setup = mlx5_rx_queue_setup,
231 .tx_queue_setup = mlx5_tx_queue_setup,
232 .rx_queue_release = mlx5_rx_queue_release,
233 .tx_queue_release = mlx5_tx_queue_release,
234 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
235 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
236 .mac_addr_remove = mlx5_mac_addr_remove,
237 .mac_addr_add = mlx5_mac_addr_add,
238 .mac_addr_set = mlx5_mac_addr_set,
239 .mtu_set = mlx5_dev_set_mtu,
240 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
241 .vlan_offload_set = mlx5_vlan_offload_set,
242 .reta_update = mlx5_dev_rss_reta_update,
243 .reta_query = mlx5_dev_rss_reta_query,
244 .rss_hash_update = mlx5_rss_hash_update,
245 .rss_hash_conf_get = mlx5_rss_hash_conf_get,
246 .filter_ctrl = mlx5_dev_filter_ctrl,
247 .rx_descriptor_status = mlx5_rx_descriptor_status,
248 .tx_descriptor_status = mlx5_tx_descriptor_status,
249 #ifdef HAVE_UPDATE_CQ_CI
250 .rx_queue_intr_enable = mlx5_rx_intr_enable,
251 .rx_queue_intr_disable = mlx5_rx_intr_disable,
256 struct rte_pci_addr pci_addr; /* associated PCI address */
257 uint32_t ports; /* physical ports bitfield. */
261 * Get device index in mlx5_dev[] from PCI bus address.
263 * @param[in] pci_addr
264 * PCI bus address to look for.
267 * mlx5_dev[] index on success, -1 on failure.
270 mlx5_dev_idx(struct rte_pci_addr *pci_addr)
275 assert(pci_addr != NULL);
276 for (i = 0; (i != RTE_DIM(mlx5_dev)); ++i) {
277 if ((mlx5_dev[i].pci_addr.domain == pci_addr->domain) &&
278 (mlx5_dev[i].pci_addr.bus == pci_addr->bus) &&
279 (mlx5_dev[i].pci_addr.devid == pci_addr->devid) &&
280 (mlx5_dev[i].pci_addr.function == pci_addr->function))
282 if ((mlx5_dev[i].ports == 0) && (ret == -1))
289 * Verify and store value for device argument.
292 * Key argument to verify.
294 * Value associated with key.
299 * 0 on success, negative errno value on failure.
302 mlx5_args_check(const char *key, const char *val, void *opaque)
304 struct mlx5_args *args = opaque;
308 tmp = strtoul(val, NULL, 0);
310 WARN("%s: \"%s\" is not a valid integer", key, val);
313 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
314 args->cqe_comp = !!tmp;
315 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
316 args->txq_inline = tmp;
317 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
318 args->txqs_inline = tmp;
319 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
321 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
322 args->mpw_hdr_dseg = !!tmp;
323 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
324 args->inline_max_packet_sz = tmp;
325 } else if (strcmp(MLX5_TSO, key) == 0) {
328 WARN("%s: unknown parameter", key);
335 * Parse device parameters.
338 * Pointer to private structure.
340 * Device arguments structure.
343 * 0 on success, errno value on failure.
346 mlx5_args(struct mlx5_args *args, struct rte_devargs *devargs)
348 const char **params = (const char *[]){
349 MLX5_RXQ_CQE_COMP_EN,
351 MLX5_TXQS_MIN_INLINE,
353 MLX5_TXQ_MPW_HDR_DSEG_EN,
354 MLX5_TXQ_MAX_INLINE_LEN,
358 struct rte_kvargs *kvlist;
364 /* Following UGLY cast is done to pass checkpatch. */
365 kvlist = rte_kvargs_parse(devargs->args, params);
368 /* Process parameters. */
369 for (i = 0; (params[i] != NULL); ++i) {
370 if (rte_kvargs_count(kvlist, params[i])) {
371 ret = rte_kvargs_process(kvlist, params[i],
372 mlx5_args_check, args);
374 rte_kvargs_free(kvlist);
379 rte_kvargs_free(kvlist);
383 static struct rte_pci_driver mlx5_driver;
386 * Assign parameters from args into priv, only non default
387 * values are considered.
390 * Pointer to private structure.
392 * Pointer to args values.
395 mlx5_args_assign(struct priv *priv, struct mlx5_args *args)
397 if (args->cqe_comp != MLX5_ARG_UNSET)
398 priv->cqe_comp = args->cqe_comp;
399 if (args->txq_inline != MLX5_ARG_UNSET)
400 priv->txq_inline = args->txq_inline;
401 if (args->txqs_inline != MLX5_ARG_UNSET)
402 priv->txqs_inline = args->txqs_inline;
403 if (args->mps != MLX5_ARG_UNSET)
404 priv->mps = args->mps ? priv->mps : 0;
405 if (args->mpw_hdr_dseg != MLX5_ARG_UNSET)
406 priv->mpw_hdr_dseg = args->mpw_hdr_dseg;
407 if (args->inline_max_packet_sz != MLX5_ARG_UNSET)
408 priv->inline_max_packet_sz = args->inline_max_packet_sz;
409 if (args->tso != MLX5_ARG_UNSET)
410 priv->tso = args->tso;
414 * DPDK callback to register a PCI device.
416 * This function creates an Ethernet device for each port of a given
420 * PCI driver structure (mlx5_driver).
422 * PCI device information.
425 * 0 on success, negative errno value on failure.
428 mlx5_pci_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
430 struct ibv_device **list;
431 struct ibv_device *ibv_dev;
433 struct ibv_context *attr_ctx = NULL;
434 struct ibv_device_attr device_attr;
437 unsigned int tunnel_en;
442 assert(pci_drv == &mlx5_driver);
443 /* Get mlx5_dev[] index. */
444 idx = mlx5_dev_idx(&pci_dev->addr);
446 ERROR("this driver cannot support any more adapters");
449 DEBUG("using driver device index %d", idx);
451 /* Save PCI address. */
452 mlx5_dev[idx].pci_addr = pci_dev->addr;
453 list = ibv_get_device_list(&i);
457 ERROR("cannot list devices, is ib_uverbs loaded?");
462 * For each listed device, check related sysfs entry against
463 * the provided PCI ID.
466 struct rte_pci_addr pci_addr;
469 DEBUG("checking device \"%s\"", list[i]->name);
470 if (mlx5_ibv_device_to_pci_addr(list[i], &pci_addr))
472 if ((pci_dev->addr.domain != pci_addr.domain) ||
473 (pci_dev->addr.bus != pci_addr.bus) ||
474 (pci_dev->addr.devid != pci_addr.devid) ||
475 (pci_dev->addr.function != pci_addr.function))
477 sriov = ((pci_dev->id.device_id ==
478 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF) ||
479 (pci_dev->id.device_id ==
480 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF) ||
481 (pci_dev->id.device_id ==
482 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF) ||
483 (pci_dev->id.device_id ==
484 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF));
486 * Multi-packet send is supported by ConnectX-4 Lx PF as well
487 * as all ConnectX-5 devices.
489 switch (pci_dev->id.device_id) {
490 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
492 mps = MLX5_MPW_DISABLED;
494 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
497 case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
498 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
499 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
500 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
502 mps = MLX5_MPW_ENHANCED;
505 mps = MLX5_MPW_DISABLED;
507 INFO("PCI information matches, using device \"%s\""
508 " (SR-IOV: %s, %sMPS: %s)",
510 sriov ? "true" : "false",
511 mps == MLX5_MPW_ENHANCED ? "Enhanced " : "",
512 mps != MLX5_MPW_DISABLED ? "true" : "false");
513 attr_ctx = ibv_open_device(list[i]);
517 if (attr_ctx == NULL) {
518 ibv_free_device_list(list);
521 ERROR("cannot access device, is mlx5_ib loaded?");
524 ERROR("cannot use device, are drivers up to date?");
532 DEBUG("device opened");
533 if (ibv_query_device(attr_ctx, &device_attr))
535 INFO("%u port(s) detected", device_attr.phys_port_cnt);
537 for (i = 0; i < device_attr.phys_port_cnt; i++) {
538 uint32_t port = i + 1; /* ports are indexed from one */
539 uint32_t test = (1 << i);
540 struct ibv_context *ctx = NULL;
541 struct ibv_port_attr port_attr;
542 struct ibv_pd *pd = NULL;
543 struct priv *priv = NULL;
544 struct rte_eth_dev *eth_dev;
545 struct ibv_exp_device_attr exp_device_attr;
546 struct ether_addr mac;
547 uint16_t num_vfs = 0;
548 struct mlx5_args args = {
549 .cqe_comp = MLX5_ARG_UNSET,
550 .txq_inline = MLX5_ARG_UNSET,
551 .txqs_inline = MLX5_ARG_UNSET,
552 .mps = MLX5_ARG_UNSET,
553 .mpw_hdr_dseg = MLX5_ARG_UNSET,
554 .inline_max_packet_sz = MLX5_ARG_UNSET,
555 .tso = MLX5_ARG_UNSET,
558 exp_device_attr.comp_mask =
559 IBV_EXP_DEVICE_ATTR_EXP_CAP_FLAGS |
560 IBV_EXP_DEVICE_ATTR_RX_HASH |
561 IBV_EXP_DEVICE_ATTR_VLAN_OFFLOADS |
562 IBV_EXP_DEVICE_ATTR_RX_PAD_END_ALIGN |
563 IBV_EXP_DEVICE_ATTR_TSO_CAPS |
566 DEBUG("using port %u (%08" PRIx32 ")", port, test);
568 ctx = ibv_open_device(ibv_dev);
572 /* Check port status. */
573 err = ibv_query_port(ctx, port, &port_attr);
575 ERROR("port query failed: %s", strerror(err));
579 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
580 ERROR("port %d is not configured in Ethernet mode",
585 if (port_attr.state != IBV_PORT_ACTIVE)
586 DEBUG("port %d is not active: \"%s\" (%d)",
587 port, ibv_port_state_str(port_attr.state),
590 /* Allocate protection domain. */
591 pd = ibv_alloc_pd(ctx);
593 ERROR("PD allocation failure");
598 mlx5_dev[idx].ports |= test;
600 /* from rte_ethdev.c */
601 priv = rte_zmalloc("ethdev private structure",
603 RTE_CACHE_LINE_SIZE);
605 ERROR("priv allocation failure");
611 priv->device_attr = device_attr;
614 priv->mtu = ETHER_MTU;
615 priv->mps = mps; /* Enable MPW by default if supported. */
616 priv->cqe_comp = 1; /* Enable compression by default. */
617 priv->tunnel_en = tunnel_en;
618 err = mlx5_args(&args, pci_dev->device.devargs);
620 ERROR("failed to process device arguments: %s",
624 mlx5_args_assign(priv, &args);
625 if (ibv_exp_query_device(ctx, &exp_device_attr)) {
626 ERROR("ibv_exp_query_device() failed");
631 ((exp_device_attr.exp_device_cap_flags &
632 IBV_EXP_DEVICE_RX_CSUM_TCP_UDP_PKT) &&
633 (exp_device_attr.exp_device_cap_flags &
634 IBV_EXP_DEVICE_RX_CSUM_IP_PKT));
635 DEBUG("checksum offloading is %ssupported",
636 (priv->hw_csum ? "" : "not "));
638 priv->hw_csum_l2tun = !!(exp_device_attr.exp_device_cap_flags &
639 IBV_EXP_DEVICE_VXLAN_SUPPORT);
640 DEBUG("L2 tunnel checksum offloads are %ssupported",
641 (priv->hw_csum_l2tun ? "" : "not "));
643 priv->ind_table_max_size = exp_device_attr.rx_hash_caps.max_rwq_indirection_table_size;
644 /* Remove this check once DPDK supports larger/variable
645 * indirection tables. */
646 if (priv->ind_table_max_size >
647 (unsigned int)ETH_RSS_RETA_SIZE_512)
648 priv->ind_table_max_size = ETH_RSS_RETA_SIZE_512;
649 DEBUG("maximum RX indirection table size is %u",
650 priv->ind_table_max_size);
651 priv->hw_vlan_strip = !!(exp_device_attr.wq_vlan_offloads_cap &
652 IBV_EXP_RECEIVE_WQ_CVLAN_STRIP);
653 DEBUG("VLAN stripping is %ssupported",
654 (priv->hw_vlan_strip ? "" : "not "));
656 priv->hw_fcs_strip = !!(exp_device_attr.exp_device_cap_flags &
657 IBV_EXP_DEVICE_SCATTER_FCS);
658 DEBUG("FCS stripping configuration is %ssupported",
659 (priv->hw_fcs_strip ? "" : "not "));
661 priv->hw_padding = !!exp_device_attr.rx_pad_end_addr_align;
662 DEBUG("hardware RX end alignment padding is %ssupported",
663 (priv->hw_padding ? "" : "not "));
665 priv_get_num_vfs(priv, &num_vfs);
666 priv->sriov = (num_vfs || sriov);
667 priv->tso = ((priv->tso) &&
668 (exp_device_attr.tso_caps.max_tso > 0) &&
669 (exp_device_attr.tso_caps.supported_qpts &
670 (1 << IBV_QPT_RAW_ETH)));
672 priv->max_tso_payload_sz =
673 exp_device_attr.tso_caps.max_tso;
674 if (priv->mps && !mps) {
675 ERROR("multi-packet send not supported on this device"
676 " (" MLX5_TXQ_MPW_EN ")");
679 } else if (priv->mps && priv->tso) {
680 WARN("multi-packet send not supported in conjunction "
681 "with TSO. MPS disabled");
685 priv->mps == MLX5_MPW_ENHANCED ? "Enhanced " : "",
686 priv->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled");
687 /* Set default values for Enhanced MPW, a.k.a MPWv2. */
688 if (priv->mps == MLX5_MPW_ENHANCED) {
689 if (args.txqs_inline == MLX5_ARG_UNSET)
690 priv->txqs_inline = MLX5_EMPW_MIN_TXQS;
691 if (args.inline_max_packet_sz == MLX5_ARG_UNSET)
692 priv->inline_max_packet_sz =
693 MLX5_EMPW_MAX_INLINE_LEN;
694 if (args.txq_inline == MLX5_ARG_UNSET)
695 priv->txq_inline = MLX5_WQE_SIZE_MAX -
698 /* Allocate and register default RSS hash keys. */
699 priv->rss_conf = rte_calloc(__func__, hash_rxq_init_n,
700 sizeof((*priv->rss_conf)[0]), 0);
701 if (priv->rss_conf == NULL) {
705 err = rss_hash_rss_conf_new_key(priv,
706 rss_hash_default_key,
707 rss_hash_default_key_len,
711 /* Configure the first MAC address by default. */
712 if (priv_get_mac(priv, &mac.addr_bytes)) {
713 ERROR("cannot get MAC address, is mlx5_en loaded?"
714 " (errno: %s)", strerror(errno));
717 INFO("port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x",
719 mac.addr_bytes[0], mac.addr_bytes[1],
720 mac.addr_bytes[2], mac.addr_bytes[3],
721 mac.addr_bytes[4], mac.addr_bytes[5]);
722 /* Register MAC address. */
723 claim_zero(priv_mac_addr_add(priv, 0,
724 (const uint8_t (*)[ETHER_ADDR_LEN])
726 /* Initialize FD filters list. */
727 err = fdir_init_filters_list(priv);
732 char ifname[IF_NAMESIZE];
734 if (priv_get_ifname(priv, &ifname) == 0)
735 DEBUG("port %u ifname is \"%s\"",
738 DEBUG("port %u ifname is unknown", priv->port);
741 /* Get actual MTU if possible. */
742 priv_get_mtu(priv, &priv->mtu);
743 DEBUG("port %u MTU is %u", priv->port, priv->mtu);
745 /* from rte_ethdev.c */
747 char name[RTE_ETH_NAME_MAX_LEN];
749 snprintf(name, sizeof(name), "%s port %u",
750 ibv_get_device_name(ibv_dev), port);
751 eth_dev = rte_eth_dev_allocate(name);
753 if (eth_dev == NULL) {
754 ERROR("can not allocate rte ethdev");
759 /* Secondary processes have to use local storage for their
760 * private data as well as a copy of eth_dev->data, but this
761 * pointer must not be modified before burst functions are
762 * actually called. */
763 if (mlx5_is_secondary()) {
764 struct mlx5_secondary_data *sd =
765 &mlx5_secondary_data[eth_dev->data->port_id];
766 sd->primary_priv = eth_dev->data->dev_private;
767 if (sd->primary_priv == NULL) {
768 ERROR("no private data for port %u",
769 eth_dev->data->port_id);
773 sd->shared_dev_data = eth_dev->data;
774 rte_spinlock_init(&sd->lock);
775 memcpy(sd->data.name, sd->shared_dev_data->name,
776 sizeof(sd->data.name));
777 sd->data.dev_private = priv;
778 sd->data.rx_mbuf_alloc_failed = 0;
779 sd->data.mtu = ETHER_MTU;
780 sd->data.port_id = sd->shared_dev_data->port_id;
781 sd->data.mac_addrs = priv->mac;
782 eth_dev->tx_pkt_burst = mlx5_tx_burst_secondary_setup;
783 eth_dev->rx_pkt_burst = mlx5_rx_burst_secondary_setup;
785 eth_dev->data->dev_private = priv;
786 eth_dev->data->mac_addrs = priv->mac;
789 eth_dev->device = &pci_dev->device;
790 rte_eth_copy_pci_info(eth_dev, pci_dev);
791 eth_dev->device->driver = &mlx5_driver.driver;
793 eth_dev->dev_ops = &mlx5_dev_ops;
794 TAILQ_INIT(&priv->flows);
796 /* Bring Ethernet device up. */
797 DEBUG("forcing Ethernet interface up");
798 priv_set_flags(priv, ~IFF_UP, IFF_UP);
799 mlx5_link_update(priv->dev, 1);
804 rte_free(priv->rss_conf);
808 claim_zero(ibv_dealloc_pd(pd));
810 claim_zero(ibv_close_device(ctx));
815 * XXX if something went wrong in the loop above, there is a resource
816 * leak (ctx, pd, priv, dpdk ethdev) but we can do nothing about it as
817 * long as the dpdk does not provide a way to deallocate a ethdev and a
818 * way to enumerate the registered ethdevs to free the previous ones.
821 /* no port found, complain */
822 if (!mlx5_dev[idx].ports) {
829 claim_zero(ibv_close_device(attr_ctx));
831 ibv_free_device_list(list);
836 static const struct rte_pci_id mlx5_pci_id_map[] = {
838 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
839 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
842 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
843 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
846 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
847 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
850 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
851 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
854 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
855 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
858 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
859 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
862 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
863 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
866 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
867 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
874 static struct rte_pci_driver mlx5_driver = {
876 .name = MLX5_DRIVER_NAME
878 .id_table = mlx5_pci_id_map,
879 .probe = mlx5_pci_probe,
880 .drv_flags = RTE_PCI_DRV_INTR_LSC,
884 * Driver initialization routine.
886 RTE_INIT(rte_mlx5_pmd_init);
888 rte_mlx5_pmd_init(void)
891 * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use
892 * huge pages. Calling ibv_fork_init() during init allows
893 * applications to use fork() safely for purposes other than
894 * using this PMD, which is not supported in forked processes.
896 setenv("RDMAV_HUGEPAGES_SAFE", "1", 1);
898 rte_pci_register(&mlx5_driver);
901 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
902 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
903 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");