drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <stdint.h>
  10 #include <stdlib.h>
  11 #include <errno.h>
  12
  13 #include <rte_malloc.h>
  14 #include <ethdev_driver.h>
  15 #include <rte_pci.h>
  16 #include <rte_bus_pci.h>
  17 #include <rte_common.h>
  18 #include <rte_kvargs.h>
  19 #include <rte_rwlock.h>
  20 #include <rte_spinlock.h>
  21 #include <rte_string_fns.h>
  22 #include <rte_alarm.h>
  23 #include <rte_cycles.h>
  24
  25 #include <mlx5_glue.h>
  26 #include <mlx5_devx_cmds.h>
  27 #include <mlx5_common.h>
  28 #include <mlx5_common_os.h>
  29 #include <mlx5_common_mp.h>
  30 #include <mlx5_malloc.h>
  31
  32 #include "mlx5_defs.h"
  33 #include "mlx5.h"
  34 #include "mlx5_utils.h"
  35 #include "mlx5_rxtx.h"
  36 #include "mlx5_rx.h"
  37 #include "mlx5_tx.h"
  38 #include "mlx5_autoconf.h"
  39 #include "mlx5_flow.h"
  40 #include "mlx5_flow_os.h"
  41 #include "rte_pmd_mlx5.h"
  42
  43 #define MLX5_ETH_DRIVER_NAME mlx5_eth
  44
  45 /* Driver type key for new device global syntax. */
  46 #define MLX5_DRIVER_KEY "driver"
  47
  48 /* Device parameter to enable RX completion queue compression. */
  49 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  50
  51 /* Device parameter to enable padding Rx packet to cacheline size. */
  52 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
  53
  54 /* Device parameter to enable Multi-Packet Rx queue. */
  55 #define MLX5_RX_MPRQ_EN "mprq_en"
  56
  57 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
  58 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
  59
  60 /* Device parameter to configure log 2 of the stride size for MPRQ. */
  61 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
  62
  63 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
  64 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
  65
  66 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
  67 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
  68
  69 /* Device parameter to configure inline send. Deprecated, ignored.*/
  70 #define MLX5_TXQ_INLINE "txq_inline"
  71
  72 /* Device parameter to limit packet size to inline with ordinary SEND. */
  73 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
  74
  75 /* Device parameter to configure minimal data size to inline. */
  76 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
  77
  78 /* Device parameter to limit packet size to inline with Enhanced MPW. */
  79 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
  80
  81 /*
  82  * Device parameter to configure the number of TX queues threshold for
  83  * enabling inline send.
  84  */
  85 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  86
  87 /*
  88  * Device parameter to configure the number of TX queues threshold for
  89  * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
  90  */
  91 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
  92
  93 /* Device parameter to enable multi-packet send WQEs. */
  94 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
  95
  96 /*
  97  * Device parameter to force doorbell register mapping
  98  * to non-cahed region eliminating the extra write memory barrier.
  99  */
 100 #define MLX5_TX_DB_NC "tx_db_nc"
 101
 102 /*
 103  * Device parameter to include 2 dsegs in the title WQEBB.
 104  * Deprecated, ignored.
 105  */
 106 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
 107
 108 /*
 109  * Device parameter to limit the size of inlining packet.
 110  * Deprecated, ignored.
 111  */
 112 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
 113
 114 /*
 115  * Device parameter to enable Tx scheduling on timestamps
 116  * and specify the packet pacing granularity in nanoseconds.
 117  */
 118 #define MLX5_TX_PP "tx_pp"
 119
 120 /*
 121  * Device parameter to specify skew in nanoseconds on Tx datapath,
 122  * it represents the time between SQ start WQE processing and
 123  * appearing actual packet data on the wire.
 124  */
 125 #define MLX5_TX_SKEW "tx_skew"
 126
 127 /*
 128  * Device parameter to enable hardware Tx vector.
 129  * Deprecated, ignored (no vectorized Tx routines anymore).
 130  */
 131 #define MLX5_TX_VEC_EN "tx_vec_en"
 132
 133 /* Device parameter to enable hardware Rx vector. */
 134 #define MLX5_RX_VEC_EN "rx_vec_en"
 135
 136 /* Allow L3 VXLAN flow creation. */
 137 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
 138
 139 /* Activate DV E-Switch flow steering. */
 140 #define MLX5_DV_ESW_EN "dv_esw_en"
 141
 142 /* Activate DV flow steering. */
 143 #define MLX5_DV_FLOW_EN "dv_flow_en"
 144
 145 /* Enable extensive flow metadata support. */
 146 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
 147
 148 /* Device parameter to let the user manage the lacp traffic of bonded device */
 149 #define MLX5_LACP_BY_USER "lacp_by_user"
 150
 151 /* Activate Netlink support in VF mode. */
 152 #define MLX5_VF_NL_EN "vf_nl_en"
 153
 154 /* Enable extending memsegs when creating a MR. */
 155 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
 156
 157 /* Select port representors to instantiate. */
 158 #define MLX5_REPRESENTOR "representor"
 159
 160 /* Device parameter to configure the maximum number of dump files per queue. */
 161 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
 162
 163 /* Configure timeout of LRO session (in microseconds). */
 164 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
 165
 166 /*
 167  * Device parameter to configure the total data buffer size for a single
 168  * hairpin queue (logarithm value).
 169  */
 170 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
 171
 172 /* Flow memory reclaim mode. */
 173 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
 174
 175 /* The default memory allocator used in PMD. */
 176 #define MLX5_SYS_MEM_EN "sys_mem_en"
 177 /* Decap will be used or not. */
 178 #define MLX5_DECAP_EN "decap_en"
 179
 180 /* Device parameter to configure allow or prevent duplicate rules pattern. */
 181 #define MLX5_ALLOW_DUPLICATE_PATTERN "allow_duplicate_pattern"
 182
 183 /* Device parameter to configure implicit registration of mempool memory. */
 184 #define MLX5_MR_MEMPOOL_REG_EN "mr_mempool_reg_en"
 185
 186 /* Shared memory between primary and secondary processes. */
 187 struct mlx5_shared_data *mlx5_shared_data;
 188
 189 /** Driver-specific log messages type. */
 190 int mlx5_logtype;
 191
 192 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
 193                                                 LIST_HEAD_INITIALIZER();
 194 static pthread_mutex_t mlx5_dev_ctx_list_mutex;
 195 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
 196 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
 197         [MLX5_IPOOL_DECAP_ENCAP] = {
 198                 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
 199                 .trunk_size = 64,
 200                 .grow_trunk = 3,
 201                 .grow_shift = 2,
 202                 .need_lock = 1,
 203                 .release_mem_en = 1,
 204                 .malloc = mlx5_malloc,
 205                 .free = mlx5_free,
 206                 .type = "mlx5_encap_decap_ipool",
 207         },
 208         [MLX5_IPOOL_PUSH_VLAN] = {
 209                 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
 210                 .trunk_size = 64,
 211                 .grow_trunk = 3,
 212                 .grow_shift = 2,
 213                 .need_lock = 1,
 214                 .release_mem_en = 1,
 215                 .malloc = mlx5_malloc,
 216                 .free = mlx5_free,
 217                 .type = "mlx5_push_vlan_ipool",
 218         },
 219         [MLX5_IPOOL_TAG] = {
 220                 .size = sizeof(struct mlx5_flow_dv_tag_resource),
 221                 .trunk_size = 64,
 222                 .grow_trunk = 3,
 223                 .grow_shift = 2,
 224                 .need_lock = 1,
 225                 .release_mem_en = 0,
 226                 .per_core_cache = (1 << 16),
 227                 .malloc = mlx5_malloc,
 228                 .free = mlx5_free,
 229                 .type = "mlx5_tag_ipool",
 230         },
 231         [MLX5_IPOOL_PORT_ID] = {
 232                 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
 233                 .trunk_size = 64,
 234                 .grow_trunk = 3,
 235                 .grow_shift = 2,
 236                 .need_lock = 1,
 237                 .release_mem_en = 1,
 238                 .malloc = mlx5_malloc,
 239                 .free = mlx5_free,
 240                 .type = "mlx5_port_id_ipool",
 241         },
 242         [MLX5_IPOOL_JUMP] = {
 243                 .size = sizeof(struct mlx5_flow_tbl_data_entry),
 244                 .trunk_size = 64,
 245                 .grow_trunk = 3,
 246                 .grow_shift = 2,
 247                 .need_lock = 1,
 248                 .release_mem_en = 1,
 249                 .malloc = mlx5_malloc,
 250                 .free = mlx5_free,
 251                 .type = "mlx5_jump_ipool",
 252         },
 253         [MLX5_IPOOL_SAMPLE] = {
 254                 .size = sizeof(struct mlx5_flow_dv_sample_resource),
 255                 .trunk_size = 64,
 256                 .grow_trunk = 3,
 257                 .grow_shift = 2,
 258                 .need_lock = 1,
 259                 .release_mem_en = 1,
 260                 .malloc = mlx5_malloc,
 261                 .free = mlx5_free,
 262                 .type = "mlx5_sample_ipool",
 263         },
 264         [MLX5_IPOOL_DEST_ARRAY] = {
 265                 .size = sizeof(struct mlx5_flow_dv_dest_array_resource),
 266                 .trunk_size = 64,
 267                 .grow_trunk = 3,
 268                 .grow_shift = 2,
 269                 .need_lock = 1,
 270                 .release_mem_en = 1,
 271                 .malloc = mlx5_malloc,
 272                 .free = mlx5_free,
 273                 .type = "mlx5_dest_array_ipool",
 274         },
 275         [MLX5_IPOOL_TUNNEL_ID] = {
 276                 .size = sizeof(struct mlx5_flow_tunnel),
 277                 .trunk_size = MLX5_MAX_TUNNELS,
 278                 .need_lock = 1,
 279                 .release_mem_en = 1,
 280                 .type = "mlx5_tunnel_offload",
 281         },
 282         [MLX5_IPOOL_TNL_TBL_ID] = {
 283                 .size = 0,
 284                 .need_lock = 1,
 285                 .type = "mlx5_flow_tnl_tbl_ipool",
 286         },
 287 #endif
 288         [MLX5_IPOOL_MTR] = {
 289                 /**
 290                  * The ipool index should grow continually from small to big,
 291                  * for meter idx, so not set grow_trunk to avoid meter index
 292                  * not jump continually.
 293                  */
 294                 .size = sizeof(struct mlx5_legacy_flow_meter),
 295                 .trunk_size = 64,
 296                 .need_lock = 1,
 297                 .release_mem_en = 1,
 298                 .malloc = mlx5_malloc,
 299                 .free = mlx5_free,
 300                 .type = "mlx5_meter_ipool",
 301         },
 302         [MLX5_IPOOL_MCP] = {
 303                 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
 304                 .trunk_size = 64,
 305                 .grow_trunk = 3,
 306                 .grow_shift = 2,
 307                 .need_lock = 1,
 308                 .release_mem_en = 1,
 309                 .malloc = mlx5_malloc,
 310                 .free = mlx5_free,
 311                 .type = "mlx5_mcp_ipool",
 312         },
 313         [MLX5_IPOOL_HRXQ] = {
 314                 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
 315                 .trunk_size = 64,
 316                 .grow_trunk = 3,
 317                 .grow_shift = 2,
 318                 .need_lock = 1,
 319                 .release_mem_en = 1,
 320                 .malloc = mlx5_malloc,
 321                 .free = mlx5_free,
 322                 .type = "mlx5_hrxq_ipool",
 323         },
 324         [MLX5_IPOOL_MLX5_FLOW] = {
 325                 /*
 326                  * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
 327                  * It set in run time according to PCI function configuration.
 328                  */
 329                 .size = 0,
 330                 .trunk_size = 64,
 331                 .grow_trunk = 3,
 332                 .grow_shift = 2,
 333                 .need_lock = 1,
 334                 .release_mem_en = 0,
 335                 .per_core_cache = 1 << 19,
 336                 .malloc = mlx5_malloc,
 337                 .free = mlx5_free,
 338                 .type = "mlx5_flow_handle_ipool",
 339         },
 340         [MLX5_IPOOL_RTE_FLOW] = {
 341                 .size = sizeof(struct rte_flow),
 342                 .trunk_size = 4096,
 343                 .need_lock = 1,
 344                 .release_mem_en = 1,
 345                 .malloc = mlx5_malloc,
 346                 .free = mlx5_free,
 347                 .type = "rte_flow_ipool",
 348         },
 349         [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID] = {
 350                 .size = 0,
 351                 .need_lock = 1,
 352                 .type = "mlx5_flow_rss_id_ipool",
 353         },
 354         [MLX5_IPOOL_RSS_SHARED_ACTIONS] = {
 355                 .size = sizeof(struct mlx5_shared_action_rss),
 356                 .trunk_size = 64,
 357                 .grow_trunk = 3,
 358                 .grow_shift = 2,
 359                 .need_lock = 1,
 360                 .release_mem_en = 1,
 361                 .malloc = mlx5_malloc,
 362                 .free = mlx5_free,
 363                 .type = "mlx5_shared_action_rss",
 364         },
 365         [MLX5_IPOOL_MTR_POLICY] = {
 366                 /**
 367                  * The ipool index should grow continually from small to big,
 368                  * for policy idx, so not set grow_trunk to avoid policy index
 369                  * not jump continually.
 370                  */
 371                 .size = sizeof(struct mlx5_flow_meter_sub_policy),
 372                 .trunk_size = 64,
 373                 .need_lock = 1,
 374                 .release_mem_en = 1,
 375                 .malloc = mlx5_malloc,
 376                 .free = mlx5_free,
 377                 .type = "mlx5_meter_policy_ipool",
 378         },
 379 };
 380
 381
 382 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
 383 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
 384
 385 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 1024
 386
 387 /**
 388  * Decide whether representor ID is a HPF(host PF) port on BF2.
 389  *
 390  * @param dev
 391  *   Pointer to Ethernet device structure.
 392  *
 393  * @return
 394  *   Non-zero if HPF, otherwise 0.
 395  */
 396 bool
 397 mlx5_is_hpf(struct rte_eth_dev *dev)
 398 {
 399         struct mlx5_priv *priv = dev->data->dev_private;
 400         uint16_t repr = MLX5_REPRESENTOR_REPR(priv->representor_id);
 401         int type = MLX5_REPRESENTOR_TYPE(priv->representor_id);
 402
 403         return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_VF &&
 404                MLX5_REPRESENTOR_REPR(-1) == repr;
 405 }
 406
 407 /**
 408  * Decide whether representor ID is a SF port representor.
 409  *
 410  * @param dev
 411  *   Pointer to Ethernet device structure.
 412  *
 413  * @return
 414  *   Non-zero if HPF, otherwise 0.
 415  */
 416 bool
 417 mlx5_is_sf_repr(struct rte_eth_dev *dev)
 418 {
 419         struct mlx5_priv *priv = dev->data->dev_private;
 420         int type = MLX5_REPRESENTOR_TYPE(priv->representor_id);
 421
 422         return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_SF;
 423 }
 424
 425 /**
 426  * Initialize the ASO aging management structure.
 427  *
 428  * @param[in] sh
 429  *   Pointer to mlx5_dev_ctx_shared object to free
 430  *
 431  * @return
 432  *   0 on success, a negative errno value otherwise and rte_errno is set.
 433  */
 434 int
 435 mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh)
 436 {
 437         int err;
 438
 439         if (sh->aso_age_mng)
 440                 return 0;
 441         sh->aso_age_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->aso_age_mng),
 442                                       RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 443         if (!sh->aso_age_mng) {
 444                 DRV_LOG(ERR, "aso_age_mng allocation was failed.");
 445                 rte_errno = ENOMEM;
 446                 return -ENOMEM;
 447         }
 448         err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_FLOW_HIT);
 449         if (err) {
 450                 mlx5_free(sh->aso_age_mng);
 451                 return -1;
 452         }
 453         rte_spinlock_init(&sh->aso_age_mng->resize_sl);
 454         rte_spinlock_init(&sh->aso_age_mng->free_sl);
 455         LIST_INIT(&sh->aso_age_mng->free);
 456         return 0;
 457 }
 458
 459 /**
 460  * Close and release all the resources of the ASO aging management structure.
 461  *
 462  * @param[in] sh
 463  *   Pointer to mlx5_dev_ctx_shared object to free.
 464  */
 465 static void
 466 mlx5_flow_aso_age_mng_close(struct mlx5_dev_ctx_shared *sh)
 467 {
 468         int i, j;
 469
 470         mlx5_aso_flow_hit_queue_poll_stop(sh);
 471         mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_FLOW_HIT);
 472         if (sh->aso_age_mng->pools) {
 473                 struct mlx5_aso_age_pool *pool;
 474
 475                 for (i = 0; i < sh->aso_age_mng->next; ++i) {
 476                         pool = sh->aso_age_mng->pools[i];
 477                         claim_zero(mlx5_devx_cmd_destroy
 478                                                 (pool->flow_hit_aso_obj));
 479                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j)
 480                                 if (pool->actions[j].dr_action)
 481                                         claim_zero
 482                                             (mlx5_flow_os_destroy_flow_action
 483                                               (pool->actions[j].dr_action));
 484                         mlx5_free(pool);
 485                 }
 486                 mlx5_free(sh->aso_age_mng->pools);
 487         }
 488         mlx5_free(sh->aso_age_mng);
 489 }
 490
 491 /**
 492  * Initialize the shared aging list information per port.
 493  *
 494  * @param[in] sh
 495  *   Pointer to mlx5_dev_ctx_shared object.
 496  */
 497 static void
 498 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
 499 {
 500         uint32_t i;
 501         struct mlx5_age_info *age_info;
 502
 503         for (i = 0; i < sh->max_port; i++) {
 504                 age_info = &sh->port[i].age_info;
 505                 age_info->flags = 0;
 506                 TAILQ_INIT(&age_info->aged_counters);
 507                 LIST_INIT(&age_info->aged_aso);
 508                 rte_spinlock_init(&age_info->aged_sl);
 509                 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
 510         }
 511 }
 512
 513 /**
 514  * Initialize the counters management structure.
 515  *
 516  * @param[in] sh
 517  *   Pointer to mlx5_dev_ctx_shared object to free
 518  */
 519 static void
 520 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
 521 {
 522         struct mlx5_hca_attr *attr = &sh->cdev->config.hca_attr;
 523         int i;
 524
 525         memset(&sh->cmng, 0, sizeof(sh->cmng));
 526         TAILQ_INIT(&sh->cmng.flow_counters);
 527         sh->cmng.min_id = MLX5_CNT_BATCH_OFFSET;
 528         sh->cmng.max_id = -1;
 529         sh->cmng.last_pool_idx = POOL_IDX_INVALID;
 530         rte_spinlock_init(&sh->cmng.pool_update_sl);
 531         for (i = 0; i < MLX5_COUNTER_TYPE_MAX; i++) {
 532                 TAILQ_INIT(&sh->cmng.counters[i]);
 533                 rte_spinlock_init(&sh->cmng.csl[i]);
 534         }
 535         if (sh->devx && !haswell_broadwell_cpu) {
 536                 sh->cmng.relaxed_ordering_write = attr->relaxed_ordering_write;
 537                 sh->cmng.relaxed_ordering_read = attr->relaxed_ordering_read;
 538         }
 539 }
 540
 541 /**
 542  * Destroy all the resources allocated for a counter memory management.
 543  *
 544  * @param[in] mng
 545  *   Pointer to the memory management structure.
 546  */
 547 static void
 548 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
 549 {
 550         uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
 551
 552         LIST_REMOVE(mng, next);
 553         claim_zero(mlx5_devx_cmd_destroy(mng->dm));
 554         claim_zero(mlx5_os_umem_dereg(mng->umem));
 555         mlx5_free(mem);
 556 }
 557
 558 /**
 559  * Close and release all the resources of the counters management.
 560  *
 561  * @param[in] sh
 562  *   Pointer to mlx5_dev_ctx_shared object to free.
 563  */
 564 static void
 565 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
 566 {
 567         struct mlx5_counter_stats_mem_mng *mng;
 568         int i, j;
 569         int retries = 1024;
 570
 571         rte_errno = 0;
 572         while (--retries) {
 573                 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
 574                 if (rte_errno != EINPROGRESS)
 575                         break;
 576                 rte_pause();
 577         }
 578
 579         if (sh->cmng.pools) {
 580                 struct mlx5_flow_counter_pool *pool;
 581                 uint16_t n_valid = sh->cmng.n_valid;
 582                 bool fallback = sh->cmng.counter_fallback;
 583
 584                 for (i = 0; i < n_valid; ++i) {
 585                         pool = sh->cmng.pools[i];
 586                         if (!fallback && pool->min_dcs)
 587                                 claim_zero(mlx5_devx_cmd_destroy
 588                                                                (pool->min_dcs));
 589                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
 590                                 struct mlx5_flow_counter *cnt =
 591                                                 MLX5_POOL_GET_CNT(pool, j);
 592
 593                                 if (cnt->action)
 594                                         claim_zero
 595                                          (mlx5_flow_os_destroy_flow_action
 596                                           (cnt->action));
 597                                 if (fallback && MLX5_POOL_GET_CNT
 598                                     (pool, j)->dcs_when_free)
 599                                         claim_zero(mlx5_devx_cmd_destroy
 600                                                    (cnt->dcs_when_free));
 601                         }
 602                         mlx5_free(pool);
 603                 }
 604                 mlx5_free(sh->cmng.pools);
 605         }
 606         mng = LIST_FIRST(&sh->cmng.mem_mngs);
 607         while (mng) {
 608                 mlx5_flow_destroy_counter_stat_mem_mng(mng);
 609                 mng = LIST_FIRST(&sh->cmng.mem_mngs);
 610         }
 611         memset(&sh->cmng, 0, sizeof(sh->cmng));
 612 }
 613
 614 /**
 615  * Initialize the aso flow meters management structure.
 616  *
 617  * @param[in] sh
 618  *   Pointer to mlx5_dev_ctx_shared object to free
 619  */
 620 int
 621 mlx5_aso_flow_mtrs_mng_init(struct mlx5_dev_ctx_shared *sh)
 622 {
 623         if (!sh->mtrmng) {
 624                 sh->mtrmng = mlx5_malloc(MLX5_MEM_ZERO,
 625                         sizeof(*sh->mtrmng),
 626                         RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 627                 if (!sh->mtrmng) {
 628                         DRV_LOG(ERR,
 629                         "meter management allocation was failed.");
 630                         rte_errno = ENOMEM;
 631                         return -ENOMEM;
 632                 }
 633                 if (sh->meter_aso_en) {
 634                         rte_spinlock_init(&sh->mtrmng->pools_mng.mtrsl);
 635                         LIST_INIT(&sh->mtrmng->pools_mng.meters);
 636                 }
 637                 sh->mtrmng->def_policy_id = MLX5_INVALID_POLICY_ID;
 638         }
 639         return 0;
 640 }
 641
 642 /**
 643  * Close and release all the resources of
 644  * the ASO flow meter management structure.
 645  *
 646  * @param[in] sh
 647  *   Pointer to mlx5_dev_ctx_shared object to free.
 648  */
 649 static void
 650 mlx5_aso_flow_mtrs_mng_close(struct mlx5_dev_ctx_shared *sh)
 651 {
 652         struct mlx5_aso_mtr_pool *mtr_pool;
 653         struct mlx5_flow_mtr_mng *mtrmng = sh->mtrmng;
 654         uint32_t idx;
 655 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
 656         struct mlx5_aso_mtr *aso_mtr;
 657         int i;
 658 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
 659
 660         if (sh->meter_aso_en) {
 661                 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_POLICER);
 662                 idx = mtrmng->pools_mng.n_valid;
 663                 while (idx--) {
 664                         mtr_pool = mtrmng->pools_mng.pools[idx];
 665 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
 666                         for (i = 0; i < MLX5_ASO_MTRS_PER_POOL; i++) {
 667                                 aso_mtr = &mtr_pool->mtrs[i];
 668                                 if (aso_mtr->fm.meter_action)
 669                                         claim_zero
 670                                         (mlx5_glue->destroy_flow_action
 671                                         (aso_mtr->fm.meter_action));
 672                         }
 673 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
 674                         claim_zero(mlx5_devx_cmd_destroy
 675                                                 (mtr_pool->devx_obj));
 676                         mtrmng->pools_mng.n_valid--;
 677                         mlx5_free(mtr_pool);
 678                 }
 679                 mlx5_free(sh->mtrmng->pools_mng.pools);
 680         }
 681         mlx5_free(sh->mtrmng);
 682         sh->mtrmng = NULL;
 683 }
 684
 685 /* Send FLOW_AGED event if needed. */
 686 void
 687 mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh)
 688 {
 689         struct mlx5_age_info *age_info;
 690         uint32_t i;
 691
 692         for (i = 0; i < sh->max_port; i++) {
 693                 age_info = &sh->port[i].age_info;
 694                 if (!MLX5_AGE_GET(age_info, MLX5_AGE_EVENT_NEW))
 695                         continue;
 696                 MLX5_AGE_UNSET(age_info, MLX5_AGE_EVENT_NEW);
 697                 if (MLX5_AGE_GET(age_info, MLX5_AGE_TRIGGER)) {
 698                         MLX5_AGE_UNSET(age_info, MLX5_AGE_TRIGGER);
 699                         rte_eth_dev_callback_process
 700                                 (&rte_eth_devices[sh->port[i].devx_ih_port_id],
 701                                 RTE_ETH_EVENT_FLOW_AGED, NULL);
 702                 }
 703         }
 704 }
 705
 706 /*
 707  * Initialize the ASO connection tracking structure.
 708  *
 709  * @param[in] sh
 710  *   Pointer to mlx5_dev_ctx_shared object.
 711  *
 712  * @return
 713  *   0 on success, a negative errno value otherwise and rte_errno is set.
 714  */
 715 int
 716 mlx5_flow_aso_ct_mng_init(struct mlx5_dev_ctx_shared *sh)
 717 {
 718         int err;
 719
 720         if (sh->ct_mng)
 721                 return 0;
 722         sh->ct_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->ct_mng),
 723                                  RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 724         if (!sh->ct_mng) {
 725                 DRV_LOG(ERR, "ASO CT management allocation failed.");
 726                 rte_errno = ENOMEM;
 727                 return -rte_errno;
 728         }
 729         err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_CONNECTION_TRACKING);
 730         if (err) {
 731                 mlx5_free(sh->ct_mng);
 732                 /* rte_errno should be extracted from the failure. */
 733                 rte_errno = EINVAL;
 734                 return -rte_errno;
 735         }
 736         rte_spinlock_init(&sh->ct_mng->ct_sl);
 737         rte_rwlock_init(&sh->ct_mng->resize_rwl);
 738         LIST_INIT(&sh->ct_mng->free_cts);
 739         return 0;
 740 }
 741
 742 /*
 743  * Close and release all the resources of the
 744  * ASO connection tracking management structure.
 745  *
 746  * @param[in] sh
 747  *   Pointer to mlx5_dev_ctx_shared object to free.
 748  */
 749 static void
 750 mlx5_flow_aso_ct_mng_close(struct mlx5_dev_ctx_shared *sh)
 751 {
 752         struct mlx5_aso_ct_pools_mng *mng = sh->ct_mng;
 753         struct mlx5_aso_ct_pool *ct_pool;
 754         struct mlx5_aso_ct_action *ct;
 755         uint32_t idx;
 756         uint32_t val;
 757         uint32_t cnt;
 758         int i;
 759
 760         mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_CONNECTION_TRACKING);
 761         idx = mng->next;
 762         while (idx--) {
 763                 cnt = 0;
 764                 ct_pool = mng->pools[idx];
 765                 for (i = 0; i < MLX5_ASO_CT_ACTIONS_PER_POOL; i++) {
 766                         ct = &ct_pool->actions[i];
 767                         val = __atomic_fetch_sub(&ct->refcnt, 1,
 768                                                  __ATOMIC_RELAXED);
 769                         MLX5_ASSERT(val == 1);
 770                         if (val > 1)
 771                                 cnt++;
 772 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
 773                         if (ct->dr_action_orig)
 774                                 claim_zero(mlx5_glue->destroy_flow_action
 775                                                         (ct->dr_action_orig));
 776                         if (ct->dr_action_rply)
 777                                 claim_zero(mlx5_glue->destroy_flow_action
 778                                                         (ct->dr_action_rply));
 779 #endif
 780                 }
 781                 claim_zero(mlx5_devx_cmd_destroy(ct_pool->devx_obj));
 782                 if (cnt) {
 783                         DRV_LOG(DEBUG, "%u ASO CT objects are being used in the pool %u",
 784                                 cnt, i);
 785                 }
 786                 mlx5_free(ct_pool);
 787                 /* in case of failure. */
 788                 mng->next--;
 789         }
 790         mlx5_free(mng->pools);
 791         mlx5_free(mng);
 792         /* Management structure must be cleared to 0s during allocation. */
 793         sh->ct_mng = NULL;
 794 }
 795
 796 /**
 797  * Initialize the flow resources' indexed mempool.
 798  *
 799  * @param[in] sh
 800  *   Pointer to mlx5_dev_ctx_shared object.
 801  * @param[in] config
 802  *   Pointer to user dev config.
 803  */
 804 static void
 805 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
 806                        const struct mlx5_dev_config *config)
 807 {
 808         uint8_t i;
 809         struct mlx5_indexed_pool_config cfg;
 810
 811         for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
 812                 cfg = mlx5_ipool_cfg[i];
 813                 switch (i) {
 814                 default:
 815                         break;
 816                 /*
 817                  * Set MLX5_IPOOL_MLX5_FLOW ipool size
 818                  * according to PCI function flow configuration.
 819                  */
 820                 case MLX5_IPOOL_MLX5_FLOW:
 821                         cfg.size = config->dv_flow_en ?
 822                                 sizeof(struct mlx5_flow_handle) :
 823                                 MLX5_FLOW_HANDLE_VERBS_SIZE;
 824                         break;
 825                 }
 826                 if (config->reclaim_mode) {
 827                         cfg.release_mem_en = 1;
 828                         cfg.per_core_cache = 0;
 829                 } else {
 830                         cfg.release_mem_en = 0;
 831                 }
 832                 sh->ipool[i] = mlx5_ipool_create(&cfg);
 833         }
 834 }
 835
 836
 837 /**
 838  * Release the flow resources' indexed mempool.
 839  *
 840  * @param[in] sh
 841  *   Pointer to mlx5_dev_ctx_shared object.
 842  */
 843 static void
 844 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
 845 {
 846         uint8_t i;
 847
 848         for (i = 0; i < MLX5_IPOOL_MAX; ++i)
 849                 mlx5_ipool_destroy(sh->ipool[i]);
 850         for (i = 0; i < MLX5_MAX_MODIFY_NUM; ++i)
 851                 if (sh->mdh_ipools[i])
 852                         mlx5_ipool_destroy(sh->mdh_ipools[i]);
 853 }
 854
 855 /*
 856  * Check if dynamic flex parser for eCPRI already exists.
 857  *
 858  * @param dev
 859  *   Pointer to Ethernet device structure.
 860  *
 861  * @return
 862  *   true on exists, false on not.
 863  */
 864 bool
 865 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
 866 {
 867         struct mlx5_priv *priv = dev->data->dev_private;
 868         struct mlx5_flex_parser_profiles *prf =
 869                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 870
 871         return !!prf->obj;
 872 }
 873
 874 /*
 875  * Allocation of a flex parser for eCPRI. Once created, this parser related
 876  * resources will be held until the device is closed.
 877  *
 878  * @param dev
 879  *   Pointer to Ethernet device structure.
 880  *
 881  * @return
 882  *   0 on success, a negative errno value otherwise and rte_errno is set.
 883  */
 884 int
 885 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
 886 {
 887         struct mlx5_priv *priv = dev->data->dev_private;
 888         struct mlx5_flex_parser_profiles *prf =
 889                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 890         struct mlx5_devx_graph_node_attr node = {
 891                 .modify_field_select = 0,
 892         };
 893         uint32_t ids[8];
 894         int ret;
 895
 896         if (!priv->config.hca_attr.parse_graph_flex_node) {
 897                 DRV_LOG(ERR, "Dynamic flex parser is not supported "
 898                         "for device %s.", priv->dev_data->name);
 899                 return -ENOTSUP;
 900         }
 901         node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED;
 902         /* 8 bytes now: 4B common header + 4B message body header. */
 903         node.header_length_base_value = 0x8;
 904         /* After MAC layer: Ether / VLAN. */
 905         node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC;
 906         /* Type of compared condition should be 0xAEFE in the L2 layer. */
 907         node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI;
 908         /* Sample #0: type in common header. */
 909         node.sample[0].flow_match_sample_en = 1;
 910         /* Fixed offset. */
 911         node.sample[0].flow_match_sample_offset_mode = 0x0;
 912         /* Only the 2nd byte will be used. */
 913         node.sample[0].flow_match_sample_field_base_offset = 0x0;
 914         /* Sample #1: message payload. */
 915         node.sample[1].flow_match_sample_en = 1;
 916         /* Fixed offset. */
 917         node.sample[1].flow_match_sample_offset_mode = 0x0;
 918         /*
 919          * Only the first two bytes will be used right now, and its offset will
 920          * start after the common header that with the length of a DW(u32).
 921          */
 922         node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);
 923         prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->cdev->ctx, &node);
 924         if (!prf->obj) {
 925                 DRV_LOG(ERR, "Failed to create flex parser node object.");
 926                 return (rte_errno == 0) ? -ENODEV : -rte_errno;
 927         }
 928         prf->num = 2;
 929         ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num);
 930         if (ret) {
 931                 DRV_LOG(ERR, "Failed to query sample IDs.");
 932                 return (rte_errno == 0) ? -ENODEV : -rte_errno;
 933         }
 934         prf->offset[0] = 0x0;
 935         prf->offset[1] = sizeof(uint32_t);
 936         prf->ids[0] = ids[0];
 937         prf->ids[1] = ids[1];
 938         return 0;
 939 }
 940
 941 /*
 942  * Destroy the flex parser node, including the parser itself, input / output
 943  * arcs and DW samples. Resources could be reused then.
 944  *
 945  * @param dev
 946  *   Pointer to Ethernet device structure.
 947  */
 948 static void
 949 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
 950 {
 951         struct mlx5_priv *priv = dev->data->dev_private;
 952         struct mlx5_flex_parser_profiles *prf =
 953                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 954
 955         if (prf->obj)
 956                 mlx5_devx_cmd_destroy(prf->obj);
 957         prf->obj = NULL;
 958 }
 959
 960 uint32_t
 961 mlx5_get_supported_sw_parsing_offloads(const struct mlx5_hca_attr *attr)
 962 {
 963         uint32_t sw_parsing_offloads = 0;
 964
 965         if (attr->swp) {
 966                 sw_parsing_offloads |= MLX5_SW_PARSING_CAP;
 967                 if (attr->swp_csum)
 968                         sw_parsing_offloads |= MLX5_SW_PARSING_CSUM_CAP;
 969
 970                 if (attr->swp_lso)
 971                         sw_parsing_offloads |= MLX5_SW_PARSING_TSO_CAP;
 972         }
 973         return sw_parsing_offloads;
 974 }
 975
 976 uint32_t
 977 mlx5_get_supported_tunneling_offloads(const struct mlx5_hca_attr *attr)
 978 {
 979         uint32_t tn_offloads = 0;
 980
 981         if (attr->tunnel_stateless_vxlan)
 982                 tn_offloads |= MLX5_TUNNELED_OFFLOADS_VXLAN_CAP;
 983         if (attr->tunnel_stateless_gre)
 984                 tn_offloads |= MLX5_TUNNELED_OFFLOADS_GRE_CAP;
 985         if (attr->tunnel_stateless_geneve_rx)
 986                 tn_offloads |= MLX5_TUNNELED_OFFLOADS_GENEVE_CAP;
 987         return tn_offloads;
 988 }
 989
 990 /*
 991  * Allocate Rx and Tx UARs in robust fashion.
 992  * This routine handles the following UAR allocation issues:
 993  *
 994  *  - tries to allocate the UAR with the most appropriate memory
 995  *    mapping type from the ones supported by the host
 996  *
 997  *  - tries to allocate the UAR with non-NULL base address
 998  *    OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as
 999  *    UAR base address if UAR was not the first object in the UAR page.
1000  *    It caused the PMD failure and we should try to get another UAR
1001  *    till we get the first one with non-NULL base address returned.
1002  */
1003 static int
1004 mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh,
1005                      const struct mlx5_common_dev_config *config)
1006 {
1007         uint32_t uar_mapping, retry;
1008         int err = 0;
1009         void *base_addr;
1010
1011         for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
1012 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
1013                 /* Control the mapping type according to the settings. */
1014                 uar_mapping = (config->dbnc == MLX5_TXDB_NCACHED) ?
1015                               MLX5DV_UAR_ALLOC_TYPE_NC :
1016                               MLX5DV_UAR_ALLOC_TYPE_BF;
1017 #else
1018                 RTE_SET_USED(config);
1019                 /*
1020                  * It seems we have no way to control the memory mapping type
1021                  * for the UAR, the default "Write-Combining" type is supposed.
1022                  * The UAR initialization on queue creation queries the
1023                  * actual mapping type done by Verbs/kernel and setups the
1024                  * PMD datapath accordingly.
1025                  */
1026                 uar_mapping = 0;
1027 #endif
1028                 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->cdev->ctx,
1029                                                        uar_mapping);
1030 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
1031                 if (!sh->tx_uar &&
1032                     uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
1033                         if (config->dbnc == MLX5_TXDB_CACHED ||
1034                             config->dbnc == MLX5_TXDB_HEURISTIC)
1035                                 DRV_LOG(WARNING, "Devarg tx_db_nc setting "
1036                                                  "is not supported by DevX");
1037                         /*
1038                          * In some environments like virtual machine
1039                          * the Write Combining mapped might be not supported
1040                          * and UAR allocation fails. We try "Non-Cached"
1041                          * mapping for the case. The tx_burst routines take
1042                          * the UAR mapping type into account on UAR setup
1043                          * on queue creation.
1044                          */
1045                         DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (BF)");
1046                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
1047                         sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->cdev->ctx,
1048                                                                uar_mapping);
1049                 } else if (!sh->tx_uar &&
1050                            uar_mapping == MLX5DV_UAR_ALLOC_TYPE_NC) {
1051                         if (config->dbnc == MLX5_TXDB_NCACHED)
1052                                 DRV_LOG(WARNING, "Devarg tx_db_nc settings "
1053                                                  "is not supported by DevX");
1054                         /*
1055                          * If Verbs/kernel does not support "Non-Cached"
1056                          * try the "Write-Combining".
1057                          */
1058                         DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (NC)");
1059                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_BF;
1060                         sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->cdev->ctx,
1061                                                                uar_mapping);
1062                 }
1063 #endif
1064                 if (!sh->tx_uar) {
1065                         DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (BF/NC)");
1066                         err = ENOMEM;
1067                         goto exit;
1068                 }
1069                 base_addr = mlx5_os_get_devx_uar_base_addr(sh->tx_uar);
1070                 if (base_addr)
1071                         break;
1072                 /*
1073                  * The UARs are allocated by rdma_core within the
1074                  * IB device context, on context closure all UARs
1075                  * will be freed, should be no memory/object leakage.
1076                  */
1077                 DRV_LOG(DEBUG, "Retrying to allocate Tx DevX UAR");
1078                 sh->tx_uar = NULL;
1079         }
1080         /* Check whether we finally succeeded with valid UAR allocation. */
1081         if (!sh->tx_uar) {
1082                 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (NULL base)");
1083                 err = ENOMEM;
1084                 goto exit;
1085         }
1086         for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
1087                 uar_mapping = 0;
1088                 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar(sh->cdev->ctx,
1089                                                             uar_mapping);
1090 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
1091                 if (!sh->devx_rx_uar &&
1092                     uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
1093                         /*
1094                          * Rx UAR is used to control interrupts only,
1095                          * should be no datapath noticeable impact,
1096                          * can try "Non-Cached" mapping safely.
1097                          */
1098                         DRV_LOG(DEBUG, "Failed to allocate Rx DevX UAR (BF)");
1099                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
1100                         sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
1101                                                    (sh->cdev->ctx, uar_mapping);
1102                 }
1103 #endif
1104                 if (!sh->devx_rx_uar) {
1105                         DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (BF/NC)");
1106                         err = ENOMEM;
1107                         goto exit;
1108                 }
1109                 base_addr = mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar);
1110                 if (base_addr)
1111                         break;
1112                 /*
1113                  * The UARs are allocated by rdma_core within the
1114                  * IB device context, on context closure all UARs
1115                  * will be freed, should be no memory/object leakage.
1116                  */
1117                 DRV_LOG(DEBUG, "Retrying to allocate Rx DevX UAR");
1118                 sh->devx_rx_uar = NULL;
1119         }
1120         /* Check whether we finally succeeded with valid UAR allocation. */
1121         if (!sh->devx_rx_uar) {
1122                 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (NULL base)");
1123                 err = ENOMEM;
1124         }
1125 exit:
1126         return err;
1127 }
1128
1129 /**
1130  * rte_mempool_walk() callback to unregister Rx mempools.
1131  * It used when implicit mempool registration is disabled.
1132  *
1133  * @param mp
1134  *   The mempool being walked.
1135  * @param arg
1136  *   Pointer to the device shared context.
1137  */
1138 static void
1139 mlx5_dev_ctx_shared_rx_mempool_unregister_cb(struct rte_mempool *mp, void *arg)
1140 {
1141         struct mlx5_dev_ctx_shared *sh = arg;
1142
1143         mlx5_dev_mempool_unregister(sh->cdev, mp);
1144 }
1145
1146 /**
1147  * Callback used when implicit mempool registration is disabled
1148  * in order to track Rx mempool destruction.
1149  *
1150  * @param event
1151  *   Mempool life cycle event.
1152  * @param mp
1153  *   An Rx mempool registered explicitly when the port is started.
1154  * @param arg
1155  *   Pointer to a device shared context.
1156  */
1157 static void
1158 mlx5_dev_ctx_shared_rx_mempool_event_cb(enum rte_mempool_event event,
1159                                         struct rte_mempool *mp, void *arg)
1160 {
1161         struct mlx5_dev_ctx_shared *sh = arg;
1162
1163         if (event == RTE_MEMPOOL_EVENT_DESTROY)
1164                 mlx5_dev_mempool_unregister(sh->cdev, mp);
1165 }
1166
1167 int
1168 mlx5_dev_ctx_shared_mempool_subscribe(struct rte_eth_dev *dev)
1169 {
1170         struct mlx5_priv *priv = dev->data->dev_private;
1171         struct mlx5_dev_ctx_shared *sh = priv->sh;
1172         int ret;
1173
1174         /* Check if we only need to track Rx mempool destruction. */
1175         if (!sh->cdev->config.mr_mempool_reg_en) {
1176                 ret = rte_mempool_event_callback_register
1177                                 (mlx5_dev_ctx_shared_rx_mempool_event_cb, sh);
1178                 return ret == 0 || rte_errno == EEXIST ? 0 : ret;
1179         }
1180         return mlx5_dev_mempool_subscribe(sh->cdev);
1181 }
1182
1183 /**
1184  * Allocate shared device context. If there is multiport device the
1185  * master and representors will share this context, if there is single
1186  * port dedicated device, the context will be used by only given
1187  * port due to unification.
1188  *
1189  * Routine first searches the context for the specified device name,
1190  * if found the shared context assumed and reference counter is incremented.
1191  * If no context found the new one is created and initialized with specified
1192  * device context and parameters.
1193  *
1194  * @param[in] spawn
1195  *   Pointer to the device attributes (name, port, etc).
1196  * @param[in] config
1197  *   Pointer to device configuration structure.
1198  *
1199  * @return
1200  *   Pointer to mlx5_dev_ctx_shared object on success,
1201  *   otherwise NULL and rte_errno is set.
1202  */
1203 struct mlx5_dev_ctx_shared *
1204 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
1205                           const struct mlx5_dev_config *config)
1206 {
1207         struct mlx5_dev_ctx_shared *sh;
1208         int err = 0;
1209         uint32_t i;
1210         struct mlx5_devx_tis_attr tis_attr = { 0 };
1211
1212         MLX5_ASSERT(spawn);
1213         /* Secondary process should not create the shared context. */
1214         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1215         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1216         /* Search for IB context by device name. */
1217         LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
1218                 if (!strcmp(sh->ibdev_name, spawn->phys_dev_name)) {
1219                         sh->refcnt++;
1220                         goto exit;
1221                 }
1222         }
1223         /* No device found, we have to create new shared context. */
1224         MLX5_ASSERT(spawn->max_port);
1225         sh = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
1226                          sizeof(struct mlx5_dev_ctx_shared) +
1227                          spawn->max_port *
1228                          sizeof(struct mlx5_dev_shared_port),
1229                          RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
1230         if (!sh) {
1231                 DRV_LOG(ERR, "shared context allocation failure");
1232                 rte_errno  = ENOMEM;
1233                 goto exit;
1234         }
1235         pthread_mutex_init(&sh->txpp.mutex, NULL);
1236         sh->numa_node = spawn->cdev->dev->numa_node;
1237         sh->cdev = spawn->cdev;
1238         sh->devx = sh->cdev->config.devx;
1239         if (spawn->bond_info)
1240                 sh->bond = *spawn->bond_info;
1241         err = mlx5_os_get_dev_attr(sh->cdev, &sh->device_attr);
1242         if (err) {
1243                 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
1244                 goto error;
1245         }
1246         sh->refcnt = 1;
1247         sh->max_port = spawn->max_port;
1248         sh->reclaim_mode = config->reclaim_mode;
1249         strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->cdev->ctx),
1250                 sizeof(sh->ibdev_name) - 1);
1251         strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->cdev->ctx),
1252                 sizeof(sh->ibdev_path) - 1);
1253         /*
1254          * Setting port_id to max unallowed value means
1255          * there is no interrupt subhandler installed for
1256          * the given port index i.
1257          */
1258         for (i = 0; i < sh->max_port; i++) {
1259                 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
1260                 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
1261         }
1262         if (sh->devx) {
1263                 sh->td = mlx5_devx_cmd_create_td(sh->cdev->ctx);
1264                 if (!sh->td) {
1265                         DRV_LOG(ERR, "TD allocation failure");
1266                         err = ENOMEM;
1267                         goto error;
1268                 }
1269                 tis_attr.transport_domain = sh->td->id;
1270                 sh->tis = mlx5_devx_cmd_create_tis(sh->cdev->ctx, &tis_attr);
1271                 if (!sh->tis) {
1272                         DRV_LOG(ERR, "TIS allocation failure");
1273                         err = ENOMEM;
1274                         goto error;
1275                 }
1276                 err = mlx5_alloc_rxtx_uars(sh, &sh->cdev->config);
1277                 if (err)
1278                         goto error;
1279                 MLX5_ASSERT(sh->tx_uar);
1280                 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->tx_uar));
1281
1282                 MLX5_ASSERT(sh->devx_rx_uar);
1283                 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar));
1284         }
1285 #ifndef RTE_ARCH_64
1286         /* Initialize UAR access locks for 32bit implementations. */
1287         rte_spinlock_init(&sh->uar_lock_cq);
1288         for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
1289                 rte_spinlock_init(&sh->uar_lock[i]);
1290 #endif
1291         mlx5_os_dev_shared_handler_install(sh);
1292         if (LIST_EMPTY(&mlx5_dev_ctx_list)) {
1293                 err = mlx5_flow_os_init_workspace_once();
1294                 if (err)
1295                         goto error;
1296         }
1297         mlx5_flow_aging_init(sh);
1298         mlx5_flow_counters_mng_init(sh);
1299         mlx5_flow_ipool_create(sh, config);
1300         /* Add context to the global device list. */
1301         LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
1302         rte_spinlock_init(&sh->geneve_tlv_opt_sl);
1303 exit:
1304         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1305         return sh;
1306 error:
1307         pthread_mutex_destroy(&sh->txpp.mutex);
1308         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1309         MLX5_ASSERT(sh);
1310         if (sh->tis)
1311                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1312         if (sh->td)
1313                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1314         if (sh->devx_rx_uar)
1315                 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1316         if (sh->tx_uar)
1317                 mlx5_glue->devx_free_uar(sh->tx_uar);
1318         mlx5_free(sh);
1319         MLX5_ASSERT(err > 0);
1320         rte_errno = err;
1321         return NULL;
1322 }
1323
1324 /**
1325  * Free shared IB device context. Decrement counter and if zero free
1326  * all allocated resources and close handles.
1327  *
1328  * @param[in] sh
1329  *   Pointer to mlx5_dev_ctx_shared object to free
1330  */
1331 void
1332 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
1333 {
1334         int ret;
1335
1336         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1337 #ifdef RTE_LIBRTE_MLX5_DEBUG
1338         /* Check the object presence in the list. */
1339         struct mlx5_dev_ctx_shared *lctx;
1340
1341         LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
1342                 if (lctx == sh)
1343                         break;
1344         MLX5_ASSERT(lctx);
1345         if (lctx != sh) {
1346                 DRV_LOG(ERR, "Freeing non-existing shared IB context");
1347                 goto exit;
1348         }
1349 #endif
1350         MLX5_ASSERT(sh);
1351         MLX5_ASSERT(sh->refcnt);
1352         /* Secondary process should not free the shared context. */
1353         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1354         if (--sh->refcnt)
1355                 goto exit;
1356         /* Stop watching for mempool events and unregister all mempools. */
1357         if (!sh->cdev->config.mr_mempool_reg_en) {
1358                 ret = rte_mempool_event_callback_unregister
1359                                 (mlx5_dev_ctx_shared_rx_mempool_event_cb, sh);
1360                 if (ret == 0)
1361                         rte_mempool_walk
1362                              (mlx5_dev_ctx_shared_rx_mempool_unregister_cb, sh);
1363         }
1364         /* Remove context from the global device list. */
1365         LIST_REMOVE(sh, next);
1366         /* Release flow workspaces objects on the last device. */
1367         if (LIST_EMPTY(&mlx5_dev_ctx_list))
1368                 mlx5_flow_os_release_workspace();
1369         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1370         /*
1371          *  Ensure there is no async event handler installed.
1372          *  Only primary process handles async device events.
1373          **/
1374         mlx5_flow_counters_mng_close(sh);
1375         if (sh->aso_age_mng) {
1376                 mlx5_flow_aso_age_mng_close(sh);
1377                 sh->aso_age_mng = NULL;
1378         }
1379         if (sh->mtrmng)
1380                 mlx5_aso_flow_mtrs_mng_close(sh);
1381         mlx5_flow_ipool_destroy(sh);
1382         mlx5_os_dev_shared_handler_uninstall(sh);
1383         if (sh->tx_uar) {
1384                 mlx5_glue->devx_free_uar(sh->tx_uar);
1385                 sh->tx_uar = NULL;
1386         }
1387         if (sh->tis)
1388                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1389         if (sh->td)
1390                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1391         if (sh->devx_rx_uar)
1392                 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1393         MLX5_ASSERT(sh->geneve_tlv_option_resource == NULL);
1394         pthread_mutex_destroy(&sh->txpp.mutex);
1395         mlx5_free(sh);
1396         return;
1397 exit:
1398         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1399 }
1400
1401 /**
1402  * Destroy table hash list.
1403  *
1404  * @param[in] priv
1405  *   Pointer to the private device data structure.
1406  */
1407 void
1408 mlx5_free_table_hash_list(struct mlx5_priv *priv)
1409 {
1410         struct mlx5_dev_ctx_shared *sh = priv->sh;
1411
1412         if (!sh->flow_tbls)
1413                 return;
1414         mlx5_hlist_destroy(sh->flow_tbls);
1415         sh->flow_tbls = NULL;
1416 }
1417
1418 /**
1419  * Initialize flow table hash list and create the root tables entry
1420  * for each domain.
1421  *
1422  * @param[in] priv
1423  *   Pointer to the private device data structure.
1424  *
1425  * @return
1426  *   Zero on success, positive error code otherwise.
1427  */
1428 int
1429 mlx5_alloc_table_hash_list(struct mlx5_priv *priv __rte_unused)
1430 {
1431         int err = 0;
1432         /* Tables are only used in DV and DR modes. */
1433 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
1434         struct mlx5_dev_ctx_shared *sh = priv->sh;
1435         char s[MLX5_NAME_SIZE];
1436
1437         MLX5_ASSERT(sh);
1438         snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1439         sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE,
1440                                           false, true, sh,
1441                                           flow_dv_tbl_create_cb,
1442                                           flow_dv_tbl_match_cb,
1443                                           flow_dv_tbl_remove_cb,
1444                                           flow_dv_tbl_clone_cb,
1445                                           flow_dv_tbl_clone_free_cb);
1446         if (!sh->flow_tbls) {
1447                 DRV_LOG(ERR, "flow tables with hash creation failed.");
1448                 err = ENOMEM;
1449                 return err;
1450         }
1451 #ifndef HAVE_MLX5DV_DR
1452         struct rte_flow_error error;
1453         struct rte_eth_dev *dev = &rte_eth_devices[priv->dev_data->port_id];
1454
1455         /*
1456          * In case we have not DR support, the zero tables should be created
1457          * because DV expect to see them even if they cannot be created by
1458          * RDMA-CORE.
1459          */
1460         if (!flow_dv_tbl_resource_get(dev, 0, 0, 0, 0,
1461                 NULL, 0, 1, 0, &error) ||
1462             !flow_dv_tbl_resource_get(dev, 0, 1, 0, 0,
1463                 NULL, 0, 1, 0, &error) ||
1464             !flow_dv_tbl_resource_get(dev, 0, 0, 1, 0,
1465                 NULL, 0, 1, 0, &error)) {
1466                 err = ENOMEM;
1467                 goto error;
1468         }
1469         return err;
1470 error:
1471         mlx5_free_table_hash_list(priv);
1472 #endif /* HAVE_MLX5DV_DR */
1473 #endif
1474         return err;
1475 }
1476
1477 /**
1478  * Retrieve integer value from environment variable.
1479  *
1480  * @param[in] name
1481  *   Environment variable name.
1482  *
1483  * @return
1484  *   Integer value, 0 if the variable is not set.
1485  */
1486 int
1487 mlx5_getenv_int(const char *name)
1488 {
1489         const char *val = getenv(name);
1490
1491         if (val == NULL)
1492                 return 0;
1493         return atoi(val);
1494 }
1495
1496 /**
1497  * DPDK callback to add udp tunnel port
1498  *
1499  * @param[in] dev
1500  *   A pointer to eth_dev
1501  * @param[in] udp_tunnel
1502  *   A pointer to udp tunnel
1503  *
1504  * @return
1505  *   0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1506  */
1507 int
1508 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1509                          struct rte_eth_udp_tunnel *udp_tunnel)
1510 {
1511         MLX5_ASSERT(udp_tunnel != NULL);
1512         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1513             udp_tunnel->udp_port == 4789)
1514                 return 0;
1515         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1516             udp_tunnel->udp_port == 4790)
1517                 return 0;
1518         return -ENOTSUP;
1519 }
1520
1521 /**
1522  * Initialize process private data structure.
1523  *
1524  * @param dev
1525  *   Pointer to Ethernet device structure.
1526  *
1527  * @return
1528  *   0 on success, a negative errno value otherwise and rte_errno is set.
1529  */
1530 int
1531 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1532 {
1533         struct mlx5_priv *priv = dev->data->dev_private;
1534         struct mlx5_proc_priv *ppriv;
1535         size_t ppriv_size;
1536
1537         mlx5_proc_priv_uninit(dev);
1538         /*
1539          * UAR register table follows the process private structure. BlueFlame
1540          * registers for Tx queues are stored in the table.
1541          */
1542         ppriv_size =
1543                 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1544         ppriv = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, ppriv_size,
1545                             RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1546         if (!ppriv) {
1547                 rte_errno = ENOMEM;
1548                 return -rte_errno;
1549         }
1550         ppriv->uar_table_sz = priv->txqs_n;
1551         dev->process_private = ppriv;
1552         return 0;
1553 }
1554
1555 /**
1556  * Un-initialize process private data structure.
1557  *
1558  * @param dev
1559  *   Pointer to Ethernet device structure.
1560  */
1561 void
1562 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1563 {
1564         if (!dev->process_private)
1565                 return;
1566         mlx5_free(dev->process_private);
1567         dev->process_private = NULL;
1568 }
1569
1570 /**
1571  * DPDK callback to close the device.
1572  *
1573  * Destroy all queues and objects, free memory.
1574  *
1575  * @param dev
1576  *   Pointer to Ethernet device structure.
1577  */
1578 int
1579 mlx5_dev_close(struct rte_eth_dev *dev)
1580 {
1581         struct mlx5_priv *priv = dev->data->dev_private;
1582         unsigned int i;
1583         int ret;
1584
1585         if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1586                 /* Check if process_private released. */
1587                 if (!dev->process_private)
1588                         return 0;
1589                 mlx5_tx_uar_uninit_secondary(dev);
1590                 mlx5_proc_priv_uninit(dev);
1591                 rte_eth_dev_release_port(dev);
1592                 return 0;
1593         }
1594         if (!priv->sh)
1595                 return 0;
1596         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1597                 dev->data->port_id,
1598                 ((priv->sh->cdev->ctx != NULL) ?
1599                 mlx5_os_get_ctx_device_name(priv->sh->cdev->ctx) : ""));
1600         /*
1601          * If default mreg copy action is removed at the stop stage,
1602          * the search will return none and nothing will be done anymore.
1603          */
1604         mlx5_flow_stop_default(dev);
1605         mlx5_traffic_disable(dev);
1606         /*
1607          * If all the flows are already flushed in the device stop stage,
1608          * then this will return directly without any action.
1609          */
1610         mlx5_flow_list_flush(dev, MLX5_FLOW_TYPE_GEN, true);
1611         mlx5_action_handle_flush(dev);
1612         mlx5_flow_meter_flush(dev, NULL);
1613         /* Prevent crashes when queues are still in use. */
1614         dev->rx_pkt_burst = removed_rx_burst;
1615         dev->tx_pkt_burst = removed_tx_burst;
1616         rte_wmb();
1617         /* Disable datapath on secondary process. */
1618         mlx5_mp_os_req_stop_rxtx(dev);
1619         /* Free the eCPRI flex parser resource. */
1620         mlx5_flex_parser_ecpri_release(dev);
1621         if (priv->rxqs != NULL) {
1622                 /* XXX race condition if mlx5_rx_burst() is still running. */
1623                 rte_delay_us_sleep(1000);
1624                 for (i = 0; (i != priv->rxqs_n); ++i)
1625                         mlx5_rxq_release(dev, i);
1626                 priv->rxqs_n = 0;
1627                 priv->rxqs = NULL;
1628         }
1629         if (priv->representor) {
1630                 /* Each representor has a dedicated interrupts handler */
1631                 mlx5_free(dev->intr_handle);
1632                 dev->intr_handle = NULL;
1633         }
1634         if (priv->txqs != NULL) {
1635                 /* XXX race condition if mlx5_tx_burst() is still running. */
1636                 rte_delay_us_sleep(1000);
1637                 for (i = 0; (i != priv->txqs_n); ++i)
1638                         mlx5_txq_release(dev, i);
1639                 priv->txqs_n = 0;
1640                 priv->txqs = NULL;
1641         }
1642         mlx5_proc_priv_uninit(dev);
1643         if (priv->q_counters) {
1644                 mlx5_devx_cmd_destroy(priv->q_counters);
1645                 priv->q_counters = NULL;
1646         }
1647         if (priv->drop_queue.hrxq)
1648                 mlx5_drop_action_destroy(dev);
1649         if (priv->mreg_cp_tbl)
1650                 mlx5_hlist_destroy(priv->mreg_cp_tbl);
1651         mlx5_mprq_free_mp(dev);
1652         if (priv->sh->ct_mng)
1653                 mlx5_flow_aso_ct_mng_close(priv->sh);
1654         mlx5_os_free_shared_dr(priv);
1655         if (priv->rss_conf.rss_key != NULL)
1656                 mlx5_free(priv->rss_conf.rss_key);
1657         if (priv->reta_idx != NULL)
1658                 mlx5_free(priv->reta_idx);
1659         if (priv->config.vf)
1660                 mlx5_os_mac_addr_flush(dev);
1661         if (priv->nl_socket_route >= 0)
1662                 close(priv->nl_socket_route);
1663         if (priv->nl_socket_rdma >= 0)
1664                 close(priv->nl_socket_rdma);
1665         if (priv->vmwa_context)
1666                 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1667         ret = mlx5_hrxq_verify(dev);
1668         if (ret)
1669                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1670                         dev->data->port_id);
1671         ret = mlx5_ind_table_obj_verify(dev);
1672         if (ret)
1673                 DRV_LOG(WARNING, "port %u some indirection table still remain",
1674                         dev->data->port_id);
1675         ret = mlx5_rxq_obj_verify(dev);
1676         if (ret)
1677                 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1678                         dev->data->port_id);
1679         ret = mlx5_rxq_verify(dev);
1680         if (ret)
1681                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1682                         dev->data->port_id);
1683         ret = mlx5_txq_obj_verify(dev);
1684         if (ret)
1685                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1686                         dev->data->port_id);
1687         ret = mlx5_txq_verify(dev);
1688         if (ret)
1689                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1690                         dev->data->port_id);
1691         ret = mlx5_flow_verify(dev);
1692         if (ret)
1693                 DRV_LOG(WARNING, "port %u some flows still remain",
1694                         dev->data->port_id);
1695         if (priv->hrxqs)
1696                 mlx5_list_destroy(priv->hrxqs);
1697         /*
1698          * Free the shared context in last turn, because the cleanup
1699          * routines above may use some shared fields, like
1700          * mlx5_os_mac_addr_flush() uses ibdev_path for retrieveing
1701          * ifindex if Netlink fails.
1702          */
1703         mlx5_free_shared_dev_ctx(priv->sh);
1704         if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1705                 unsigned int c = 0;
1706                 uint16_t port_id;
1707
1708                 MLX5_ETH_FOREACH_DEV(port_id, dev->device) {
1709                         struct mlx5_priv *opriv =
1710                                 rte_eth_devices[port_id].data->dev_private;
1711
1712                         if (!opriv ||
1713                             opriv->domain_id != priv->domain_id ||
1714                             &rte_eth_devices[port_id] == dev)
1715                                 continue;
1716                         ++c;
1717                         break;
1718                 }
1719                 if (!c)
1720                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1721         }
1722         memset(priv, 0, sizeof(*priv));
1723         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1724         /*
1725          * Reset mac_addrs to NULL such that it is not freed as part of
1726          * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1727          * it is freed when dev_private is freed.
1728          */
1729         dev->data->mac_addrs = NULL;
1730         return 0;
1731 }
1732
1733 const struct eth_dev_ops mlx5_dev_ops = {
1734         .dev_configure = mlx5_dev_configure,
1735         .dev_start = mlx5_dev_start,
1736         .dev_stop = mlx5_dev_stop,
1737         .dev_set_link_down = mlx5_set_link_down,
1738         .dev_set_link_up = mlx5_set_link_up,
1739         .dev_close = mlx5_dev_close,
1740         .promiscuous_enable = mlx5_promiscuous_enable,
1741         .promiscuous_disable = mlx5_promiscuous_disable,
1742         .allmulticast_enable = mlx5_allmulticast_enable,
1743         .allmulticast_disable = mlx5_allmulticast_disable,
1744         .link_update = mlx5_link_update,
1745         .stats_get = mlx5_stats_get,
1746         .stats_reset = mlx5_stats_reset,
1747         .xstats_get = mlx5_xstats_get,
1748         .xstats_reset = mlx5_xstats_reset,
1749         .xstats_get_names = mlx5_xstats_get_names,
1750         .fw_version_get = mlx5_fw_version_get,
1751         .dev_infos_get = mlx5_dev_infos_get,
1752         .representor_info_get = mlx5_representor_info_get,
1753         .read_clock = mlx5_txpp_read_clock,
1754         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1755         .vlan_filter_set = mlx5_vlan_filter_set,
1756         .rx_queue_setup = mlx5_rx_queue_setup,
1757         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1758         .tx_queue_setup = mlx5_tx_queue_setup,
1759         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1760         .rx_queue_release = mlx5_rx_queue_release,
1761         .tx_queue_release = mlx5_tx_queue_release,
1762         .rx_queue_start = mlx5_rx_queue_start,
1763         .rx_queue_stop = mlx5_rx_queue_stop,
1764         .tx_queue_start = mlx5_tx_queue_start,
1765         .tx_queue_stop = mlx5_tx_queue_stop,
1766         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1767         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1768         .mac_addr_remove = mlx5_mac_addr_remove,
1769         .mac_addr_add = mlx5_mac_addr_add,
1770         .mac_addr_set = mlx5_mac_addr_set,
1771         .set_mc_addr_list = mlx5_set_mc_addr_list,
1772         .mtu_set = mlx5_dev_set_mtu,
1773         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1774         .vlan_offload_set = mlx5_vlan_offload_set,
1775         .reta_update = mlx5_dev_rss_reta_update,
1776         .reta_query = mlx5_dev_rss_reta_query,
1777         .rss_hash_update = mlx5_rss_hash_update,
1778         .rss_hash_conf_get = mlx5_rss_hash_conf_get,
1779         .flow_ops_get = mlx5_flow_ops_get,
1780         .rxq_info_get = mlx5_rxq_info_get,
1781         .txq_info_get = mlx5_txq_info_get,
1782         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1783         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1784         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1785         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1786         .is_removed = mlx5_is_removed,
1787         .udp_tunnel_port_add  = mlx5_udp_tunnel_port_add,
1788         .get_module_info = mlx5_get_module_info,
1789         .get_module_eeprom = mlx5_get_module_eeprom,
1790         .hairpin_cap_get = mlx5_hairpin_cap_get,
1791         .mtr_ops_get = mlx5_flow_meter_ops_get,
1792         .hairpin_bind = mlx5_hairpin_bind,
1793         .hairpin_unbind = mlx5_hairpin_unbind,
1794         .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1795         .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1796         .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1797         .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1798         .get_monitor_addr = mlx5_get_monitor_addr,
1799 };
1800
1801 /* Available operations from secondary process. */
1802 const struct eth_dev_ops mlx5_dev_sec_ops = {
1803         .stats_get = mlx5_stats_get,
1804         .stats_reset = mlx5_stats_reset,
1805         .xstats_get = mlx5_xstats_get,
1806         .xstats_reset = mlx5_xstats_reset,
1807         .xstats_get_names = mlx5_xstats_get_names,
1808         .fw_version_get = mlx5_fw_version_get,
1809         .dev_infos_get = mlx5_dev_infos_get,
1810         .representor_info_get = mlx5_representor_info_get,
1811         .read_clock = mlx5_txpp_read_clock,
1812         .rx_queue_start = mlx5_rx_queue_start,
1813         .rx_queue_stop = mlx5_rx_queue_stop,
1814         .tx_queue_start = mlx5_tx_queue_start,
1815         .tx_queue_stop = mlx5_tx_queue_stop,
1816         .rxq_info_get = mlx5_rxq_info_get,
1817         .txq_info_get = mlx5_txq_info_get,
1818         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1819         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1820         .get_module_info = mlx5_get_module_info,
1821         .get_module_eeprom = mlx5_get_module_eeprom,
1822 };
1823
1824 /* Available operations in flow isolated mode. */
1825 const struct eth_dev_ops mlx5_dev_ops_isolate = {
1826         .dev_configure = mlx5_dev_configure,
1827         .dev_start = mlx5_dev_start,
1828         .dev_stop = mlx5_dev_stop,
1829         .dev_set_link_down = mlx5_set_link_down,
1830         .dev_set_link_up = mlx5_set_link_up,
1831         .dev_close = mlx5_dev_close,
1832         .promiscuous_enable = mlx5_promiscuous_enable,
1833         .promiscuous_disable = mlx5_promiscuous_disable,
1834         .allmulticast_enable = mlx5_allmulticast_enable,
1835         .allmulticast_disable = mlx5_allmulticast_disable,
1836         .link_update = mlx5_link_update,
1837         .stats_get = mlx5_stats_get,
1838         .stats_reset = mlx5_stats_reset,
1839         .xstats_get = mlx5_xstats_get,
1840         .xstats_reset = mlx5_xstats_reset,
1841         .xstats_get_names = mlx5_xstats_get_names,
1842         .fw_version_get = mlx5_fw_version_get,
1843         .dev_infos_get = mlx5_dev_infos_get,
1844         .representor_info_get = mlx5_representor_info_get,
1845         .read_clock = mlx5_txpp_read_clock,
1846         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1847         .vlan_filter_set = mlx5_vlan_filter_set,
1848         .rx_queue_setup = mlx5_rx_queue_setup,
1849         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1850         .tx_queue_setup = mlx5_tx_queue_setup,
1851         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1852         .rx_queue_release = mlx5_rx_queue_release,
1853         .tx_queue_release = mlx5_tx_queue_release,
1854         .rx_queue_start = mlx5_rx_queue_start,
1855         .rx_queue_stop = mlx5_rx_queue_stop,
1856         .tx_queue_start = mlx5_tx_queue_start,
1857         .tx_queue_stop = mlx5_tx_queue_stop,
1858         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1859         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1860         .mac_addr_remove = mlx5_mac_addr_remove,
1861         .mac_addr_add = mlx5_mac_addr_add,
1862         .mac_addr_set = mlx5_mac_addr_set,
1863         .set_mc_addr_list = mlx5_set_mc_addr_list,
1864         .mtu_set = mlx5_dev_set_mtu,
1865         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1866         .vlan_offload_set = mlx5_vlan_offload_set,
1867         .flow_ops_get = mlx5_flow_ops_get,
1868         .rxq_info_get = mlx5_rxq_info_get,
1869         .txq_info_get = mlx5_txq_info_get,
1870         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1871         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1872         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1873         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1874         .is_removed = mlx5_is_removed,
1875         .get_module_info = mlx5_get_module_info,
1876         .get_module_eeprom = mlx5_get_module_eeprom,
1877         .hairpin_cap_get = mlx5_hairpin_cap_get,
1878         .mtr_ops_get = mlx5_flow_meter_ops_get,
1879         .hairpin_bind = mlx5_hairpin_bind,
1880         .hairpin_unbind = mlx5_hairpin_unbind,
1881         .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1882         .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1883         .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1884         .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1885         .get_monitor_addr = mlx5_get_monitor_addr,
1886 };
1887
1888 /**
1889  * Verify and store value for device argument.
1890  *
1891  * @param[in] key
1892  *   Key argument to verify.
1893  * @param[in] val
1894  *   Value associated with key.
1895  * @param opaque
1896  *   User data.
1897  *
1898  * @return
1899  *   0 on success, a negative errno value otherwise and rte_errno is set.
1900  */
1901 static int
1902 mlx5_args_check(const char *key, const char *val, void *opaque)
1903 {
1904         struct mlx5_dev_config *config = opaque;
1905         unsigned long mod;
1906         signed long tmp;
1907
1908         /* No-op, port representors are processed in mlx5_dev_spawn(). */
1909         if (!strcmp(MLX5_DRIVER_KEY, key) || !strcmp(MLX5_REPRESENTOR, key) ||
1910             !strcmp(MLX5_SYS_MEM_EN, key) || !strcmp(MLX5_TX_DB_NC, key) ||
1911             !strcmp(MLX5_MR_MEMPOOL_REG_EN, key) ||
1912             !strcmp(MLX5_MR_EXT_MEMSEG_EN, key))
1913                 return 0;
1914         errno = 0;
1915         tmp = strtol(val, NULL, 0);
1916         if (errno) {
1917                 rte_errno = errno;
1918                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1919                 return -rte_errno;
1920         }
1921         if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
1922                 /* Negative values are acceptable for some keys only. */
1923                 rte_errno = EINVAL;
1924                 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
1925                 return -rte_errno;
1926         }
1927         mod = tmp >= 0 ? tmp : -tmp;
1928         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1929                 if (tmp > MLX5_CQE_RESP_FORMAT_L34H_STRIDX) {
1930                         DRV_LOG(ERR, "invalid CQE compression "
1931                                      "format parameter");
1932                         rte_errno = EINVAL;
1933                         return -rte_errno;
1934                 }
1935                 config->cqe_comp = !!tmp;
1936                 config->cqe_comp_fmt = tmp;
1937         } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1938                 config->hw_padding = !!tmp;
1939         } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1940                 config->mprq.enabled = !!tmp;
1941         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1942                 config->mprq.stride_num_n = tmp;
1943         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1944                 config->mprq.stride_size_n = tmp;
1945         } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1946                 config->mprq.max_memcpy_len = tmp;
1947         } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1948                 config->mprq.min_rxqs_num = tmp;
1949         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1950                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1951                                  " converted to txq_inline_max", key);
1952                 config->txq_inline_max = tmp;
1953         } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1954                 config->txq_inline_max = tmp;
1955         } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1956                 config->txq_inline_min = tmp;
1957         } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1958                 config->txq_inline_mpw = tmp;
1959         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1960                 config->txqs_inline = tmp;
1961         } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1962                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1963         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1964                 config->mps = !!tmp;
1965         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1966                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1967         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1968                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1969                                  " converted to txq_inline_mpw", key);
1970                 config->txq_inline_mpw = tmp;
1971         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1972                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1973         } else if (strcmp(MLX5_TX_PP, key) == 0) {
1974                 if (!mod) {
1975                         DRV_LOG(ERR, "Zero Tx packet pacing parameter");
1976                         rte_errno = EINVAL;
1977                         return -rte_errno;
1978                 }
1979                 config->tx_pp = tmp;
1980         } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
1981                 config->tx_skew = tmp;
1982         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1983                 config->rx_vec_en = !!tmp;
1984         } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1985                 config->l3_vxlan_en = !!tmp;
1986         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1987                 config->vf_nl_en = !!tmp;
1988         } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1989                 config->dv_esw_en = !!tmp;
1990         } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1991                 config->dv_flow_en = !!tmp;
1992         } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1993                 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1994                     tmp != MLX5_XMETA_MODE_META16 &&
1995                     tmp != MLX5_XMETA_MODE_META32 &&
1996                     tmp != MLX5_XMETA_MODE_MISS_INFO) {
1997                         DRV_LOG(ERR, "invalid extensive "
1998                                      "metadata parameter");
1999                         rte_errno = EINVAL;
2000                         return -rte_errno;
2001                 }
2002                 if (tmp != MLX5_XMETA_MODE_MISS_INFO)
2003                         config->dv_xmeta_en = tmp;
2004                 else
2005                         config->dv_miss_info = 1;
2006         } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
2007                 config->lacp_by_user = !!tmp;
2008         } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
2009                 config->max_dump_files_num = tmp;
2010         } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
2011                 config->lro.timeout = tmp;
2012         } else if (strcmp(RTE_DEVARGS_KEY_CLASS, key) == 0) {
2013                 DRV_LOG(DEBUG, "class argument is %s.", val);
2014         } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
2015                 config->log_hp_size = tmp;
2016         } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
2017                 if (tmp != MLX5_RCM_NONE &&
2018                     tmp != MLX5_RCM_LIGHT &&
2019                     tmp != MLX5_RCM_AGGR) {
2020                         DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
2021                         rte_errno = EINVAL;
2022                         return -rte_errno;
2023                 }
2024                 config->reclaim_mode = tmp;
2025         } else if (strcmp(MLX5_DECAP_EN, key) == 0) {
2026                 config->decap_en = !!tmp;
2027         } else if (strcmp(MLX5_ALLOW_DUPLICATE_PATTERN, key) == 0) {
2028                 config->allow_duplicate_pattern = !!tmp;
2029         } else {
2030                 DRV_LOG(WARNING, "%s: unknown parameter", key);
2031                 rte_errno = EINVAL;
2032                 return -rte_errno;
2033         }
2034         return 0;
2035 }
2036
2037 /**
2038  * Parse device parameters.
2039  *
2040  * @param config
2041  *   Pointer to device configuration structure.
2042  * @param devargs
2043  *   Device arguments structure.
2044  *
2045  * @return
2046  *   0 on success, a negative errno value otherwise and rte_errno is set.
2047  */
2048 int
2049 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
2050 {
2051         const char **params = (const char *[]){
2052                 MLX5_DRIVER_KEY,
2053                 MLX5_RXQ_CQE_COMP_EN,
2054                 MLX5_RXQ_PKT_PAD_EN,
2055                 MLX5_RX_MPRQ_EN,
2056                 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
2057                 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
2058                 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
2059                 MLX5_RXQS_MIN_MPRQ,
2060                 MLX5_TXQ_INLINE,
2061                 MLX5_TXQ_INLINE_MIN,
2062                 MLX5_TXQ_INLINE_MAX,
2063                 MLX5_TXQ_INLINE_MPW,
2064                 MLX5_TXQS_MIN_INLINE,
2065                 MLX5_TXQS_MAX_VEC,
2066                 MLX5_TXQ_MPW_EN,
2067                 MLX5_TXQ_MPW_HDR_DSEG_EN,
2068                 MLX5_TXQ_MAX_INLINE_LEN,
2069                 MLX5_TX_DB_NC,
2070                 MLX5_TX_PP,
2071                 MLX5_TX_SKEW,
2072                 MLX5_TX_VEC_EN,
2073                 MLX5_RX_VEC_EN,
2074                 MLX5_L3_VXLAN_EN,
2075                 MLX5_VF_NL_EN,
2076                 MLX5_DV_ESW_EN,
2077                 MLX5_DV_FLOW_EN,
2078                 MLX5_DV_XMETA_EN,
2079                 MLX5_LACP_BY_USER,
2080                 MLX5_MR_EXT_MEMSEG_EN,
2081                 MLX5_REPRESENTOR,
2082                 MLX5_MAX_DUMP_FILES_NUM,
2083                 MLX5_LRO_TIMEOUT_USEC,
2084                 RTE_DEVARGS_KEY_CLASS,
2085                 MLX5_HP_BUF_SIZE,
2086                 MLX5_RECLAIM_MEM,
2087                 MLX5_SYS_MEM_EN,
2088                 MLX5_DECAP_EN,
2089                 MLX5_ALLOW_DUPLICATE_PATTERN,
2090                 MLX5_MR_MEMPOOL_REG_EN,
2091                 NULL,
2092         };
2093         struct rte_kvargs *kvlist;
2094         int ret = 0;
2095         int i;
2096
2097         if (devargs == NULL)
2098                 return 0;
2099         /* Following UGLY cast is done to pass checkpatch. */
2100         kvlist = rte_kvargs_parse(devargs->args, params);
2101         if (kvlist == NULL) {
2102                 rte_errno = EINVAL;
2103                 return -rte_errno;
2104         }
2105         /* Process parameters. */
2106         for (i = 0; (params[i] != NULL); ++i) {
2107                 if (rte_kvargs_count(kvlist, params[i])) {
2108                         ret = rte_kvargs_process(kvlist, params[i],
2109                                                  mlx5_args_check, config);
2110                         if (ret) {
2111                                 rte_errno = EINVAL;
2112                                 rte_kvargs_free(kvlist);
2113                                 return -rte_errno;
2114                         }
2115                 }
2116         }
2117         rte_kvargs_free(kvlist);
2118         return 0;
2119 }
2120
2121 /**
2122  * Configures the minimal amount of data to inline into WQE
2123  * while sending packets.
2124  *
2125  * - the txq_inline_min has the maximal priority, if this
2126  *   key is specified in devargs
2127  * - if DevX is enabled the inline mode is queried from the
2128  *   device (HCA attributes and NIC vport context if needed).
2129  * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
2130  *   and none (0 bytes) for other NICs
2131  *
2132  * @param spawn
2133  *   Verbs device parameters (name, port, switch_info) to spawn.
2134  * @param config
2135  *   Device configuration parameters.
2136  */
2137 void
2138 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
2139                     struct mlx5_dev_config *config)
2140 {
2141         if (config->txq_inline_min != MLX5_ARG_UNSET) {
2142                 /* Application defines size of inlined data explicitly. */
2143                 if (spawn->pci_dev != NULL) {
2144                         switch (spawn->pci_dev->id.device_id) {
2145                         case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2146                         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2147                                 if (config->txq_inline_min <
2148                                                (int)MLX5_INLINE_HSIZE_L2) {
2149                                         DRV_LOG(DEBUG,
2150                                                 "txq_inline_mix aligned to minimal ConnectX-4 required value %d",
2151                                                 (int)MLX5_INLINE_HSIZE_L2);
2152                                         config->txq_inline_min =
2153                                                         MLX5_INLINE_HSIZE_L2;
2154                                 }
2155                                 break;
2156                         }
2157                 }
2158                 goto exit;
2159         }
2160         if (config->hca_attr.eth_net_offloads) {
2161                 /* We have DevX enabled, inline mode queried successfully. */
2162                 switch (config->hca_attr.wqe_inline_mode) {
2163                 case MLX5_CAP_INLINE_MODE_L2:
2164                         /* outer L2 header must be inlined. */
2165                         config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2166                         goto exit;
2167                 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
2168                         /* No inline data are required by NIC. */
2169                         config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2170                         config->hw_vlan_insert =
2171                                 config->hca_attr.wqe_vlan_insert;
2172                         DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
2173                         goto exit;
2174                 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
2175                         /* inline mode is defined by NIC vport context. */
2176                         if (!config->hca_attr.eth_virt)
2177                                 break;
2178                         switch (config->hca_attr.vport_inline_mode) {
2179                         case MLX5_INLINE_MODE_NONE:
2180                                 config->txq_inline_min =
2181                                         MLX5_INLINE_HSIZE_NONE;
2182                                 goto exit;
2183                         case MLX5_INLINE_MODE_L2:
2184                                 config->txq_inline_min =
2185                                         MLX5_INLINE_HSIZE_L2;
2186                                 goto exit;
2187                         case MLX5_INLINE_MODE_IP:
2188                                 config->txq_inline_min =
2189                                         MLX5_INLINE_HSIZE_L3;
2190                                 goto exit;
2191                         case MLX5_INLINE_MODE_TCP_UDP:
2192                                 config->txq_inline_min =
2193                                         MLX5_INLINE_HSIZE_L4;
2194                                 goto exit;
2195                         case MLX5_INLINE_MODE_INNER_L2:
2196                                 config->txq_inline_min =
2197                                         MLX5_INLINE_HSIZE_INNER_L2;
2198                                 goto exit;
2199                         case MLX5_INLINE_MODE_INNER_IP:
2200                                 config->txq_inline_min =
2201                                         MLX5_INLINE_HSIZE_INNER_L3;
2202                                 goto exit;
2203                         case MLX5_INLINE_MODE_INNER_TCP_UDP:
2204                                 config->txq_inline_min =
2205                                         MLX5_INLINE_HSIZE_INNER_L4;
2206                                 goto exit;
2207                         }
2208                 }
2209         }
2210         if (spawn->pci_dev == NULL) {
2211                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2212                 goto exit;
2213         }
2214         /*
2215          * We get here if we are unable to deduce
2216          * inline data size with DevX. Try PCI ID
2217          * to determine old NICs.
2218          */
2219         switch (spawn->pci_dev->id.device_id) {
2220         case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2221         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2222         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
2223         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
2224                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2225                 config->hw_vlan_insert = 0;
2226                 break;
2227         case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
2228         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
2229         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
2230         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
2231                 /*
2232                  * These NICs support VLAN insertion from WQE and
2233                  * report the wqe_vlan_insert flag. But there is the bug
2234                  * and PFC control may be broken, so disable feature.
2235                  */
2236                 config->hw_vlan_insert = 0;
2237                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2238                 break;
2239         default:
2240                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2241                 break;
2242         }
2243 exit:
2244         DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
2245 }
2246
2247 /**
2248  * Configures the metadata mask fields in the shared context.
2249  *
2250  * @param [in] dev
2251  *   Pointer to Ethernet device.
2252  */
2253 void
2254 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
2255 {
2256         struct mlx5_priv *priv = dev->data->dev_private;
2257         struct mlx5_dev_ctx_shared *sh = priv->sh;
2258         uint32_t meta, mark, reg_c0;
2259
2260         reg_c0 = ~priv->vport_meta_mask;
2261         switch (priv->config.dv_xmeta_en) {
2262         case MLX5_XMETA_MODE_LEGACY:
2263                 meta = UINT32_MAX;
2264                 mark = MLX5_FLOW_MARK_MASK;
2265                 break;
2266         case MLX5_XMETA_MODE_META16:
2267                 meta = reg_c0 >> rte_bsf32(reg_c0);
2268                 mark = MLX5_FLOW_MARK_MASK;
2269                 break;
2270         case MLX5_XMETA_MODE_META32:
2271                 meta = UINT32_MAX;
2272                 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
2273                 break;
2274         default:
2275                 meta = 0;
2276                 mark = 0;
2277                 MLX5_ASSERT(false);
2278                 break;
2279         }
2280         if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
2281                 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
2282                                  sh->dv_mark_mask, mark);
2283         else
2284                 sh->dv_mark_mask = mark;
2285         if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
2286                 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
2287                                  sh->dv_meta_mask, meta);
2288         else
2289                 sh->dv_meta_mask = meta;
2290         if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
2291                 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
2292                                  sh->dv_meta_mask, reg_c0);
2293         else
2294                 sh->dv_regc0_mask = reg_c0;
2295         DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
2296         DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
2297         DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
2298         DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
2299 }
2300
2301 int
2302 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
2303 {
2304         static const char *const dynf_names[] = {
2305                 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
2306                 RTE_MBUF_DYNFLAG_METADATA_NAME,
2307                 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
2308         };
2309         unsigned int i;
2310
2311         if (n < RTE_DIM(dynf_names))
2312                 return -ENOMEM;
2313         for (i = 0; i < RTE_DIM(dynf_names); i++) {
2314                 if (names[i] == NULL)
2315                         return -EINVAL;
2316                 strcpy(names[i], dynf_names[i]);
2317         }
2318         return RTE_DIM(dynf_names);
2319 }
2320
2321 /**
2322  * Comparison callback to sort device data.
2323  *
2324  * This is meant to be used with qsort().
2325  *
2326  * @param a[in]
2327  *   Pointer to pointer to first data object.
2328  * @param b[in]
2329  *   Pointer to pointer to second data object.
2330  *
2331  * @return
2332  *   0 if both objects are equal, less than 0 if the first argument is less
2333  *   than the second, greater than 0 otherwise.
2334  */
2335 int
2336 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
2337                               struct mlx5_dev_config *config,
2338                               struct rte_device *dpdk_dev)
2339 {
2340         struct mlx5_dev_ctx_shared *sh = priv->sh;
2341         struct mlx5_dev_config *sh_conf = NULL;
2342         uint16_t port_id;
2343
2344         MLX5_ASSERT(sh);
2345         /* Nothing to compare for the single/first device. */
2346         if (sh->refcnt == 1)
2347                 return 0;
2348         /* Find the device with shared context. */
2349         MLX5_ETH_FOREACH_DEV(port_id, dpdk_dev) {
2350                 struct mlx5_priv *opriv =
2351                         rte_eth_devices[port_id].data->dev_private;
2352
2353                 if (opriv && opriv != priv && opriv->sh == sh) {
2354                         sh_conf = &opriv->config;
2355                         break;
2356                 }
2357         }
2358         if (!sh_conf)
2359                 return 0;
2360         if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
2361                 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
2362                              " for shared %s context", sh->ibdev_name);
2363                 rte_errno = EINVAL;
2364                 return rte_errno;
2365         }
2366         if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
2367                 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
2368                              " for shared %s context", sh->ibdev_name);
2369                 rte_errno = EINVAL;
2370                 return rte_errno;
2371         }
2372         return 0;
2373 }
2374
2375 /**
2376  * Look for the ethernet device belonging to mlx5 driver.
2377  *
2378  * @param[in] port_id
2379  *   port_id to start looking for device.
2380  * @param[in] odev
2381  *   Pointer to the hint device. When device is being probed
2382  *   the its siblings (master and preceding representors might
2383  *   not have assigned driver yet (because the mlx5_os_pci_probe()
2384  *   is not completed yet, for this case match on hint
2385  *   device may be used to detect sibling device.
2386  *
2387  * @return
2388  *   port_id of found device, RTE_MAX_ETHPORT if not found.
2389  */
2390 uint16_t
2391 mlx5_eth_find_next(uint16_t port_id, struct rte_device *odev)
2392 {
2393         while (port_id < RTE_MAX_ETHPORTS) {
2394                 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
2395
2396                 if (dev->state != RTE_ETH_DEV_UNUSED &&
2397                     dev->device &&
2398                     (dev->device == odev ||
2399                      (dev->device->driver &&
2400                      dev->device->driver->name &&
2401                      ((strcmp(dev->device->driver->name,
2402                               MLX5_PCI_DRIVER_NAME) == 0) ||
2403                       (strcmp(dev->device->driver->name,
2404                               MLX5_AUXILIARY_DRIVER_NAME) == 0)))))
2405                         break;
2406                 port_id++;
2407         }
2408         if (port_id >= RTE_MAX_ETHPORTS)
2409                 return RTE_MAX_ETHPORTS;
2410         return port_id;
2411 }
2412
2413 /**
2414  * Callback to remove a device.
2415  *
2416  * This function removes all Ethernet devices belong to a given device.
2417  *
2418  * @param[in] cdev
2419  *   Pointer to the generic device.
2420  *
2421  * @return
2422  *   0 on success, the function cannot fail.
2423  */
2424 int
2425 mlx5_net_remove(struct mlx5_common_device *cdev)
2426 {
2427         uint16_t port_id;
2428         int ret = 0;
2429
2430         RTE_ETH_FOREACH_DEV_OF(port_id, cdev->dev) {
2431                 /*
2432                  * mlx5_dev_close() is not registered to secondary process,
2433                  * call the close function explicitly for secondary process.
2434                  */
2435                 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
2436                         ret |= mlx5_dev_close(&rte_eth_devices[port_id]);
2437                 else
2438                         ret |= rte_eth_dev_close(port_id);
2439         }
2440         return ret == 0 ? 0 : -EIO;
2441 }
2442
2443 static const struct rte_pci_id mlx5_pci_id_map[] = {
2444         {
2445                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2446                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
2447         },
2448         {
2449                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2450                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
2451         },
2452         {
2453                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2454                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
2455         },
2456         {
2457                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2458                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
2459         },
2460         {
2461                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2462                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
2463         },
2464         {
2465                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2466                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
2467         },
2468         {
2469                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2470                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
2471         },
2472         {
2473                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2474                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
2475         },
2476         {
2477                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2478                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
2479         },
2480         {
2481                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2482                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
2483         },
2484         {
2485                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2486                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
2487         },
2488         {
2489                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2490                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
2491         },
2492         {
2493                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2494                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
2495         },
2496         {
2497                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2498                                 PCI_DEVICE_ID_MELLANOX_CONNECTXVF)
2499         },
2500         {
2501                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2502                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
2503         },
2504         {
2505                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2506                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
2507         },
2508         {
2509                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2510                                 PCI_DEVICE_ID_MELLANOX_CONNECTX7)
2511         },
2512         {
2513                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2514                                 PCI_DEVICE_ID_MELLANOX_CONNECTX7BF)
2515         },
2516         {
2517                 .vendor_id = 0
2518         }
2519 };
2520
2521 static struct mlx5_class_driver mlx5_net_driver = {
2522         .drv_class = MLX5_CLASS_ETH,
2523         .name = RTE_STR(MLX5_ETH_DRIVER_NAME),
2524         .id_table = mlx5_pci_id_map,
2525         .probe = mlx5_os_net_probe,
2526         .remove = mlx5_net_remove,
2527         .probe_again = 1,
2528         .intr_lsc = 1,
2529         .intr_rmv = 1,
2530 };
2531
2532 /* Initialize driver log type. */
2533 RTE_LOG_REGISTER_DEFAULT(mlx5_logtype, NOTICE)
2534
2535 /**
2536  * Driver initialization routine.
2537  */
2538 RTE_INIT(rte_mlx5_pmd_init)
2539 {
2540         pthread_mutex_init(&mlx5_dev_ctx_list_mutex, NULL);
2541         mlx5_common_init();
2542         /* Build the static tables for Verbs conversion. */
2543         mlx5_set_ptype_table();
2544         mlx5_set_cksum_table();
2545         mlx5_set_swp_types_table();
2546         if (mlx5_glue)
2547                 mlx5_class_driver_register(&mlx5_net_driver);
2548 }
2549
2550 RTE_PMD_EXPORT_NAME(MLX5_ETH_DRIVER_NAME, __COUNTER__);
2551 RTE_PMD_REGISTER_PCI_TABLE(MLX5_ETH_DRIVER_NAME, mlx5_pci_id_map);
2552 RTE_PMD_REGISTER_KMOD_DEP(MLX5_ETH_DRIVER_NAME, "* ib_uverbs & mlx5_core & mlx5_ib");