1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox.
18 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
20 #pragma GCC diagnostic ignored "-Wpedantic"
22 #include <infiniband/verbs.h>
24 #pragma GCC diagnostic error "-Wpedantic"
27 #include <rte_malloc.h>
28 #include <rte_ethdev_driver.h>
29 #include <rte_ethdev_pci.h>
31 #include <rte_bus_pci.h>
32 #include <rte_common.h>
33 #include <rte_config.h>
34 #include <rte_eal_memconfig.h>
35 #include <rte_kvargs.h>
38 #include "mlx5_utils.h"
39 #include "mlx5_rxtx.h"
40 #include "mlx5_autoconf.h"
41 #include "mlx5_defs.h"
42 #include "mlx5_glue.h"
44 /* Device parameter to enable RX completion queue compression. */
45 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
47 /* Device parameter to configure inline send. */
48 #define MLX5_TXQ_INLINE "txq_inline"
51 * Device parameter to configure the number of TX queues threshold for
52 * enabling inline send.
54 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
56 /* Device parameter to enable multi-packet send WQEs. */
57 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
59 /* Device parameter to include 2 dsegs in the title WQEBB. */
60 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
62 /* Device parameter to limit the size of inlining packet. */
63 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
65 /* Device parameter to enable hardware Tx vector. */
66 #define MLX5_TX_VEC_EN "tx_vec_en"
68 /* Device parameter to enable hardware Rx vector. */
69 #define MLX5_RX_VEC_EN "rx_vec_en"
71 #ifndef HAVE_IBV_MLX5_MOD_MPW
72 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2)
73 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3)
76 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP
77 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4)
81 * Retrieve integer value from environment variable.
84 * Environment variable name.
87 * Integer value, 0 if the variable is not set.
90 mlx5_getenv_int(const char *name)
92 const char *val = getenv(name);
100 * Verbs callback to allocate a memory. This function should allocate the space
101 * according to the size provided residing inside a huge page.
102 * Please note that all allocation must respect the alignment from libmlx5
103 * (i.e. currently sysconf(_SC_PAGESIZE)).
106 * The size in bytes of the memory to allocate.
108 * A pointer to the callback data.
111 * Allocated buffer, NULL otherwise and rte_errno is set.
114 mlx5_alloc_verbs_buf(size_t size, void *data)
116 struct priv *priv = data;
118 size_t alignment = sysconf(_SC_PAGESIZE);
119 unsigned int socket = SOCKET_ID_ANY;
121 if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) {
122 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
124 socket = ctrl->socket;
125 } else if (priv->verbs_alloc_ctx.type ==
126 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) {
127 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
129 socket = ctrl->socket;
131 assert(data != NULL);
132 ret = rte_malloc_socket(__func__, size, alignment, socket);
135 DEBUG("Extern alloc size: %lu, align: %lu: %p", size, alignment, ret);
140 * Verbs callback to free a memory.
143 * A pointer to the memory to free.
145 * A pointer to the callback data.
148 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused)
150 assert(data != NULL);
151 DEBUG("Extern free request: %p", ptr);
156 * DPDK callback to close the device.
158 * Destroy all queues and objects, free memory.
161 * Pointer to Ethernet device structure.
164 mlx5_dev_close(struct rte_eth_dev *dev)
166 struct priv *priv = dev->data->dev_private;
170 DEBUG("%p: closing device \"%s\"",
172 ((priv->ctx != NULL) ? priv->ctx->device->name : ""));
173 /* In case mlx5_dev_stop() has not been called. */
174 mlx5_dev_interrupt_handler_uninstall(dev);
175 mlx5_traffic_disable(dev);
176 /* Prevent crashes when queues are still in use. */
177 dev->rx_pkt_burst = removed_rx_burst;
178 dev->tx_pkt_burst = removed_tx_burst;
179 if (priv->rxqs != NULL) {
180 /* XXX race condition if mlx5_rx_burst() is still running. */
182 for (i = 0; (i != priv->rxqs_n); ++i)
183 mlx5_rxq_release(dev, i);
187 if (priv->txqs != NULL) {
188 /* XXX race condition if mlx5_tx_burst() is still running. */
190 for (i = 0; (i != priv->txqs_n); ++i)
191 mlx5_txq_release(dev, i);
195 if (priv->pd != NULL) {
196 assert(priv->ctx != NULL);
197 claim_zero(mlx5_glue->dealloc_pd(priv->pd));
198 claim_zero(mlx5_glue->close_device(priv->ctx));
200 assert(priv->ctx == NULL);
201 if (priv->rss_conf.rss_key != NULL)
202 rte_free(priv->rss_conf.rss_key);
203 if (priv->reta_idx != NULL)
204 rte_free(priv->reta_idx);
205 if (priv->primary_socket)
206 mlx5_socket_uninit(dev);
207 ret = mlx5_hrxq_ibv_verify(dev);
209 WARN("%p: some Hash Rx queue still remain", (void *)dev);
210 ret = mlx5_ind_table_ibv_verify(dev);
212 WARN("%p: some Indirection table still remain", (void *)dev);
213 ret = mlx5_rxq_ibv_verify(dev);
215 WARN("%p: some Verbs Rx queue still remain", (void *)dev);
216 ret = mlx5_rxq_verify(dev);
218 WARN("%p: some Rx Queues still remain", (void *)dev);
219 ret = mlx5_txq_ibv_verify(dev);
221 WARN("%p: some Verbs Tx queue still remain", (void *)dev);
222 ret = mlx5_txq_verify(dev);
224 WARN("%p: some Tx Queues still remain", (void *)dev);
225 ret = mlx5_flow_verify(dev);
227 WARN("%p: some flows still remain", (void *)dev);
228 ret = mlx5_mr_verify(dev);
230 WARN("%p: some Memory Region still remain", (void *)dev);
231 memset(priv, 0, sizeof(*priv));
234 const struct eth_dev_ops mlx5_dev_ops = {
235 .dev_configure = mlx5_dev_configure,
236 .dev_start = mlx5_dev_start,
237 .dev_stop = mlx5_dev_stop,
238 .dev_set_link_down = mlx5_set_link_down,
239 .dev_set_link_up = mlx5_set_link_up,
240 .dev_close = mlx5_dev_close,
241 .promiscuous_enable = mlx5_promiscuous_enable,
242 .promiscuous_disable = mlx5_promiscuous_disable,
243 .allmulticast_enable = mlx5_allmulticast_enable,
244 .allmulticast_disable = mlx5_allmulticast_disable,
245 .link_update = mlx5_link_update,
246 .stats_get = mlx5_stats_get,
247 .stats_reset = mlx5_stats_reset,
248 .xstats_get = mlx5_xstats_get,
249 .xstats_reset = mlx5_xstats_reset,
250 .xstats_get_names = mlx5_xstats_get_names,
251 .dev_infos_get = mlx5_dev_infos_get,
252 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
253 .vlan_filter_set = mlx5_vlan_filter_set,
254 .rx_queue_setup = mlx5_rx_queue_setup,
255 .tx_queue_setup = mlx5_tx_queue_setup,
256 .rx_queue_release = mlx5_rx_queue_release,
257 .tx_queue_release = mlx5_tx_queue_release,
258 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
259 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
260 .mac_addr_remove = mlx5_mac_addr_remove,
261 .mac_addr_add = mlx5_mac_addr_add,
262 .mac_addr_set = mlx5_mac_addr_set,
263 .mtu_set = mlx5_dev_set_mtu,
264 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
265 .vlan_offload_set = mlx5_vlan_offload_set,
266 .reta_update = mlx5_dev_rss_reta_update,
267 .reta_query = mlx5_dev_rss_reta_query,
268 .rss_hash_update = mlx5_rss_hash_update,
269 .rss_hash_conf_get = mlx5_rss_hash_conf_get,
270 .filter_ctrl = mlx5_dev_filter_ctrl,
271 .rx_descriptor_status = mlx5_rx_descriptor_status,
272 .tx_descriptor_status = mlx5_tx_descriptor_status,
273 .rx_queue_intr_enable = mlx5_rx_intr_enable,
274 .rx_queue_intr_disable = mlx5_rx_intr_disable,
275 .is_removed = mlx5_is_removed,
278 static const struct eth_dev_ops mlx5_dev_sec_ops = {
279 .stats_get = mlx5_stats_get,
280 .stats_reset = mlx5_stats_reset,
281 .xstats_get = mlx5_xstats_get,
282 .xstats_reset = mlx5_xstats_reset,
283 .xstats_get_names = mlx5_xstats_get_names,
284 .dev_infos_get = mlx5_dev_infos_get,
285 .rx_descriptor_status = mlx5_rx_descriptor_status,
286 .tx_descriptor_status = mlx5_tx_descriptor_status,
289 /* Available operators in flow isolated mode. */
290 const struct eth_dev_ops mlx5_dev_ops_isolate = {
291 .dev_configure = mlx5_dev_configure,
292 .dev_start = mlx5_dev_start,
293 .dev_stop = mlx5_dev_stop,
294 .dev_set_link_down = mlx5_set_link_down,
295 .dev_set_link_up = mlx5_set_link_up,
296 .dev_close = mlx5_dev_close,
297 .link_update = mlx5_link_update,
298 .stats_get = mlx5_stats_get,
299 .stats_reset = mlx5_stats_reset,
300 .xstats_get = mlx5_xstats_get,
301 .xstats_reset = mlx5_xstats_reset,
302 .xstats_get_names = mlx5_xstats_get_names,
303 .dev_infos_get = mlx5_dev_infos_get,
304 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
305 .vlan_filter_set = mlx5_vlan_filter_set,
306 .rx_queue_setup = mlx5_rx_queue_setup,
307 .tx_queue_setup = mlx5_tx_queue_setup,
308 .rx_queue_release = mlx5_rx_queue_release,
309 .tx_queue_release = mlx5_tx_queue_release,
310 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
311 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
312 .mac_addr_remove = mlx5_mac_addr_remove,
313 .mac_addr_add = mlx5_mac_addr_add,
314 .mac_addr_set = mlx5_mac_addr_set,
315 .mtu_set = mlx5_dev_set_mtu,
316 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
317 .vlan_offload_set = mlx5_vlan_offload_set,
318 .filter_ctrl = mlx5_dev_filter_ctrl,
319 .rx_descriptor_status = mlx5_rx_descriptor_status,
320 .tx_descriptor_status = mlx5_tx_descriptor_status,
321 .rx_queue_intr_enable = mlx5_rx_intr_enable,
322 .rx_queue_intr_disable = mlx5_rx_intr_disable,
323 .is_removed = mlx5_is_removed,
327 struct rte_pci_addr pci_addr; /* associated PCI address */
328 uint32_t ports; /* physical ports bitfield. */
332 * Get device index in mlx5_dev[] from PCI bus address.
334 * @param[in] pci_addr
335 * PCI bus address to look for.
338 * mlx5_dev[] index on success, -1 on failure.
341 mlx5_dev_idx(struct rte_pci_addr *pci_addr)
346 assert(pci_addr != NULL);
347 for (i = 0; (i != RTE_DIM(mlx5_dev)); ++i) {
348 if ((mlx5_dev[i].pci_addr.domain == pci_addr->domain) &&
349 (mlx5_dev[i].pci_addr.bus == pci_addr->bus) &&
350 (mlx5_dev[i].pci_addr.devid == pci_addr->devid) &&
351 (mlx5_dev[i].pci_addr.function == pci_addr->function))
353 if ((mlx5_dev[i].ports == 0) && (ret == -1))
360 * Verify and store value for device argument.
363 * Key argument to verify.
365 * Value associated with key.
370 * 0 on success, a negative errno value otherwise and rte_errno is set.
373 mlx5_args_check(const char *key, const char *val, void *opaque)
375 struct mlx5_dev_config *config = opaque;
379 tmp = strtoul(val, NULL, 0);
382 WARN("%s: \"%s\" is not a valid integer", key, val);
385 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
386 config->cqe_comp = !!tmp;
387 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
388 config->txq_inline = tmp;
389 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
390 config->txqs_inline = tmp;
391 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
392 config->mps = !!tmp ? config->mps : 0;
393 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
394 config->mpw_hdr_dseg = !!tmp;
395 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
396 config->inline_max_packet_sz = tmp;
397 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
398 config->tx_vec_en = !!tmp;
399 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
400 config->rx_vec_en = !!tmp;
402 WARN("%s: unknown parameter", key);
410 * Parse device parameters.
413 * Pointer to device configuration structure.
415 * Device arguments structure.
418 * 0 on success, a negative errno value otherwise and rte_errno is set.
421 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
423 const char **params = (const char *[]){
424 MLX5_RXQ_CQE_COMP_EN,
426 MLX5_TXQS_MIN_INLINE,
428 MLX5_TXQ_MPW_HDR_DSEG_EN,
429 MLX5_TXQ_MAX_INLINE_LEN,
434 struct rte_kvargs *kvlist;
440 /* Following UGLY cast is done to pass checkpatch. */
441 kvlist = rte_kvargs_parse(devargs->args, params);
444 /* Process parameters. */
445 for (i = 0; (params[i] != NULL); ++i) {
446 if (rte_kvargs_count(kvlist, params[i])) {
447 ret = rte_kvargs_process(kvlist, params[i],
448 mlx5_args_check, config);
451 rte_kvargs_free(kvlist);
456 rte_kvargs_free(kvlist);
460 static struct rte_pci_driver mlx5_driver;
463 * Reserved UAR address space for TXQ UAR(hw doorbell) mapping, process
464 * local resource used by both primary and secondary to avoid duplicate
466 * The space has to be available on both primary and secondary process,
467 * TXQ UAR maps to this area using fixed mmap w/o double check.
469 static void *uar_base;
472 * Reserve UAR address space for primary process.
475 * Pointer to Ethernet device.
478 * 0 on success, a negative errno value otherwise and rte_errno is set.
481 mlx5_uar_init_primary(struct rte_eth_dev *dev)
483 struct priv *priv = dev->data->dev_private;
484 void *addr = (void *)0;
486 const struct rte_mem_config *mcfg;
488 if (uar_base) { /* UAR address space mapped. */
489 priv->uar_base = uar_base;
492 /* find out lower bound of hugepage segments */
493 mcfg = rte_eal_get_configuration()->mem_config;
494 for (i = 0; i < RTE_MAX_MEMSEG && mcfg->memseg[i].addr; i++) {
496 addr = RTE_MIN(addr, mcfg->memseg[i].addr);
498 addr = mcfg->memseg[i].addr;
500 /* keep distance to hugepages to minimize potential conflicts. */
501 addr = RTE_PTR_SUB(addr, MLX5_UAR_OFFSET + MLX5_UAR_SIZE);
502 /* anonymous mmap, no real memory consumption. */
503 addr = mmap(addr, MLX5_UAR_SIZE,
504 PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
505 if (addr == MAP_FAILED) {
506 ERROR("Failed to reserve UAR address space, please adjust "
507 "MLX5_UAR_SIZE or try --base-virtaddr");
511 /* Accept either same addr or a new addr returned from mmap if target
514 INFO("Reserved UAR address space: %p", addr);
515 priv->uar_base = addr; /* for primary and secondary UAR re-mmap. */
516 uar_base = addr; /* process local, don't reserve again. */
521 * Reserve UAR address space for secondary process, align with
525 * Pointer to Ethernet device.
528 * 0 on success, a negative errno value otherwise and rte_errno is set.
531 mlx5_uar_init_secondary(struct rte_eth_dev *dev)
533 struct priv *priv = dev->data->dev_private;
536 assert(priv->uar_base);
537 if (uar_base) { /* already reserved. */
538 assert(uar_base == priv->uar_base);
541 /* anonymous mmap, no real memory consumption. */
542 addr = mmap(priv->uar_base, MLX5_UAR_SIZE,
543 PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
544 if (addr == MAP_FAILED) {
545 ERROR("UAR mmap failed: %p size: %llu",
546 priv->uar_base, MLX5_UAR_SIZE);
550 if (priv->uar_base != addr) {
551 ERROR("UAR address %p size %llu occupied, please adjust "
552 "MLX5_UAR_OFFSET or try EAL parameter --base-virtaddr",
553 priv->uar_base, MLX5_UAR_SIZE);
557 uar_base = addr; /* process local, don't reserve again */
558 INFO("Reserved UAR address space: %p", addr);
563 * DPDK callback to register a PCI device.
565 * This function creates an Ethernet device for each port of a given
569 * PCI driver structure (mlx5_driver).
571 * PCI device information.
574 * 0 on success, a negative errno value otherwise and rte_errno is set.
577 mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
578 struct rte_pci_device *pci_dev)
580 struct ibv_device **list = NULL;
581 struct ibv_device *ibv_dev;
583 struct ibv_context *attr_ctx = NULL;
584 struct ibv_device_attr_ex device_attr;
586 unsigned int cqe_comp;
587 unsigned int tunnel_en = 0;
590 struct mlx5dv_context attrs_out = {0};
591 #ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT
592 struct ibv_counter_set_description cs_desc;
595 assert(pci_drv == &mlx5_driver);
596 /* Get mlx5_dev[] index. */
597 idx = mlx5_dev_idx(&pci_dev->addr);
599 ERROR("this driver cannot support any more adapters");
603 DEBUG("using driver device index %d", idx);
604 /* Save PCI address. */
605 mlx5_dev[idx].pci_addr = pci_dev->addr;
606 list = mlx5_glue->get_device_list(&i);
611 ERROR("cannot list devices, is ib_uverbs loaded?");
616 * For each listed device, check related sysfs entry against
617 * the provided PCI ID.
620 struct rte_pci_addr pci_addr;
623 DEBUG("checking device \"%s\"", list[i]->name);
624 if (mlx5_ibv_device_to_pci_addr(list[i], &pci_addr))
626 if ((pci_dev->addr.domain != pci_addr.domain) ||
627 (pci_dev->addr.bus != pci_addr.bus) ||
628 (pci_dev->addr.devid != pci_addr.devid) ||
629 (pci_dev->addr.function != pci_addr.function))
631 INFO("PCI information matches, using device \"%s\"",
633 attr_ctx = mlx5_glue->open_device(list[i]);
638 if (attr_ctx == NULL) {
639 mlx5_glue->free_device_list(list);
642 ERROR("cannot access device, is mlx5_ib loaded?");
646 ERROR("cannot use device, are drivers up to date?");
651 DEBUG("device opened");
653 * Multi-packet send is supported by ConnectX-4 Lx PF as well
654 * as all ConnectX-5 devices.
656 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
657 attrs_out.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS;
659 mlx5_glue->dv_query_device(attr_ctx, &attrs_out);
660 if (attrs_out.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
661 if (attrs_out.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) {
662 DEBUG("Enhanced MPW is supported");
663 mps = MLX5_MPW_ENHANCED;
665 DEBUG("MPW is supported");
669 DEBUG("MPW isn't supported");
670 mps = MLX5_MPW_DISABLED;
672 if (RTE_CACHE_LINE_SIZE == 128 &&
673 !(attrs_out.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP))
677 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
678 if (attrs_out.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) {
679 tunnel_en = ((attrs_out.tunnel_offloads_caps &
680 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) &&
681 (attrs_out.tunnel_offloads_caps &
682 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE));
684 DEBUG("Tunnel offloading is %ssupported", tunnel_en ? "" : "not ");
686 WARN("Tunnel offloading disabled due to old OFED/rdma-core version");
688 if (mlx5_glue->query_device_ex(attr_ctx, NULL, &device_attr)) {
692 INFO("%u port(s) detected", device_attr.orig_attr.phys_port_cnt);
693 for (i = 0; i < device_attr.orig_attr.phys_port_cnt; i++) {
694 char name[RTE_ETH_NAME_MAX_LEN];
696 uint32_t port = i + 1; /* ports are indexed from one */
697 uint32_t test = (1 << i);
698 struct ibv_context *ctx = NULL;
699 struct ibv_port_attr port_attr;
700 struct ibv_pd *pd = NULL;
701 struct priv *priv = NULL;
702 struct rte_eth_dev *eth_dev = NULL;
703 struct ibv_device_attr_ex device_attr_ex;
704 struct ether_addr mac;
705 struct ibv_device_attr_ex device_attr;
706 struct mlx5_dev_config config = {
707 .cqe_comp = cqe_comp,
709 .tunnel_en = tunnel_en,
713 .txq_inline = MLX5_ARG_UNSET,
714 .txqs_inline = MLX5_ARG_UNSET,
715 .inline_max_packet_sz = MLX5_ARG_UNSET,
718 len = snprintf(name, sizeof(name), PCI_PRI_FMT,
719 pci_dev->addr.domain, pci_dev->addr.bus,
720 pci_dev->addr.devid, pci_dev->addr.function);
721 if (device_attr.orig_attr.phys_port_cnt > 1)
722 snprintf(name + len, sizeof(name), " port %u", i);
723 mlx5_dev[idx].ports |= test;
724 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
725 eth_dev = rte_eth_dev_attach_secondary(name);
726 if (eth_dev == NULL) {
727 ERROR("can not attach rte ethdev");
732 eth_dev->device = &pci_dev->device;
733 eth_dev->dev_ops = &mlx5_dev_sec_ops;
734 err = mlx5_uar_init_secondary(eth_dev);
737 /* Receive command fd from primary process */
738 err = mlx5_socket_connect(eth_dev);
741 /* Remap UAR for Tx queues. */
742 err = mlx5_tx_uar_remap(eth_dev, err);
746 * Ethdev pointer is still required as input since
747 * the primary device is not accessible from the
750 eth_dev->rx_pkt_burst =
751 mlx5_select_rx_function(eth_dev);
752 eth_dev->tx_pkt_burst =
753 mlx5_select_tx_function(eth_dev);
756 DEBUG("using port %u (%08" PRIx32 ")", port, test);
757 ctx = mlx5_glue->open_device(ibv_dev);
762 mlx5_glue->query_device_ex(ctx, NULL, &device_attr);
763 /* Check port status. */
764 err = mlx5_glue->query_port(ctx, port, &port_attr);
766 ERROR("port query failed: %s", strerror(err));
769 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
770 ERROR("port %d is not configured in Ethernet mode",
775 if (port_attr.state != IBV_PORT_ACTIVE)
776 DEBUG("port %d is not active: \"%s\" (%d)",
777 port, mlx5_glue->port_state_str(port_attr.state),
779 /* Allocate protection domain. */
780 pd = mlx5_glue->alloc_pd(ctx);
782 ERROR("PD allocation failure");
786 mlx5_dev[idx].ports |= test;
787 /* from rte_ethdev.c */
788 priv = rte_zmalloc("ethdev private structure",
790 RTE_CACHE_LINE_SIZE);
792 ERROR("priv allocation failure");
797 strncpy(priv->ibdev_path, priv->ctx->device->ibdev_path,
798 sizeof(priv->ibdev_path));
799 priv->device_attr = device_attr;
802 priv->mtu = ETHER_MTU;
803 err = mlx5_args(&config, pci_dev->device.devargs);
805 ERROR("failed to process device arguments: %s",
809 if (mlx5_glue->query_device_ex(ctx, NULL, &device_attr_ex)) {
810 ERROR("ibv_query_device_ex() failed");
814 config.hw_csum = !!(device_attr_ex.device_cap_flags_ex &
815 IBV_DEVICE_RAW_IP_CSUM);
816 DEBUG("checksum offloading is %ssupported",
817 (config.hw_csum ? "" : "not "));
818 #ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT
819 config.flow_counter_en = !!(device_attr.max_counter_sets);
820 mlx5_glue->describe_counter_set(ctx, 0, &cs_desc);
821 DEBUG("counter type = %d, num of cs = %ld, attributes = %d",
822 cs_desc.counter_type, cs_desc.num_of_cs,
825 config.ind_table_max_size =
826 device_attr_ex.rss_caps.max_rwq_indirection_table_size;
827 /* Remove this check once DPDK supports larger/variable
828 * indirection tables. */
829 if (config.ind_table_max_size >
830 (unsigned int)ETH_RSS_RETA_SIZE_512)
831 config.ind_table_max_size = ETH_RSS_RETA_SIZE_512;
832 DEBUG("maximum RX indirection table size is %u",
833 config.ind_table_max_size);
834 config.hw_vlan_strip = !!(device_attr_ex.raw_packet_caps &
835 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
836 DEBUG("VLAN stripping is %ssupported",
837 (config.hw_vlan_strip ? "" : "not "));
839 config.hw_fcs_strip = !!(device_attr_ex.raw_packet_caps &
840 IBV_RAW_PACKET_CAP_SCATTER_FCS);
841 DEBUG("FCS stripping configuration is %ssupported",
842 (config.hw_fcs_strip ? "" : "not "));
844 #ifdef HAVE_IBV_WQ_FLAG_RX_END_PADDING
845 config.hw_padding = !!device_attr_ex.rx_pad_end_addr_align;
847 DEBUG("hardware RX end alignment padding is %ssupported",
848 (config.hw_padding ? "" : "not "));
849 config.tso = ((device_attr_ex.tso_caps.max_tso > 0) &&
850 (device_attr_ex.tso_caps.supported_qpts &
851 (1 << IBV_QPT_RAW_PACKET)));
853 config.tso_max_payload_sz =
854 device_attr_ex.tso_caps.max_tso;
855 if (config.mps && !mps) {
856 ERROR("multi-packet send not supported on this device"
857 " (" MLX5_TXQ_MPW_EN ")");
862 config.mps == MLX5_MPW_ENHANCED ? "Enhanced " : "",
863 config.mps != MLX5_MPW_DISABLED ? "enabled" : "disabled");
864 if (config.cqe_comp && !cqe_comp) {
865 WARN("Rx CQE compression isn't supported");
868 eth_dev = rte_eth_dev_allocate(name);
869 if (eth_dev == NULL) {
870 ERROR("can not allocate rte ethdev");
874 eth_dev->data->dev_private = priv;
876 eth_dev->data->mac_addrs = priv->mac;
877 eth_dev->device = &pci_dev->device;
878 rte_eth_copy_pci_info(eth_dev, pci_dev);
879 eth_dev->device->driver = &mlx5_driver.driver;
880 err = mlx5_uar_init_primary(eth_dev);
883 /* Configure the first MAC address by default. */
884 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) {
885 ERROR("cannot get MAC address, is mlx5_en loaded?"
886 " (errno: %s)", strerror(errno));
890 INFO("port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x",
892 mac.addr_bytes[0], mac.addr_bytes[1],
893 mac.addr_bytes[2], mac.addr_bytes[3],
894 mac.addr_bytes[4], mac.addr_bytes[5]);
897 char ifname[IF_NAMESIZE];
899 if (mlx5_get_ifname(eth_dev, &ifname) == 0)
900 DEBUG("port %u ifname is \"%s\"",
903 DEBUG("port %u ifname is unknown", priv->port);
906 /* Get actual MTU if possible. */
907 err = mlx5_get_mtu(eth_dev, &priv->mtu);
910 DEBUG("port %u MTU is %u", priv->port, priv->mtu);
912 * Initialize burst functions to prevent crashes before link-up.
914 eth_dev->rx_pkt_burst = removed_rx_burst;
915 eth_dev->tx_pkt_burst = removed_tx_burst;
916 eth_dev->dev_ops = &mlx5_dev_ops;
917 /* Register MAC address. */
918 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
919 TAILQ_INIT(&priv->flows);
920 TAILQ_INIT(&priv->ctrl_flows);
921 /* Hint libmlx5 to use PMD allocator for data plane resources */
922 struct mlx5dv_ctx_allocators alctr = {
923 .alloc = &mlx5_alloc_verbs_buf,
924 .free = &mlx5_free_verbs_buf,
927 mlx5_glue->dv_set_context_attr(ctx,
928 MLX5DV_CTX_ATTR_BUF_ALLOCATORS,
929 (void *)((uintptr_t)&alctr));
930 /* Bring Ethernet device up. */
931 DEBUG("forcing Ethernet interface up");
932 mlx5_set_flags(eth_dev, ~IFF_UP, IFF_UP);
933 /* Store device configuration on private structure. */
934 priv->config = config;
940 claim_zero(mlx5_glue->dealloc_pd(pd));
942 claim_zero(mlx5_glue->close_device(ctx));
946 * XXX if something went wrong in the loop above, there is a resource
947 * leak (ctx, pd, priv, dpdk ethdev) but we can do nothing about it as
948 * long as the dpdk does not provide a way to deallocate a ethdev and a
949 * way to enumerate the registered ethdevs to free the previous ones.
951 /* no port found, complain */
952 if (!mlx5_dev[idx].ports) {
958 claim_zero(mlx5_glue->close_device(attr_ctx));
960 mlx5_glue->free_device_list(list);
968 static const struct rte_pci_id mlx5_pci_id_map[] = {
970 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
971 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
974 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
975 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
978 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
979 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
982 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
983 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
986 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
987 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
990 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
991 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
994 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
995 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
998 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
999 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
1006 static struct rte_pci_driver mlx5_driver = {
1008 .name = MLX5_DRIVER_NAME
1010 .id_table = mlx5_pci_id_map,
1011 .probe = mlx5_pci_probe,
1012 .drv_flags = RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV,
1015 #ifdef RTE_LIBRTE_MLX5_DLOPEN_DEPS
1018 * Suffix RTE_EAL_PMD_PATH with "-glue".
1020 * This function performs a sanity check on RTE_EAL_PMD_PATH before
1021 * suffixing its last component.
1024 * Output buffer, should be large enough otherwise NULL is returned.
1029 * Pointer to @p buf or @p NULL in case suffix cannot be appended.
1032 mlx5_glue_path(char *buf, size_t size)
1034 static const char *const bad[] = { "/", ".", "..", NULL };
1035 const char *path = RTE_EAL_PMD_PATH;
1036 size_t len = strlen(path);
1040 while (len && path[len - 1] == '/')
1042 for (off = len; off && path[off - 1] != '/'; --off)
1044 for (i = 0; bad[i]; ++i)
1045 if (!strncmp(path + off, bad[i], (int)(len - off)))
1047 i = snprintf(buf, size, "%.*s-glue", (int)len, path);
1048 if (i == -1 || (size_t)i >= size)
1052 ERROR("unable to append \"-glue\" to last component of"
1053 " RTE_EAL_PMD_PATH (\"" RTE_EAL_PMD_PATH "\"),"
1054 " please re-configure DPDK");
1059 * Initialization routine for run-time dependency on rdma-core.
1062 mlx5_glue_init(void)
1064 char glue_path[sizeof(RTE_EAL_PMD_PATH) - 1 + sizeof("-glue")];
1065 const char *path[] = {
1067 * A basic security check is necessary before trusting
1068 * MLX5_GLUE_PATH, which may override RTE_EAL_PMD_PATH.
1070 (geteuid() == getuid() && getegid() == getgid() ?
1071 getenv("MLX5_GLUE_PATH") : NULL),
1073 * When RTE_EAL_PMD_PATH is set, use its glue-suffixed
1074 * variant, otherwise let dlopen() look up libraries on its
1077 (*RTE_EAL_PMD_PATH ?
1078 mlx5_glue_path(glue_path, sizeof(glue_path)) : ""),
1081 void *handle = NULL;
1085 while (!handle && i != RTE_DIM(path)) {
1094 end = strpbrk(path[i], ":;");
1096 end = path[i] + strlen(path[i]);
1097 len = end - path[i];
1102 ret = snprintf(name, sizeof(name), "%.*s%s" MLX5_GLUE,
1104 (!len || *(end - 1) == '/') ? "" : "/");
1107 if (sizeof(name) != (size_t)ret + 1)
1109 DEBUG("looking for rdma-core glue as \"%s\"", name);
1110 handle = dlopen(name, RTLD_LAZY);
1121 WARN("cannot load glue library: %s", dlmsg);
1124 sym = dlsym(handle, "mlx5_glue");
1125 if (!sym || !*sym) {
1129 ERROR("cannot resolve glue symbol: %s", dlmsg);
1137 WARN("cannot initialize PMD due to missing run-time"
1138 " dependency on rdma-core libraries (libibverbs,"
1146 * Driver initialization routine.
1148 RTE_INIT(rte_mlx5_pmd_init);
1150 rte_mlx5_pmd_init(void)
1152 /* Build the static table for ptype conversion. */
1153 mlx5_set_ptype_table();
1155 * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use
1156 * huge pages. Calling ibv_fork_init() during init allows
1157 * applications to use fork() safely for purposes other than
1158 * using this PMD, which is not supported in forked processes.
1160 setenv("RDMAV_HUGEPAGES_SAFE", "1", 1);
1161 /* Match the size of Rx completion entry to the size of a cacheline. */
1162 if (RTE_CACHE_LINE_SIZE == 128)
1163 setenv("MLX5_CQE_SIZE", "128", 0);
1164 #ifdef RTE_LIBRTE_MLX5_DLOPEN_DEPS
1165 if (mlx5_glue_init())
1170 /* Glue structure must not contain any NULL pointers. */
1174 for (i = 0; i != sizeof(*mlx5_glue) / sizeof(void *); ++i)
1175 assert(((const void *const *)mlx5_glue)[i]);
1178 if (strcmp(mlx5_glue->version, MLX5_GLUE_VERSION)) {
1179 ERROR("rdma-core glue \"%s\" mismatch: \"%s\" is required",
1180 mlx5_glue->version, MLX5_GLUE_VERSION);
1183 mlx5_glue->fork_init();
1184 rte_pci_register(&mlx5_driver);
1187 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
1188 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
1189 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");