1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
13 #include <rte_malloc.h>
14 #include <rte_ethdev_driver.h>
15 #include <rte_ethdev_pci.h>
17 #include <rte_bus_pci.h>
18 #include <rte_common.h>
19 #include <rte_kvargs.h>
20 #include <rte_rwlock.h>
21 #include <rte_spinlock.h>
22 #include <rte_string_fns.h>
23 #include <rte_alarm.h>
25 #include <mlx5_glue.h>
26 #include <mlx5_devx_cmds.h>
27 #include <mlx5_common.h>
28 #include <mlx5_common_os.h>
29 #include <mlx5_common_mp.h>
30 #include <mlx5_common_pci.h>
31 #include <mlx5_malloc.h>
33 #include "mlx5_defs.h"
35 #include "mlx5_utils.h"
36 #include "mlx5_rxtx.h"
37 #include "mlx5_autoconf.h"
39 #include "mlx5_flow.h"
40 #include "rte_pmd_mlx5.h"
42 /* Device parameter to enable RX completion queue compression. */
43 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
45 /* Device parameter to enable RX completion entry padding to 128B. */
46 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
48 /* Device parameter to enable padding Rx packet to cacheline size. */
49 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
51 /* Device parameter to enable Multi-Packet Rx queue. */
52 #define MLX5_RX_MPRQ_EN "mprq_en"
54 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
55 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
57 /* Device parameter to configure log 2 of the stride size for MPRQ. */
58 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
60 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
61 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
63 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
64 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
66 /* Device parameter to configure inline send. Deprecated, ignored.*/
67 #define MLX5_TXQ_INLINE "txq_inline"
69 /* Device parameter to limit packet size to inline with ordinary SEND. */
70 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
72 /* Device parameter to configure minimal data size to inline. */
73 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
75 /* Device parameter to limit packet size to inline with Enhanced MPW. */
76 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
79 * Device parameter to configure the number of TX queues threshold for
80 * enabling inline send.
82 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
85 * Device parameter to configure the number of TX queues threshold for
86 * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
88 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
90 /* Device parameter to enable multi-packet send WQEs. */
91 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
94 * Device parameter to force doorbell register mapping
95 * to non-cahed region eliminating the extra write memory barrier.
97 #define MLX5_TX_DB_NC "tx_db_nc"
100 * Device parameter to include 2 dsegs in the title WQEBB.
101 * Deprecated, ignored.
103 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
106 * Device parameter to limit the size of inlining packet.
107 * Deprecated, ignored.
109 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
112 * Device parameter to enable Tx scheduling on timestamps
113 * and specify the packet pacing granularity in nanoseconds.
115 #define MLX5_TX_PP "tx_pp"
118 * Device parameter to specify skew in nanoseconds on Tx datapath,
119 * it represents the time between SQ start WQE processing and
120 * appearing actual packet data on the wire.
122 #define MLX5_TX_SKEW "tx_skew"
125 * Device parameter to enable hardware Tx vector.
126 * Deprecated, ignored (no vectorized Tx routines anymore).
128 #define MLX5_TX_VEC_EN "tx_vec_en"
130 /* Device parameter to enable hardware Rx vector. */
131 #define MLX5_RX_VEC_EN "rx_vec_en"
133 /* Allow L3 VXLAN flow creation. */
134 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
136 /* Activate DV E-Switch flow steering. */
137 #define MLX5_DV_ESW_EN "dv_esw_en"
139 /* Activate DV flow steering. */
140 #define MLX5_DV_FLOW_EN "dv_flow_en"
142 /* Enable extensive flow metadata support. */
143 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
145 /* Device parameter to let the user manage the lacp traffic of bonded device */
146 #define MLX5_LACP_BY_USER "lacp_by_user"
148 /* Activate Netlink support in VF mode. */
149 #define MLX5_VF_NL_EN "vf_nl_en"
151 /* Enable extending memsegs when creating a MR. */
152 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
154 /* Select port representors to instantiate. */
155 #define MLX5_REPRESENTOR "representor"
157 /* Device parameter to configure the maximum number of dump files per queue. */
158 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
160 /* Configure timeout of LRO session (in microseconds). */
161 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
164 * Device parameter to configure the total data buffer size for a single
165 * hairpin queue (logarithm value).
167 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
169 /* Flow memory reclaim mode. */
170 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
172 /* The default memory allocator used in PMD. */
173 #define MLX5_SYS_MEM_EN "sys_mem_en"
174 /* Decap will be used or not. */
175 #define MLX5_DECAP_EN "decap_en"
177 /* Shared memory between primary and secondary processes. */
178 struct mlx5_shared_data *mlx5_shared_data;
180 /** Driver-specific log messages type. */
183 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
184 LIST_HEAD_INITIALIZER();
185 static pthread_mutex_t mlx5_dev_ctx_list_mutex = PTHREAD_MUTEX_INITIALIZER;
187 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
188 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
189 [MLX5_IPOOL_DECAP_ENCAP] = {
190 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
196 .malloc = mlx5_malloc,
198 .type = "mlx5_encap_decap_ipool",
200 [MLX5_IPOOL_PUSH_VLAN] = {
201 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
207 .malloc = mlx5_malloc,
209 .type = "mlx5_push_vlan_ipool",
212 .size = sizeof(struct mlx5_flow_dv_tag_resource),
218 .malloc = mlx5_malloc,
220 .type = "mlx5_tag_ipool",
222 [MLX5_IPOOL_PORT_ID] = {
223 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
229 .malloc = mlx5_malloc,
231 .type = "mlx5_port_id_ipool",
233 [MLX5_IPOOL_JUMP] = {
234 .size = sizeof(struct mlx5_flow_tbl_data_entry),
240 .malloc = mlx5_malloc,
242 .type = "mlx5_jump_ipool",
244 [MLX5_IPOOL_SAMPLE] = {
245 .size = sizeof(struct mlx5_flow_dv_sample_resource),
251 .malloc = mlx5_malloc,
253 .type = "mlx5_sample_ipool",
255 [MLX5_IPOOL_DEST_ARRAY] = {
256 .size = sizeof(struct mlx5_flow_dv_dest_array_resource),
262 .malloc = mlx5_malloc,
264 .type = "mlx5_dest_array_ipool",
266 [MLX5_IPOOL_TUNNEL_ID] = {
267 .size = sizeof(struct mlx5_flow_tunnel),
268 .trunk_size = MLX5_MAX_TUNNELS,
271 .type = "mlx5_tunnel_offload",
273 [MLX5_IPOOL_TNL_TBL_ID] = {
276 .type = "mlx5_flow_tnl_tbl_ipool",
280 .size = sizeof(struct mlx5_flow_meter),
286 .malloc = mlx5_malloc,
288 .type = "mlx5_meter_ipool",
291 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
297 .malloc = mlx5_malloc,
299 .type = "mlx5_mcp_ipool",
301 [MLX5_IPOOL_HRXQ] = {
302 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
308 .malloc = mlx5_malloc,
310 .type = "mlx5_hrxq_ipool",
312 [MLX5_IPOOL_MLX5_FLOW] = {
314 * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
315 * It set in run time according to PCI function configuration.
323 .malloc = mlx5_malloc,
325 .type = "mlx5_flow_handle_ipool",
327 [MLX5_IPOOL_RTE_FLOW] = {
328 .size = sizeof(struct rte_flow),
332 .malloc = mlx5_malloc,
334 .type = "rte_flow_ipool",
336 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID] = {
339 .type = "mlx5_flow_rss_id_ipool",
341 [MLX5_IPOOL_RSS_SHARED_ACTIONS] = {
342 .size = sizeof(struct mlx5_shared_action_rss),
348 .malloc = mlx5_malloc,
350 .type = "mlx5_shared_action_rss",
355 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
356 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
358 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
361 * Initialize the ASO aging management structure.
364 * Pointer to mlx5_dev_ctx_shared object to free
367 * 0 on success, a negative errno value otherwise and rte_errno is set.
370 mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh)
376 sh->aso_age_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->aso_age_mng),
377 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
378 if (!sh->aso_age_mng) {
379 DRV_LOG(ERR, "aso_age_mng allocation was failed.");
383 err = mlx5_aso_queue_init(sh);
385 mlx5_free(sh->aso_age_mng);
388 rte_spinlock_init(&sh->aso_age_mng->resize_sl);
389 rte_spinlock_init(&sh->aso_age_mng->free_sl);
390 LIST_INIT(&sh->aso_age_mng->free);
395 * Close and release all the resources of the ASO aging management structure.
398 * Pointer to mlx5_dev_ctx_shared object to free.
401 mlx5_flow_aso_age_mng_close(struct mlx5_dev_ctx_shared *sh)
405 mlx5_aso_queue_stop(sh);
406 mlx5_aso_queue_uninit(sh);
407 if (sh->aso_age_mng->pools) {
408 struct mlx5_aso_age_pool *pool;
410 for (i = 0; i < sh->aso_age_mng->next; ++i) {
411 pool = sh->aso_age_mng->pools[i];
412 claim_zero(mlx5_devx_cmd_destroy
413 (pool->flow_hit_aso_obj));
414 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j)
415 if (pool->actions[j].dr_action)
417 (mlx5_glue->destroy_flow_action
418 (pool->actions[j].dr_action));
421 mlx5_free(sh->aso_age_mng->pools);
423 mlx5_free(sh->aso_age_mng);
427 * Initialize the shared aging list information per port.
430 * Pointer to mlx5_dev_ctx_shared object.
433 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
436 struct mlx5_age_info *age_info;
438 for (i = 0; i < sh->max_port; i++) {
439 age_info = &sh->port[i].age_info;
441 TAILQ_INIT(&age_info->aged_counters);
442 LIST_INIT(&age_info->aged_aso);
443 rte_spinlock_init(&age_info->aged_sl);
444 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
449 * Initialize the counters management structure.
452 * Pointer to mlx5_dev_ctx_shared object to free
455 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
459 memset(&sh->cmng, 0, sizeof(sh->cmng));
460 TAILQ_INIT(&sh->cmng.flow_counters);
461 sh->cmng.min_id = MLX5_CNT_BATCH_OFFSET;
462 sh->cmng.max_id = -1;
463 sh->cmng.last_pool_idx = POOL_IDX_INVALID;
464 rte_spinlock_init(&sh->cmng.pool_update_sl);
465 for (i = 0; i < MLX5_COUNTER_TYPE_MAX; i++) {
466 TAILQ_INIT(&sh->cmng.counters[i]);
467 rte_spinlock_init(&sh->cmng.csl[i]);
472 * Destroy all the resources allocated for a counter memory management.
475 * Pointer to the memory management structure.
478 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
480 uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
482 LIST_REMOVE(mng, next);
483 claim_zero(mlx5_devx_cmd_destroy(mng->dm));
484 claim_zero(mlx5_glue->devx_umem_dereg(mng->umem));
489 * Close and release all the resources of the counters management.
492 * Pointer to mlx5_dev_ctx_shared object to free.
495 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
497 struct mlx5_counter_stats_mem_mng *mng;
503 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
504 if (rte_errno != EINPROGRESS)
509 if (sh->cmng.pools) {
510 struct mlx5_flow_counter_pool *pool;
511 uint16_t n_valid = sh->cmng.n_valid;
512 bool fallback = sh->cmng.counter_fallback;
514 for (i = 0; i < n_valid; ++i) {
515 pool = sh->cmng.pools[i];
516 if (!fallback && pool->min_dcs)
517 claim_zero(mlx5_devx_cmd_destroy
519 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
520 struct mlx5_flow_counter *cnt =
521 MLX5_POOL_GET_CNT(pool, j);
525 (mlx5_glue->destroy_flow_action
527 if (fallback && MLX5_POOL_GET_CNT
528 (pool, j)->dcs_when_free)
529 claim_zero(mlx5_devx_cmd_destroy
530 (cnt->dcs_when_free));
534 mlx5_free(sh->cmng.pools);
536 mng = LIST_FIRST(&sh->cmng.mem_mngs);
538 mlx5_flow_destroy_counter_stat_mem_mng(mng);
539 mng = LIST_FIRST(&sh->cmng.mem_mngs);
541 memset(&sh->cmng, 0, sizeof(sh->cmng));
544 /* Send FLOW_AGED event if needed. */
546 mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh)
548 struct mlx5_age_info *age_info;
551 for (i = 0; i < sh->max_port; i++) {
552 age_info = &sh->port[i].age_info;
553 if (!MLX5_AGE_GET(age_info, MLX5_AGE_EVENT_NEW))
555 if (MLX5_AGE_GET(age_info, MLX5_AGE_TRIGGER))
556 rte_eth_dev_callback_process
557 (&rte_eth_devices[sh->port[i].devx_ih_port_id],
558 RTE_ETH_EVENT_FLOW_AGED, NULL);
564 * Initialize the flow resources' indexed mempool.
567 * Pointer to mlx5_dev_ctx_shared object.
569 * Pointer to user dev config.
572 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
573 const struct mlx5_dev_config *config)
576 struct mlx5_indexed_pool_config cfg;
578 for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
579 cfg = mlx5_ipool_cfg[i];
584 * Set MLX5_IPOOL_MLX5_FLOW ipool size
585 * according to PCI function flow configuration.
587 case MLX5_IPOOL_MLX5_FLOW:
588 cfg.size = config->dv_flow_en ?
589 sizeof(struct mlx5_flow_handle) :
590 MLX5_FLOW_HANDLE_VERBS_SIZE;
593 if (config->reclaim_mode)
594 cfg.release_mem_en = 1;
595 sh->ipool[i] = mlx5_ipool_create(&cfg);
600 * Release the flow resources' indexed mempool.
603 * Pointer to mlx5_dev_ctx_shared object.
606 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
610 for (i = 0; i < MLX5_IPOOL_MAX; ++i)
611 mlx5_ipool_destroy(sh->ipool[i]);
615 * Check if dynamic flex parser for eCPRI already exists.
618 * Pointer to Ethernet device structure.
621 * true on exists, false on not.
624 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
626 struct mlx5_priv *priv = dev->data->dev_private;
627 struct mlx5_flex_parser_profiles *prf =
628 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
634 * Allocation of a flex parser for eCPRI. Once created, this parser related
635 * resources will be held until the device is closed.
638 * Pointer to Ethernet device structure.
641 * 0 on success, a negative errno value otherwise and rte_errno is set.
644 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
646 struct mlx5_priv *priv = dev->data->dev_private;
647 struct mlx5_flex_parser_profiles *prf =
648 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
649 struct mlx5_devx_graph_node_attr node = {
650 .modify_field_select = 0,
655 if (!priv->config.hca_attr.parse_graph_flex_node) {
656 DRV_LOG(ERR, "Dynamic flex parser is not supported "
657 "for device %s.", priv->dev_data->name);
660 node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED;
661 /* 8 bytes now: 4B common header + 4B message body header. */
662 node.header_length_base_value = 0x8;
663 /* After MAC layer: Ether / VLAN. */
664 node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC;
665 /* Type of compared condition should be 0xAEFE in the L2 layer. */
666 node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI;
667 /* Sample #0: type in common header. */
668 node.sample[0].flow_match_sample_en = 1;
670 node.sample[0].flow_match_sample_offset_mode = 0x0;
671 /* Only the 2nd byte will be used. */
672 node.sample[0].flow_match_sample_field_base_offset = 0x0;
673 /* Sample #1: message payload. */
674 node.sample[1].flow_match_sample_en = 1;
676 node.sample[1].flow_match_sample_offset_mode = 0x0;
678 * Only the first two bytes will be used right now, and its offset will
679 * start after the common header that with the length of a DW(u32).
681 node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);
682 prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->ctx, &node);
684 DRV_LOG(ERR, "Failed to create flex parser node object.");
685 return (rte_errno == 0) ? -ENODEV : -rte_errno;
688 ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num);
690 DRV_LOG(ERR, "Failed to query sample IDs.");
691 return (rte_errno == 0) ? -ENODEV : -rte_errno;
693 prf->offset[0] = 0x0;
694 prf->offset[1] = sizeof(uint32_t);
695 prf->ids[0] = ids[0];
696 prf->ids[1] = ids[1];
701 * Destroy the flex parser node, including the parser itself, input / output
702 * arcs and DW samples. Resources could be reused then.
705 * Pointer to Ethernet device structure.
708 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
710 struct mlx5_priv *priv = dev->data->dev_private;
711 struct mlx5_flex_parser_profiles *prf =
712 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
715 mlx5_devx_cmd_destroy(prf->obj);
720 * Allocate Rx and Tx UARs in robust fashion.
721 * This routine handles the following UAR allocation issues:
723 * - tries to allocate the UAR with the most appropriate memory
724 * mapping type from the ones supported by the host
726 * - tries to allocate the UAR with non-NULL base address
727 * OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as
728 * UAR base address if UAR was not the first object in the UAR page.
729 * It caused the PMD failure and we should try to get another UAR
730 * till we get the first one with non-NULL base address returned.
733 mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh,
734 const struct mlx5_dev_config *config)
736 uint32_t uar_mapping, retry;
740 for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
741 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
742 /* Control the mapping type according to the settings. */
743 uar_mapping = (config->dbnc == MLX5_TXDB_NCACHED) ?
744 MLX5DV_UAR_ALLOC_TYPE_NC :
745 MLX5DV_UAR_ALLOC_TYPE_BF;
747 RTE_SET_USED(config);
749 * It seems we have no way to control the memory mapping type
750 * for the UAR, the default "Write-Combining" type is supposed.
751 * The UAR initialization on queue creation queries the
752 * actual mapping type done by Verbs/kernel and setups the
753 * PMD datapath accordingly.
757 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->ctx, uar_mapping);
758 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
760 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
761 if (config->dbnc == MLX5_TXDB_CACHED ||
762 config->dbnc == MLX5_TXDB_HEURISTIC)
763 DRV_LOG(WARNING, "Devarg tx_db_nc setting "
764 "is not supported by DevX");
766 * In some environments like virtual machine
767 * the Write Combining mapped might be not supported
768 * and UAR allocation fails. We try "Non-Cached"
769 * mapping for the case. The tx_burst routines take
770 * the UAR mapping type into account on UAR setup
773 DRV_LOG(WARNING, "Failed to allocate Tx DevX UAR (BF)");
774 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
775 sh->tx_uar = mlx5_glue->devx_alloc_uar
776 (sh->ctx, uar_mapping);
777 } else if (!sh->tx_uar &&
778 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_NC) {
779 if (config->dbnc == MLX5_TXDB_NCACHED)
780 DRV_LOG(WARNING, "Devarg tx_db_nc settings "
781 "is not supported by DevX");
783 * If Verbs/kernel does not support "Non-Cached"
784 * try the "Write-Combining".
786 DRV_LOG(WARNING, "Failed to allocate Tx DevX UAR (NC)");
787 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_BF;
788 sh->tx_uar = mlx5_glue->devx_alloc_uar
789 (sh->ctx, uar_mapping);
793 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (BF/NC)");
797 base_addr = mlx5_os_get_devx_uar_base_addr(sh->tx_uar);
801 * The UARs are allocated by rdma_core within the
802 * IB device context, on context closure all UARs
803 * will be freed, should be no memory/object leakage.
805 DRV_LOG(WARNING, "Retrying to allocate Tx DevX UAR");
808 /* Check whether we finally succeeded with valid UAR allocation. */
810 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (NULL base)");
814 for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
816 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
817 (sh->ctx, uar_mapping);
818 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
819 if (!sh->devx_rx_uar &&
820 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
822 * Rx UAR is used to control interrupts only,
823 * should be no datapath noticeable impact,
824 * can try "Non-Cached" mapping safely.
826 DRV_LOG(WARNING, "Failed to allocate Rx DevX UAR (BF)");
827 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
828 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
829 (sh->ctx, uar_mapping);
832 if (!sh->devx_rx_uar) {
833 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (BF/NC)");
837 base_addr = mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar);
841 * The UARs are allocated by rdma_core within the
842 * IB device context, on context closure all UARs
843 * will be freed, should be no memory/object leakage.
845 DRV_LOG(WARNING, "Retrying to allocate Rx DevX UAR");
846 sh->devx_rx_uar = NULL;
848 /* Check whether we finally succeeded with valid UAR allocation. */
849 if (!sh->devx_rx_uar) {
850 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (NULL base)");
858 * Allocate shared device context. If there is multiport device the
859 * master and representors will share this context, if there is single
860 * port dedicated device, the context will be used by only given
861 * port due to unification.
863 * Routine first searches the context for the specified device name,
864 * if found the shared context assumed and reference counter is incremented.
865 * If no context found the new one is created and initialized with specified
866 * device context and parameters.
869 * Pointer to the device attributes (name, port, etc).
871 * Pointer to device configuration structure.
874 * Pointer to mlx5_dev_ctx_shared object on success,
875 * otherwise NULL and rte_errno is set.
877 struct mlx5_dev_ctx_shared *
878 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
879 const struct mlx5_dev_config *config)
881 struct mlx5_dev_ctx_shared *sh;
884 struct mlx5_devx_tis_attr tis_attr = { 0 };
887 /* Secondary process should not create the shared context. */
888 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
889 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
890 /* Search for IB context by device name. */
891 LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
892 if (!strcmp(sh->ibdev_name,
893 mlx5_os_get_dev_device_name(spawn->phys_dev))) {
898 /* No device found, we have to create new shared context. */
899 MLX5_ASSERT(spawn->max_port);
900 sh = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
901 sizeof(struct mlx5_dev_ctx_shared) +
903 sizeof(struct mlx5_dev_shared_port),
904 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
906 DRV_LOG(ERR, "shared context allocation failure");
910 err = mlx5_os_open_device(spawn, config, sh);
913 err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
915 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
919 sh->bond_dev = UINT16_MAX;
920 sh->max_port = spawn->max_port;
921 strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
922 sizeof(sh->ibdev_name) - 1);
923 strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
924 sizeof(sh->ibdev_path) - 1);
926 * Setting port_id to max unallowed value means
927 * there is no interrupt subhandler installed for
928 * the given port index i.
930 for (i = 0; i < sh->max_port; i++) {
931 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
932 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
934 sh->pd = mlx5_glue->alloc_pd(sh->ctx);
935 if (sh->pd == NULL) {
936 DRV_LOG(ERR, "PD allocation failure");
941 /* Query the EQN for this core. */
942 err = mlx5_glue->devx_query_eqn(sh->ctx, 0, &sh->eqn);
945 DRV_LOG(ERR, "Failed to query event queue number %d.",
949 err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
951 DRV_LOG(ERR, "Fail to extract pdn from PD");
954 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
956 DRV_LOG(ERR, "TD allocation failure");
960 tis_attr.transport_domain = sh->td->id;
961 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
963 DRV_LOG(ERR, "TIS allocation failure");
967 err = mlx5_alloc_rxtx_uars(sh, config);
970 MLX5_ASSERT(sh->tx_uar);
971 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->tx_uar));
973 MLX5_ASSERT(sh->devx_rx_uar);
974 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar));
977 /* Initialize UAR access locks for 32bit implementations. */
978 rte_spinlock_init(&sh->uar_lock_cq);
979 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
980 rte_spinlock_init(&sh->uar_lock[i]);
983 * Once the device is added to the list of memory event
984 * callback, its global MR cache table cannot be expanded
985 * on the fly because of deadlock. If it overflows, lookup
986 * should be done by searching MR list linearly, which is slow.
988 * At this point the device is not added to the memory
989 * event list yet, context is just being created.
991 err = mlx5_mr_btree_init(&sh->share_cache.cache,
992 MLX5_MR_BTREE_CACHE_N * 2,
993 spawn->pci_dev->device.numa_node);
998 mlx5_os_set_reg_mr_cb(&sh->share_cache.reg_mr_cb,
999 &sh->share_cache.dereg_mr_cb);
1000 mlx5_os_dev_shared_handler_install(sh);
1001 sh->cnt_id_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_DWORD);
1002 if (!sh->cnt_id_tbl) {
1006 mlx5_flow_aging_init(sh);
1007 mlx5_flow_counters_mng_init(sh);
1008 mlx5_flow_ipool_create(sh, config);
1009 /* Add device to memory callback list. */
1010 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1011 LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
1013 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1014 /* Add context to the global device list. */
1015 LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
1017 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1020 pthread_mutex_destroy(&sh->txpp.mutex);
1021 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1024 mlx5_l3t_destroy(sh->cnt_id_tbl);
1026 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1028 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1029 if (sh->devx_rx_uar)
1030 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1032 mlx5_glue->devx_free_uar(sh->tx_uar);
1034 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
1036 claim_zero(mlx5_glue->close_device(sh->ctx));
1038 MLX5_ASSERT(err > 0);
1044 * Free shared IB device context. Decrement counter and if zero free
1045 * all allocated resources and close handles.
1048 * Pointer to mlx5_dev_ctx_shared object to free
1051 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
1053 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1054 #ifdef RTE_LIBRTE_MLX5_DEBUG
1055 /* Check the object presence in the list. */
1056 struct mlx5_dev_ctx_shared *lctx;
1058 LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
1063 DRV_LOG(ERR, "Freeing non-existing shared IB context");
1068 MLX5_ASSERT(sh->refcnt);
1069 /* Secondary process should not free the shared context. */
1070 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1073 /* Remove from memory callback device list. */
1074 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1075 LIST_REMOVE(sh, mem_event_cb);
1076 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1077 /* Release created Memory Regions. */
1078 mlx5_mr_release_cache(&sh->share_cache);
1079 /* Remove context from the global device list. */
1080 LIST_REMOVE(sh, next);
1081 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1083 * Ensure there is no async event handler installed.
1084 * Only primary process handles async device events.
1086 mlx5_flow_counters_mng_close(sh);
1087 if (sh->aso_age_mng) {
1088 mlx5_flow_aso_age_mng_close(sh);
1089 sh->aso_age_mng = NULL;
1091 mlx5_flow_ipool_destroy(sh);
1092 mlx5_os_dev_shared_handler_uninstall(sh);
1093 if (sh->cnt_id_tbl) {
1094 mlx5_l3t_destroy(sh->cnt_id_tbl);
1095 sh->cnt_id_tbl = NULL;
1098 mlx5_glue->devx_free_uar(sh->tx_uar);
1102 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
1104 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1106 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1107 if (sh->devx_rx_uar)
1108 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1110 claim_zero(mlx5_glue->close_device(sh->ctx));
1111 pthread_mutex_destroy(&sh->txpp.mutex);
1115 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1119 * Destroy table hash list.
1122 * Pointer to the private device data structure.
1125 mlx5_free_table_hash_list(struct mlx5_priv *priv)
1127 struct mlx5_dev_ctx_shared *sh = priv->sh;
1131 mlx5_hlist_destroy(sh->flow_tbls);
1135 * Initialize flow table hash list and create the root tables entry
1139 * Pointer to the private device data structure.
1142 * Zero on success, positive error code otherwise.
1145 mlx5_alloc_table_hash_list(struct mlx5_priv *priv __rte_unused)
1148 /* Tables are only used in DV and DR modes. */
1149 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
1150 struct mlx5_dev_ctx_shared *sh = priv->sh;
1151 char s[MLX5_HLIST_NAMESIZE];
1154 snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1155 sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE,
1156 0, 0, flow_dv_tbl_create_cb,
1157 flow_dv_tbl_match_cb,
1158 flow_dv_tbl_remove_cb);
1159 if (!sh->flow_tbls) {
1160 DRV_LOG(ERR, "flow tables with hash creation failed.");
1164 sh->flow_tbls->ctx = sh;
1165 #ifndef HAVE_MLX5DV_DR
1166 struct rte_flow_error error;
1167 struct rte_eth_dev *dev = &rte_eth_devices[priv->dev_data->port_id];
1170 * In case we have not DR support, the zero tables should be created
1171 * because DV expect to see them even if they cannot be created by
1174 if (!flow_dv_tbl_resource_get(dev, 0, 0, 0, 0, NULL, 0, 1, &error) ||
1175 !flow_dv_tbl_resource_get(dev, 0, 1, 0, 0, NULL, 0, 1, &error) ||
1176 !flow_dv_tbl_resource_get(dev, 0, 0, 1, 0, NULL, 0, 1, &error)) {
1182 mlx5_free_table_hash_list(priv);
1183 #endif /* HAVE_MLX5DV_DR */
1189 * Retrieve integer value from environment variable.
1192 * Environment variable name.
1195 * Integer value, 0 if the variable is not set.
1198 mlx5_getenv_int(const char *name)
1200 const char *val = getenv(name);
1208 * DPDK callback to add udp tunnel port
1211 * A pointer to eth_dev
1212 * @param[in] udp_tunnel
1213 * A pointer to udp tunnel
1216 * 0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1219 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1220 struct rte_eth_udp_tunnel *udp_tunnel)
1222 MLX5_ASSERT(udp_tunnel != NULL);
1223 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1224 udp_tunnel->udp_port == 4789)
1226 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1227 udp_tunnel->udp_port == 4790)
1233 * Initialize process private data structure.
1236 * Pointer to Ethernet device structure.
1239 * 0 on success, a negative errno value otherwise and rte_errno is set.
1242 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1244 struct mlx5_priv *priv = dev->data->dev_private;
1245 struct mlx5_proc_priv *ppriv;
1249 * UAR register table follows the process private structure. BlueFlame
1250 * registers for Tx queues are stored in the table.
1253 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1254 ppriv = mlx5_malloc(MLX5_MEM_RTE, ppriv_size, RTE_CACHE_LINE_SIZE,
1255 dev->device->numa_node);
1260 ppriv->uar_table_sz = ppriv_size;
1261 dev->process_private = ppriv;
1266 * Un-initialize process private data structure.
1269 * Pointer to Ethernet device structure.
1272 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1274 if (!dev->process_private)
1276 mlx5_free(dev->process_private);
1277 dev->process_private = NULL;
1281 * DPDK callback to close the device.
1283 * Destroy all queues and objects, free memory.
1286 * Pointer to Ethernet device structure.
1289 mlx5_dev_close(struct rte_eth_dev *dev)
1291 struct mlx5_priv *priv = dev->data->dev_private;
1295 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1296 /* Check if process_private released. */
1297 if (!dev->process_private)
1299 mlx5_tx_uar_uninit_secondary(dev);
1300 mlx5_proc_priv_uninit(dev);
1301 rte_eth_dev_release_port(dev);
1306 DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1308 ((priv->sh->ctx != NULL) ?
1309 mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
1311 * If default mreg copy action is removed at the stop stage,
1312 * the search will return none and nothing will be done anymore.
1314 mlx5_flow_stop_default(dev);
1315 mlx5_traffic_disable(dev);
1317 * If all the flows are already flushed in the device stop stage,
1318 * then this will return directly without any action.
1320 mlx5_flow_list_flush(dev, &priv->flows, true);
1321 mlx5_shared_action_flush(dev);
1322 mlx5_flow_meter_flush(dev, NULL);
1323 /* Prevent crashes when queues are still in use. */
1324 dev->rx_pkt_burst = removed_rx_burst;
1325 dev->tx_pkt_burst = removed_tx_burst;
1327 /* Disable datapath on secondary process. */
1328 mlx5_mp_os_req_stop_rxtx(dev);
1329 /* Free the eCPRI flex parser resource. */
1330 mlx5_flex_parser_ecpri_release(dev);
1331 if (priv->rxqs != NULL) {
1332 /* XXX race condition if mlx5_rx_burst() is still running. */
1334 for (i = 0; (i != priv->rxqs_n); ++i)
1335 mlx5_rxq_release(dev, i);
1339 if (priv->txqs != NULL) {
1340 /* XXX race condition if mlx5_tx_burst() is still running. */
1342 for (i = 0; (i != priv->txqs_n); ++i)
1343 mlx5_txq_release(dev, i);
1347 mlx5_proc_priv_uninit(dev);
1348 if (priv->drop_queue.hrxq)
1349 mlx5_drop_action_destroy(dev);
1350 if (priv->mreg_cp_tbl)
1351 mlx5_hlist_destroy(priv->mreg_cp_tbl);
1352 mlx5_mprq_free_mp(dev);
1353 mlx5_os_free_shared_dr(priv);
1354 if (priv->rss_conf.rss_key != NULL)
1355 mlx5_free(priv->rss_conf.rss_key);
1356 if (priv->reta_idx != NULL)
1357 mlx5_free(priv->reta_idx);
1358 if (priv->config.vf)
1359 mlx5_os_mac_addr_flush(dev);
1360 if (priv->nl_socket_route >= 0)
1361 close(priv->nl_socket_route);
1362 if (priv->nl_socket_rdma >= 0)
1363 close(priv->nl_socket_rdma);
1364 if (priv->vmwa_context)
1365 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1366 ret = mlx5_hrxq_verify(dev);
1368 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1369 dev->data->port_id);
1370 ret = mlx5_ind_table_obj_verify(dev);
1372 DRV_LOG(WARNING, "port %u some indirection table still remain",
1373 dev->data->port_id);
1374 ret = mlx5_rxq_obj_verify(dev);
1376 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1377 dev->data->port_id);
1378 ret = mlx5_rxq_verify(dev);
1380 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1381 dev->data->port_id);
1382 ret = mlx5_txq_obj_verify(dev);
1384 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1385 dev->data->port_id);
1386 ret = mlx5_txq_verify(dev);
1388 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1389 dev->data->port_id);
1390 ret = mlx5_flow_verify(dev);
1392 DRV_LOG(WARNING, "port %u some flows still remain",
1393 dev->data->port_id);
1394 mlx5_cache_list_destroy(&priv->hrxqs);
1396 * Free the shared context in last turn, because the cleanup
1397 * routines above may use some shared fields, like
1398 * mlx5_os_mac_addr_flush() uses ibdev_path for retrieveing
1399 * ifindex if Netlink fails.
1401 mlx5_free_shared_dev_ctx(priv->sh);
1402 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1406 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1407 struct mlx5_priv *opriv =
1408 rte_eth_devices[port_id].data->dev_private;
1411 opriv->domain_id != priv->domain_id ||
1412 &rte_eth_devices[port_id] == dev)
1418 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1420 memset(priv, 0, sizeof(*priv));
1421 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1423 * Reset mac_addrs to NULL such that it is not freed as part of
1424 * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1425 * it is freed when dev_private is freed.
1427 dev->data->mac_addrs = NULL;
1432 * Verify and store value for device argument.
1435 * Key argument to verify.
1437 * Value associated with key.
1442 * 0 on success, a negative errno value otherwise and rte_errno is set.
1445 mlx5_args_check(const char *key, const char *val, void *opaque)
1447 struct mlx5_dev_config *config = opaque;
1451 /* No-op, port representors are processed in mlx5_dev_spawn(). */
1452 if (!strcmp(MLX5_REPRESENTOR, key))
1455 tmp = strtol(val, NULL, 0);
1458 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1461 if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
1462 /* Negative values are acceptable for some keys only. */
1464 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
1467 mod = tmp >= 0 ? tmp : -tmp;
1468 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1469 if (tmp > MLX5_CQE_RESP_FORMAT_L34H_STRIDX) {
1470 DRV_LOG(ERR, "invalid CQE compression "
1471 "format parameter");
1475 config->cqe_comp = !!tmp;
1476 config->cqe_comp_fmt = tmp;
1477 } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
1478 config->cqe_pad = !!tmp;
1479 } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1480 config->hw_padding = !!tmp;
1481 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1482 config->mprq.enabled = !!tmp;
1483 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1484 config->mprq.stride_num_n = tmp;
1485 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1486 config->mprq.stride_size_n = tmp;
1487 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1488 config->mprq.max_memcpy_len = tmp;
1489 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1490 config->mprq.min_rxqs_num = tmp;
1491 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1492 DRV_LOG(WARNING, "%s: deprecated parameter,"
1493 " converted to txq_inline_max", key);
1494 config->txq_inline_max = tmp;
1495 } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1496 config->txq_inline_max = tmp;
1497 } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1498 config->txq_inline_min = tmp;
1499 } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1500 config->txq_inline_mpw = tmp;
1501 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1502 config->txqs_inline = tmp;
1503 } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1504 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1505 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1506 config->mps = !!tmp;
1507 } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1508 if (tmp != MLX5_TXDB_CACHED &&
1509 tmp != MLX5_TXDB_NCACHED &&
1510 tmp != MLX5_TXDB_HEURISTIC) {
1511 DRV_LOG(ERR, "invalid Tx doorbell "
1512 "mapping parameter");
1517 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1518 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1519 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1520 DRV_LOG(WARNING, "%s: deprecated parameter,"
1521 " converted to txq_inline_mpw", key);
1522 config->txq_inline_mpw = tmp;
1523 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1524 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1525 } else if (strcmp(MLX5_TX_PP, key) == 0) {
1527 DRV_LOG(ERR, "Zero Tx packet pacing parameter");
1531 config->tx_pp = tmp;
1532 } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
1533 config->tx_skew = tmp;
1534 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1535 config->rx_vec_en = !!tmp;
1536 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1537 config->l3_vxlan_en = !!tmp;
1538 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1539 config->vf_nl_en = !!tmp;
1540 } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1541 config->dv_esw_en = !!tmp;
1542 } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1543 config->dv_flow_en = !!tmp;
1544 } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1545 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1546 tmp != MLX5_XMETA_MODE_META16 &&
1547 tmp != MLX5_XMETA_MODE_META32 &&
1548 tmp != MLX5_XMETA_MODE_MISS_INFO) {
1549 DRV_LOG(ERR, "invalid extensive "
1550 "metadata parameter");
1554 if (tmp != MLX5_XMETA_MODE_MISS_INFO)
1555 config->dv_xmeta_en = tmp;
1557 config->dv_miss_info = 1;
1558 } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
1559 config->lacp_by_user = !!tmp;
1560 } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1561 config->mr_ext_memseg_en = !!tmp;
1562 } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1563 config->max_dump_files_num = tmp;
1564 } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1565 config->lro.timeout = tmp;
1566 } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1567 DRV_LOG(DEBUG, "class argument is %s.", val);
1568 } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1569 config->log_hp_size = tmp;
1570 } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1571 if (tmp != MLX5_RCM_NONE &&
1572 tmp != MLX5_RCM_LIGHT &&
1573 tmp != MLX5_RCM_AGGR) {
1574 DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1578 config->reclaim_mode = tmp;
1579 } else if (strcmp(MLX5_SYS_MEM_EN, key) == 0) {
1580 config->sys_mem_en = !!tmp;
1581 } else if (strcmp(MLX5_DECAP_EN, key) == 0) {
1582 config->decap_en = !!tmp;
1584 DRV_LOG(WARNING, "%s: unknown parameter", key);
1592 * Parse device parameters.
1595 * Pointer to device configuration structure.
1597 * Device arguments structure.
1600 * 0 on success, a negative errno value otherwise and rte_errno is set.
1603 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1605 const char **params = (const char *[]){
1606 MLX5_RXQ_CQE_COMP_EN,
1607 MLX5_RXQ_CQE_PAD_EN,
1608 MLX5_RXQ_PKT_PAD_EN,
1610 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1611 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1612 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1615 MLX5_TXQ_INLINE_MIN,
1616 MLX5_TXQ_INLINE_MAX,
1617 MLX5_TXQ_INLINE_MPW,
1618 MLX5_TXQS_MIN_INLINE,
1621 MLX5_TXQ_MPW_HDR_DSEG_EN,
1622 MLX5_TXQ_MAX_INLINE_LEN,
1634 MLX5_MR_EXT_MEMSEG_EN,
1636 MLX5_MAX_DUMP_FILES_NUM,
1637 MLX5_LRO_TIMEOUT_USEC,
1638 MLX5_CLASS_ARG_NAME,
1645 struct rte_kvargs *kvlist;
1649 if (devargs == NULL)
1651 /* Following UGLY cast is done to pass checkpatch. */
1652 kvlist = rte_kvargs_parse(devargs->args, params);
1653 if (kvlist == NULL) {
1657 /* Process parameters. */
1658 for (i = 0; (params[i] != NULL); ++i) {
1659 if (rte_kvargs_count(kvlist, params[i])) {
1660 ret = rte_kvargs_process(kvlist, params[i],
1661 mlx5_args_check, config);
1664 rte_kvargs_free(kvlist);
1669 rte_kvargs_free(kvlist);
1674 * Configures the minimal amount of data to inline into WQE
1675 * while sending packets.
1677 * - the txq_inline_min has the maximal priority, if this
1678 * key is specified in devargs
1679 * - if DevX is enabled the inline mode is queried from the
1680 * device (HCA attributes and NIC vport context if needed).
1681 * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1682 * and none (0 bytes) for other NICs
1685 * Verbs device parameters (name, port, switch_info) to spawn.
1687 * Device configuration parameters.
1690 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1691 struct mlx5_dev_config *config)
1693 if (config->txq_inline_min != MLX5_ARG_UNSET) {
1694 /* Application defines size of inlined data explicitly. */
1695 switch (spawn->pci_dev->id.device_id) {
1696 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1697 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1698 if (config->txq_inline_min <
1699 (int)MLX5_INLINE_HSIZE_L2) {
1701 "txq_inline_mix aligned to minimal"
1702 " ConnectX-4 required value %d",
1703 (int)MLX5_INLINE_HSIZE_L2);
1704 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1710 if (config->hca_attr.eth_net_offloads) {
1711 /* We have DevX enabled, inline mode queried successfully. */
1712 switch (config->hca_attr.wqe_inline_mode) {
1713 case MLX5_CAP_INLINE_MODE_L2:
1714 /* outer L2 header must be inlined. */
1715 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1717 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1718 /* No inline data are required by NIC. */
1719 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1720 config->hw_vlan_insert =
1721 config->hca_attr.wqe_vlan_insert;
1722 DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1724 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1725 /* inline mode is defined by NIC vport context. */
1726 if (!config->hca_attr.eth_virt)
1728 switch (config->hca_attr.vport_inline_mode) {
1729 case MLX5_INLINE_MODE_NONE:
1730 config->txq_inline_min =
1731 MLX5_INLINE_HSIZE_NONE;
1733 case MLX5_INLINE_MODE_L2:
1734 config->txq_inline_min =
1735 MLX5_INLINE_HSIZE_L2;
1737 case MLX5_INLINE_MODE_IP:
1738 config->txq_inline_min =
1739 MLX5_INLINE_HSIZE_L3;
1741 case MLX5_INLINE_MODE_TCP_UDP:
1742 config->txq_inline_min =
1743 MLX5_INLINE_HSIZE_L4;
1745 case MLX5_INLINE_MODE_INNER_L2:
1746 config->txq_inline_min =
1747 MLX5_INLINE_HSIZE_INNER_L2;
1749 case MLX5_INLINE_MODE_INNER_IP:
1750 config->txq_inline_min =
1751 MLX5_INLINE_HSIZE_INNER_L3;
1753 case MLX5_INLINE_MODE_INNER_TCP_UDP:
1754 config->txq_inline_min =
1755 MLX5_INLINE_HSIZE_INNER_L4;
1761 * We get here if we are unable to deduce
1762 * inline data size with DevX. Try PCI ID
1763 * to determine old NICs.
1765 switch (spawn->pci_dev->id.device_id) {
1766 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1767 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1768 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
1769 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1770 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1771 config->hw_vlan_insert = 0;
1773 case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
1774 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1775 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
1776 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1778 * These NICs support VLAN insertion from WQE and
1779 * report the wqe_vlan_insert flag. But there is the bug
1780 * and PFC control may be broken, so disable feature.
1782 config->hw_vlan_insert = 0;
1783 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1786 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1790 DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
1794 * Configures the metadata mask fields in the shared context.
1797 * Pointer to Ethernet device.
1800 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
1802 struct mlx5_priv *priv = dev->data->dev_private;
1803 struct mlx5_dev_ctx_shared *sh = priv->sh;
1804 uint32_t meta, mark, reg_c0;
1806 reg_c0 = ~priv->vport_meta_mask;
1807 switch (priv->config.dv_xmeta_en) {
1808 case MLX5_XMETA_MODE_LEGACY:
1810 mark = MLX5_FLOW_MARK_MASK;
1812 case MLX5_XMETA_MODE_META16:
1813 meta = reg_c0 >> rte_bsf32(reg_c0);
1814 mark = MLX5_FLOW_MARK_MASK;
1816 case MLX5_XMETA_MODE_META32:
1818 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
1826 if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
1827 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
1828 sh->dv_mark_mask, mark);
1830 sh->dv_mark_mask = mark;
1831 if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
1832 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
1833 sh->dv_meta_mask, meta);
1835 sh->dv_meta_mask = meta;
1836 if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
1837 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
1838 sh->dv_meta_mask, reg_c0);
1840 sh->dv_regc0_mask = reg_c0;
1841 DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
1842 DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
1843 DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
1844 DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
1848 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
1850 static const char *const dynf_names[] = {
1851 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
1852 RTE_MBUF_DYNFLAG_METADATA_NAME,
1853 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
1857 if (n < RTE_DIM(dynf_names))
1859 for (i = 0; i < RTE_DIM(dynf_names); i++) {
1860 if (names[i] == NULL)
1862 strcpy(names[i], dynf_names[i]);
1864 return RTE_DIM(dynf_names);
1868 * Comparison callback to sort device data.
1870 * This is meant to be used with qsort().
1873 * Pointer to pointer to first data object.
1875 * Pointer to pointer to second data object.
1878 * 0 if both objects are equal, less than 0 if the first argument is less
1879 * than the second, greater than 0 otherwise.
1882 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
1883 struct mlx5_dev_config *config)
1885 struct mlx5_dev_ctx_shared *sh = priv->sh;
1886 struct mlx5_dev_config *sh_conf = NULL;
1890 /* Nothing to compare for the single/first device. */
1891 if (sh->refcnt == 1)
1893 /* Find the device with shared context. */
1894 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1895 struct mlx5_priv *opriv =
1896 rte_eth_devices[port_id].data->dev_private;
1898 if (opriv && opriv != priv && opriv->sh == sh) {
1899 sh_conf = &opriv->config;
1905 if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
1906 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
1907 " for shared %s context", sh->ibdev_name);
1911 if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
1912 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
1913 " for shared %s context", sh->ibdev_name);
1921 * Look for the ethernet device belonging to mlx5 driver.
1923 * @param[in] port_id
1924 * port_id to start looking for device.
1925 * @param[in] pci_dev
1926 * Pointer to the hint PCI device. When device is being probed
1927 * the its siblings (master and preceding representors might
1928 * not have assigned driver yet (because the mlx5_os_pci_probe()
1929 * is not completed yet, for this case match on hint PCI
1930 * device may be used to detect sibling device.
1933 * port_id of found device, RTE_MAX_ETHPORT if not found.
1936 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
1938 while (port_id < RTE_MAX_ETHPORTS) {
1939 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
1941 if (dev->state != RTE_ETH_DEV_UNUSED &&
1943 (dev->device == &pci_dev->device ||
1944 (dev->device->driver &&
1945 dev->device->driver->name &&
1946 !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
1950 if (port_id >= RTE_MAX_ETHPORTS)
1951 return RTE_MAX_ETHPORTS;
1956 * DPDK callback to remove a PCI device.
1958 * This function removes all Ethernet devices belong to a given PCI device.
1960 * @param[in] pci_dev
1961 * Pointer to the PCI device.
1964 * 0 on success, the function cannot fail.
1967 mlx5_pci_remove(struct rte_pci_device *pci_dev)
1972 RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
1974 * mlx5_dev_close() is not registered to secondary process,
1975 * call the close function explicitly for secondary process.
1977 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
1978 ret |= mlx5_dev_close(&rte_eth_devices[port_id]);
1980 ret |= rte_eth_dev_close(port_id);
1982 return ret == 0 ? 0 : -EIO;
1985 static const struct rte_pci_id mlx5_pci_id_map[] = {
1987 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1988 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
1991 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1992 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
1995 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1996 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
1999 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2000 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
2003 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2004 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
2007 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2008 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
2011 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2012 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
2015 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2016 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
2019 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2020 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
2023 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2024 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
2027 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2028 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
2031 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2032 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
2035 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2036 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
2039 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2040 PCI_DEVICE_ID_MELLANOX_CONNECTXVF)
2043 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2044 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
2047 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2048 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
2051 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2052 PCI_DEVICE_ID_MELLANOX_CONNECTX7)
2055 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2056 PCI_DEVICE_ID_MELLANOX_CONNECTX7BF)
2063 static struct mlx5_pci_driver mlx5_driver = {
2064 .driver_class = MLX5_CLASS_NET,
2067 .name = MLX5_DRIVER_NAME,
2069 .id_table = mlx5_pci_id_map,
2070 .probe = mlx5_os_pci_probe,
2071 .remove = mlx5_pci_remove,
2072 .dma_map = mlx5_dma_map,
2073 .dma_unmap = mlx5_dma_unmap,
2074 .drv_flags = PCI_DRV_FLAGS,
2078 /* Initialize driver log type. */
2079 RTE_LOG_REGISTER(mlx5_logtype, pmd.net.mlx5, NOTICE)
2082 * Driver initialization routine.
2084 RTE_INIT(rte_mlx5_pmd_init)
2087 /* Build the static tables for Verbs conversion. */
2088 mlx5_set_ptype_table();
2089 mlx5_set_cksum_table();
2090 mlx5_set_swp_types_table();
2092 mlx5_pci_driver_register(&mlx5_driver);
2095 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
2096 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
2097 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");