1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
14 #include <linux/rtnetlink.h>
17 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
19 #pragma GCC diagnostic ignored "-Wpedantic"
21 #include <infiniband/verbs.h>
23 #pragma GCC diagnostic error "-Wpedantic"
26 #include <rte_malloc.h>
27 #include <rte_ethdev_driver.h>
28 #include <rte_ethdev_pci.h>
30 #include <rte_bus_pci.h>
31 #include <rte_common.h>
32 #include <rte_kvargs.h>
33 #include <rte_rwlock.h>
34 #include <rte_spinlock.h>
35 #include <rte_string_fns.h>
36 #include <rte_alarm.h>
38 #include <mlx5_glue.h>
39 #include <mlx5_devx_cmds.h>
40 #include <mlx5_common.h>
41 #include <mlx5_common_mp.h>
43 #include "mlx5_defs.h"
45 #include "mlx5_utils.h"
46 #include "mlx5_rxtx.h"
47 #include "mlx5_autoconf.h"
49 #include "mlx5_flow.h"
50 #include "rte_pmd_mlx5.h"
52 /* Device parameter to enable RX completion queue compression. */
53 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
55 /* Device parameter to enable RX completion entry padding to 128B. */
56 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
58 /* Device parameter to enable padding Rx packet to cacheline size. */
59 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
61 /* Device parameter to enable Multi-Packet Rx queue. */
62 #define MLX5_RX_MPRQ_EN "mprq_en"
64 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
65 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
67 /* Device parameter to configure log 2 of the stride size for MPRQ. */
68 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
70 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
71 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
73 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
74 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
76 /* Device parameter to configure inline send. Deprecated, ignored.*/
77 #define MLX5_TXQ_INLINE "txq_inline"
79 /* Device parameter to limit packet size to inline with ordinary SEND. */
80 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
82 /* Device parameter to configure minimal data size to inline. */
83 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
85 /* Device parameter to limit packet size to inline with Enhanced MPW. */
86 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
89 * Device parameter to configure the number of TX queues threshold for
90 * enabling inline send.
92 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
95 * Device parameter to configure the number of TX queues threshold for
96 * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
98 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
100 /* Device parameter to enable multi-packet send WQEs. */
101 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
104 * Device parameter to force doorbell register mapping
105 * to non-cahed region eliminating the extra write memory barrier.
107 #define MLX5_TX_DB_NC "tx_db_nc"
110 * Device parameter to include 2 dsegs in the title WQEBB.
111 * Deprecated, ignored.
113 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
116 * Device parameter to limit the size of inlining packet.
117 * Deprecated, ignored.
119 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
122 * Device parameter to enable hardware Tx vector.
123 * Deprecated, ignored (no vectorized Tx routines anymore).
125 #define MLX5_TX_VEC_EN "tx_vec_en"
127 /* Device parameter to enable hardware Rx vector. */
128 #define MLX5_RX_VEC_EN "rx_vec_en"
130 /* Allow L3 VXLAN flow creation. */
131 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
133 /* Activate DV E-Switch flow steering. */
134 #define MLX5_DV_ESW_EN "dv_esw_en"
136 /* Activate DV flow steering. */
137 #define MLX5_DV_FLOW_EN "dv_flow_en"
139 /* Enable extensive flow metadata support. */
140 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
142 /* Activate Netlink support in VF mode. */
143 #define MLX5_VF_NL_EN "vf_nl_en"
145 /* Enable extending memsegs when creating a MR. */
146 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
148 /* Select port representors to instantiate. */
149 #define MLX5_REPRESENTOR "representor"
151 /* Device parameter to configure the maximum number of dump files per queue. */
152 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
154 /* Configure timeout of LRO session (in microseconds). */
155 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
158 * Device parameter to configure the total data buffer size for a single
159 * hairpin queue (logarithm value).
161 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
163 /* Flow memory reclaim mode. */
164 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
166 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
168 /* Shared memory between primary and secondary processes. */
169 struct mlx5_shared_data *mlx5_shared_data;
171 /* Spinlock for mlx5_shared_data allocation. */
172 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
174 /* Process local data for secondary processes. */
175 static struct mlx5_local_data mlx5_local_data;
176 /** Driver-specific log messages type. */
179 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
180 LIST_HEAD_INITIALIZER();
181 static pthread_mutex_t mlx5_dev_ctx_list_mutex = PTHREAD_MUTEX_INITIALIZER;
183 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
184 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
186 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
192 .malloc = rte_malloc_socket,
194 .type = "mlx5_encap_decap_ipool",
197 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
203 .malloc = rte_malloc_socket,
205 .type = "mlx5_push_vlan_ipool",
208 .size = sizeof(struct mlx5_flow_dv_tag_resource),
214 .malloc = rte_malloc_socket,
216 .type = "mlx5_tag_ipool",
219 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
225 .malloc = rte_malloc_socket,
227 .type = "mlx5_port_id_ipool",
230 .size = sizeof(struct mlx5_flow_tbl_data_entry),
236 .malloc = rte_malloc_socket,
238 .type = "mlx5_jump_ipool",
242 .size = sizeof(struct mlx5_flow_meter),
248 .malloc = rte_malloc_socket,
250 .type = "mlx5_meter_ipool",
253 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
259 .malloc = rte_malloc_socket,
261 .type = "mlx5_mcp_ipool",
264 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
270 .malloc = rte_malloc_socket,
272 .type = "mlx5_hrxq_ipool",
276 * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
277 * It set in run time according to PCI function configuration.
285 .malloc = rte_malloc_socket,
287 .type = "mlx5_flow_handle_ipool",
290 .size = sizeof(struct rte_flow),
294 .malloc = rte_malloc_socket,
296 .type = "rte_flow_ipool",
301 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
302 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
304 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
307 * Allocate ID pool structure.
310 * The maximum id can be allocated from the pool.
313 * Pointer to pool object, NULL value otherwise.
315 struct mlx5_flow_id_pool *
316 mlx5_flow_id_pool_alloc(uint32_t max_id)
318 struct mlx5_flow_id_pool *pool;
321 pool = rte_zmalloc("id pool allocation", sizeof(*pool),
322 RTE_CACHE_LINE_SIZE);
324 DRV_LOG(ERR, "can't allocate id pool");
328 mem = rte_zmalloc("", MLX5_FLOW_MIN_ID_POOL_SIZE * sizeof(uint32_t),
329 RTE_CACHE_LINE_SIZE);
331 DRV_LOG(ERR, "can't allocate mem for id pool");
335 pool->free_arr = mem;
336 pool->curr = pool->free_arr;
337 pool->last = pool->free_arr + MLX5_FLOW_MIN_ID_POOL_SIZE;
338 pool->base_index = 0;
339 pool->max_id = max_id;
347 * Release ID pool structure.
350 * Pointer to flow id pool object to free.
353 mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool)
355 rte_free(pool->free_arr);
363 * Pointer to flow id pool.
368 * 0 on success, error value otherwise.
371 mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id)
373 if (pool->curr == pool->free_arr) {
374 if (pool->base_index == pool->max_id) {
376 DRV_LOG(ERR, "no free id");
379 *id = ++pool->base_index;
382 *id = *(--pool->curr);
390 * Pointer to flow id pool.
395 * 0 on success, error value otherwise.
398 mlx5_flow_id_release(struct mlx5_flow_id_pool *pool, uint32_t id)
404 if (pool->curr == pool->last) {
405 size = pool->curr - pool->free_arr;
406 size2 = size * MLX5_ID_GENERATION_ARRAY_FACTOR;
407 MLX5_ASSERT(size2 > size);
408 mem = rte_malloc("", size2 * sizeof(uint32_t), 0);
410 DRV_LOG(ERR, "can't allocate mem for id pool");
414 memcpy(mem, pool->free_arr, size * sizeof(uint32_t));
415 rte_free(pool->free_arr);
416 pool->free_arr = mem;
417 pool->curr = pool->free_arr + size;
418 pool->last = pool->free_arr + size2;
426 * Initialize the shared aging list information per port.
429 * Pointer to mlx5_dev_ctx_shared object.
432 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
435 struct mlx5_age_info *age_info;
437 for (i = 0; i < sh->max_port; i++) {
438 age_info = &sh->port[i].age_info;
440 TAILQ_INIT(&age_info->aged_counters);
441 rte_spinlock_init(&age_info->aged_sl);
442 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
447 * Initialize the counters management structure.
450 * Pointer to mlx5_dev_ctx_shared object to free
453 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
457 memset(&sh->cmng, 0, sizeof(sh->cmng));
458 TAILQ_INIT(&sh->cmng.flow_counters);
459 for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
460 TAILQ_INIT(&sh->cmng.ccont[i].pool_list);
461 rte_spinlock_init(&sh->cmng.ccont[i].resize_sl);
466 * Destroy all the resources allocated for a counter memory management.
469 * Pointer to the memory management structure.
472 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
474 uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
476 LIST_REMOVE(mng, next);
477 claim_zero(mlx5_devx_cmd_destroy(mng->dm));
478 claim_zero(mlx5_glue->devx_umem_dereg(mng->umem));
483 * Close and release all the resources of the counters management.
486 * Pointer to mlx5_dev_ctx_shared object to free.
489 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
491 struct mlx5_counter_stats_mem_mng *mng;
498 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
499 if (rte_errno != EINPROGRESS)
503 for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
504 struct mlx5_flow_counter_pool *pool;
505 uint32_t batch = !!(i > 1);
507 if (!sh->cmng.ccont[i].pools)
509 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
511 if (batch && pool->min_dcs)
512 claim_zero(mlx5_devx_cmd_destroy
514 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
515 if (MLX5_POOL_GET_CNT(pool, j)->action)
517 (mlx5_glue->destroy_flow_action
520 if (!batch && MLX5_GET_POOL_CNT_EXT
522 claim_zero(mlx5_devx_cmd_destroy
523 (MLX5_GET_POOL_CNT_EXT
526 TAILQ_REMOVE(&sh->cmng.ccont[i].pool_list, pool, next);
528 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
530 rte_free(sh->cmng.ccont[i].pools);
532 mng = LIST_FIRST(&sh->cmng.mem_mngs);
534 mlx5_flow_destroy_counter_stat_mem_mng(mng);
535 mng = LIST_FIRST(&sh->cmng.mem_mngs);
537 memset(&sh->cmng, 0, sizeof(sh->cmng));
541 * Initialize the flow resources' indexed mempool.
544 * Pointer to mlx5_dev_ctx_shared object.
546 * Pointer to user dev config.
549 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
550 const struct mlx5_dev_config *config)
553 struct mlx5_indexed_pool_config cfg;
555 for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
556 cfg = mlx5_ipool_cfg[i];
561 * Set MLX5_IPOOL_MLX5_FLOW ipool size
562 * according to PCI function flow configuration.
564 case MLX5_IPOOL_MLX5_FLOW:
565 cfg.size = config->dv_flow_en ?
566 sizeof(struct mlx5_flow_handle) :
567 MLX5_FLOW_HANDLE_VERBS_SIZE;
570 if (config->reclaim_mode)
571 cfg.release_mem_en = 1;
572 sh->ipool[i] = mlx5_ipool_create(&cfg);
577 * Release the flow resources' indexed mempool.
580 * Pointer to mlx5_dev_ctx_shared object.
583 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
587 for (i = 0; i < MLX5_IPOOL_MAX; ++i)
588 mlx5_ipool_destroy(sh->ipool[i]);
592 * Allocate shared device context. If there is multiport device the
593 * master and representors will share this context, if there is single
594 * port dedicated device, the context will be used by only given
595 * port due to unification.
597 * Routine first searches the context for the specified device name,
598 * if found the shared context assumed and reference counter is incremented.
599 * If no context found the new one is created and initialized with specified
600 * device context and parameters.
603 * Pointer to the device attributes (name, port, etc).
605 * Pointer to device configuration structure.
608 * Pointer to mlx5_dev_ctx_shared object on success,
609 * otherwise NULL and rte_errno is set.
611 struct mlx5_dev_ctx_shared *
612 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
613 const struct mlx5_dev_config *config)
615 struct mlx5_dev_ctx_shared *sh;
618 struct mlx5_devx_tis_attr tis_attr = { 0 };
621 /* Secondary process should not create the shared context. */
622 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
623 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
624 /* Search for IB context by device name. */
625 LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
626 if (!strcmp(sh->ibdev_name,
627 mlx5_os_get_dev_device_name(spawn->phys_dev))) {
632 /* No device found, we have to create new shared context. */
633 MLX5_ASSERT(spawn->max_port);
634 sh = rte_zmalloc("ethdev shared ib context",
635 sizeof(struct mlx5_dev_ctx_shared) +
637 sizeof(struct mlx5_dev_shared_port),
638 RTE_CACHE_LINE_SIZE);
640 DRV_LOG(ERR, "shared context allocation failure");
644 err = mlx5_os_open_device(spawn, config, sh);
647 err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
649 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
653 sh->max_port = spawn->max_port;
654 strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
655 sizeof(sh->ibdev_name) - 1);
656 strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
657 sizeof(sh->ibdev_path) - 1);
659 * Setting port_id to max unallowed value means
660 * there is no interrupt subhandler installed for
661 * the given port index i.
663 for (i = 0; i < sh->max_port; i++) {
664 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
665 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
667 sh->pd = mlx5_glue->alloc_pd(sh->ctx);
668 if (sh->pd == NULL) {
669 DRV_LOG(ERR, "PD allocation failure");
674 err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
676 DRV_LOG(ERR, "Fail to extract pdn from PD");
679 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
681 DRV_LOG(ERR, "TD allocation failure");
685 tis_attr.transport_domain = sh->td->id;
686 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
688 DRV_LOG(ERR, "TIS allocation failure");
693 sh->flow_id_pool = mlx5_flow_id_pool_alloc
694 ((1 << HAIRPIN_FLOW_ID_BITS) - 1);
695 if (!sh->flow_id_pool) {
696 DRV_LOG(ERR, "can't create flow id pool");
701 * Once the device is added to the list of memory event
702 * callback, its global MR cache table cannot be expanded
703 * on the fly because of deadlock. If it overflows, lookup
704 * should be done by searching MR list linearly, which is slow.
706 * At this point the device is not added to the memory
707 * event list yet, context is just being created.
709 err = mlx5_mr_btree_init(&sh->share_cache.cache,
710 MLX5_MR_BTREE_CACHE_N * 2,
711 spawn->pci_dev->device.numa_node);
716 mlx5_os_set_reg_mr_cb(&sh->share_cache.reg_mr_cb,
717 &sh->share_cache.dereg_mr_cb);
718 mlx5_os_dev_shared_handler_install(sh);
719 mlx5_flow_aging_init(sh);
720 mlx5_flow_counters_mng_init(sh);
721 mlx5_flow_ipool_create(sh, config);
722 /* Add device to memory callback list. */
723 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
724 LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
726 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
727 /* Add context to the global device list. */
728 LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
730 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
733 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
736 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
738 claim_zero(mlx5_devx_cmd_destroy(sh->td));
740 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
742 claim_zero(mlx5_glue->close_device(sh->ctx));
743 if (sh->flow_id_pool)
744 mlx5_flow_id_pool_release(sh->flow_id_pool);
746 MLX5_ASSERT(err > 0);
752 * Free shared IB device context. Decrement counter and if zero free
753 * all allocated resources and close handles.
756 * Pointer to mlx5_dev_ctx_shared object to free
759 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
761 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
762 #ifdef RTE_LIBRTE_MLX5_DEBUG
763 /* Check the object presence in the list. */
764 struct mlx5_dev_ctx_shared *lctx;
766 LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
771 DRV_LOG(ERR, "Freeing non-existing shared IB context");
776 MLX5_ASSERT(sh->refcnt);
777 /* Secondary process should not free the shared context. */
778 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
781 /* Remove from memory callback device list. */
782 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
783 LIST_REMOVE(sh, mem_event_cb);
784 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
785 /* Release created Memory Regions. */
786 mlx5_mr_release_cache(&sh->share_cache);
787 /* Remove context from the global device list. */
788 LIST_REMOVE(sh, next);
790 * Ensure there is no async event handler installed.
791 * Only primary process handles async device events.
793 mlx5_flow_counters_mng_close(sh);
794 mlx5_flow_ipool_destroy(sh);
795 mlx5_os_dev_shared_handler_uninstall(sh);
797 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
799 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
801 claim_zero(mlx5_devx_cmd_destroy(sh->td));
803 claim_zero(mlx5_glue->close_device(sh->ctx));
804 if (sh->flow_id_pool)
805 mlx5_flow_id_pool_release(sh->flow_id_pool);
808 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
812 * Destroy table hash list and all the root entries per domain.
815 * Pointer to the private device data structure.
818 mlx5_free_table_hash_list(struct mlx5_priv *priv)
820 struct mlx5_dev_ctx_shared *sh = priv->sh;
821 struct mlx5_flow_tbl_data_entry *tbl_data;
822 union mlx5_flow_tbl_key table_key = {
830 struct mlx5_hlist_entry *pos;
834 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
836 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
838 MLX5_ASSERT(tbl_data);
839 mlx5_hlist_remove(sh->flow_tbls, pos);
842 table_key.direction = 1;
843 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
845 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
847 MLX5_ASSERT(tbl_data);
848 mlx5_hlist_remove(sh->flow_tbls, pos);
851 table_key.direction = 0;
852 table_key.domain = 1;
853 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
855 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
857 MLX5_ASSERT(tbl_data);
858 mlx5_hlist_remove(sh->flow_tbls, pos);
861 mlx5_hlist_destroy(sh->flow_tbls, NULL, NULL);
865 * Initialize flow table hash list and create the root tables entry
869 * Pointer to the private device data structure.
872 * Zero on success, positive error code otherwise.
875 mlx5_alloc_table_hash_list(struct mlx5_priv *priv)
877 struct mlx5_dev_ctx_shared *sh = priv->sh;
878 char s[MLX5_HLIST_NAMESIZE];
882 snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
883 sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE);
884 if (!sh->flow_tbls) {
885 DRV_LOG(ERR, "flow tables with hash creation failed.\n");
889 #ifndef HAVE_MLX5DV_DR
891 * In case we have not DR support, the zero tables should be created
892 * because DV expect to see them even if they cannot be created by
895 union mlx5_flow_tbl_key table_key = {
903 struct mlx5_flow_tbl_data_entry *tbl_data = rte_zmalloc(NULL,
904 sizeof(*tbl_data), 0);
910 tbl_data->entry.key = table_key.v64;
911 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
914 rte_atomic32_init(&tbl_data->tbl.refcnt);
915 rte_atomic32_inc(&tbl_data->tbl.refcnt);
916 table_key.direction = 1;
917 tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
922 tbl_data->entry.key = table_key.v64;
923 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
926 rte_atomic32_init(&tbl_data->tbl.refcnt);
927 rte_atomic32_inc(&tbl_data->tbl.refcnt);
928 table_key.direction = 0;
929 table_key.domain = 1;
930 tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
935 tbl_data->entry.key = table_key.v64;
936 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
939 rte_atomic32_init(&tbl_data->tbl.refcnt);
940 rte_atomic32_inc(&tbl_data->tbl.refcnt);
943 mlx5_free_table_hash_list(priv);
944 #endif /* HAVE_MLX5DV_DR */
949 * Initialize shared data between primary and secondary process.
951 * A memzone is reserved by primary process and secondary processes attach to
955 * 0 on success, a negative errno value otherwise and rte_errno is set.
958 mlx5_init_shared_data(void)
960 const struct rte_memzone *mz;
963 rte_spinlock_lock(&mlx5_shared_data_lock);
964 if (mlx5_shared_data == NULL) {
965 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
966 /* Allocate shared memory. */
967 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
968 sizeof(*mlx5_shared_data),
972 "Cannot allocate mlx5 shared data");
976 mlx5_shared_data = mz->addr;
977 memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data));
978 rte_spinlock_init(&mlx5_shared_data->lock);
980 /* Lookup allocated shared memory. */
981 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA);
984 "Cannot attach mlx5 shared data");
988 mlx5_shared_data = mz->addr;
989 memset(&mlx5_local_data, 0, sizeof(mlx5_local_data));
993 rte_spinlock_unlock(&mlx5_shared_data_lock);
998 * Retrieve integer value from environment variable.
1001 * Environment variable name.
1004 * Integer value, 0 if the variable is not set.
1007 mlx5_getenv_int(const char *name)
1009 const char *val = getenv(name);
1017 * DPDK callback to add udp tunnel port
1020 * A pointer to eth_dev
1021 * @param[in] udp_tunnel
1022 * A pointer to udp tunnel
1025 * 0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1028 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1029 struct rte_eth_udp_tunnel *udp_tunnel)
1031 MLX5_ASSERT(udp_tunnel != NULL);
1032 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1033 udp_tunnel->udp_port == 4789)
1035 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1036 udp_tunnel->udp_port == 4790)
1042 * Initialize process private data structure.
1045 * Pointer to Ethernet device structure.
1048 * 0 on success, a negative errno value otherwise and rte_errno is set.
1051 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1053 struct mlx5_priv *priv = dev->data->dev_private;
1054 struct mlx5_proc_priv *ppriv;
1058 * UAR register table follows the process private structure. BlueFlame
1059 * registers for Tx queues are stored in the table.
1062 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1063 ppriv = rte_malloc_socket("mlx5_proc_priv", ppriv_size,
1064 RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1069 ppriv->uar_table_sz = ppriv_size;
1070 dev->process_private = ppriv;
1075 * Un-initialize process private data structure.
1078 * Pointer to Ethernet device structure.
1081 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1083 if (!dev->process_private)
1085 rte_free(dev->process_private);
1086 dev->process_private = NULL;
1090 * DPDK callback to close the device.
1092 * Destroy all queues and objects, free memory.
1095 * Pointer to Ethernet device structure.
1098 mlx5_dev_close(struct rte_eth_dev *dev)
1100 struct mlx5_priv *priv = dev->data->dev_private;
1104 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1105 /* Check if process_private released. */
1106 if (!dev->process_private)
1108 mlx5_tx_uar_uninit_secondary(dev);
1109 mlx5_proc_priv_uninit(dev);
1110 rte_eth_dev_release_port(dev);
1115 DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1117 ((priv->sh->ctx != NULL) ?
1118 mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
1120 * If default mreg copy action is removed at the stop stage,
1121 * the search will return none and nothing will be done anymore.
1123 mlx5_flow_stop_default(dev);
1124 mlx5_traffic_disable(dev);
1126 * If all the flows are already flushed in the device stop stage,
1127 * then this will return directly without any action.
1129 mlx5_flow_list_flush(dev, &priv->flows, true);
1130 mlx5_flow_meter_flush(dev, NULL);
1131 /* Free the intermediate buffers for flow creation. */
1132 mlx5_flow_free_intermediate(dev);
1133 /* Prevent crashes when queues are still in use. */
1134 dev->rx_pkt_burst = removed_rx_burst;
1135 dev->tx_pkt_burst = removed_tx_burst;
1137 /* Disable datapath on secondary process. */
1138 mlx5_mp_req_stop_rxtx(dev);
1139 if (priv->rxqs != NULL) {
1140 /* XXX race condition if mlx5_rx_burst() is still running. */
1142 for (i = 0; (i != priv->rxqs_n); ++i)
1143 mlx5_rxq_release(dev, i);
1147 if (priv->txqs != NULL) {
1148 /* XXX race condition if mlx5_tx_burst() is still running. */
1150 for (i = 0; (i != priv->txqs_n); ++i)
1151 mlx5_txq_release(dev, i);
1155 mlx5_proc_priv_uninit(dev);
1156 if (priv->mreg_cp_tbl)
1157 mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
1158 mlx5_mprq_free_mp(dev);
1159 mlx5_os_free_shared_dr(priv);
1160 if (priv->rss_conf.rss_key != NULL)
1161 rte_free(priv->rss_conf.rss_key);
1162 if (priv->reta_idx != NULL)
1163 rte_free(priv->reta_idx);
1164 if (priv->config.vf)
1165 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev),
1166 dev->data->mac_addrs,
1167 MLX5_MAX_MAC_ADDRESSES, priv->mac_own);
1168 if (priv->nl_socket_route >= 0)
1169 close(priv->nl_socket_route);
1170 if (priv->nl_socket_rdma >= 0)
1171 close(priv->nl_socket_rdma);
1172 if (priv->vmwa_context)
1173 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1174 ret = mlx5_hrxq_verify(dev);
1176 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1177 dev->data->port_id);
1178 ret = mlx5_ind_table_obj_verify(dev);
1180 DRV_LOG(WARNING, "port %u some indirection table still remain",
1181 dev->data->port_id);
1182 ret = mlx5_rxq_obj_verify(dev);
1184 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1185 dev->data->port_id);
1186 ret = mlx5_rxq_verify(dev);
1188 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1189 dev->data->port_id);
1190 ret = mlx5_txq_obj_verify(dev);
1192 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1193 dev->data->port_id);
1194 ret = mlx5_txq_verify(dev);
1196 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1197 dev->data->port_id);
1198 ret = mlx5_flow_verify(dev);
1200 DRV_LOG(WARNING, "port %u some flows still remain",
1201 dev->data->port_id);
1203 * Free the shared context in last turn, because the cleanup
1204 * routines above may use some shared fields, like
1205 * mlx5_nl_mac_addr_flush() uses ibdev_path for retrieveing
1206 * ifindex if Netlink fails.
1208 mlx5_free_shared_dev_ctx(priv->sh);
1209 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1213 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1214 struct mlx5_priv *opriv =
1215 rte_eth_devices[port_id].data->dev_private;
1218 opriv->domain_id != priv->domain_id ||
1219 &rte_eth_devices[port_id] == dev)
1225 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1227 memset(priv, 0, sizeof(*priv));
1228 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1230 * Reset mac_addrs to NULL such that it is not freed as part of
1231 * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1232 * it is freed when dev_private is freed.
1234 dev->data->mac_addrs = NULL;
1238 * Verify and store value for device argument.
1241 * Key argument to verify.
1243 * Value associated with key.
1248 * 0 on success, a negative errno value otherwise and rte_errno is set.
1251 mlx5_args_check(const char *key, const char *val, void *opaque)
1253 struct mlx5_dev_config *config = opaque;
1256 /* No-op, port representors are processed in mlx5_dev_spawn(). */
1257 if (!strcmp(MLX5_REPRESENTOR, key))
1260 tmp = strtoul(val, NULL, 0);
1263 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1266 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1267 config->cqe_comp = !!tmp;
1268 } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
1269 config->cqe_pad = !!tmp;
1270 } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1271 config->hw_padding = !!tmp;
1272 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1273 config->mprq.enabled = !!tmp;
1274 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1275 config->mprq.stride_num_n = tmp;
1276 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1277 config->mprq.stride_size_n = tmp;
1278 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1279 config->mprq.max_memcpy_len = tmp;
1280 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1281 config->mprq.min_rxqs_num = tmp;
1282 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1283 DRV_LOG(WARNING, "%s: deprecated parameter,"
1284 " converted to txq_inline_max", key);
1285 config->txq_inline_max = tmp;
1286 } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1287 config->txq_inline_max = tmp;
1288 } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1289 config->txq_inline_min = tmp;
1290 } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1291 config->txq_inline_mpw = tmp;
1292 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1293 config->txqs_inline = tmp;
1294 } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1295 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1296 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1297 config->mps = !!tmp;
1298 } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1299 if (tmp != MLX5_TXDB_CACHED &&
1300 tmp != MLX5_TXDB_NCACHED &&
1301 tmp != MLX5_TXDB_HEURISTIC) {
1302 DRV_LOG(ERR, "invalid Tx doorbell "
1303 "mapping parameter");
1308 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1309 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1310 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1311 DRV_LOG(WARNING, "%s: deprecated parameter,"
1312 " converted to txq_inline_mpw", key);
1313 config->txq_inline_mpw = tmp;
1314 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1315 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1316 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1317 config->rx_vec_en = !!tmp;
1318 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1319 config->l3_vxlan_en = !!tmp;
1320 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1321 config->vf_nl_en = !!tmp;
1322 } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1323 config->dv_esw_en = !!tmp;
1324 } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1325 config->dv_flow_en = !!tmp;
1326 } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1327 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1328 tmp != MLX5_XMETA_MODE_META16 &&
1329 tmp != MLX5_XMETA_MODE_META32) {
1330 DRV_LOG(ERR, "invalid extensive "
1331 "metadata parameter");
1335 config->dv_xmeta_en = tmp;
1336 } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1337 config->mr_ext_memseg_en = !!tmp;
1338 } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1339 config->max_dump_files_num = tmp;
1340 } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1341 config->lro.timeout = tmp;
1342 } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1343 DRV_LOG(DEBUG, "class argument is %s.", val);
1344 } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1345 config->log_hp_size = tmp;
1346 } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1347 if (tmp != MLX5_RCM_NONE &&
1348 tmp != MLX5_RCM_LIGHT &&
1349 tmp != MLX5_RCM_AGGR) {
1350 DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1354 config->reclaim_mode = tmp;
1356 DRV_LOG(WARNING, "%s: unknown parameter", key);
1364 * Parse device parameters.
1367 * Pointer to device configuration structure.
1369 * Device arguments structure.
1372 * 0 on success, a negative errno value otherwise and rte_errno is set.
1375 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1377 const char **params = (const char *[]){
1378 MLX5_RXQ_CQE_COMP_EN,
1379 MLX5_RXQ_CQE_PAD_EN,
1380 MLX5_RXQ_PKT_PAD_EN,
1382 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1383 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1384 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1387 MLX5_TXQ_INLINE_MIN,
1388 MLX5_TXQ_INLINE_MAX,
1389 MLX5_TXQ_INLINE_MPW,
1390 MLX5_TXQS_MIN_INLINE,
1393 MLX5_TXQ_MPW_HDR_DSEG_EN,
1394 MLX5_TXQ_MAX_INLINE_LEN,
1403 MLX5_MR_EXT_MEMSEG_EN,
1405 MLX5_MAX_DUMP_FILES_NUM,
1406 MLX5_LRO_TIMEOUT_USEC,
1407 MLX5_CLASS_ARG_NAME,
1412 struct rte_kvargs *kvlist;
1416 if (devargs == NULL)
1418 /* Following UGLY cast is done to pass checkpatch. */
1419 kvlist = rte_kvargs_parse(devargs->args, params);
1420 if (kvlist == NULL) {
1424 /* Process parameters. */
1425 for (i = 0; (params[i] != NULL); ++i) {
1426 if (rte_kvargs_count(kvlist, params[i])) {
1427 ret = rte_kvargs_process(kvlist, params[i],
1428 mlx5_args_check, config);
1431 rte_kvargs_free(kvlist);
1436 rte_kvargs_free(kvlist);
1441 * PMD global initialization.
1443 * Independent from individual device, this function initializes global
1444 * per-PMD data structures distinguishing primary and secondary processes.
1445 * Hence, each initialization is called once per a process.
1448 * 0 on success, a negative errno value otherwise and rte_errno is set.
1451 mlx5_init_once(void)
1453 struct mlx5_shared_data *sd;
1454 struct mlx5_local_data *ld = &mlx5_local_data;
1457 if (mlx5_init_shared_data())
1459 sd = mlx5_shared_data;
1461 rte_spinlock_lock(&sd->lock);
1462 switch (rte_eal_process_type()) {
1463 case RTE_PROC_PRIMARY:
1466 LIST_INIT(&sd->mem_event_cb_list);
1467 rte_rwlock_init(&sd->mem_event_rwlock);
1468 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
1469 mlx5_mr_mem_event_cb, NULL);
1470 ret = mlx5_mp_init_primary(MLX5_MP_NAME,
1471 mlx5_mp_primary_handle);
1474 sd->init_done = true;
1476 case RTE_PROC_SECONDARY:
1479 ret = mlx5_mp_init_secondary(MLX5_MP_NAME,
1480 mlx5_mp_secondary_handle);
1483 ++sd->secondary_cnt;
1484 ld->init_done = true;
1490 rte_spinlock_unlock(&sd->lock);
1495 * Configures the minimal amount of data to inline into WQE
1496 * while sending packets.
1498 * - the txq_inline_min has the maximal priority, if this
1499 * key is specified in devargs
1500 * - if DevX is enabled the inline mode is queried from the
1501 * device (HCA attributes and NIC vport context if needed).
1502 * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1503 * and none (0 bytes) for other NICs
1506 * Verbs device parameters (name, port, switch_info) to spawn.
1508 * Device configuration parameters.
1511 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1512 struct mlx5_dev_config *config)
1514 if (config->txq_inline_min != MLX5_ARG_UNSET) {
1515 /* Application defines size of inlined data explicitly. */
1516 switch (spawn->pci_dev->id.device_id) {
1517 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1518 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1519 if (config->txq_inline_min <
1520 (int)MLX5_INLINE_HSIZE_L2) {
1522 "txq_inline_mix aligned to minimal"
1523 " ConnectX-4 required value %d",
1524 (int)MLX5_INLINE_HSIZE_L2);
1525 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1531 if (config->hca_attr.eth_net_offloads) {
1532 /* We have DevX enabled, inline mode queried successfully. */
1533 switch (config->hca_attr.wqe_inline_mode) {
1534 case MLX5_CAP_INLINE_MODE_L2:
1535 /* outer L2 header must be inlined. */
1536 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1538 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1539 /* No inline data are required by NIC. */
1540 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1541 config->hw_vlan_insert =
1542 config->hca_attr.wqe_vlan_insert;
1543 DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1545 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1546 /* inline mode is defined by NIC vport context. */
1547 if (!config->hca_attr.eth_virt)
1549 switch (config->hca_attr.vport_inline_mode) {
1550 case MLX5_INLINE_MODE_NONE:
1551 config->txq_inline_min =
1552 MLX5_INLINE_HSIZE_NONE;
1554 case MLX5_INLINE_MODE_L2:
1555 config->txq_inline_min =
1556 MLX5_INLINE_HSIZE_L2;
1558 case MLX5_INLINE_MODE_IP:
1559 config->txq_inline_min =
1560 MLX5_INLINE_HSIZE_L3;
1562 case MLX5_INLINE_MODE_TCP_UDP:
1563 config->txq_inline_min =
1564 MLX5_INLINE_HSIZE_L4;
1566 case MLX5_INLINE_MODE_INNER_L2:
1567 config->txq_inline_min =
1568 MLX5_INLINE_HSIZE_INNER_L2;
1570 case MLX5_INLINE_MODE_INNER_IP:
1571 config->txq_inline_min =
1572 MLX5_INLINE_HSIZE_INNER_L3;
1574 case MLX5_INLINE_MODE_INNER_TCP_UDP:
1575 config->txq_inline_min =
1576 MLX5_INLINE_HSIZE_INNER_L4;
1582 * We get here if we are unable to deduce
1583 * inline data size with DevX. Try PCI ID
1584 * to determine old NICs.
1586 switch (spawn->pci_dev->id.device_id) {
1587 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1588 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1589 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
1590 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1591 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1592 config->hw_vlan_insert = 0;
1594 case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
1595 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1596 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
1597 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1599 * These NICs support VLAN insertion from WQE and
1600 * report the wqe_vlan_insert flag. But there is the bug
1601 * and PFC control may be broken, so disable feature.
1603 config->hw_vlan_insert = 0;
1604 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1607 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1611 DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
1615 * Configures the metadata mask fields in the shared context.
1618 * Pointer to Ethernet device.
1621 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
1623 struct mlx5_priv *priv = dev->data->dev_private;
1624 struct mlx5_dev_ctx_shared *sh = priv->sh;
1625 uint32_t meta, mark, reg_c0;
1627 reg_c0 = ~priv->vport_meta_mask;
1628 switch (priv->config.dv_xmeta_en) {
1629 case MLX5_XMETA_MODE_LEGACY:
1631 mark = MLX5_FLOW_MARK_MASK;
1633 case MLX5_XMETA_MODE_META16:
1634 meta = reg_c0 >> rte_bsf32(reg_c0);
1635 mark = MLX5_FLOW_MARK_MASK;
1637 case MLX5_XMETA_MODE_META32:
1639 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
1647 if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
1648 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
1649 sh->dv_mark_mask, mark);
1651 sh->dv_mark_mask = mark;
1652 if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
1653 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
1654 sh->dv_meta_mask, meta);
1656 sh->dv_meta_mask = meta;
1657 if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
1658 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
1659 sh->dv_meta_mask, reg_c0);
1661 sh->dv_regc0_mask = reg_c0;
1662 DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
1663 DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
1664 DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
1665 DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
1669 * Allocate page of door-bells and register it using DevX API.
1672 * Pointer to Ethernet device.
1675 * Pointer to new page on success, NULL otherwise.
1677 static struct mlx5_devx_dbr_page *
1678 mlx5_alloc_dbr_page(struct rte_eth_dev *dev)
1680 struct mlx5_priv *priv = dev->data->dev_private;
1681 struct mlx5_devx_dbr_page *page;
1683 /* Allocate space for door-bell page and management data. */
1684 page = rte_calloc_socket(__func__, 1, sizeof(struct mlx5_devx_dbr_page),
1685 RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1687 DRV_LOG(ERR, "port %u cannot allocate dbr page",
1688 dev->data->port_id);
1691 /* Register allocated memory. */
1692 page->umem = mlx5_glue->devx_umem_reg(priv->sh->ctx, page->dbrs,
1693 MLX5_DBR_PAGE_SIZE, 0);
1695 DRV_LOG(ERR, "port %u cannot umem reg dbr page",
1696 dev->data->port_id);
1704 * Find the next available door-bell, allocate new page if needed.
1707 * Pointer to Ethernet device.
1708 * @param [out] dbr_page
1709 * Door-bell page containing the page data.
1712 * Door-bell address offset on success, a negative error value otherwise.
1715 mlx5_get_dbr(struct rte_eth_dev *dev, struct mlx5_devx_dbr_page **dbr_page)
1717 struct mlx5_priv *priv = dev->data->dev_private;
1718 struct mlx5_devx_dbr_page *page = NULL;
1721 LIST_FOREACH(page, &priv->dbrpgs, next)
1722 if (page->dbr_count < MLX5_DBR_PER_PAGE)
1724 if (!page) { /* No page with free door-bell exists. */
1725 page = mlx5_alloc_dbr_page(dev);
1726 if (!page) /* Failed to allocate new page. */
1728 LIST_INSERT_HEAD(&priv->dbrpgs, page, next);
1730 /* Loop to find bitmap part with clear bit. */
1732 i < MLX5_DBR_BITMAP_SIZE && page->dbr_bitmap[i] == UINT64_MAX;
1735 /* Find the first clear bit. */
1736 MLX5_ASSERT(i < MLX5_DBR_BITMAP_SIZE);
1737 j = rte_bsf64(~page->dbr_bitmap[i]);
1738 page->dbr_bitmap[i] |= (UINT64_C(1) << j);
1741 return (((i * 64) + j) * sizeof(uint64_t));
1745 * Release a door-bell record.
1748 * Pointer to Ethernet device.
1749 * @param [in] umem_id
1750 * UMEM ID of page containing the door-bell record to release.
1751 * @param [in] offset
1752 * Offset of door-bell record in page.
1755 * 0 on success, a negative error value otherwise.
1758 mlx5_release_dbr(struct rte_eth_dev *dev, uint32_t umem_id, uint64_t offset)
1760 struct mlx5_priv *priv = dev->data->dev_private;
1761 struct mlx5_devx_dbr_page *page = NULL;
1764 LIST_FOREACH(page, &priv->dbrpgs, next)
1765 /* Find the page this address belongs to. */
1766 if (mlx5_os_get_umem_id(page->umem) == umem_id)
1771 if (!page->dbr_count) {
1772 /* Page not used, free it and remove from list. */
1773 LIST_REMOVE(page, next);
1775 ret = -mlx5_glue->devx_umem_dereg(page->umem);
1778 /* Mark in bitmap that this door-bell is not in use. */
1779 offset /= MLX5_DBR_SIZE;
1780 int i = offset / 64;
1781 int j = offset % 64;
1783 page->dbr_bitmap[i] &= ~(UINT64_C(1) << j);
1789 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
1791 static const char *const dynf_names[] = {
1792 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
1793 RTE_MBUF_DYNFLAG_METADATA_NAME
1797 if (n < RTE_DIM(dynf_names))
1799 for (i = 0; i < RTE_DIM(dynf_names); i++) {
1800 if (names[i] == NULL)
1802 strcpy(names[i], dynf_names[i]);
1804 return RTE_DIM(dynf_names);
1808 * Comparison callback to sort device data.
1810 * This is meant to be used with qsort().
1813 * Pointer to pointer to first data object.
1815 * Pointer to pointer to second data object.
1818 * 0 if both objects are equal, less than 0 if the first argument is less
1819 * than the second, greater than 0 otherwise.
1822 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
1823 struct mlx5_dev_config *config)
1825 struct mlx5_dev_ctx_shared *sh = priv->sh;
1826 struct mlx5_dev_config *sh_conf = NULL;
1830 /* Nothing to compare for the single/first device. */
1831 if (sh->refcnt == 1)
1833 /* Find the device with shared context. */
1834 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1835 struct mlx5_priv *opriv =
1836 rte_eth_devices[port_id].data->dev_private;
1838 if (opriv && opriv != priv && opriv->sh == sh) {
1839 sh_conf = &opriv->config;
1845 if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
1846 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
1847 " for shared %s context", sh->ibdev_name);
1851 if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
1852 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
1853 " for shared %s context", sh->ibdev_name);
1861 * Look for the ethernet device belonging to mlx5 driver.
1863 * @param[in] port_id
1864 * port_id to start looking for device.
1865 * @param[in] pci_dev
1866 * Pointer to the hint PCI device. When device is being probed
1867 * the its siblings (master and preceding representors might
1868 * not have assigned driver yet (because the mlx5_os_pci_probe()
1869 * is not completed yet, for this case match on hint PCI
1870 * device may be used to detect sibling device.
1873 * port_id of found device, RTE_MAX_ETHPORT if not found.
1876 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
1878 while (port_id < RTE_MAX_ETHPORTS) {
1879 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
1881 if (dev->state != RTE_ETH_DEV_UNUSED &&
1883 (dev->device == &pci_dev->device ||
1884 (dev->device->driver &&
1885 dev->device->driver->name &&
1886 !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
1890 if (port_id >= RTE_MAX_ETHPORTS)
1891 return RTE_MAX_ETHPORTS;
1896 * DPDK callback to remove a PCI device.
1898 * This function removes all Ethernet devices belong to a given PCI device.
1900 * @param[in] pci_dev
1901 * Pointer to the PCI device.
1904 * 0 on success, the function cannot fail.
1907 mlx5_pci_remove(struct rte_pci_device *pci_dev)
1911 RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
1913 * mlx5_dev_close() is not registered to secondary process,
1914 * call the close function explicitly for secondary process.
1916 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
1917 mlx5_dev_close(&rte_eth_devices[port_id]);
1919 rte_eth_dev_close(port_id);
1924 static const struct rte_pci_id mlx5_pci_id_map[] = {
1926 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1927 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
1930 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1931 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
1934 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1935 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
1938 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1939 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
1942 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1943 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
1946 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1947 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
1950 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1951 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
1954 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1955 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
1958 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1959 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
1962 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1963 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
1966 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1967 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
1970 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1971 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
1974 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1975 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
1978 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1979 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF)
1982 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1983 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
1990 struct rte_pci_driver mlx5_driver = {
1992 .name = MLX5_DRIVER_NAME
1994 .id_table = mlx5_pci_id_map,
1995 .probe = mlx5_os_pci_probe,
1996 .remove = mlx5_pci_remove,
1997 .dma_map = mlx5_dma_map,
1998 .dma_unmap = mlx5_dma_unmap,
1999 .drv_flags = PCI_DRV_FLAGS,
2003 * Driver initialization routine.
2005 RTE_INIT(rte_mlx5_pmd_init)
2007 /* Initialize driver log type. */
2008 mlx5_logtype = rte_log_register("pmd.net.mlx5");
2009 if (mlx5_logtype >= 0)
2010 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE);
2012 /* Build the static tables for Verbs conversion. */
2013 mlx5_set_ptype_table();
2014 mlx5_set_cksum_table();
2015 mlx5_set_swp_types_table();
2017 rte_pci_register(&mlx5_driver);
2020 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
2021 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
2022 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");