1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
16 #include <linux/rtnetlink.h>
19 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
21 #pragma GCC diagnostic ignored "-Wpedantic"
23 #include <infiniband/verbs.h>
25 #pragma GCC diagnostic error "-Wpedantic"
28 #include <rte_malloc.h>
29 #include <rte_ethdev_driver.h>
30 #include <rte_ethdev_pci.h>
32 #include <rte_bus_pci.h>
33 #include <rte_common.h>
34 #include <rte_config.h>
35 #include <rte_eal_memconfig.h>
36 #include <rte_kvargs.h>
39 #include "mlx5_utils.h"
40 #include "mlx5_rxtx.h"
41 #include "mlx5_autoconf.h"
42 #include "mlx5_defs.h"
43 #include "mlx5_glue.h"
45 /* Device parameter to enable RX completion queue compression. */
46 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
48 /* Device parameter to configure inline send. */
49 #define MLX5_TXQ_INLINE "txq_inline"
52 * Device parameter to configure the number of TX queues threshold for
53 * enabling inline send.
55 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
57 /* Device parameter to enable multi-packet send WQEs. */
58 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
60 /* Device parameter to include 2 dsegs in the title WQEBB. */
61 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
63 /* Device parameter to limit the size of inlining packet. */
64 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
66 /* Device parameter to enable hardware Tx vector. */
67 #define MLX5_TX_VEC_EN "tx_vec_en"
69 /* Device parameter to enable hardware Rx vector. */
70 #define MLX5_RX_VEC_EN "rx_vec_en"
72 /* Activate Netlink support in VF mode. */
73 #define MLX5_VF_NL_EN "vf_nl_en"
75 #ifndef HAVE_IBV_MLX5_MOD_MPW
76 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2)
77 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3)
80 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP
81 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4)
84 /** Driver-specific log messages type. */
88 * Retrieve integer value from environment variable.
91 * Environment variable name.
94 * Integer value, 0 if the variable is not set.
97 mlx5_getenv_int(const char *name)
99 const char *val = getenv(name);
107 * Verbs callback to allocate a memory. This function should allocate the space
108 * according to the size provided residing inside a huge page.
109 * Please note that all allocation must respect the alignment from libmlx5
110 * (i.e. currently sysconf(_SC_PAGESIZE)).
113 * The size in bytes of the memory to allocate.
115 * A pointer to the callback data.
118 * Allocated buffer, NULL otherwise and rte_errno is set.
121 mlx5_alloc_verbs_buf(size_t size, void *data)
123 struct priv *priv = data;
125 size_t alignment = sysconf(_SC_PAGESIZE);
126 unsigned int socket = SOCKET_ID_ANY;
128 if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) {
129 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
131 socket = ctrl->socket;
132 } else if (priv->verbs_alloc_ctx.type ==
133 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) {
134 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
136 socket = ctrl->socket;
138 assert(data != NULL);
139 ret = rte_malloc_socket(__func__, size, alignment, socket);
146 * Verbs callback to free a memory.
149 * A pointer to the memory to free.
151 * A pointer to the callback data.
154 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused)
156 assert(data != NULL);
161 * DPDK callback to close the device.
163 * Destroy all queues and objects, free memory.
166 * Pointer to Ethernet device structure.
169 mlx5_dev_close(struct rte_eth_dev *dev)
171 struct priv *priv = dev->data->dev_private;
175 DRV_LOG(DEBUG, "port %u closing device \"%s\"",
177 ((priv->ctx != NULL) ? priv->ctx->device->name : ""));
178 /* In case mlx5_dev_stop() has not been called. */
179 mlx5_dev_interrupt_handler_uninstall(dev);
180 mlx5_traffic_disable(dev);
181 /* Prevent crashes when queues are still in use. */
182 dev->rx_pkt_burst = removed_rx_burst;
183 dev->tx_pkt_burst = removed_tx_burst;
184 if (priv->rxqs != NULL) {
185 /* XXX race condition if mlx5_rx_burst() is still running. */
187 for (i = 0; (i != priv->rxqs_n); ++i)
188 mlx5_rxq_release(dev, i);
192 if (priv->txqs != NULL) {
193 /* XXX race condition if mlx5_tx_burst() is still running. */
195 for (i = 0; (i != priv->txqs_n); ++i)
196 mlx5_txq_release(dev, i);
200 if (priv->pd != NULL) {
201 assert(priv->ctx != NULL);
202 claim_zero(mlx5_glue->dealloc_pd(priv->pd));
203 claim_zero(mlx5_glue->close_device(priv->ctx));
205 assert(priv->ctx == NULL);
206 if (priv->rss_conf.rss_key != NULL)
207 rte_free(priv->rss_conf.rss_key);
208 if (priv->reta_idx != NULL)
209 rte_free(priv->reta_idx);
210 if (priv->primary_socket)
211 mlx5_socket_uninit(dev);
213 mlx5_nl_mac_addr_flush(dev);
214 if (priv->nl_socket >= 0)
215 close(priv->nl_socket);
216 ret = mlx5_hrxq_ibv_verify(dev);
218 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
220 ret = mlx5_ind_table_ibv_verify(dev);
222 DRV_LOG(WARNING, "port %u some indirection table still remain",
224 ret = mlx5_rxq_ibv_verify(dev);
226 DRV_LOG(WARNING, "port %u some Verbs Rx queue still remain",
228 ret = mlx5_rxq_verify(dev);
230 DRV_LOG(WARNING, "port %u some Rx queues still remain",
232 ret = mlx5_txq_ibv_verify(dev);
234 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
236 ret = mlx5_txq_verify(dev);
238 DRV_LOG(WARNING, "port %u some Tx queues still remain",
240 ret = mlx5_flow_verify(dev);
242 DRV_LOG(WARNING, "port %u some flows still remain",
244 ret = mlx5_mr_verify(dev);
246 DRV_LOG(WARNING, "port %u some memory region still remain",
248 memset(priv, 0, sizeof(*priv));
251 const struct eth_dev_ops mlx5_dev_ops = {
252 .dev_configure = mlx5_dev_configure,
253 .dev_start = mlx5_dev_start,
254 .dev_stop = mlx5_dev_stop,
255 .dev_set_link_down = mlx5_set_link_down,
256 .dev_set_link_up = mlx5_set_link_up,
257 .dev_close = mlx5_dev_close,
258 .promiscuous_enable = mlx5_promiscuous_enable,
259 .promiscuous_disable = mlx5_promiscuous_disable,
260 .allmulticast_enable = mlx5_allmulticast_enable,
261 .allmulticast_disable = mlx5_allmulticast_disable,
262 .link_update = mlx5_link_update,
263 .stats_get = mlx5_stats_get,
264 .stats_reset = mlx5_stats_reset,
265 .xstats_get = mlx5_xstats_get,
266 .xstats_reset = mlx5_xstats_reset,
267 .xstats_get_names = mlx5_xstats_get_names,
268 .dev_infos_get = mlx5_dev_infos_get,
269 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
270 .vlan_filter_set = mlx5_vlan_filter_set,
271 .rx_queue_setup = mlx5_rx_queue_setup,
272 .tx_queue_setup = mlx5_tx_queue_setup,
273 .rx_queue_release = mlx5_rx_queue_release,
274 .tx_queue_release = mlx5_tx_queue_release,
275 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
276 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
277 .mac_addr_remove = mlx5_mac_addr_remove,
278 .mac_addr_add = mlx5_mac_addr_add,
279 .mac_addr_set = mlx5_mac_addr_set,
280 .set_mc_addr_list = mlx5_set_mc_addr_list,
281 .mtu_set = mlx5_dev_set_mtu,
282 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
283 .vlan_offload_set = mlx5_vlan_offload_set,
284 .reta_update = mlx5_dev_rss_reta_update,
285 .reta_query = mlx5_dev_rss_reta_query,
286 .rss_hash_update = mlx5_rss_hash_update,
287 .rss_hash_conf_get = mlx5_rss_hash_conf_get,
288 .filter_ctrl = mlx5_dev_filter_ctrl,
289 .rx_descriptor_status = mlx5_rx_descriptor_status,
290 .tx_descriptor_status = mlx5_tx_descriptor_status,
291 .rx_queue_intr_enable = mlx5_rx_intr_enable,
292 .rx_queue_intr_disable = mlx5_rx_intr_disable,
293 .is_removed = mlx5_is_removed,
296 static const struct eth_dev_ops mlx5_dev_sec_ops = {
297 .stats_get = mlx5_stats_get,
298 .stats_reset = mlx5_stats_reset,
299 .xstats_get = mlx5_xstats_get,
300 .xstats_reset = mlx5_xstats_reset,
301 .xstats_get_names = mlx5_xstats_get_names,
302 .dev_infos_get = mlx5_dev_infos_get,
303 .rx_descriptor_status = mlx5_rx_descriptor_status,
304 .tx_descriptor_status = mlx5_tx_descriptor_status,
307 /* Available operators in flow isolated mode. */
308 const struct eth_dev_ops mlx5_dev_ops_isolate = {
309 .dev_configure = mlx5_dev_configure,
310 .dev_start = mlx5_dev_start,
311 .dev_stop = mlx5_dev_stop,
312 .dev_set_link_down = mlx5_set_link_down,
313 .dev_set_link_up = mlx5_set_link_up,
314 .dev_close = mlx5_dev_close,
315 .link_update = mlx5_link_update,
316 .stats_get = mlx5_stats_get,
317 .stats_reset = mlx5_stats_reset,
318 .xstats_get = mlx5_xstats_get,
319 .xstats_reset = mlx5_xstats_reset,
320 .xstats_get_names = mlx5_xstats_get_names,
321 .dev_infos_get = mlx5_dev_infos_get,
322 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
323 .vlan_filter_set = mlx5_vlan_filter_set,
324 .rx_queue_setup = mlx5_rx_queue_setup,
325 .tx_queue_setup = mlx5_tx_queue_setup,
326 .rx_queue_release = mlx5_rx_queue_release,
327 .tx_queue_release = mlx5_tx_queue_release,
328 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
329 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
330 .mac_addr_remove = mlx5_mac_addr_remove,
331 .mac_addr_add = mlx5_mac_addr_add,
332 .mac_addr_set = mlx5_mac_addr_set,
333 .set_mc_addr_list = mlx5_set_mc_addr_list,
334 .mtu_set = mlx5_dev_set_mtu,
335 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
336 .vlan_offload_set = mlx5_vlan_offload_set,
337 .filter_ctrl = mlx5_dev_filter_ctrl,
338 .rx_descriptor_status = mlx5_rx_descriptor_status,
339 .tx_descriptor_status = mlx5_tx_descriptor_status,
340 .rx_queue_intr_enable = mlx5_rx_intr_enable,
341 .rx_queue_intr_disable = mlx5_rx_intr_disable,
342 .is_removed = mlx5_is_removed,
346 struct rte_pci_addr pci_addr; /* associated PCI address */
347 uint32_t ports; /* physical ports bitfield. */
351 * Get device index in mlx5_dev[] from PCI bus address.
353 * @param[in] pci_addr
354 * PCI bus address to look for.
357 * mlx5_dev[] index on success, -1 on failure.
360 mlx5_dev_idx(struct rte_pci_addr *pci_addr)
365 assert(pci_addr != NULL);
366 for (i = 0; (i != RTE_DIM(mlx5_dev)); ++i) {
367 if ((mlx5_dev[i].pci_addr.domain == pci_addr->domain) &&
368 (mlx5_dev[i].pci_addr.bus == pci_addr->bus) &&
369 (mlx5_dev[i].pci_addr.devid == pci_addr->devid) &&
370 (mlx5_dev[i].pci_addr.function == pci_addr->function))
372 if ((mlx5_dev[i].ports == 0) && (ret == -1))
379 * Verify and store value for device argument.
382 * Key argument to verify.
384 * Value associated with key.
389 * 0 on success, a negative errno value otherwise and rte_errno is set.
392 mlx5_args_check(const char *key, const char *val, void *opaque)
394 struct mlx5_dev_config *config = opaque;
398 tmp = strtoul(val, NULL, 0);
401 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
404 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
405 config->cqe_comp = !!tmp;
406 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
407 config->txq_inline = tmp;
408 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
409 config->txqs_inline = tmp;
410 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
411 config->mps = !!tmp ? config->mps : 0;
412 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
413 config->mpw_hdr_dseg = !!tmp;
414 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
415 config->inline_max_packet_sz = tmp;
416 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
417 config->tx_vec_en = !!tmp;
418 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
419 config->rx_vec_en = !!tmp;
420 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
421 config->vf_nl_en = !!tmp;
423 DRV_LOG(WARNING, "%s: unknown parameter", key);
431 * Parse device parameters.
434 * Pointer to device configuration structure.
436 * Device arguments structure.
439 * 0 on success, a negative errno value otherwise and rte_errno is set.
442 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
444 const char **params = (const char *[]){
445 MLX5_RXQ_CQE_COMP_EN,
447 MLX5_TXQS_MIN_INLINE,
449 MLX5_TXQ_MPW_HDR_DSEG_EN,
450 MLX5_TXQ_MAX_INLINE_LEN,
456 struct rte_kvargs *kvlist;
462 /* Following UGLY cast is done to pass checkpatch. */
463 kvlist = rte_kvargs_parse(devargs->args, params);
466 /* Process parameters. */
467 for (i = 0; (params[i] != NULL); ++i) {
468 if (rte_kvargs_count(kvlist, params[i])) {
469 ret = rte_kvargs_process(kvlist, params[i],
470 mlx5_args_check, config);
473 rte_kvargs_free(kvlist);
478 rte_kvargs_free(kvlist);
482 static struct rte_pci_driver mlx5_driver;
485 * Reserved UAR address space for TXQ UAR(hw doorbell) mapping, process
486 * local resource used by both primary and secondary to avoid duplicate
488 * The space has to be available on both primary and secondary process,
489 * TXQ UAR maps to this area using fixed mmap w/o double check.
491 static void *uar_base;
494 find_lower_va_bound(const struct rte_memseg_list *msl __rte_unused,
495 const struct rte_memseg *ms, void *arg)
502 *addr = RTE_MIN(*addr, ms->addr);
508 * Reserve UAR address space for primary process.
511 * Pointer to Ethernet device.
514 * 0 on success, a negative errno value otherwise and rte_errno is set.
517 mlx5_uar_init_primary(struct rte_eth_dev *dev)
519 struct priv *priv = dev->data->dev_private;
520 void *addr = (void *)0;
522 if (uar_base) { /* UAR address space mapped. */
523 priv->uar_base = uar_base;
526 /* find out lower bound of hugepage segments */
527 rte_memseg_walk(find_lower_va_bound, &addr);
529 /* keep distance to hugepages to minimize potential conflicts. */
530 addr = RTE_PTR_SUB(addr, MLX5_UAR_OFFSET + MLX5_UAR_SIZE);
531 /* anonymous mmap, no real memory consumption. */
532 addr = mmap(addr, MLX5_UAR_SIZE,
533 PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
534 if (addr == MAP_FAILED) {
536 "port %u failed to reserve UAR address space, please"
537 " adjust MLX5_UAR_SIZE or try --base-virtaddr",
542 /* Accept either same addr or a new addr returned from mmap if target
545 DRV_LOG(INFO, "port %u reserved UAR address space: %p",
546 dev->data->port_id, addr);
547 priv->uar_base = addr; /* for primary and secondary UAR re-mmap. */
548 uar_base = addr; /* process local, don't reserve again. */
553 * Reserve UAR address space for secondary process, align with
557 * Pointer to Ethernet device.
560 * 0 on success, a negative errno value otherwise and rte_errno is set.
563 mlx5_uar_init_secondary(struct rte_eth_dev *dev)
565 struct priv *priv = dev->data->dev_private;
568 assert(priv->uar_base);
569 if (uar_base) { /* already reserved. */
570 assert(uar_base == priv->uar_base);
573 /* anonymous mmap, no real memory consumption. */
574 addr = mmap(priv->uar_base, MLX5_UAR_SIZE,
575 PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
576 if (addr == MAP_FAILED) {
577 DRV_LOG(ERR, "port %u UAR mmap failed: %p size: %llu",
578 dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE);
582 if (priv->uar_base != addr) {
584 "port %u UAR address %p size %llu occupied, please"
585 " adjust MLX5_UAR_OFFSET or try EAL parameter"
587 dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE);
591 uar_base = addr; /* process local, don't reserve again */
592 DRV_LOG(INFO, "port %u reserved UAR address space: %p",
593 dev->data->port_id, addr);
598 * DPDK callback to register a PCI device.
600 * This function creates an Ethernet device for each port of a given
604 * PCI driver structure (mlx5_driver).
606 * PCI device information.
609 * 0 on success, a negative errno value otherwise and rte_errno is set.
612 mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
613 struct rte_pci_device *pci_dev)
615 struct ibv_device **list = NULL;
616 struct ibv_device *ibv_dev;
618 struct ibv_context *attr_ctx = NULL;
619 struct ibv_device_attr_ex device_attr;
622 unsigned int cqe_comp;
623 unsigned int tunnel_en = 0;
624 unsigned int swp = 0;
627 struct mlx5dv_context attrs_out = {0};
628 #ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT
629 struct ibv_counter_set_description cs_desc;
632 assert(pci_drv == &mlx5_driver);
633 /* Get mlx5_dev[] index. */
634 idx = mlx5_dev_idx(&pci_dev->addr);
636 DRV_LOG(ERR, "this driver cannot support any more adapters");
640 DRV_LOG(DEBUG, "using driver device index %d", idx);
641 /* Save PCI address. */
642 mlx5_dev[idx].pci_addr = pci_dev->addr;
643 list = mlx5_glue->get_device_list(&i);
649 "cannot list devices, is ib_uverbs loaded?");
654 * For each listed device, check related sysfs entry against
655 * the provided PCI ID.
658 struct rte_pci_addr pci_addr;
661 DRV_LOG(DEBUG, "checking device \"%s\"", list[i]->name);
662 if (mlx5_ibv_device_to_pci_addr(list[i], &pci_addr))
664 if ((pci_dev->addr.domain != pci_addr.domain) ||
665 (pci_dev->addr.bus != pci_addr.bus) ||
666 (pci_dev->addr.devid != pci_addr.devid) ||
667 (pci_dev->addr.function != pci_addr.function))
669 DRV_LOG(INFO, "PCI information matches, using device \"%s\"",
671 vf = ((pci_dev->id.device_id ==
672 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF) ||
673 (pci_dev->id.device_id ==
674 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF) ||
675 (pci_dev->id.device_id ==
676 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF) ||
677 (pci_dev->id.device_id ==
678 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF));
679 attr_ctx = mlx5_glue->open_device(list[i]);
684 if (attr_ctx == NULL) {
685 mlx5_glue->free_device_list(list);
689 "cannot access device, is mlx5_ib loaded?");
694 "cannot use device, are drivers up to date?");
699 DRV_LOG(DEBUG, "device opened");
700 #ifdef HAVE_IBV_MLX5_MOD_SWP
701 attrs_out.comp_mask |= MLX5DV_CONTEXT_MASK_SWP;
704 * Multi-packet send is supported by ConnectX-4 Lx PF as well
705 * as all ConnectX-5 devices.
707 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
708 attrs_out.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS;
710 mlx5_glue->dv_query_device(attr_ctx, &attrs_out);
711 if (attrs_out.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
712 if (attrs_out.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) {
713 DRV_LOG(DEBUG, "enhanced MPW is supported");
714 mps = MLX5_MPW_ENHANCED;
716 DRV_LOG(DEBUG, "MPW is supported");
720 DRV_LOG(DEBUG, "MPW isn't supported");
721 mps = MLX5_MPW_DISABLED;
723 #ifdef HAVE_IBV_MLX5_MOD_SWP
724 if (attrs_out.comp_mask | MLX5DV_CONTEXT_MASK_SWP)
725 swp = attrs_out.sw_parsing_caps.sw_parsing_offloads;
726 DRV_LOG(DEBUG, "SWP support: %u", swp);
728 if (RTE_CACHE_LINE_SIZE == 128 &&
729 !(attrs_out.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP))
733 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
734 if (attrs_out.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) {
735 tunnel_en = ((attrs_out.tunnel_offloads_caps &
736 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) &&
737 (attrs_out.tunnel_offloads_caps &
738 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE));
740 DRV_LOG(DEBUG, "tunnel offloading is %ssupported",
741 tunnel_en ? "" : "not ");
744 "tunnel offloading disabled due to old OFED/rdma-core version");
746 if (mlx5_glue->query_device_ex(attr_ctx, NULL, &device_attr)) {
750 DRV_LOG(INFO, "%u port(s) detected",
751 device_attr.orig_attr.phys_port_cnt);
752 for (i = 0; i < device_attr.orig_attr.phys_port_cnt; i++) {
753 char name[RTE_ETH_NAME_MAX_LEN];
755 uint32_t port = i + 1; /* ports are indexed from one */
756 uint32_t test = (1 << i);
757 struct ibv_context *ctx = NULL;
758 struct ibv_port_attr port_attr;
759 struct ibv_pd *pd = NULL;
760 struct priv *priv = NULL;
761 struct rte_eth_dev *eth_dev = NULL;
762 struct ibv_device_attr_ex device_attr_ex;
763 struct ether_addr mac;
764 struct mlx5_dev_config config = {
765 .cqe_comp = cqe_comp,
767 .tunnel_en = tunnel_en,
771 .txq_inline = MLX5_ARG_UNSET,
772 .txqs_inline = MLX5_ARG_UNSET,
773 .inline_max_packet_sz = MLX5_ARG_UNSET,
778 len = snprintf(name, sizeof(name), PCI_PRI_FMT,
779 pci_dev->addr.domain, pci_dev->addr.bus,
780 pci_dev->addr.devid, pci_dev->addr.function);
781 if (device_attr.orig_attr.phys_port_cnt > 1)
782 snprintf(name + len, sizeof(name), " port %u", i);
783 mlx5_dev[idx].ports |= test;
784 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
785 eth_dev = rte_eth_dev_attach_secondary(name);
786 if (eth_dev == NULL) {
787 DRV_LOG(ERR, "can not attach rte ethdev");
792 eth_dev->device = &pci_dev->device;
793 eth_dev->dev_ops = &mlx5_dev_sec_ops;
794 err = mlx5_uar_init_secondary(eth_dev);
797 /* Receive command fd from primary process */
798 err = mlx5_socket_connect(eth_dev);
801 /* Remap UAR for Tx queues. */
802 err = mlx5_tx_uar_remap(eth_dev, err);
806 * Ethdev pointer is still required as input since
807 * the primary device is not accessible from the
810 eth_dev->rx_pkt_burst =
811 mlx5_select_rx_function(eth_dev);
812 eth_dev->tx_pkt_burst =
813 mlx5_select_tx_function(eth_dev);
816 DRV_LOG(DEBUG, "using port %u (%08" PRIx32 ")", port, test);
817 ctx = mlx5_glue->open_device(ibv_dev);
822 /* Check port status. */
823 err = mlx5_glue->query_port(ctx, port, &port_attr);
825 DRV_LOG(ERR, "port query failed: %s", strerror(err));
828 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
830 "port %d is not configured in Ethernet mode",
835 if (port_attr.state != IBV_PORT_ACTIVE)
836 DRV_LOG(DEBUG, "port %d is not active: \"%s\" (%d)",
838 mlx5_glue->port_state_str(port_attr.state),
840 /* Allocate protection domain. */
841 pd = mlx5_glue->alloc_pd(ctx);
843 DRV_LOG(ERR, "PD allocation failure");
847 mlx5_dev[idx].ports |= test;
848 /* from rte_ethdev.c */
849 priv = rte_zmalloc("ethdev private structure",
851 RTE_CACHE_LINE_SIZE);
853 DRV_LOG(ERR, "priv allocation failure");
858 strncpy(priv->ibdev_path, priv->ctx->device->ibdev_path,
859 sizeof(priv->ibdev_path));
860 priv->device_attr = device_attr;
863 priv->mtu = ETHER_MTU;
864 err = mlx5_args(&config, pci_dev->device.devargs);
866 DRV_LOG(ERR, "failed to process device arguments: %s",
870 if (mlx5_glue->query_device_ex(ctx, NULL, &device_attr_ex)) {
871 DRV_LOG(ERR, "ibv_query_device_ex() failed");
875 config.hw_csum = !!(device_attr_ex.device_cap_flags_ex &
876 IBV_DEVICE_RAW_IP_CSUM);
877 DRV_LOG(DEBUG, "checksum offloading is %ssupported",
878 (config.hw_csum ? "" : "not "));
879 #ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT
880 config.flow_counter_en = !!(device_attr.max_counter_sets);
881 mlx5_glue->describe_counter_set(ctx, 0, &cs_desc);
883 "counter type = %d, num of cs = %ld, attributes = %d",
884 cs_desc.counter_type, cs_desc.num_of_cs,
887 config.ind_table_max_size =
888 device_attr_ex.rss_caps.max_rwq_indirection_table_size;
889 /* Remove this check once DPDK supports larger/variable
890 * indirection tables. */
891 if (config.ind_table_max_size >
892 (unsigned int)ETH_RSS_RETA_SIZE_512)
893 config.ind_table_max_size = ETH_RSS_RETA_SIZE_512;
894 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u",
895 config.ind_table_max_size);
896 config.hw_vlan_strip = !!(device_attr_ex.raw_packet_caps &
897 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
898 DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
899 (config.hw_vlan_strip ? "" : "not "));
901 config.hw_fcs_strip = !!(device_attr_ex.raw_packet_caps &
902 IBV_RAW_PACKET_CAP_SCATTER_FCS);
903 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported",
904 (config.hw_fcs_strip ? "" : "not "));
906 #ifdef HAVE_IBV_WQ_FLAG_RX_END_PADDING
907 config.hw_padding = !!device_attr_ex.rx_pad_end_addr_align;
910 "hardware Rx end alignment padding is %ssupported",
911 (config.hw_padding ? "" : "not "));
913 config.tso = ((device_attr_ex.tso_caps.max_tso > 0) &&
914 (device_attr_ex.tso_caps.supported_qpts &
915 (1 << IBV_QPT_RAW_PACKET)));
917 config.tso_max_payload_sz =
918 device_attr_ex.tso_caps.max_tso;
919 if (config.mps && !mps) {
921 "multi-packet send not supported on this device"
922 " (" MLX5_TXQ_MPW_EN ")");
926 DRV_LOG(INFO, "%s MPS is %s",
927 config.mps == MLX5_MPW_ENHANCED ? "enhanced " : "",
928 config.mps != MLX5_MPW_DISABLED ? "enabled" :
930 if (config.cqe_comp && !cqe_comp) {
931 DRV_LOG(WARNING, "Rx CQE compression isn't supported");
934 eth_dev = rte_eth_dev_allocate(name);
935 if (eth_dev == NULL) {
936 DRV_LOG(ERR, "can not allocate rte ethdev");
940 eth_dev->data->dev_private = priv;
942 eth_dev->data->mac_addrs = priv->mac;
943 eth_dev->device = &pci_dev->device;
944 rte_eth_copy_pci_info(eth_dev, pci_dev);
945 eth_dev->device->driver = &mlx5_driver.driver;
946 err = mlx5_uar_init_primary(eth_dev);
949 /* Configure the first MAC address by default. */
950 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) {
952 "port %u cannot get MAC address, is mlx5_en"
953 " loaded? (errno: %s)",
954 eth_dev->data->port_id, strerror(errno));
959 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x",
960 eth_dev->data->port_id,
961 mac.addr_bytes[0], mac.addr_bytes[1],
962 mac.addr_bytes[2], mac.addr_bytes[3],
963 mac.addr_bytes[4], mac.addr_bytes[5]);
966 char ifname[IF_NAMESIZE];
968 if (mlx5_get_ifname(eth_dev, &ifname) == 0)
969 DRV_LOG(DEBUG, "port %u ifname is \"%s\"",
970 eth_dev->data->port_id, ifname);
972 DRV_LOG(DEBUG, "port %u ifname is unknown",
973 eth_dev->data->port_id);
976 /* Get actual MTU if possible. */
977 err = mlx5_get_mtu(eth_dev, &priv->mtu);
980 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id,
983 * Initialize burst functions to prevent crashes before link-up.
985 eth_dev->rx_pkt_burst = removed_rx_burst;
986 eth_dev->tx_pkt_burst = removed_tx_burst;
987 eth_dev->dev_ops = &mlx5_dev_ops;
988 /* Register MAC address. */
989 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
990 priv->nl_socket = -1;
992 if (vf && config.vf_nl_en) {
993 priv->nl_socket = mlx5_nl_init(RTMGRP_LINK);
994 if (priv->nl_socket < 0)
995 priv->nl_socket = -1;
996 mlx5_nl_mac_addr_sync(eth_dev);
998 TAILQ_INIT(&priv->flows);
999 TAILQ_INIT(&priv->ctrl_flows);
1000 /* Hint libmlx5 to use PMD allocator for data plane resources */
1001 struct mlx5dv_ctx_allocators alctr = {
1002 .alloc = &mlx5_alloc_verbs_buf,
1003 .free = &mlx5_free_verbs_buf,
1006 mlx5_glue->dv_set_context_attr(ctx,
1007 MLX5DV_CTX_ATTR_BUF_ALLOCATORS,
1008 (void *)((uintptr_t)&alctr));
1009 /* Bring Ethernet device up. */
1010 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up",
1011 eth_dev->data->port_id);
1012 mlx5_set_link_up(eth_dev);
1014 * Even though the interrupt handler is not installed yet,
1015 * interrupts will still trigger on the asyn_fd from
1016 * Verbs context returned by ibv_open_device().
1018 mlx5_link_update(eth_dev, 0);
1019 /* Store device configuration on private structure. */
1020 priv->config = config;
1026 claim_zero(mlx5_glue->dealloc_pd(pd));
1028 claim_zero(mlx5_glue->close_device(ctx));
1032 * XXX if something went wrong in the loop above, there is a resource
1033 * leak (ctx, pd, priv, dpdk ethdev) but we can do nothing about it as
1034 * long as the dpdk does not provide a way to deallocate a ethdev and a
1035 * way to enumerate the registered ethdevs to free the previous ones.
1037 /* no port found, complain */
1038 if (!mlx5_dev[idx].ports) {
1044 claim_zero(mlx5_glue->close_device(attr_ctx));
1046 mlx5_glue->free_device_list(list);
1054 static const struct rte_pci_id mlx5_pci_id_map[] = {
1056 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1057 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
1060 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1061 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
1064 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1065 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
1068 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1069 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
1072 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1073 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
1076 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1077 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
1080 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1081 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
1084 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1085 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
1092 static struct rte_pci_driver mlx5_driver = {
1094 .name = MLX5_DRIVER_NAME
1096 .id_table = mlx5_pci_id_map,
1097 .probe = mlx5_pci_probe,
1098 .drv_flags = RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV,
1101 #ifdef RTE_LIBRTE_MLX5_DLOPEN_DEPS
1104 * Suffix RTE_EAL_PMD_PATH with "-glue".
1106 * This function performs a sanity check on RTE_EAL_PMD_PATH before
1107 * suffixing its last component.
1110 * Output buffer, should be large enough otherwise NULL is returned.
1115 * Pointer to @p buf or @p NULL in case suffix cannot be appended.
1118 mlx5_glue_path(char *buf, size_t size)
1120 static const char *const bad[] = { "/", ".", "..", NULL };
1121 const char *path = RTE_EAL_PMD_PATH;
1122 size_t len = strlen(path);
1126 while (len && path[len - 1] == '/')
1128 for (off = len; off && path[off - 1] != '/'; --off)
1130 for (i = 0; bad[i]; ++i)
1131 if (!strncmp(path + off, bad[i], (int)(len - off)))
1133 i = snprintf(buf, size, "%.*s-glue", (int)len, path);
1134 if (i == -1 || (size_t)i >= size)
1139 "unable to append \"-glue\" to last component of"
1140 " RTE_EAL_PMD_PATH (\"" RTE_EAL_PMD_PATH "\"),"
1141 " please re-configure DPDK");
1146 * Initialization routine for run-time dependency on rdma-core.
1149 mlx5_glue_init(void)
1151 char glue_path[sizeof(RTE_EAL_PMD_PATH) - 1 + sizeof("-glue")];
1152 const char *path[] = {
1154 * A basic security check is necessary before trusting
1155 * MLX5_GLUE_PATH, which may override RTE_EAL_PMD_PATH.
1157 (geteuid() == getuid() && getegid() == getgid() ?
1158 getenv("MLX5_GLUE_PATH") : NULL),
1160 * When RTE_EAL_PMD_PATH is set, use its glue-suffixed
1161 * variant, otherwise let dlopen() look up libraries on its
1164 (*RTE_EAL_PMD_PATH ?
1165 mlx5_glue_path(glue_path, sizeof(glue_path)) : ""),
1168 void *handle = NULL;
1172 while (!handle && i != RTE_DIM(path)) {
1181 end = strpbrk(path[i], ":;");
1183 end = path[i] + strlen(path[i]);
1184 len = end - path[i];
1189 ret = snprintf(name, sizeof(name), "%.*s%s" MLX5_GLUE,
1191 (!len || *(end - 1) == '/') ? "" : "/");
1194 if (sizeof(name) != (size_t)ret + 1)
1196 DRV_LOG(DEBUG, "looking for rdma-core glue as \"%s\"",
1198 handle = dlopen(name, RTLD_LAZY);
1209 DRV_LOG(WARNING, "cannot load glue library: %s", dlmsg);
1212 sym = dlsym(handle, "mlx5_glue");
1213 if (!sym || !*sym) {
1217 DRV_LOG(ERR, "cannot resolve glue symbol: %s", dlmsg);
1226 "cannot initialize PMD due to missing run-time dependency on"
1227 " rdma-core libraries (libibverbs, libmlx5)");
1234 * Driver initialization routine.
1236 RTE_INIT(rte_mlx5_pmd_init);
1238 rte_mlx5_pmd_init(void)
1240 /* Build the static tables for Verbs conversion. */
1241 mlx5_set_ptype_table();
1242 mlx5_set_cksum_table();
1243 mlx5_set_swp_types_table();
1245 * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use
1246 * huge pages. Calling ibv_fork_init() during init allows
1247 * applications to use fork() safely for purposes other than
1248 * using this PMD, which is not supported in forked processes.
1250 setenv("RDMAV_HUGEPAGES_SAFE", "1", 1);
1251 /* Match the size of Rx completion entry to the size of a cacheline. */
1252 if (RTE_CACHE_LINE_SIZE == 128)
1253 setenv("MLX5_CQE_SIZE", "128", 0);
1254 #ifdef RTE_LIBRTE_MLX5_DLOPEN_DEPS
1255 if (mlx5_glue_init())
1260 /* Glue structure must not contain any NULL pointers. */
1264 for (i = 0; i != sizeof(*mlx5_glue) / sizeof(void *); ++i)
1265 assert(((const void *const *)mlx5_glue)[i]);
1268 if (strcmp(mlx5_glue->version, MLX5_GLUE_VERSION)) {
1270 "rdma-core glue \"%s\" mismatch: \"%s\" is required",
1271 mlx5_glue->version, MLX5_GLUE_VERSION);
1274 mlx5_glue->fork_init();
1275 rte_pci_register(&mlx5_driver);
1278 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
1279 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
1280 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");
1282 /** Initialize driver log type. */
1283 RTE_INIT(vdev_netvsc_init_log)
1285 mlx5_logtype = rte_log_register("pmd.net.mlx5");
1286 if (mlx5_logtype >= 0)
1287 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE);