1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
14 #include <linux/rtnetlink.h>
17 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
19 #pragma GCC diagnostic ignored "-Wpedantic"
21 #include <infiniband/verbs.h>
23 #pragma GCC diagnostic error "-Wpedantic"
26 #include <rte_malloc.h>
27 #include <rte_ethdev_driver.h>
28 #include <rte_ethdev_pci.h>
30 #include <rte_bus_pci.h>
31 #include <rte_common.h>
32 #include <rte_kvargs.h>
33 #include <rte_rwlock.h>
34 #include <rte_spinlock.h>
35 #include <rte_string_fns.h>
36 #include <rte_alarm.h>
38 #include <mlx5_glue.h>
39 #include <mlx5_devx_cmds.h>
40 #include <mlx5_common.h>
42 #include "mlx5_defs.h"
44 #include "mlx5_utils.h"
45 #include "mlx5_rxtx.h"
46 #include "mlx5_autoconf.h"
48 #include "mlx5_flow.h"
49 #include "rte_pmd_mlx5.h"
51 /* Device parameter to enable RX completion queue compression. */
52 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
54 /* Device parameter to enable RX completion entry padding to 128B. */
55 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
57 /* Device parameter to enable padding Rx packet to cacheline size. */
58 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
60 /* Device parameter to enable Multi-Packet Rx queue. */
61 #define MLX5_RX_MPRQ_EN "mprq_en"
63 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
64 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
66 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
67 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
69 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
70 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
72 /* Device parameter to configure inline send. Deprecated, ignored.*/
73 #define MLX5_TXQ_INLINE "txq_inline"
75 /* Device parameter to limit packet size to inline with ordinary SEND. */
76 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
78 /* Device parameter to configure minimal data size to inline. */
79 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
81 /* Device parameter to limit packet size to inline with Enhanced MPW. */
82 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
85 * Device parameter to configure the number of TX queues threshold for
86 * enabling inline send.
88 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
91 * Device parameter to configure the number of TX queues threshold for
92 * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
94 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
96 /* Device parameter to enable multi-packet send WQEs. */
97 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
100 * Device parameter to force doorbell register mapping
101 * to non-cahed region eliminating the extra write memory barrier.
103 #define MLX5_TX_DB_NC "tx_db_nc"
106 * Device parameter to include 2 dsegs in the title WQEBB.
107 * Deprecated, ignored.
109 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
112 * Device parameter to limit the size of inlining packet.
113 * Deprecated, ignored.
115 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
118 * Device parameter to enable hardware Tx vector.
119 * Deprecated, ignored (no vectorized Tx routines anymore).
121 #define MLX5_TX_VEC_EN "tx_vec_en"
123 /* Device parameter to enable hardware Rx vector. */
124 #define MLX5_RX_VEC_EN "rx_vec_en"
126 /* Allow L3 VXLAN flow creation. */
127 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
129 /* Activate DV E-Switch flow steering. */
130 #define MLX5_DV_ESW_EN "dv_esw_en"
132 /* Activate DV flow steering. */
133 #define MLX5_DV_FLOW_EN "dv_flow_en"
135 /* Enable extensive flow metadata support. */
136 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
138 /* Activate Netlink support in VF mode. */
139 #define MLX5_VF_NL_EN "vf_nl_en"
141 /* Enable extending memsegs when creating a MR. */
142 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
144 /* Select port representors to instantiate. */
145 #define MLX5_REPRESENTOR "representor"
147 /* Device parameter to configure the maximum number of dump files per queue. */
148 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
150 /* Configure timeout of LRO session (in microseconds). */
151 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
154 * Device parameter to configure the total data buffer size for a single
155 * hairpin queue (logarithm value).
157 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
159 #ifndef HAVE_IBV_MLX5_MOD_MPW
160 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2)
161 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3)
164 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP
165 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4)
168 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
170 /* Shared memory between primary and secondary processes. */
171 struct mlx5_shared_data *mlx5_shared_data;
173 /* Spinlock for mlx5_shared_data allocation. */
174 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
176 /* Process local data for secondary processes. */
177 static struct mlx5_local_data mlx5_local_data;
179 /** Driver-specific log messages type. */
182 /** Data associated with devices to spawn. */
183 struct mlx5_dev_spawn_data {
184 uint32_t ifindex; /**< Network interface index. */
185 uint32_t max_port; /**< IB device maximal port index. */
186 uint32_t ibv_port; /**< IB device physical port index. */
187 int pf_bond; /**< bonding device PF index. < 0 - no bonding */
188 struct mlx5_switch_info info; /**< Switch information. */
189 struct ibv_device *ibv_dev; /**< Associated IB device. */
190 struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */
191 struct rte_pci_device *pci_dev; /**< Backend PCI device. */
194 static LIST_HEAD(, mlx5_ibv_shared) mlx5_ibv_list = LIST_HEAD_INITIALIZER();
195 static pthread_mutex_t mlx5_ibv_list_mutex = PTHREAD_MUTEX_INITIALIZER;
197 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
198 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
200 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
201 #define MLX5_TAGS_HLIST_ARRAY_SIZE 8192
204 * Allocate ID pool structure.
207 * The maximum id can be allocated from the pool.
210 * Pointer to pool object, NULL value otherwise.
212 struct mlx5_flow_id_pool *
213 mlx5_flow_id_pool_alloc(uint32_t max_id)
215 struct mlx5_flow_id_pool *pool;
218 pool = rte_zmalloc("id pool allocation", sizeof(*pool),
219 RTE_CACHE_LINE_SIZE);
221 DRV_LOG(ERR, "can't allocate id pool");
225 mem = rte_zmalloc("", MLX5_FLOW_MIN_ID_POOL_SIZE * sizeof(uint32_t),
226 RTE_CACHE_LINE_SIZE);
228 DRV_LOG(ERR, "can't allocate mem for id pool");
232 pool->free_arr = mem;
233 pool->curr = pool->free_arr;
234 pool->last = pool->free_arr + MLX5_FLOW_MIN_ID_POOL_SIZE;
235 pool->base_index = 0;
236 pool->max_id = max_id;
244 * Release ID pool structure.
247 * Pointer to flow id pool object to free.
250 mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool)
252 rte_free(pool->free_arr);
260 * Pointer to flow id pool.
265 * 0 on success, error value otherwise.
268 mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id)
270 if (pool->curr == pool->free_arr) {
271 if (pool->base_index == pool->max_id) {
273 DRV_LOG(ERR, "no free id");
276 *id = ++pool->base_index;
279 *id = *(--pool->curr);
287 * Pointer to flow id pool.
292 * 0 on success, error value otherwise.
295 mlx5_flow_id_release(struct mlx5_flow_id_pool *pool, uint32_t id)
301 if (pool->curr == pool->last) {
302 size = pool->curr - pool->free_arr;
303 size2 = size * MLX5_ID_GENERATION_ARRAY_FACTOR;
304 MLX5_ASSERT(size2 > size);
305 mem = rte_malloc("", size2 * sizeof(uint32_t), 0);
307 DRV_LOG(ERR, "can't allocate mem for id pool");
311 memcpy(mem, pool->free_arr, size * sizeof(uint32_t));
312 rte_free(pool->free_arr);
313 pool->free_arr = mem;
314 pool->curr = pool->free_arr + size;
315 pool->last = pool->free_arr + size2;
323 * Initialize the counters management structure.
326 * Pointer to mlx5_ibv_shared object to free
329 mlx5_flow_counters_mng_init(struct mlx5_ibv_shared *sh)
333 TAILQ_INIT(&sh->cmng.flow_counters);
334 for (i = 0; i < RTE_DIM(sh->cmng.ccont); ++i)
335 TAILQ_INIT(&sh->cmng.ccont[i].pool_list);
339 * Destroy all the resources allocated for a counter memory management.
342 * Pointer to the memory management structure.
345 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
347 uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
349 LIST_REMOVE(mng, next);
350 claim_zero(mlx5_devx_cmd_destroy(mng->dm));
351 claim_zero(mlx5_glue->devx_umem_dereg(mng->umem));
356 * Close and release all the resources of the counters management.
359 * Pointer to mlx5_ibv_shared object to free.
362 mlx5_flow_counters_mng_close(struct mlx5_ibv_shared *sh)
364 struct mlx5_counter_stats_mem_mng *mng;
371 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
372 if (rte_errno != EINPROGRESS)
376 for (i = 0; i < RTE_DIM(sh->cmng.ccont); ++i) {
377 struct mlx5_flow_counter_pool *pool;
378 uint32_t batch = !!(i % 2);
380 if (!sh->cmng.ccont[i].pools)
382 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
387 (mlx5_devx_cmd_destroy(pool->min_dcs));
389 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
390 if (pool->counters_raw[j].action)
392 (mlx5_glue->destroy_flow_action
393 (pool->counters_raw[j].action));
394 if (!batch && pool->counters_raw[j].dcs)
395 claim_zero(mlx5_devx_cmd_destroy
396 (pool->counters_raw[j].dcs));
398 TAILQ_REMOVE(&sh->cmng.ccont[i].pool_list, pool,
401 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
403 rte_free(sh->cmng.ccont[i].pools);
405 mng = LIST_FIRST(&sh->cmng.mem_mngs);
407 mlx5_flow_destroy_counter_stat_mem_mng(mng);
408 mng = LIST_FIRST(&sh->cmng.mem_mngs);
410 memset(&sh->cmng, 0, sizeof(sh->cmng));
414 * Extract pdn of PD object using DV API.
417 * Pointer to the verbs PD object.
419 * Pointer to the PD object number variable.
422 * 0 on success, error value otherwise.
424 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
426 mlx5_get_pdn(struct ibv_pd *pd __rte_unused, uint32_t *pdn __rte_unused)
428 struct mlx5dv_obj obj;
429 struct mlx5dv_pd pd_info;
433 obj.pd.out = &pd_info;
434 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD);
436 DRV_LOG(DEBUG, "Fail to get PD object info");
442 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
445 mlx5_config_doorbell_mapping_env(const struct mlx5_dev_config *config)
450 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
451 /* Get environment variable to store. */
452 env = getenv(MLX5_SHUT_UP_BF);
453 value = env ? !!strcmp(env, "0") : MLX5_ARG_UNSET;
454 if (config->dbnc == MLX5_ARG_UNSET)
455 setenv(MLX5_SHUT_UP_BF, MLX5_SHUT_UP_BF_DEFAULT, 1);
457 setenv(MLX5_SHUT_UP_BF,
458 config->dbnc == MLX5_TXDB_NCACHED ? "1" : "0", 1);
463 mlx5_restore_doorbell_mapping_env(int value)
465 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
466 /* Restore the original environment variable state. */
467 if (value == MLX5_ARG_UNSET)
468 unsetenv(MLX5_SHUT_UP_BF);
470 setenv(MLX5_SHUT_UP_BF, value ? "1" : "0", 1);
474 * Allocate shared IB device context. If there is multiport device the
475 * master and representors will share this context, if there is single
476 * port dedicated IB device, the context will be used by only given
477 * port due to unification.
479 * Routine first searches the context for the specified IB device name,
480 * if found the shared context assumed and reference counter is incremented.
481 * If no context found the new one is created and initialized with specified
482 * IB device context and parameters.
485 * Pointer to the IB device attributes (name, port, etc).
487 * Pointer to device configuration structure.
490 * Pointer to mlx5_ibv_shared object on success,
491 * otherwise NULL and rte_errno is set.
493 static struct mlx5_ibv_shared *
494 mlx5_alloc_shared_ibctx(const struct mlx5_dev_spawn_data *spawn,
495 const struct mlx5_dev_config *config)
497 struct mlx5_ibv_shared *sh;
501 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
502 struct mlx5_devx_tis_attr tis_attr = { 0 };
506 /* Secondary process should not create the shared context. */
507 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
508 pthread_mutex_lock(&mlx5_ibv_list_mutex);
509 /* Search for IB context by device name. */
510 LIST_FOREACH(sh, &mlx5_ibv_list, next) {
511 if (!strcmp(sh->ibdev_name, spawn->ibv_dev->name)) {
516 /* No device found, we have to create new shared context. */
517 MLX5_ASSERT(spawn->max_port);
518 sh = rte_zmalloc("ethdev shared ib context",
519 sizeof(struct mlx5_ibv_shared) +
521 sizeof(struct mlx5_ibv_shared_port),
522 RTE_CACHE_LINE_SIZE);
524 DRV_LOG(ERR, "shared context allocation failure");
529 * Configure environment variable "MLX5_BF_SHUT_UP"
530 * before the device creation. The rdma_core library
531 * checks the variable at device creation and
532 * stores the result internally.
534 dbmap_env = mlx5_config_doorbell_mapping_env(config);
535 /* Try to open IB device with DV first, then usual Verbs. */
537 sh->ctx = mlx5_glue->dv_open_device(spawn->ibv_dev);
540 DRV_LOG(DEBUG, "DevX is supported");
541 /* The device is created, no need for environment. */
542 mlx5_restore_doorbell_mapping_env(dbmap_env);
544 /* The environment variable is still configured. */
545 sh->ctx = mlx5_glue->open_device(spawn->ibv_dev);
546 err = errno ? errno : ENODEV;
548 * The environment variable is not needed anymore,
549 * all device creation attempts are completed.
551 mlx5_restore_doorbell_mapping_env(dbmap_env);
554 DRV_LOG(DEBUG, "DevX is NOT supported");
556 err = mlx5_glue->query_device_ex(sh->ctx, NULL, &sh->device_attr);
558 DRV_LOG(DEBUG, "ibv_query_device_ex() failed");
562 sh->max_port = spawn->max_port;
563 strncpy(sh->ibdev_name, sh->ctx->device->name,
564 sizeof(sh->ibdev_name));
565 strncpy(sh->ibdev_path, sh->ctx->device->ibdev_path,
566 sizeof(sh->ibdev_path));
567 pthread_mutex_init(&sh->intr_mutex, NULL);
569 * Setting port_id to max unallowed value means
570 * there is no interrupt subhandler installed for
571 * the given port index i.
573 for (i = 0; i < sh->max_port; i++) {
574 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
575 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
577 sh->pd = mlx5_glue->alloc_pd(sh->ctx);
578 if (sh->pd == NULL) {
579 DRV_LOG(ERR, "PD allocation failure");
583 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
585 err = mlx5_get_pdn(sh->pd, &sh->pdn);
587 DRV_LOG(ERR, "Fail to extract pdn from PD");
590 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
592 DRV_LOG(ERR, "TD allocation failure");
596 tis_attr.transport_domain = sh->td->id;
597 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
599 DRV_LOG(ERR, "TIS allocation failure");
604 sh->flow_id_pool = mlx5_flow_id_pool_alloc(UINT32_MAX);
605 if (!sh->flow_id_pool) {
606 DRV_LOG(ERR, "can't create flow id pool");
610 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
612 * Once the device is added to the list of memory event
613 * callback, its global MR cache table cannot be expanded
614 * on the fly because of deadlock. If it overflows, lookup
615 * should be done by searching MR list linearly, which is slow.
617 * At this point the device is not added to the memory
618 * event list yet, context is just being created.
620 err = mlx5_mr_btree_init(&sh->mr.cache,
621 MLX5_MR_BTREE_CACHE_N * 2,
622 spawn->pci_dev->device.numa_node);
627 mlx5_flow_counters_mng_init(sh);
628 /* Add device to memory callback list. */
629 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
630 LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
632 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
633 /* Add context to the global device list. */
634 LIST_INSERT_HEAD(&mlx5_ibv_list, sh, next);
636 pthread_mutex_unlock(&mlx5_ibv_list_mutex);
639 pthread_mutex_unlock(&mlx5_ibv_list_mutex);
642 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
644 claim_zero(mlx5_devx_cmd_destroy(sh->td));
646 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
648 claim_zero(mlx5_glue->close_device(sh->ctx));
649 if (sh->flow_id_pool)
650 mlx5_flow_id_pool_release(sh->flow_id_pool);
652 MLX5_ASSERT(err > 0);
658 * Free shared IB device context. Decrement counter and if zero free
659 * all allocated resources and close handles.
662 * Pointer to mlx5_ibv_shared object to free
665 mlx5_free_shared_ibctx(struct mlx5_ibv_shared *sh)
667 pthread_mutex_lock(&mlx5_ibv_list_mutex);
668 #ifdef RTE_LIBRTE_MLX5_DEBUG
669 /* Check the object presence in the list. */
670 struct mlx5_ibv_shared *lctx;
672 LIST_FOREACH(lctx, &mlx5_ibv_list, next)
677 DRV_LOG(ERR, "Freeing non-existing shared IB context");
682 MLX5_ASSERT(sh->refcnt);
683 /* Secondary process should not free the shared context. */
684 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
687 /* Remove from memory callback device list. */
688 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
689 LIST_REMOVE(sh, mem_event_cb);
690 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
691 /* Release created Memory Regions. */
693 /* Remove context from the global device list. */
694 LIST_REMOVE(sh, next);
696 * Ensure there is no async event handler installed.
697 * Only primary process handles async device events.
699 mlx5_flow_counters_mng_close(sh);
700 MLX5_ASSERT(!sh->intr_cnt);
702 mlx5_intr_callback_unregister
703 (&sh->intr_handle, mlx5_dev_interrupt_handler, sh);
704 #ifdef HAVE_MLX5_DEVX_ASYNC_SUPPORT
705 if (sh->devx_intr_cnt) {
706 if (sh->intr_handle_devx.fd)
707 rte_intr_callback_unregister(&sh->intr_handle_devx,
708 mlx5_dev_interrupt_handler_devx, sh);
710 mlx5dv_devx_destroy_cmd_comp(sh->devx_comp);
713 pthread_mutex_destroy(&sh->intr_mutex);
715 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
717 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
719 claim_zero(mlx5_devx_cmd_destroy(sh->td));
721 claim_zero(mlx5_glue->close_device(sh->ctx));
722 if (sh->flow_id_pool)
723 mlx5_flow_id_pool_release(sh->flow_id_pool);
726 pthread_mutex_unlock(&mlx5_ibv_list_mutex);
730 * Destroy table hash list and all the root entries per domain.
733 * Pointer to the private device data structure.
736 mlx5_free_table_hash_list(struct mlx5_priv *priv)
738 struct mlx5_ibv_shared *sh = priv->sh;
739 struct mlx5_flow_tbl_data_entry *tbl_data;
740 union mlx5_flow_tbl_key table_key = {
748 struct mlx5_hlist_entry *pos;
752 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
754 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
756 MLX5_ASSERT(tbl_data);
757 mlx5_hlist_remove(sh->flow_tbls, pos);
760 table_key.direction = 1;
761 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
763 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
765 MLX5_ASSERT(tbl_data);
766 mlx5_hlist_remove(sh->flow_tbls, pos);
769 table_key.direction = 0;
770 table_key.domain = 1;
771 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
773 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
775 MLX5_ASSERT(tbl_data);
776 mlx5_hlist_remove(sh->flow_tbls, pos);
779 mlx5_hlist_destroy(sh->flow_tbls, NULL, NULL);
783 * Initialize flow table hash list and create the root tables entry
787 * Pointer to the private device data structure.
790 * Zero on success, positive error code otherwise.
793 mlx5_alloc_table_hash_list(struct mlx5_priv *priv)
795 struct mlx5_ibv_shared *sh = priv->sh;
796 char s[MLX5_HLIST_NAMESIZE];
800 snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
801 sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE);
802 if (!sh->flow_tbls) {
803 DRV_LOG(ERR, "flow tables with hash creation failed.\n");
807 #ifndef HAVE_MLX5DV_DR
809 * In case we have not DR support, the zero tables should be created
810 * because DV expect to see them even if they cannot be created by
813 union mlx5_flow_tbl_key table_key = {
821 struct mlx5_flow_tbl_data_entry *tbl_data = rte_zmalloc(NULL,
822 sizeof(*tbl_data), 0);
828 tbl_data->entry.key = table_key.v64;
829 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
832 rte_atomic32_init(&tbl_data->tbl.refcnt);
833 rte_atomic32_inc(&tbl_data->tbl.refcnt);
834 table_key.direction = 1;
835 tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
840 tbl_data->entry.key = table_key.v64;
841 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
844 rte_atomic32_init(&tbl_data->tbl.refcnt);
845 rte_atomic32_inc(&tbl_data->tbl.refcnt);
846 table_key.direction = 0;
847 table_key.domain = 1;
848 tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
853 tbl_data->entry.key = table_key.v64;
854 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
857 rte_atomic32_init(&tbl_data->tbl.refcnt);
858 rte_atomic32_inc(&tbl_data->tbl.refcnt);
861 mlx5_free_table_hash_list(priv);
862 #endif /* HAVE_MLX5DV_DR */
867 * Initialize DR related data within private structure.
868 * Routine checks the reference counter and does actual
869 * resources creation/initialization only if counter is zero.
872 * Pointer to the private device data structure.
875 * Zero on success, positive error code otherwise.
878 mlx5_alloc_shared_dr(struct mlx5_priv *priv)
880 struct mlx5_ibv_shared *sh = priv->sh;
881 char s[MLX5_HLIST_NAMESIZE];
885 err = mlx5_alloc_table_hash_list(priv);
887 DRV_LOG(DEBUG, "sh->flow_tbls[%p] already created, reuse\n",
888 (void *)sh->flow_tbls);
891 /* Create tags hash list table. */
892 snprintf(s, sizeof(s), "%s_tags", sh->ibdev_name);
893 sh->tag_table = mlx5_hlist_create(s, MLX5_TAGS_HLIST_ARRAY_SIZE);
894 if (!sh->tag_table) {
895 DRV_LOG(ERR, "tags with hash creation failed.\n");
899 #ifdef HAVE_MLX5DV_DR
903 /* Shared DV/DR structures is already initialized. */
908 /* Reference counter is zero, we should initialize structures. */
909 domain = mlx5_glue->dr_create_domain(sh->ctx,
910 MLX5DV_DR_DOMAIN_TYPE_NIC_RX);
912 DRV_LOG(ERR, "ingress mlx5dv_dr_create_domain failed");
916 sh->rx_domain = domain;
917 domain = mlx5_glue->dr_create_domain(sh->ctx,
918 MLX5DV_DR_DOMAIN_TYPE_NIC_TX);
920 DRV_LOG(ERR, "egress mlx5dv_dr_create_domain failed");
924 pthread_mutex_init(&sh->dv_mutex, NULL);
925 sh->tx_domain = domain;
926 #ifdef HAVE_MLX5DV_DR_ESWITCH
927 if (priv->config.dv_esw_en) {
928 domain = mlx5_glue->dr_create_domain
929 (sh->ctx, MLX5DV_DR_DOMAIN_TYPE_FDB);
931 DRV_LOG(ERR, "FDB mlx5dv_dr_create_domain failed");
935 sh->fdb_domain = domain;
936 sh->esw_drop_action = mlx5_glue->dr_create_flow_action_drop();
939 sh->pop_vlan_action = mlx5_glue->dr_create_flow_action_pop_vlan();
940 #endif /* HAVE_MLX5DV_DR */
945 /* Rollback the created objects. */
947 mlx5_glue->dr_destroy_domain(sh->rx_domain);
948 sh->rx_domain = NULL;
951 mlx5_glue->dr_destroy_domain(sh->tx_domain);
952 sh->tx_domain = NULL;
954 if (sh->fdb_domain) {
955 mlx5_glue->dr_destroy_domain(sh->fdb_domain);
956 sh->fdb_domain = NULL;
958 if (sh->esw_drop_action) {
959 mlx5_glue->destroy_flow_action(sh->esw_drop_action);
960 sh->esw_drop_action = NULL;
962 if (sh->pop_vlan_action) {
963 mlx5_glue->destroy_flow_action(sh->pop_vlan_action);
964 sh->pop_vlan_action = NULL;
967 /* tags should be destroyed with flow before. */
968 mlx5_hlist_destroy(sh->tag_table, NULL, NULL);
969 sh->tag_table = NULL;
971 mlx5_free_table_hash_list(priv);
976 * Destroy DR related data within private structure.
979 * Pointer to the private device data structure.
982 mlx5_free_shared_dr(struct mlx5_priv *priv)
984 struct mlx5_ibv_shared *sh;
986 if (!priv->dr_shared)
991 #ifdef HAVE_MLX5DV_DR
992 MLX5_ASSERT(sh->dv_refcnt);
993 if (sh->dv_refcnt && --sh->dv_refcnt)
996 mlx5_glue->dr_destroy_domain(sh->rx_domain);
997 sh->rx_domain = NULL;
1000 mlx5_glue->dr_destroy_domain(sh->tx_domain);
1001 sh->tx_domain = NULL;
1003 #ifdef HAVE_MLX5DV_DR_ESWITCH
1004 if (sh->fdb_domain) {
1005 mlx5_glue->dr_destroy_domain(sh->fdb_domain);
1006 sh->fdb_domain = NULL;
1008 if (sh->esw_drop_action) {
1009 mlx5_glue->destroy_flow_action(sh->esw_drop_action);
1010 sh->esw_drop_action = NULL;
1013 if (sh->pop_vlan_action) {
1014 mlx5_glue->destroy_flow_action(sh->pop_vlan_action);
1015 sh->pop_vlan_action = NULL;
1017 pthread_mutex_destroy(&sh->dv_mutex);
1018 #endif /* HAVE_MLX5DV_DR */
1019 if (sh->tag_table) {
1020 /* tags should be destroyed with flow before. */
1021 mlx5_hlist_destroy(sh->tag_table, NULL, NULL);
1022 sh->tag_table = NULL;
1024 mlx5_free_table_hash_list(priv);
1028 * Initialize shared data between primary and secondary process.
1030 * A memzone is reserved by primary process and secondary processes attach to
1034 * 0 on success, a negative errno value otherwise and rte_errno is set.
1037 mlx5_init_shared_data(void)
1039 const struct rte_memzone *mz;
1042 rte_spinlock_lock(&mlx5_shared_data_lock);
1043 if (mlx5_shared_data == NULL) {
1044 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
1045 /* Allocate shared memory. */
1046 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
1047 sizeof(*mlx5_shared_data),
1051 "Cannot allocate mlx5 shared data");
1055 mlx5_shared_data = mz->addr;
1056 memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data));
1057 rte_spinlock_init(&mlx5_shared_data->lock);
1059 /* Lookup allocated shared memory. */
1060 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA);
1063 "Cannot attach mlx5 shared data");
1067 mlx5_shared_data = mz->addr;
1068 memset(&mlx5_local_data, 0, sizeof(mlx5_local_data));
1072 rte_spinlock_unlock(&mlx5_shared_data_lock);
1077 * Retrieve integer value from environment variable.
1080 * Environment variable name.
1083 * Integer value, 0 if the variable is not set.
1086 mlx5_getenv_int(const char *name)
1088 const char *val = getenv(name);
1096 * Verbs callback to allocate a memory. This function should allocate the space
1097 * according to the size provided residing inside a huge page.
1098 * Please note that all allocation must respect the alignment from libmlx5
1099 * (i.e. currently sysconf(_SC_PAGESIZE)).
1102 * The size in bytes of the memory to allocate.
1104 * A pointer to the callback data.
1107 * Allocated buffer, NULL otherwise and rte_errno is set.
1110 mlx5_alloc_verbs_buf(size_t size, void *data)
1112 struct mlx5_priv *priv = data;
1114 size_t alignment = sysconf(_SC_PAGESIZE);
1115 unsigned int socket = SOCKET_ID_ANY;
1117 if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) {
1118 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
1120 socket = ctrl->socket;
1121 } else if (priv->verbs_alloc_ctx.type ==
1122 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) {
1123 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
1125 socket = ctrl->socket;
1127 MLX5_ASSERT(data != NULL);
1128 ret = rte_malloc_socket(__func__, size, alignment, socket);
1135 * Verbs callback to free a memory.
1138 * A pointer to the memory to free.
1140 * A pointer to the callback data.
1143 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused)
1145 MLX5_ASSERT(data != NULL);
1150 * DPDK callback to add udp tunnel port
1153 * A pointer to eth_dev
1154 * @param[in] udp_tunnel
1155 * A pointer to udp tunnel
1158 * 0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1161 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1162 struct rte_eth_udp_tunnel *udp_tunnel)
1164 MLX5_ASSERT(udp_tunnel != NULL);
1165 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1166 udp_tunnel->udp_port == 4789)
1168 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1169 udp_tunnel->udp_port == 4790)
1175 * Initialize process private data structure.
1178 * Pointer to Ethernet device structure.
1181 * 0 on success, a negative errno value otherwise and rte_errno is set.
1184 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1186 struct mlx5_priv *priv = dev->data->dev_private;
1187 struct mlx5_proc_priv *ppriv;
1191 * UAR register table follows the process private structure. BlueFlame
1192 * registers for Tx queues are stored in the table.
1195 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1196 ppriv = rte_malloc_socket("mlx5_proc_priv", ppriv_size,
1197 RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1202 ppriv->uar_table_sz = ppriv_size;
1203 dev->process_private = ppriv;
1208 * Un-initialize process private data structure.
1211 * Pointer to Ethernet device structure.
1214 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1216 if (!dev->process_private)
1218 rte_free(dev->process_private);
1219 dev->process_private = NULL;
1223 * DPDK callback to close the device.
1225 * Destroy all queues and objects, free memory.
1228 * Pointer to Ethernet device structure.
1231 mlx5_dev_close(struct rte_eth_dev *dev)
1233 struct mlx5_priv *priv = dev->data->dev_private;
1237 DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1239 ((priv->sh->ctx != NULL) ? priv->sh->ctx->device->name : ""));
1240 /* In case mlx5_dev_stop() has not been called. */
1241 mlx5_dev_interrupt_handler_uninstall(dev);
1242 mlx5_dev_interrupt_handler_devx_uninstall(dev);
1244 * If default mreg copy action is removed at the stop stage,
1245 * the search will return none and nothing will be done anymore.
1247 mlx5_flow_stop_default(dev);
1248 mlx5_traffic_disable(dev);
1250 * If all the flows are already flushed in the device stop stage,
1251 * then this will return directly without any action.
1253 mlx5_flow_list_flush(dev, &priv->flows, true);
1254 mlx5_flow_meter_flush(dev, NULL);
1255 /* Free the intermediate buffers for flow creation. */
1256 mlx5_flow_free_intermediate(dev);
1257 /* Prevent crashes when queues are still in use. */
1258 dev->rx_pkt_burst = removed_rx_burst;
1259 dev->tx_pkt_burst = removed_tx_burst;
1261 /* Disable datapath on secondary process. */
1262 mlx5_mp_req_stop_rxtx(dev);
1263 if (priv->rxqs != NULL) {
1264 /* XXX race condition if mlx5_rx_burst() is still running. */
1266 for (i = 0; (i != priv->rxqs_n); ++i)
1267 mlx5_rxq_release(dev, i);
1271 if (priv->txqs != NULL) {
1272 /* XXX race condition if mlx5_tx_burst() is still running. */
1274 for (i = 0; (i != priv->txqs_n); ++i)
1275 mlx5_txq_release(dev, i);
1279 mlx5_proc_priv_uninit(dev);
1280 if (priv->mreg_cp_tbl)
1281 mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
1282 mlx5_mprq_free_mp(dev);
1283 mlx5_free_shared_dr(priv);
1284 if (priv->rss_conf.rss_key != NULL)
1285 rte_free(priv->rss_conf.rss_key);
1286 if (priv->reta_idx != NULL)
1287 rte_free(priv->reta_idx);
1288 if (priv->config.vf)
1289 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev),
1290 dev->data->mac_addrs,
1291 MLX5_MAX_MAC_ADDRESSES, priv->mac_own);
1292 if (priv->nl_socket_route >= 0)
1293 close(priv->nl_socket_route);
1294 if (priv->nl_socket_rdma >= 0)
1295 close(priv->nl_socket_rdma);
1296 if (priv->vmwa_context)
1297 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1300 * Free the shared context in last turn, because the cleanup
1301 * routines above may use some shared fields, like
1302 * mlx5_nl_mac_addr_flush() uses ibdev_path for retrieveing
1303 * ifindex if Netlink fails.
1305 mlx5_free_shared_ibctx(priv->sh);
1308 ret = mlx5_hrxq_verify(dev);
1310 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1311 dev->data->port_id);
1312 ret = mlx5_ind_table_obj_verify(dev);
1314 DRV_LOG(WARNING, "port %u some indirection table still remain",
1315 dev->data->port_id);
1316 ret = mlx5_rxq_obj_verify(dev);
1318 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1319 dev->data->port_id);
1320 ret = mlx5_rxq_verify(dev);
1322 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1323 dev->data->port_id);
1324 ret = mlx5_txq_obj_verify(dev);
1326 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1327 dev->data->port_id);
1328 ret = mlx5_txq_verify(dev);
1330 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1331 dev->data->port_id);
1332 ret = mlx5_flow_verify(dev);
1334 DRV_LOG(WARNING, "port %u some flows still remain",
1335 dev->data->port_id);
1336 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1340 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1341 struct mlx5_priv *opriv =
1342 rte_eth_devices[port_id].data->dev_private;
1345 opriv->domain_id != priv->domain_id ||
1346 &rte_eth_devices[port_id] == dev)
1352 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1354 memset(priv, 0, sizeof(*priv));
1355 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1357 * Reset mac_addrs to NULL such that it is not freed as part of
1358 * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1359 * it is freed when dev_private is freed.
1361 dev->data->mac_addrs = NULL;
1364 const struct eth_dev_ops mlx5_dev_ops = {
1365 .dev_configure = mlx5_dev_configure,
1366 .dev_start = mlx5_dev_start,
1367 .dev_stop = mlx5_dev_stop,
1368 .dev_set_link_down = mlx5_set_link_down,
1369 .dev_set_link_up = mlx5_set_link_up,
1370 .dev_close = mlx5_dev_close,
1371 .promiscuous_enable = mlx5_promiscuous_enable,
1372 .promiscuous_disable = mlx5_promiscuous_disable,
1373 .allmulticast_enable = mlx5_allmulticast_enable,
1374 .allmulticast_disable = mlx5_allmulticast_disable,
1375 .link_update = mlx5_link_update,
1376 .stats_get = mlx5_stats_get,
1377 .stats_reset = mlx5_stats_reset,
1378 .xstats_get = mlx5_xstats_get,
1379 .xstats_reset = mlx5_xstats_reset,
1380 .xstats_get_names = mlx5_xstats_get_names,
1381 .fw_version_get = mlx5_fw_version_get,
1382 .dev_infos_get = mlx5_dev_infos_get,
1383 .read_clock = mlx5_read_clock,
1384 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1385 .vlan_filter_set = mlx5_vlan_filter_set,
1386 .rx_queue_setup = mlx5_rx_queue_setup,
1387 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1388 .tx_queue_setup = mlx5_tx_queue_setup,
1389 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1390 .rx_queue_release = mlx5_rx_queue_release,
1391 .tx_queue_release = mlx5_tx_queue_release,
1392 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1393 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1394 .mac_addr_remove = mlx5_mac_addr_remove,
1395 .mac_addr_add = mlx5_mac_addr_add,
1396 .mac_addr_set = mlx5_mac_addr_set,
1397 .set_mc_addr_list = mlx5_set_mc_addr_list,
1398 .mtu_set = mlx5_dev_set_mtu,
1399 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1400 .vlan_offload_set = mlx5_vlan_offload_set,
1401 .reta_update = mlx5_dev_rss_reta_update,
1402 .reta_query = mlx5_dev_rss_reta_query,
1403 .rss_hash_update = mlx5_rss_hash_update,
1404 .rss_hash_conf_get = mlx5_rss_hash_conf_get,
1405 .filter_ctrl = mlx5_dev_filter_ctrl,
1406 .rx_descriptor_status = mlx5_rx_descriptor_status,
1407 .tx_descriptor_status = mlx5_tx_descriptor_status,
1408 .rxq_info_get = mlx5_rxq_info_get,
1409 .txq_info_get = mlx5_txq_info_get,
1410 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1411 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1412 .rx_queue_count = mlx5_rx_queue_count,
1413 .rx_queue_intr_enable = mlx5_rx_intr_enable,
1414 .rx_queue_intr_disable = mlx5_rx_intr_disable,
1415 .is_removed = mlx5_is_removed,
1416 .udp_tunnel_port_add = mlx5_udp_tunnel_port_add,
1417 .get_module_info = mlx5_get_module_info,
1418 .get_module_eeprom = mlx5_get_module_eeprom,
1419 .hairpin_cap_get = mlx5_hairpin_cap_get,
1420 .mtr_ops_get = mlx5_flow_meter_ops_get,
1423 /* Available operations from secondary process. */
1424 static const struct eth_dev_ops mlx5_dev_sec_ops = {
1425 .stats_get = mlx5_stats_get,
1426 .stats_reset = mlx5_stats_reset,
1427 .xstats_get = mlx5_xstats_get,
1428 .xstats_reset = mlx5_xstats_reset,
1429 .xstats_get_names = mlx5_xstats_get_names,
1430 .fw_version_get = mlx5_fw_version_get,
1431 .dev_infos_get = mlx5_dev_infos_get,
1432 .rx_descriptor_status = mlx5_rx_descriptor_status,
1433 .tx_descriptor_status = mlx5_tx_descriptor_status,
1434 .rxq_info_get = mlx5_rxq_info_get,
1435 .txq_info_get = mlx5_txq_info_get,
1436 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1437 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1438 .get_module_info = mlx5_get_module_info,
1439 .get_module_eeprom = mlx5_get_module_eeprom,
1442 /* Available operations in flow isolated mode. */
1443 const struct eth_dev_ops mlx5_dev_ops_isolate = {
1444 .dev_configure = mlx5_dev_configure,
1445 .dev_start = mlx5_dev_start,
1446 .dev_stop = mlx5_dev_stop,
1447 .dev_set_link_down = mlx5_set_link_down,
1448 .dev_set_link_up = mlx5_set_link_up,
1449 .dev_close = mlx5_dev_close,
1450 .promiscuous_enable = mlx5_promiscuous_enable,
1451 .promiscuous_disable = mlx5_promiscuous_disable,
1452 .allmulticast_enable = mlx5_allmulticast_enable,
1453 .allmulticast_disable = mlx5_allmulticast_disable,
1454 .link_update = mlx5_link_update,
1455 .stats_get = mlx5_stats_get,
1456 .stats_reset = mlx5_stats_reset,
1457 .xstats_get = mlx5_xstats_get,
1458 .xstats_reset = mlx5_xstats_reset,
1459 .xstats_get_names = mlx5_xstats_get_names,
1460 .fw_version_get = mlx5_fw_version_get,
1461 .dev_infos_get = mlx5_dev_infos_get,
1462 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1463 .vlan_filter_set = mlx5_vlan_filter_set,
1464 .rx_queue_setup = mlx5_rx_queue_setup,
1465 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1466 .tx_queue_setup = mlx5_tx_queue_setup,
1467 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1468 .rx_queue_release = mlx5_rx_queue_release,
1469 .tx_queue_release = mlx5_tx_queue_release,
1470 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1471 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1472 .mac_addr_remove = mlx5_mac_addr_remove,
1473 .mac_addr_add = mlx5_mac_addr_add,
1474 .mac_addr_set = mlx5_mac_addr_set,
1475 .set_mc_addr_list = mlx5_set_mc_addr_list,
1476 .mtu_set = mlx5_dev_set_mtu,
1477 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1478 .vlan_offload_set = mlx5_vlan_offload_set,
1479 .filter_ctrl = mlx5_dev_filter_ctrl,
1480 .rx_descriptor_status = mlx5_rx_descriptor_status,
1481 .tx_descriptor_status = mlx5_tx_descriptor_status,
1482 .rxq_info_get = mlx5_rxq_info_get,
1483 .txq_info_get = mlx5_txq_info_get,
1484 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1485 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1486 .rx_queue_intr_enable = mlx5_rx_intr_enable,
1487 .rx_queue_intr_disable = mlx5_rx_intr_disable,
1488 .is_removed = mlx5_is_removed,
1489 .get_module_info = mlx5_get_module_info,
1490 .get_module_eeprom = mlx5_get_module_eeprom,
1491 .hairpin_cap_get = mlx5_hairpin_cap_get,
1492 .mtr_ops_get = mlx5_flow_meter_ops_get,
1496 * Verify and store value for device argument.
1499 * Key argument to verify.
1501 * Value associated with key.
1506 * 0 on success, a negative errno value otherwise and rte_errno is set.
1509 mlx5_args_check(const char *key, const char *val, void *opaque)
1511 struct mlx5_dev_config *config = opaque;
1514 /* No-op, port representors are processed in mlx5_dev_spawn(). */
1515 if (!strcmp(MLX5_REPRESENTOR, key))
1518 tmp = strtoul(val, NULL, 0);
1521 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1524 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1525 config->cqe_comp = !!tmp;
1526 } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
1527 config->cqe_pad = !!tmp;
1528 } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1529 config->hw_padding = !!tmp;
1530 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1531 config->mprq.enabled = !!tmp;
1532 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1533 config->mprq.stride_num_n = tmp;
1534 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1535 config->mprq.max_memcpy_len = tmp;
1536 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1537 config->mprq.min_rxqs_num = tmp;
1538 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1539 DRV_LOG(WARNING, "%s: deprecated parameter,"
1540 " converted to txq_inline_max", key);
1541 config->txq_inline_max = tmp;
1542 } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1543 config->txq_inline_max = tmp;
1544 } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1545 config->txq_inline_min = tmp;
1546 } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1547 config->txq_inline_mpw = tmp;
1548 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1549 config->txqs_inline = tmp;
1550 } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1551 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1552 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1553 config->mps = !!tmp;
1554 } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1555 if (tmp != MLX5_TXDB_CACHED &&
1556 tmp != MLX5_TXDB_NCACHED &&
1557 tmp != MLX5_TXDB_HEURISTIC) {
1558 DRV_LOG(ERR, "invalid Tx doorbell "
1559 "mapping parameter");
1564 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1565 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1566 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1567 DRV_LOG(WARNING, "%s: deprecated parameter,"
1568 " converted to txq_inline_mpw", key);
1569 config->txq_inline_mpw = tmp;
1570 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1571 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1572 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1573 config->rx_vec_en = !!tmp;
1574 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1575 config->l3_vxlan_en = !!tmp;
1576 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1577 config->vf_nl_en = !!tmp;
1578 } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1579 config->dv_esw_en = !!tmp;
1580 } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1581 config->dv_flow_en = !!tmp;
1582 } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1583 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1584 tmp != MLX5_XMETA_MODE_META16 &&
1585 tmp != MLX5_XMETA_MODE_META32) {
1586 DRV_LOG(ERR, "invalid extensive "
1587 "metadata parameter");
1591 config->dv_xmeta_en = tmp;
1592 } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1593 config->mr_ext_memseg_en = !!tmp;
1594 } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1595 config->max_dump_files_num = tmp;
1596 } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1597 config->lro.timeout = tmp;
1598 } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1599 DRV_LOG(DEBUG, "class argument is %s.", val);
1600 } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1601 config->log_hp_size = tmp;
1603 DRV_LOG(WARNING, "%s: unknown parameter", key);
1611 * Parse device parameters.
1614 * Pointer to device configuration structure.
1616 * Device arguments structure.
1619 * 0 on success, a negative errno value otherwise and rte_errno is set.
1622 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1624 const char **params = (const char *[]){
1625 MLX5_RXQ_CQE_COMP_EN,
1626 MLX5_RXQ_CQE_PAD_EN,
1627 MLX5_RXQ_PKT_PAD_EN,
1629 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1630 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1633 MLX5_TXQ_INLINE_MIN,
1634 MLX5_TXQ_INLINE_MAX,
1635 MLX5_TXQ_INLINE_MPW,
1636 MLX5_TXQS_MIN_INLINE,
1639 MLX5_TXQ_MPW_HDR_DSEG_EN,
1640 MLX5_TXQ_MAX_INLINE_LEN,
1649 MLX5_MR_EXT_MEMSEG_EN,
1651 MLX5_MAX_DUMP_FILES_NUM,
1652 MLX5_LRO_TIMEOUT_USEC,
1653 MLX5_CLASS_ARG_NAME,
1657 struct rte_kvargs *kvlist;
1661 if (devargs == NULL)
1663 /* Following UGLY cast is done to pass checkpatch. */
1664 kvlist = rte_kvargs_parse(devargs->args, params);
1665 if (kvlist == NULL) {
1669 /* Process parameters. */
1670 for (i = 0; (params[i] != NULL); ++i) {
1671 if (rte_kvargs_count(kvlist, params[i])) {
1672 ret = rte_kvargs_process(kvlist, params[i],
1673 mlx5_args_check, config);
1676 rte_kvargs_free(kvlist);
1681 rte_kvargs_free(kvlist);
1685 static struct rte_pci_driver mlx5_driver;
1688 * PMD global initialization.
1690 * Independent from individual device, this function initializes global
1691 * per-PMD data structures distinguishing primary and secondary processes.
1692 * Hence, each initialization is called once per a process.
1695 * 0 on success, a negative errno value otherwise and rte_errno is set.
1698 mlx5_init_once(void)
1700 struct mlx5_shared_data *sd;
1701 struct mlx5_local_data *ld = &mlx5_local_data;
1704 if (mlx5_init_shared_data())
1706 sd = mlx5_shared_data;
1708 rte_spinlock_lock(&sd->lock);
1709 switch (rte_eal_process_type()) {
1710 case RTE_PROC_PRIMARY:
1713 LIST_INIT(&sd->mem_event_cb_list);
1714 rte_rwlock_init(&sd->mem_event_rwlock);
1715 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
1716 mlx5_mr_mem_event_cb, NULL);
1717 ret = mlx5_mp_init_primary();
1720 sd->init_done = true;
1722 case RTE_PROC_SECONDARY:
1725 ret = mlx5_mp_init_secondary();
1728 ++sd->secondary_cnt;
1729 ld->init_done = true;
1735 rte_spinlock_unlock(&sd->lock);
1740 * Configures the minimal amount of data to inline into WQE
1741 * while sending packets.
1743 * - the txq_inline_min has the maximal priority, if this
1744 * key is specified in devargs
1745 * - if DevX is enabled the inline mode is queried from the
1746 * device (HCA attributes and NIC vport context if needed).
1747 * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1748 * and none (0 bytes) for other NICs
1751 * Verbs device parameters (name, port, switch_info) to spawn.
1753 * Device configuration parameters.
1756 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1757 struct mlx5_dev_config *config)
1759 if (config->txq_inline_min != MLX5_ARG_UNSET) {
1760 /* Application defines size of inlined data explicitly. */
1761 switch (spawn->pci_dev->id.device_id) {
1762 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1763 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1764 if (config->txq_inline_min <
1765 (int)MLX5_INLINE_HSIZE_L2) {
1767 "txq_inline_mix aligned to minimal"
1768 " ConnectX-4 required value %d",
1769 (int)MLX5_INLINE_HSIZE_L2);
1770 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1776 if (config->hca_attr.eth_net_offloads) {
1777 /* We have DevX enabled, inline mode queried successfully. */
1778 switch (config->hca_attr.wqe_inline_mode) {
1779 case MLX5_CAP_INLINE_MODE_L2:
1780 /* outer L2 header must be inlined. */
1781 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1783 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1784 /* No inline data are required by NIC. */
1785 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1786 config->hw_vlan_insert =
1787 config->hca_attr.wqe_vlan_insert;
1788 DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1790 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1791 /* inline mode is defined by NIC vport context. */
1792 if (!config->hca_attr.eth_virt)
1794 switch (config->hca_attr.vport_inline_mode) {
1795 case MLX5_INLINE_MODE_NONE:
1796 config->txq_inline_min =
1797 MLX5_INLINE_HSIZE_NONE;
1799 case MLX5_INLINE_MODE_L2:
1800 config->txq_inline_min =
1801 MLX5_INLINE_HSIZE_L2;
1803 case MLX5_INLINE_MODE_IP:
1804 config->txq_inline_min =
1805 MLX5_INLINE_HSIZE_L3;
1807 case MLX5_INLINE_MODE_TCP_UDP:
1808 config->txq_inline_min =
1809 MLX5_INLINE_HSIZE_L4;
1811 case MLX5_INLINE_MODE_INNER_L2:
1812 config->txq_inline_min =
1813 MLX5_INLINE_HSIZE_INNER_L2;
1815 case MLX5_INLINE_MODE_INNER_IP:
1816 config->txq_inline_min =
1817 MLX5_INLINE_HSIZE_INNER_L3;
1819 case MLX5_INLINE_MODE_INNER_TCP_UDP:
1820 config->txq_inline_min =
1821 MLX5_INLINE_HSIZE_INNER_L4;
1827 * We get here if we are unable to deduce
1828 * inline data size with DevX. Try PCI ID
1829 * to determine old NICs.
1831 switch (spawn->pci_dev->id.device_id) {
1832 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1833 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1834 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
1835 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1836 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1837 config->hw_vlan_insert = 0;
1839 case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
1840 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1841 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
1842 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1844 * These NICs support VLAN insertion from WQE and
1845 * report the wqe_vlan_insert flag. But there is the bug
1846 * and PFC control may be broken, so disable feature.
1848 config->hw_vlan_insert = 0;
1849 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1852 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1856 DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
1860 * Configures the metadata mask fields in the shared context.
1863 * Pointer to Ethernet device.
1866 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
1868 struct mlx5_priv *priv = dev->data->dev_private;
1869 struct mlx5_ibv_shared *sh = priv->sh;
1870 uint32_t meta, mark, reg_c0;
1872 reg_c0 = ~priv->vport_meta_mask;
1873 switch (priv->config.dv_xmeta_en) {
1874 case MLX5_XMETA_MODE_LEGACY:
1876 mark = MLX5_FLOW_MARK_MASK;
1878 case MLX5_XMETA_MODE_META16:
1879 meta = reg_c0 >> rte_bsf32(reg_c0);
1880 mark = MLX5_FLOW_MARK_MASK;
1882 case MLX5_XMETA_MODE_META32:
1884 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
1892 if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
1893 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
1894 sh->dv_mark_mask, mark);
1896 sh->dv_mark_mask = mark;
1897 if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
1898 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
1899 sh->dv_meta_mask, meta);
1901 sh->dv_meta_mask = meta;
1902 if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
1903 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
1904 sh->dv_meta_mask, reg_c0);
1906 sh->dv_regc0_mask = reg_c0;
1907 DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
1908 DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
1909 DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
1910 DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
1914 * Allocate page of door-bells and register it using DevX API.
1917 * Pointer to Ethernet device.
1920 * Pointer to new page on success, NULL otherwise.
1922 static struct mlx5_devx_dbr_page *
1923 mlx5_alloc_dbr_page(struct rte_eth_dev *dev)
1925 struct mlx5_priv *priv = dev->data->dev_private;
1926 struct mlx5_devx_dbr_page *page;
1928 /* Allocate space for door-bell page and management data. */
1929 page = rte_calloc_socket(__func__, 1, sizeof(struct mlx5_devx_dbr_page),
1930 RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1932 DRV_LOG(ERR, "port %u cannot allocate dbr page",
1933 dev->data->port_id);
1936 /* Register allocated memory. */
1937 page->umem = mlx5_glue->devx_umem_reg(priv->sh->ctx, page->dbrs,
1938 MLX5_DBR_PAGE_SIZE, 0);
1940 DRV_LOG(ERR, "port %u cannot umem reg dbr page",
1941 dev->data->port_id);
1949 * Find the next available door-bell, allocate new page if needed.
1952 * Pointer to Ethernet device.
1953 * @param [out] dbr_page
1954 * Door-bell page containing the page data.
1957 * Door-bell address offset on success, a negative error value otherwise.
1960 mlx5_get_dbr(struct rte_eth_dev *dev, struct mlx5_devx_dbr_page **dbr_page)
1962 struct mlx5_priv *priv = dev->data->dev_private;
1963 struct mlx5_devx_dbr_page *page = NULL;
1966 LIST_FOREACH(page, &priv->dbrpgs, next)
1967 if (page->dbr_count < MLX5_DBR_PER_PAGE)
1969 if (!page) { /* No page with free door-bell exists. */
1970 page = mlx5_alloc_dbr_page(dev);
1971 if (!page) /* Failed to allocate new page. */
1973 LIST_INSERT_HEAD(&priv->dbrpgs, page, next);
1975 /* Loop to find bitmap part with clear bit. */
1977 i < MLX5_DBR_BITMAP_SIZE && page->dbr_bitmap[i] == UINT64_MAX;
1980 /* Find the first clear bit. */
1981 j = rte_bsf64(~page->dbr_bitmap[i]);
1982 MLX5_ASSERT(i < (MLX5_DBR_PER_PAGE / 64));
1983 page->dbr_bitmap[i] |= (1 << j);
1986 return (((i * 64) + j) * sizeof(uint64_t));
1990 * Release a door-bell record.
1993 * Pointer to Ethernet device.
1994 * @param [in] umem_id
1995 * UMEM ID of page containing the door-bell record to release.
1996 * @param [in] offset
1997 * Offset of door-bell record in page.
2000 * 0 on success, a negative error value otherwise.
2003 mlx5_release_dbr(struct rte_eth_dev *dev, uint32_t umem_id, uint64_t offset)
2005 struct mlx5_priv *priv = dev->data->dev_private;
2006 struct mlx5_devx_dbr_page *page = NULL;
2009 LIST_FOREACH(page, &priv->dbrpgs, next)
2010 /* Find the page this address belongs to. */
2011 if (page->umem->umem_id == umem_id)
2016 if (!page->dbr_count) {
2017 /* Page not used, free it and remove from list. */
2018 LIST_REMOVE(page, next);
2020 ret = -mlx5_glue->devx_umem_dereg(page->umem);
2023 /* Mark in bitmap that this door-bell is not in use. */
2024 offset /= MLX5_DBR_SIZE;
2025 int i = offset / 64;
2026 int j = offset % 64;
2028 page->dbr_bitmap[i] &= ~(1 << j);
2034 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
2036 static const char *const dynf_names[] = {
2037 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
2038 RTE_MBUF_DYNFLAG_METADATA_NAME
2042 if (n < RTE_DIM(dynf_names))
2044 for (i = 0; i < RTE_DIM(dynf_names); i++) {
2045 if (names[i] == NULL)
2047 strcpy(names[i], dynf_names[i]);
2049 return RTE_DIM(dynf_names);
2053 * Check sibling device configurations.
2055 * Sibling devices sharing the Infiniband device context
2056 * should have compatible configurations. This regards
2057 * representors and bonding slaves.
2060 * Private device descriptor.
2062 * Configuration of the device is going to be created.
2065 * 0 on success, EINVAL otherwise
2068 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
2069 struct mlx5_dev_config *config)
2071 struct mlx5_ibv_shared *sh = priv->sh;
2072 struct mlx5_dev_config *sh_conf = NULL;
2076 /* Nothing to compare for the single/first device. */
2077 if (sh->refcnt == 1)
2079 /* Find the device with shared context. */
2080 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
2081 struct mlx5_priv *opriv =
2082 rte_eth_devices[port_id].data->dev_private;
2084 if (opriv && opriv != priv && opriv->sh == sh) {
2085 sh_conf = &opriv->config;
2091 if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
2092 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
2093 " for shared %s context", sh->ibdev_name);
2097 if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
2098 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
2099 " for shared %s context", sh->ibdev_name);
2106 * Spawn an Ethernet device from Verbs information.
2109 * Backing DPDK device.
2111 * Verbs device parameters (name, port, switch_info) to spawn.
2113 * Device configuration parameters.
2116 * A valid Ethernet device object on success, NULL otherwise and rte_errno
2117 * is set. The following errors are defined:
2119 * EBUSY: device is not supposed to be spawned.
2120 * EEXIST: device is already spawned
2122 static struct rte_eth_dev *
2123 mlx5_dev_spawn(struct rte_device *dpdk_dev,
2124 struct mlx5_dev_spawn_data *spawn,
2125 struct mlx5_dev_config config)
2127 const struct mlx5_switch_info *switch_info = &spawn->info;
2128 struct mlx5_ibv_shared *sh = NULL;
2129 struct ibv_port_attr port_attr;
2130 struct mlx5dv_context dv_attr = { .comp_mask = 0 };
2131 struct rte_eth_dev *eth_dev = NULL;
2132 struct mlx5_priv *priv = NULL;
2134 unsigned int hw_padding = 0;
2136 unsigned int cqe_comp;
2137 unsigned int cqe_pad = 0;
2138 unsigned int tunnel_en = 0;
2139 unsigned int mpls_en = 0;
2140 unsigned int swp = 0;
2141 unsigned int mprq = 0;
2142 unsigned int mprq_min_stride_size_n = 0;
2143 unsigned int mprq_max_stride_size_n = 0;
2144 unsigned int mprq_min_stride_num_n = 0;
2145 unsigned int mprq_max_stride_num_n = 0;
2146 struct rte_ether_addr mac;
2147 char name[RTE_ETH_NAME_MAX_LEN];
2148 int own_domain_id = 0;
2151 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
2152 struct mlx5dv_devx_port devx_port = { .comp_mask = 0 };
2155 /* Determine if this port representor is supposed to be spawned. */
2156 if (switch_info->representor && dpdk_dev->devargs) {
2157 struct rte_eth_devargs eth_da;
2159 err = rte_eth_devargs_parse(dpdk_dev->devargs->args, ð_da);
2162 DRV_LOG(ERR, "failed to process device arguments: %s",
2163 strerror(rte_errno));
2166 for (i = 0; i < eth_da.nb_representor_ports; ++i)
2167 if (eth_da.representor_ports[i] ==
2168 (uint16_t)switch_info->port_name)
2170 if (i == eth_da.nb_representor_ports) {
2175 /* Build device name. */
2176 if (spawn->pf_bond < 0) {
2177 /* Single device. */
2178 if (!switch_info->representor)
2179 strlcpy(name, dpdk_dev->name, sizeof(name));
2181 snprintf(name, sizeof(name), "%s_representor_%u",
2182 dpdk_dev->name, switch_info->port_name);
2184 /* Bonding device. */
2185 if (!switch_info->representor)
2186 snprintf(name, sizeof(name), "%s_%s",
2187 dpdk_dev->name, spawn->ibv_dev->name);
2189 snprintf(name, sizeof(name), "%s_%s_representor_%u",
2190 dpdk_dev->name, spawn->ibv_dev->name,
2191 switch_info->port_name);
2193 /* check if the device is already spawned */
2194 if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) {
2198 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name);
2199 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
2200 eth_dev = rte_eth_dev_attach_secondary(name);
2201 if (eth_dev == NULL) {
2202 DRV_LOG(ERR, "can not attach rte ethdev");
2206 eth_dev->device = dpdk_dev;
2207 eth_dev->dev_ops = &mlx5_dev_sec_ops;
2208 err = mlx5_proc_priv_init(eth_dev);
2211 /* Receive command fd from primary process */
2212 err = mlx5_mp_req_verbs_cmd_fd(eth_dev);
2215 /* Remap UAR for Tx queues. */
2216 err = mlx5_tx_uar_init_secondary(eth_dev, err);
2220 * Ethdev pointer is still required as input since
2221 * the primary device is not accessible from the
2222 * secondary process.
2224 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev);
2225 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev);
2229 * Some parameters ("tx_db_nc" in particularly) are needed in
2230 * advance to create dv/verbs device context. We proceed the
2231 * devargs here to get ones, and later proceed devargs again
2232 * to override some hardware settings.
2234 err = mlx5_args(&config, dpdk_dev->devargs);
2237 DRV_LOG(ERR, "failed to process device arguments: %s",
2238 strerror(rte_errno));
2241 sh = mlx5_alloc_shared_ibctx(spawn, &config);
2244 config.devx = sh->devx;
2245 #ifdef HAVE_MLX5DV_DR_ACTION_DEST_DEVX_TIR
2246 config.dest_tir = 1;
2248 #ifdef HAVE_IBV_MLX5_MOD_SWP
2249 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP;
2252 * Multi-packet send is supported by ConnectX-4 Lx PF as well
2253 * as all ConnectX-5 devices.
2255 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
2256 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS;
2258 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
2259 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ;
2261 mlx5_glue->dv_query_device(sh->ctx, &dv_attr);
2262 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
2263 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) {
2264 DRV_LOG(DEBUG, "enhanced MPW is supported");
2265 mps = MLX5_MPW_ENHANCED;
2267 DRV_LOG(DEBUG, "MPW is supported");
2271 DRV_LOG(DEBUG, "MPW isn't supported");
2272 mps = MLX5_MPW_DISABLED;
2274 #ifdef HAVE_IBV_MLX5_MOD_SWP
2275 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP)
2276 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads;
2277 DRV_LOG(DEBUG, "SWP support: %u", swp);
2280 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
2281 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) {
2282 struct mlx5dv_striding_rq_caps mprq_caps =
2283 dv_attr.striding_rq_caps;
2285 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d",
2286 mprq_caps.min_single_stride_log_num_of_bytes);
2287 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d",
2288 mprq_caps.max_single_stride_log_num_of_bytes);
2289 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d",
2290 mprq_caps.min_single_wqe_log_num_of_strides);
2291 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d",
2292 mprq_caps.max_single_wqe_log_num_of_strides);
2293 DRV_LOG(DEBUG, "\tsupported_qpts: %d",
2294 mprq_caps.supported_qpts);
2295 DRV_LOG(DEBUG, "device supports Multi-Packet RQ");
2297 mprq_min_stride_size_n =
2298 mprq_caps.min_single_stride_log_num_of_bytes;
2299 mprq_max_stride_size_n =
2300 mprq_caps.max_single_stride_log_num_of_bytes;
2301 mprq_min_stride_num_n =
2302 mprq_caps.min_single_wqe_log_num_of_strides;
2303 mprq_max_stride_num_n =
2304 mprq_caps.max_single_wqe_log_num_of_strides;
2305 config.mprq.stride_num_n = RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,
2306 mprq_min_stride_num_n);
2309 if (RTE_CACHE_LINE_SIZE == 128 &&
2310 !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP))
2314 config.cqe_comp = cqe_comp;
2315 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD
2316 /* Whether device supports 128B Rx CQE padding. */
2317 cqe_pad = RTE_CACHE_LINE_SIZE == 128 &&
2318 (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_PAD);
2320 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
2321 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) {
2322 tunnel_en = ((dv_attr.tunnel_offloads_caps &
2323 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) &&
2324 (dv_attr.tunnel_offloads_caps &
2325 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE) &&
2326 (dv_attr.tunnel_offloads_caps &
2327 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE));
2329 DRV_LOG(DEBUG, "tunnel offloading is %ssupported",
2330 tunnel_en ? "" : "not ");
2333 "tunnel offloading disabled due to old OFED/rdma-core version");
2335 config.tunnel_en = tunnel_en;
2336 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
2337 mpls_en = ((dv_attr.tunnel_offloads_caps &
2338 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) &&
2339 (dv_attr.tunnel_offloads_caps &
2340 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP));
2341 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported",
2342 mpls_en ? "" : "not ");
2344 DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to"
2345 " old OFED/rdma-core version or firmware configuration");
2347 config.mpls_en = mpls_en;
2348 /* Check port status. */
2349 err = mlx5_glue->query_port(sh->ctx, spawn->ibv_port, &port_attr);
2351 DRV_LOG(ERR, "port query failed: %s", strerror(err));
2354 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
2355 DRV_LOG(ERR, "port is not configured in Ethernet mode");
2359 if (port_attr.state != IBV_PORT_ACTIVE)
2360 DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)",
2361 mlx5_glue->port_state_str(port_attr.state),
2363 /* Allocate private eth device data. */
2364 priv = rte_zmalloc("ethdev private structure",
2366 RTE_CACHE_LINE_SIZE);
2368 DRV_LOG(ERR, "priv allocation failure");
2373 priv->ibv_port = spawn->ibv_port;
2374 priv->pci_dev = spawn->pci_dev;
2375 priv->mtu = RTE_ETHER_MTU;
2377 /* Initialize UAR access locks for 32bit implementations. */
2378 rte_spinlock_init(&priv->uar_lock_cq);
2379 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
2380 rte_spinlock_init(&priv->uar_lock[i]);
2382 /* Some internal functions rely on Netlink sockets, open them now. */
2383 priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA);
2384 priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE);
2385 priv->representor = !!switch_info->representor;
2386 priv->master = !!switch_info->master;
2387 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
2388 priv->vport_meta_tag = 0;
2389 priv->vport_meta_mask = 0;
2390 priv->pf_bond = spawn->pf_bond;
2391 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
2393 * The DevX port query API is implemented. E-Switch may use
2394 * either vport or reg_c[0] metadata register to match on
2395 * vport index. The engaged part of metadata register is
2398 if (switch_info->representor || switch_info->master) {
2399 devx_port.comp_mask = MLX5DV_DEVX_PORT_VPORT |
2400 MLX5DV_DEVX_PORT_MATCH_REG_C_0;
2401 err = mlx5_glue->devx_port_query(sh->ctx, spawn->ibv_port,
2405 "can't query devx port %d on device %s",
2406 spawn->ibv_port, spawn->ibv_dev->name);
2407 devx_port.comp_mask = 0;
2410 if (devx_port.comp_mask & MLX5DV_DEVX_PORT_MATCH_REG_C_0) {
2411 priv->vport_meta_tag = devx_port.reg_c_0.value;
2412 priv->vport_meta_mask = devx_port.reg_c_0.mask;
2413 if (!priv->vport_meta_mask) {
2414 DRV_LOG(ERR, "vport zero mask for port %d"
2415 " on bonding device %s",
2416 spawn->ibv_port, spawn->ibv_dev->name);
2420 if (priv->vport_meta_tag & ~priv->vport_meta_mask) {
2421 DRV_LOG(ERR, "invalid vport tag for port %d"
2422 " on bonding device %s",
2423 spawn->ibv_port, spawn->ibv_dev->name);
2428 if (devx_port.comp_mask & MLX5DV_DEVX_PORT_VPORT) {
2429 priv->vport_id = devx_port.vport_num;
2430 } else if (spawn->pf_bond >= 0) {
2431 DRV_LOG(ERR, "can't deduce vport index for port %d"
2432 " on bonding device %s",
2433 spawn->ibv_port, spawn->ibv_dev->name);
2437 /* Suppose vport index in compatible way. */
2438 priv->vport_id = switch_info->representor ?
2439 switch_info->port_name + 1 : -1;
2443 * Kernel/rdma_core support single E-Switch per PF configurations
2444 * only and vport_id field contains the vport index for
2445 * associated VF, which is deduced from representor port name.
2446 * For example, let's have the IB device port 10, it has
2447 * attached network device eth0, which has port name attribute
2448 * pf0vf2, we can deduce the VF number as 2, and set vport index
2449 * as 3 (2+1). This assigning schema should be changed if the
2450 * multiple E-Switch instances per PF configurations or/and PCI
2451 * subfunctions are added.
2453 priv->vport_id = switch_info->representor ?
2454 switch_info->port_name + 1 : -1;
2456 /* representor_id field keeps the unmodified VF index. */
2457 priv->representor_id = switch_info->representor ?
2458 switch_info->port_name : -1;
2460 * Look for sibling devices in order to reuse their switch domain
2461 * if any, otherwise allocate one.
2463 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
2464 const struct mlx5_priv *opriv =
2465 rte_eth_devices[port_id].data->dev_private;
2468 opriv->sh != priv->sh ||
2470 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID)
2472 priv->domain_id = opriv->domain_id;
2475 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
2476 err = rte_eth_switch_domain_alloc(&priv->domain_id);
2479 DRV_LOG(ERR, "unable to allocate switch domain: %s",
2480 strerror(rte_errno));
2485 /* Override some values set by hardware configuration. */
2486 mlx5_args(&config, dpdk_dev->devargs);
2487 err = mlx5_dev_check_sibling_config(priv, &config);
2490 config.hw_csum = !!(sh->device_attr.device_cap_flags_ex &
2491 IBV_DEVICE_RAW_IP_CSUM);
2492 DRV_LOG(DEBUG, "checksum offloading is %ssupported",
2493 (config.hw_csum ? "" : "not "));
2494 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \
2495 !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
2496 DRV_LOG(DEBUG, "counters are not supported");
2498 #if !defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_MLX5DV_DR)
2499 if (config.dv_flow_en) {
2500 DRV_LOG(WARNING, "DV flow is not supported");
2501 config.dv_flow_en = 0;
2504 config.ind_table_max_size =
2505 sh->device_attr.rss_caps.max_rwq_indirection_table_size;
2507 * Remove this check once DPDK supports larger/variable
2508 * indirection tables.
2510 if (config.ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512)
2511 config.ind_table_max_size = ETH_RSS_RETA_SIZE_512;
2512 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u",
2513 config.ind_table_max_size);
2514 config.hw_vlan_strip = !!(sh->device_attr.raw_packet_caps &
2515 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
2516 DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
2517 (config.hw_vlan_strip ? "" : "not "));
2518 config.hw_fcs_strip = !!(sh->device_attr.raw_packet_caps &
2519 IBV_RAW_PACKET_CAP_SCATTER_FCS);
2520 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported",
2521 (config.hw_fcs_strip ? "" : "not "));
2522 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING)
2523 hw_padding = !!sh->device_attr.rx_pad_end_addr_align;
2524 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING)
2525 hw_padding = !!(sh->device_attr.device_cap_flags_ex &
2526 IBV_DEVICE_PCI_WRITE_END_PADDING);
2528 if (config.hw_padding && !hw_padding) {
2529 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported");
2530 config.hw_padding = 0;
2531 } else if (config.hw_padding) {
2532 DRV_LOG(DEBUG, "Rx end alignment padding is enabled");
2534 config.tso = (sh->device_attr.tso_caps.max_tso > 0 &&
2535 (sh->device_attr.tso_caps.supported_qpts &
2536 (1 << IBV_QPT_RAW_PACKET)));
2538 config.tso_max_payload_sz = sh->device_attr.tso_caps.max_tso;
2540 * MPW is disabled by default, while the Enhanced MPW is enabled
2543 if (config.mps == MLX5_ARG_UNSET)
2544 config.mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED :
2547 config.mps = config.mps ? mps : MLX5_MPW_DISABLED;
2548 DRV_LOG(INFO, "%sMPS is %s",
2549 config.mps == MLX5_MPW_ENHANCED ? "enhanced " :
2550 config.mps == MLX5_MPW ? "legacy " : "",
2551 config.mps != MLX5_MPW_DISABLED ? "enabled" : "disabled");
2552 if (config.cqe_comp && !cqe_comp) {
2553 DRV_LOG(WARNING, "Rx CQE compression isn't supported");
2554 config.cqe_comp = 0;
2556 if (config.cqe_pad && !cqe_pad) {
2557 DRV_LOG(WARNING, "Rx CQE padding isn't supported");
2559 } else if (config.cqe_pad) {
2560 DRV_LOG(INFO, "Rx CQE padding is enabled");
2563 priv->counter_fallback = 0;
2564 err = mlx5_devx_cmd_query_hca_attr(sh->ctx, &config.hca_attr);
2569 if (!config.hca_attr.flow_counters_dump)
2570 priv->counter_fallback = 1;
2571 #ifndef HAVE_IBV_DEVX_ASYNC
2572 priv->counter_fallback = 1;
2574 if (priv->counter_fallback)
2575 DRV_LOG(INFO, "Use fall-back DV counter management");
2576 /* Check for LRO support. */
2577 if (config.dest_tir && config.hca_attr.lro_cap &&
2578 config.dv_flow_en) {
2579 /* TBD check tunnel lro caps. */
2580 config.lro.supported = config.hca_attr.lro_cap;
2581 DRV_LOG(DEBUG, "Device supports LRO");
2583 * If LRO timeout is not configured by application,
2584 * use the minimal supported value.
2586 if (!config.lro.timeout)
2587 config.lro.timeout =
2588 config.hca_attr.lro_timer_supported_periods[0];
2589 DRV_LOG(DEBUG, "LRO session timeout set to %d usec",
2590 config.lro.timeout);
2592 #if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_METER)
2593 if (config.hca_attr.qos.sup && config.hca_attr.qos.srtcm_sup &&
2594 config.dv_flow_en) {
2595 uint8_t reg_c_mask =
2596 config.hca_attr.qos.flow_meter_reg_c_ids;
2598 * Meter needs two REG_C's for color match and pre-sfx
2599 * flow match. Here get the REG_C for color match.
2600 * REG_C_0 and REG_C_1 is reserved for metadata feature.
2603 if (__builtin_popcount(reg_c_mask) < 1) {
2605 DRV_LOG(WARNING, "No available register for"
2608 priv->mtr_color_reg = ffs(reg_c_mask) - 1 +
2611 priv->mtr_reg_share =
2612 config.hca_attr.qos.flow_meter_reg_share;
2613 DRV_LOG(DEBUG, "The REG_C meter uses is %d",
2614 priv->mtr_color_reg);
2619 if (config.mprq.enabled && mprq) {
2620 if (config.mprq.stride_num_n > mprq_max_stride_num_n ||
2621 config.mprq.stride_num_n < mprq_min_stride_num_n) {
2622 config.mprq.stride_num_n =
2623 RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,
2624 mprq_min_stride_num_n);
2626 "the number of strides"
2627 " for Multi-Packet RQ is out of range,"
2628 " setting default value (%u)",
2629 1 << config.mprq.stride_num_n);
2631 config.mprq.min_stride_size_n = mprq_min_stride_size_n;
2632 config.mprq.max_stride_size_n = mprq_max_stride_size_n;
2633 } else if (config.mprq.enabled && !mprq) {
2634 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported");
2635 config.mprq.enabled = 0;
2637 if (config.max_dump_files_num == 0)
2638 config.max_dump_files_num = 128;
2639 eth_dev = rte_eth_dev_allocate(name);
2640 if (eth_dev == NULL) {
2641 DRV_LOG(ERR, "can not allocate rte ethdev");
2645 /* Flag to call rte_eth_dev_release_port() in rte_eth_dev_close(). */
2646 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2647 if (priv->representor) {
2648 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR;
2649 eth_dev->data->representor_id = priv->representor_id;
2652 * Store associated network device interface index. This index
2653 * is permanent throughout the lifetime of device. So, we may store
2654 * the ifindex here and use the cached value further.
2656 MLX5_ASSERT(spawn->ifindex);
2657 priv->if_index = spawn->ifindex;
2658 eth_dev->data->dev_private = priv;
2659 priv->dev_data = eth_dev->data;
2660 eth_dev->data->mac_addrs = priv->mac;
2661 eth_dev->device = dpdk_dev;
2662 /* Configure the first MAC address by default. */
2663 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) {
2665 "port %u cannot get MAC address, is mlx5_en"
2666 " loaded? (errno: %s)",
2667 eth_dev->data->port_id, strerror(rte_errno));
2672 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x",
2673 eth_dev->data->port_id,
2674 mac.addr_bytes[0], mac.addr_bytes[1],
2675 mac.addr_bytes[2], mac.addr_bytes[3],
2676 mac.addr_bytes[4], mac.addr_bytes[5]);
2677 #ifdef RTE_LIBRTE_MLX5_DEBUG
2679 char ifname[IF_NAMESIZE];
2681 if (mlx5_get_ifname(eth_dev, &ifname) == 0)
2682 DRV_LOG(DEBUG, "port %u ifname is \"%s\"",
2683 eth_dev->data->port_id, ifname);
2685 DRV_LOG(DEBUG, "port %u ifname is unknown",
2686 eth_dev->data->port_id);
2689 /* Get actual MTU if possible. */
2690 err = mlx5_get_mtu(eth_dev, &priv->mtu);
2695 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id,
2697 /* Initialize burst functions to prevent crashes before link-up. */
2698 eth_dev->rx_pkt_burst = removed_rx_burst;
2699 eth_dev->tx_pkt_burst = removed_tx_burst;
2700 eth_dev->dev_ops = &mlx5_dev_ops;
2701 /* Register MAC address. */
2702 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
2703 if (config.vf && config.vf_nl_en)
2704 mlx5_nl_mac_addr_sync(priv->nl_socket_route,
2705 mlx5_ifindex(eth_dev),
2706 eth_dev->data->mac_addrs,
2707 MLX5_MAX_MAC_ADDRESSES);
2708 TAILQ_INIT(&priv->flows);
2709 TAILQ_INIT(&priv->ctrl_flows);
2710 TAILQ_INIT(&priv->flow_meters);
2711 TAILQ_INIT(&priv->flow_meter_profiles);
2712 /* Hint libmlx5 to use PMD allocator for data plane resources */
2713 struct mlx5dv_ctx_allocators alctr = {
2714 .alloc = &mlx5_alloc_verbs_buf,
2715 .free = &mlx5_free_verbs_buf,
2718 mlx5_glue->dv_set_context_attr(sh->ctx,
2719 MLX5DV_CTX_ATTR_BUF_ALLOCATORS,
2720 (void *)((uintptr_t)&alctr));
2721 /* Bring Ethernet device up. */
2722 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up",
2723 eth_dev->data->port_id);
2724 mlx5_set_link_up(eth_dev);
2726 * Even though the interrupt handler is not installed yet,
2727 * interrupts will still trigger on the async_fd from
2728 * Verbs context returned by ibv_open_device().
2730 mlx5_link_update(eth_dev, 0);
2731 #ifdef HAVE_MLX5DV_DR_ESWITCH
2732 if (!(config.hca_attr.eswitch_manager && config.dv_flow_en &&
2733 (switch_info->representor || switch_info->master)))
2734 config.dv_esw_en = 0;
2736 config.dv_esw_en = 0;
2738 /* Detect minimal data bytes to inline. */
2739 mlx5_set_min_inline(spawn, &config);
2740 /* Store device configuration on private structure. */
2741 priv->config = config;
2742 /* Create context for virtual machine VLAN workaround. */
2743 priv->vmwa_context = mlx5_vlan_vmwa_init(eth_dev, spawn->ifindex);
2744 if (config.dv_flow_en) {
2745 err = mlx5_alloc_shared_dr(priv);
2749 * RSS id is shared with meter flow id. Meter flow id can only
2750 * use the 24 MSB of the register.
2752 priv->qrss_id_pool = mlx5_flow_id_pool_alloc(UINT32_MAX >>
2753 MLX5_MTR_COLOR_BITS);
2754 if (!priv->qrss_id_pool) {
2755 DRV_LOG(ERR, "can't create flow id pool");
2760 /* Supported Verbs flow priority number detection. */
2761 err = mlx5_flow_discover_priorities(eth_dev);
2766 priv->config.flow_prio = err;
2767 if (!priv->config.dv_esw_en &&
2768 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
2769 DRV_LOG(WARNING, "metadata mode %u is not supported "
2770 "(no E-Switch)", priv->config.dv_xmeta_en);
2771 priv->config.dv_xmeta_en = MLX5_XMETA_MODE_LEGACY;
2773 mlx5_set_metadata_mask(eth_dev);
2774 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
2775 !priv->sh->dv_regc0_mask) {
2776 DRV_LOG(ERR, "metadata mode %u is not supported "
2777 "(no metadata reg_c[0] is available)",
2778 priv->config.dv_xmeta_en);
2783 * Allocate the buffer for flow creating, just once.
2784 * The allocation must be done before any flow creating.
2786 mlx5_flow_alloc_intermediate(eth_dev);
2787 /* Query availibility of metadata reg_c's. */
2788 err = mlx5_flow_discover_mreg_c(eth_dev);
2793 if (!mlx5_flow_ext_mreg_supported(eth_dev)) {
2795 "port %u extensive metadata register is not supported",
2796 eth_dev->data->port_id);
2797 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
2798 DRV_LOG(ERR, "metadata mode %u is not supported "
2799 "(no metadata registers available)",
2800 priv->config.dv_xmeta_en);
2805 if (priv->config.dv_flow_en &&
2806 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
2807 mlx5_flow_ext_mreg_supported(eth_dev) &&
2808 priv->sh->dv_regc0_mask) {
2809 priv->mreg_cp_tbl = mlx5_hlist_create(MLX5_FLOW_MREG_HNAME,
2810 MLX5_FLOW_MREG_HTABLE_SZ);
2811 if (!priv->mreg_cp_tbl) {
2819 if (priv->mreg_cp_tbl)
2820 mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
2822 mlx5_free_shared_dr(priv);
2823 if (priv->nl_socket_route >= 0)
2824 close(priv->nl_socket_route);
2825 if (priv->nl_socket_rdma >= 0)
2826 close(priv->nl_socket_rdma);
2827 if (priv->vmwa_context)
2828 mlx5_vlan_vmwa_exit(priv->vmwa_context);
2829 if (priv->qrss_id_pool)
2830 mlx5_flow_id_pool_release(priv->qrss_id_pool);
2832 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
2834 if (eth_dev != NULL)
2835 eth_dev->data->dev_private = NULL;
2837 if (eth_dev != NULL) {
2838 /* mac_addrs must not be freed alone because part of dev_private */
2839 eth_dev->data->mac_addrs = NULL;
2840 rte_eth_dev_release_port(eth_dev);
2843 mlx5_free_shared_ibctx(sh);
2844 MLX5_ASSERT(err > 0);
2850 * Comparison callback to sort device data.
2852 * This is meant to be used with qsort().
2855 * Pointer to pointer to first data object.
2857 * Pointer to pointer to second data object.
2860 * 0 if both objects are equal, less than 0 if the first argument is less
2861 * than the second, greater than 0 otherwise.
2864 mlx5_dev_spawn_data_cmp(const void *a, const void *b)
2866 const struct mlx5_switch_info *si_a =
2867 &((const struct mlx5_dev_spawn_data *)a)->info;
2868 const struct mlx5_switch_info *si_b =
2869 &((const struct mlx5_dev_spawn_data *)b)->info;
2872 /* Master device first. */
2873 ret = si_b->master - si_a->master;
2876 /* Then representor devices. */
2877 ret = si_b->representor - si_a->representor;
2880 /* Unidentified devices come last in no specific order. */
2881 if (!si_a->representor)
2883 /* Order representors by name. */
2884 return si_a->port_name - si_b->port_name;
2888 * Match PCI information for possible slaves of bonding device.
2890 * @param[in] ibv_dev
2891 * Pointer to Infiniband device structure.
2892 * @param[in] pci_dev
2893 * Pointer to PCI device structure to match PCI address.
2894 * @param[in] nl_rdma
2895 * Netlink RDMA group socket handle.
2898 * negative value if no bonding device found, otherwise
2899 * positive index of slave PF in bonding.
2902 mlx5_device_bond_pci_match(const struct ibv_device *ibv_dev,
2903 const struct rte_pci_device *pci_dev,
2906 char ifname[IF_NAMESIZE + 1];
2907 unsigned int ifindex;
2913 * Try to get master device name. If something goes
2914 * wrong suppose the lack of kernel support and no
2919 if (!strstr(ibv_dev->name, "bond"))
2921 np = mlx5_nl_portnum(nl_rdma, ibv_dev->name);
2925 * The Master device might not be on the predefined
2926 * port (not on port index 1, it is not garanted),
2927 * we have to scan all Infiniband device port and
2930 for (i = 1; i <= np; ++i) {
2931 /* Check whether Infiniband port is populated. */
2932 ifindex = mlx5_nl_ifindex(nl_rdma, ibv_dev->name, i);
2935 if (!if_indextoname(ifindex, ifname))
2937 /* Try to read bonding slave names from sysfs. */
2939 "/sys/class/net/%s/master/bonding/slaves", ifname);
2940 file = fopen(slaves, "r");
2946 /* Use safe format to check maximal buffer length. */
2947 MLX5_ASSERT(atol(RTE_STR(IF_NAMESIZE)) == IF_NAMESIZE);
2948 while (fscanf(file, "%" RTE_STR(IF_NAMESIZE) "s", ifname) == 1) {
2949 char tmp_str[IF_NAMESIZE + 32];
2950 struct rte_pci_addr pci_addr;
2951 struct mlx5_switch_info info;
2953 /* Process slave interface names in the loop. */
2954 snprintf(tmp_str, sizeof(tmp_str),
2955 "/sys/class/net/%s", ifname);
2956 if (mlx5_dev_to_pci_addr(tmp_str, &pci_addr)) {
2957 DRV_LOG(WARNING, "can not get PCI address"
2958 " for netdev \"%s\"", ifname);
2961 if (pci_dev->addr.domain != pci_addr.domain ||
2962 pci_dev->addr.bus != pci_addr.bus ||
2963 pci_dev->addr.devid != pci_addr.devid ||
2964 pci_dev->addr.function != pci_addr.function)
2966 /* Slave interface PCI address match found. */
2968 snprintf(tmp_str, sizeof(tmp_str),
2969 "/sys/class/net/%s/phys_port_name", ifname);
2970 file = fopen(tmp_str, "rb");
2973 info.name_type = MLX5_PHYS_PORT_NAME_TYPE_NOTSET;
2974 if (fscanf(file, "%32s", tmp_str) == 1)
2975 mlx5_translate_port_name(tmp_str, &info);
2976 if (info.name_type == MLX5_PHYS_PORT_NAME_TYPE_LEGACY ||
2977 info.name_type == MLX5_PHYS_PORT_NAME_TYPE_UPLINK)
2978 pf = info.port_name;
2987 * DPDK callback to register a PCI device.
2989 * This function spawns Ethernet devices out of a given PCI device.
2991 * @param[in] pci_drv
2992 * PCI driver structure (mlx5_driver).
2993 * @param[in] pci_dev
2994 * PCI device information.
2997 * 0 on success, a negative errno value otherwise and rte_errno is set.
3000 mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3001 struct rte_pci_device *pci_dev)
3003 struct ibv_device **ibv_list;
3005 * Number of found IB Devices matching with requested PCI BDF.
3006 * nd != 1 means there are multiple IB devices over the same
3007 * PCI device and we have representors and master.
3009 unsigned int nd = 0;
3011 * Number of found IB device Ports. nd = 1 and np = 1..n means
3012 * we have the single multiport IB device, and there may be
3013 * representors attached to some of found ports.
3015 unsigned int np = 0;
3017 * Number of DPDK ethernet devices to Spawn - either over
3018 * multiple IB devices or multiple ports of single IB device.
3019 * Actually this is the number of iterations to spawn.
3021 unsigned int ns = 0;
3024 * < 0 - no bonding device (single one)
3025 * >= 0 - bonding device (value is slave PF index)
3028 struct mlx5_dev_spawn_data *list = NULL;
3029 struct mlx5_dev_config dev_config;
3032 if (mlx5_class_get(pci_dev->device.devargs) != MLX5_CLASS_NET) {
3033 DRV_LOG(DEBUG, "Skip probing - should be probed by other mlx5"
3037 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
3038 mlx5_pmd_socket_init();
3039 ret = mlx5_init_once();
3041 DRV_LOG(ERR, "unable to init PMD global data: %s",
3042 strerror(rte_errno));
3045 MLX5_ASSERT(pci_drv == &mlx5_driver);
3047 ibv_list = mlx5_glue->get_device_list(&ret);
3049 rte_errno = errno ? errno : ENOSYS;
3050 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?");
3054 * First scan the list of all Infiniband devices to find
3055 * matching ones, gathering into the list.
3057 struct ibv_device *ibv_match[ret + 1];
3058 int nl_route = mlx5_nl_init(NETLINK_ROUTE);
3059 int nl_rdma = mlx5_nl_init(NETLINK_RDMA);
3063 struct rte_pci_addr pci_addr;
3065 DRV_LOG(DEBUG, "checking device \"%s\"", ibv_list[ret]->name);
3066 bd = mlx5_device_bond_pci_match
3067 (ibv_list[ret], pci_dev, nl_rdma);
3070 * Bonding device detected. Only one match is allowed,
3071 * the bonding is supported over multi-port IB device,
3072 * there should be no matches on representor PCI
3073 * functions or non VF LAG bonding devices with
3074 * specified address.
3078 "multiple PCI match on bonding device"
3079 "\"%s\" found", ibv_list[ret]->name);
3084 DRV_LOG(INFO, "PCI information matches for"
3085 " slave %d bonding device \"%s\"",
3086 bd, ibv_list[ret]->name);
3087 ibv_match[nd++] = ibv_list[ret];
3090 if (mlx5_dev_to_pci_addr
3091 (ibv_list[ret]->ibdev_path, &pci_addr))
3093 if (pci_dev->addr.domain != pci_addr.domain ||
3094 pci_dev->addr.bus != pci_addr.bus ||
3095 pci_dev->addr.devid != pci_addr.devid ||
3096 pci_dev->addr.function != pci_addr.function)
3098 DRV_LOG(INFO, "PCI information matches for device \"%s\"",
3099 ibv_list[ret]->name);
3100 ibv_match[nd++] = ibv_list[ret];
3102 ibv_match[nd] = NULL;
3104 /* No device matches, just complain and bail out. */
3106 "no Verbs device matches PCI device " PCI_PRI_FMT ","
3107 " are kernel drivers loaded?",
3108 pci_dev->addr.domain, pci_dev->addr.bus,
3109 pci_dev->addr.devid, pci_dev->addr.function);
3116 * Found single matching device may have multiple ports.
3117 * Each port may be representor, we have to check the port
3118 * number and check the representors existence.
3121 np = mlx5_nl_portnum(nl_rdma, ibv_match[0]->name);
3123 DRV_LOG(WARNING, "can not get IB device \"%s\""
3124 " ports number", ibv_match[0]->name);
3125 if (bd >= 0 && !np) {
3126 DRV_LOG(ERR, "can not get ports"
3127 " for bonding device");
3133 #ifndef HAVE_MLX5DV_DR_DEVX_PORT
3136 * This may happen if there is VF LAG kernel support and
3137 * application is compiled with older rdma_core library.
3140 "No kernel/verbs support for VF LAG bonding found.");
3141 rte_errno = ENOTSUP;
3147 * Now we can determine the maximal
3148 * amount of devices to be spawned.
3150 list = rte_zmalloc("device spawn data",
3151 sizeof(struct mlx5_dev_spawn_data) *
3153 RTE_CACHE_LINE_SIZE);
3155 DRV_LOG(ERR, "spawn data array allocation failure");
3160 if (bd >= 0 || np > 1) {
3162 * Single IB device with multiple ports found,
3163 * it may be E-Switch master device and representors.
3164 * We have to perform identification trough the ports.
3166 MLX5_ASSERT(nl_rdma >= 0);
3167 MLX5_ASSERT(ns == 0);
3168 MLX5_ASSERT(nd == 1);
3170 for (i = 1; i <= np; ++i) {
3171 list[ns].max_port = np;
3172 list[ns].ibv_port = i;
3173 list[ns].ibv_dev = ibv_match[0];
3174 list[ns].eth_dev = NULL;
3175 list[ns].pci_dev = pci_dev;
3176 list[ns].pf_bond = bd;
3177 list[ns].ifindex = mlx5_nl_ifindex
3178 (nl_rdma, list[ns].ibv_dev->name, i);
3179 if (!list[ns].ifindex) {
3181 * No network interface index found for the
3182 * specified port, it means there is no
3183 * representor on this port. It's OK,
3184 * there can be disabled ports, for example
3185 * if sriov_numvfs < sriov_totalvfs.
3191 ret = mlx5_nl_switch_info
3195 if (ret || (!list[ns].info.representor &&
3196 !list[ns].info.master)) {
3198 * We failed to recognize representors with
3199 * Netlink, let's try to perform the task
3202 ret = mlx5_sysfs_switch_info
3206 if (!ret && bd >= 0) {
3207 switch (list[ns].info.name_type) {
3208 case MLX5_PHYS_PORT_NAME_TYPE_UPLINK:
3209 if (list[ns].info.port_name == bd)
3212 case MLX5_PHYS_PORT_NAME_TYPE_PFVF:
3213 if (list[ns].info.pf_num == bd)
3221 if (!ret && (list[ns].info.representor ^
3222 list[ns].info.master))
3227 "unable to recognize master/representors"
3228 " on the IB device with multiple ports");
3235 * The existence of several matching entries (nd > 1) means
3236 * port representors have been instantiated. No existing Verbs
3237 * call nor sysfs entries can tell them apart, this can only
3238 * be done through Netlink calls assuming kernel drivers are
3239 * recent enough to support them.
3241 * In the event of identification failure through Netlink,
3242 * try again through sysfs, then:
3244 * 1. A single IB device matches (nd == 1) with single
3245 * port (np=0/1) and is not a representor, assume
3246 * no switch support.
3248 * 2. Otherwise no safe assumptions can be made;
3249 * complain louder and bail out.
3252 for (i = 0; i != nd; ++i) {
3253 memset(&list[ns].info, 0, sizeof(list[ns].info));
3254 list[ns].max_port = 1;
3255 list[ns].ibv_port = 1;
3256 list[ns].ibv_dev = ibv_match[i];
3257 list[ns].eth_dev = NULL;
3258 list[ns].pci_dev = pci_dev;
3259 list[ns].pf_bond = -1;
3260 list[ns].ifindex = 0;
3262 list[ns].ifindex = mlx5_nl_ifindex
3263 (nl_rdma, list[ns].ibv_dev->name, 1);
3264 if (!list[ns].ifindex) {
3265 char ifname[IF_NAMESIZE];
3268 * Netlink failed, it may happen with old
3269 * ib_core kernel driver (before 4.16).
3270 * We can assume there is old driver because
3271 * here we are processing single ports IB
3272 * devices. Let's try sysfs to retrieve
3273 * the ifindex. The method works for
3274 * master device only.
3278 * Multiple devices found, assume
3279 * representors, can not distinguish
3280 * master/representor and retrieve
3281 * ifindex via sysfs.
3285 ret = mlx5_get_master_ifname
3286 (ibv_match[i]->ibdev_path, &ifname);
3289 if_nametoindex(ifname);
3290 if (!list[ns].ifindex) {
3292 * No network interface index found
3293 * for the specified device, it means
3294 * there it is neither representor
3302 ret = mlx5_nl_switch_info
3306 if (ret || (!list[ns].info.representor &&
3307 !list[ns].info.master)) {
3309 * We failed to recognize representors with
3310 * Netlink, let's try to perform the task
3313 ret = mlx5_sysfs_switch_info
3317 if (!ret && (list[ns].info.representor ^
3318 list[ns].info.master)) {
3320 } else if ((nd == 1) &&
3321 !list[ns].info.representor &&
3322 !list[ns].info.master) {
3324 * Single IB device with
3325 * one physical port and
3326 * attached network device.
3327 * May be SRIOV is not enabled
3328 * or there is no representors.
3330 DRV_LOG(INFO, "no E-Switch support detected");
3337 "unable to recognize master/representors"
3338 " on the multiple IB devices");
3346 * Sort list to probe devices in natural order for users convenience
3347 * (i.e. master first, then representors from lowest to highest ID).
3349 qsort(list, ns, sizeof(*list), mlx5_dev_spawn_data_cmp);
3350 /* Default configuration. */
3351 dev_config = (struct mlx5_dev_config){
3353 .mps = MLX5_ARG_UNSET,
3354 .dbnc = MLX5_ARG_UNSET,
3356 .txq_inline_max = MLX5_ARG_UNSET,
3357 .txq_inline_min = MLX5_ARG_UNSET,
3358 .txq_inline_mpw = MLX5_ARG_UNSET,
3359 .txqs_inline = MLX5_ARG_UNSET,
3361 .mr_ext_memseg_en = 1,
3363 .enabled = 0, /* Disabled by default. */
3364 .stride_num_n = MLX5_MPRQ_STRIDE_NUM_N,
3365 .max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN,
3366 .min_rxqs_num = MLX5_MPRQ_MIN_RXQS,
3370 .log_hp_size = MLX5_ARG_UNSET,
3372 /* Device specific configuration. */
3373 switch (pci_dev->id.device_id) {
3374 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
3375 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
3376 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
3377 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
3378 case PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF:
3379 case PCI_DEVICE_ID_MELLANOX_CONNECTX6VF:
3380 case PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF:
3386 for (i = 0; i != ns; ++i) {
3389 list[i].eth_dev = mlx5_dev_spawn(&pci_dev->device,
3392 if (!list[i].eth_dev) {
3393 if (rte_errno != EBUSY && rte_errno != EEXIST)
3395 /* Device is disabled or already spawned. Ignore it. */
3398 restore = list[i].eth_dev->data->dev_flags;
3399 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev);
3400 /* Restore non-PCI flags cleared by the above call. */
3401 list[i].eth_dev->data->dev_flags |= restore;
3402 mlx5_dev_interrupt_handler_devx_install(list[i].eth_dev);
3403 rte_eth_dev_probing_finish(list[i].eth_dev);
3407 "probe of PCI device " PCI_PRI_FMT " aborted after"
3408 " encountering an error: %s",
3409 pci_dev->addr.domain, pci_dev->addr.bus,
3410 pci_dev->addr.devid, pci_dev->addr.function,
3411 strerror(rte_errno));
3415 if (!list[i].eth_dev)
3417 mlx5_dev_close(list[i].eth_dev);
3418 /* mac_addrs must not be freed because in dev_private */
3419 list[i].eth_dev->data->mac_addrs = NULL;
3420 claim_zero(rte_eth_dev_release_port(list[i].eth_dev));
3422 /* Restore original error. */
3429 * Do the routine cleanup:
3430 * - close opened Netlink sockets
3431 * - free allocated spawn data array
3432 * - free the Infiniband device list
3440 MLX5_ASSERT(ibv_list);
3441 mlx5_glue->free_device_list(ibv_list);
3446 * Look for the ethernet device belonging to mlx5 driver.
3448 * @param[in] port_id
3449 * port_id to start looking for device.
3450 * @param[in] pci_dev
3451 * Pointer to the hint PCI device. When device is being probed
3452 * the its siblings (master and preceding representors might
3453 * not have assigned driver yet (because the mlx5_pci_probe()
3454 * is not completed yet, for this case match on hint PCI
3455 * device may be used to detect sibling device.
3458 * port_id of found device, RTE_MAX_ETHPORT if not found.
3461 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
3463 while (port_id < RTE_MAX_ETHPORTS) {
3464 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
3466 if (dev->state != RTE_ETH_DEV_UNUSED &&
3468 (dev->device == &pci_dev->device ||
3469 (dev->device->driver &&
3470 dev->device->driver->name &&
3471 !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
3475 if (port_id >= RTE_MAX_ETHPORTS)
3476 return RTE_MAX_ETHPORTS;
3481 * DPDK callback to remove a PCI device.
3483 * This function removes all Ethernet devices belong to a given PCI device.
3485 * @param[in] pci_dev
3486 * Pointer to the PCI device.
3489 * 0 on success, the function cannot fail.
3492 mlx5_pci_remove(struct rte_pci_device *pci_dev)
3496 RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device)
3497 rte_eth_dev_close(port_id);
3501 static const struct rte_pci_id mlx5_pci_id_map[] = {
3503 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3504 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
3507 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3508 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
3511 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3512 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
3515 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3516 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
3519 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3520 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
3523 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3524 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
3527 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3528 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
3531 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3532 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
3535 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3536 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
3539 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3540 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
3543 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3544 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
3547 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3548 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
3551 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3552 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
3555 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3556 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF)
3559 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3560 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
3567 static struct rte_pci_driver mlx5_driver = {
3569 .name = MLX5_DRIVER_NAME
3571 .id_table = mlx5_pci_id_map,
3572 .probe = mlx5_pci_probe,
3573 .remove = mlx5_pci_remove,
3574 .dma_map = mlx5_dma_map,
3575 .dma_unmap = mlx5_dma_unmap,
3576 .drv_flags = RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV |
3577 RTE_PCI_DRV_PROBE_AGAIN,
3581 * Driver initialization routine.
3583 RTE_INIT(rte_mlx5_pmd_init)
3585 /* Initialize driver log type. */
3586 mlx5_logtype = rte_log_register("pmd.net.mlx5");
3587 if (mlx5_logtype >= 0)
3588 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE);
3590 /* Build the static tables for Verbs conversion. */
3591 mlx5_set_ptype_table();
3592 mlx5_set_cksum_table();
3593 mlx5_set_swp_types_table();
3595 rte_pci_register(&mlx5_driver);
3598 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
3599 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
3600 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");