1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
13 #include <rte_malloc.h>
14 #include <rte_ethdev_driver.h>
15 #include <rte_ethdev_pci.h>
17 #include <rte_bus_pci.h>
18 #include <rte_common.h>
19 #include <rte_kvargs.h>
20 #include <rte_rwlock.h>
21 #include <rte_spinlock.h>
22 #include <rte_string_fns.h>
23 #include <rte_alarm.h>
25 #include <mlx5_glue.h>
26 #include <mlx5_devx_cmds.h>
27 #include <mlx5_common.h>
28 #include <mlx5_common_os.h>
29 #include <mlx5_common_mp.h>
30 #include <mlx5_common_pci.h>
31 #include <mlx5_malloc.h>
33 #include "mlx5_defs.h"
35 #include "mlx5_utils.h"
36 #include "mlx5_rxtx.h"
37 #include "mlx5_autoconf.h"
39 #include "mlx5_flow.h"
40 #include "rte_pmd_mlx5.h"
42 /* Device parameter to enable RX completion queue compression. */
43 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
45 /* Device parameter to enable RX completion entry padding to 128B. */
46 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
48 /* Device parameter to enable padding Rx packet to cacheline size. */
49 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
51 /* Device parameter to enable Multi-Packet Rx queue. */
52 #define MLX5_RX_MPRQ_EN "mprq_en"
54 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
55 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
57 /* Device parameter to configure log 2 of the stride size for MPRQ. */
58 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
60 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
61 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
63 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
64 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
66 /* Device parameter to configure inline send. Deprecated, ignored.*/
67 #define MLX5_TXQ_INLINE "txq_inline"
69 /* Device parameter to limit packet size to inline with ordinary SEND. */
70 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
72 /* Device parameter to configure minimal data size to inline. */
73 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
75 /* Device parameter to limit packet size to inline with Enhanced MPW. */
76 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
79 * Device parameter to configure the number of TX queues threshold for
80 * enabling inline send.
82 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
85 * Device parameter to configure the number of TX queues threshold for
86 * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
88 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
90 /* Device parameter to enable multi-packet send WQEs. */
91 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
94 * Device parameter to force doorbell register mapping
95 * to non-cahed region eliminating the extra write memory barrier.
97 #define MLX5_TX_DB_NC "tx_db_nc"
100 * Device parameter to include 2 dsegs in the title WQEBB.
101 * Deprecated, ignored.
103 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
106 * Device parameter to limit the size of inlining packet.
107 * Deprecated, ignored.
109 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
112 * Device parameter to enable Tx scheduling on timestamps
113 * and specify the packet pacing granularity in nanoseconds.
115 #define MLX5_TX_PP "tx_pp"
118 * Device parameter to specify skew in nanoseconds on Tx datapath,
119 * it represents the time between SQ start WQE processing and
120 * appearing actual packet data on the wire.
122 #define MLX5_TX_SKEW "tx_skew"
125 * Device parameter to enable hardware Tx vector.
126 * Deprecated, ignored (no vectorized Tx routines anymore).
128 #define MLX5_TX_VEC_EN "tx_vec_en"
130 /* Device parameter to enable hardware Rx vector. */
131 #define MLX5_RX_VEC_EN "rx_vec_en"
133 /* Allow L3 VXLAN flow creation. */
134 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
136 /* Activate DV E-Switch flow steering. */
137 #define MLX5_DV_ESW_EN "dv_esw_en"
139 /* Activate DV flow steering. */
140 #define MLX5_DV_FLOW_EN "dv_flow_en"
142 /* Enable extensive flow metadata support. */
143 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
145 /* Device parameter to let the user manage the lacp traffic of bonded device */
146 #define MLX5_LACP_BY_USER "lacp_by_user"
148 /* Activate Netlink support in VF mode. */
149 #define MLX5_VF_NL_EN "vf_nl_en"
151 /* Enable extending memsegs when creating a MR. */
152 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
154 /* Select port representors to instantiate. */
155 #define MLX5_REPRESENTOR "representor"
157 /* Device parameter to configure the maximum number of dump files per queue. */
158 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
160 /* Configure timeout of LRO session (in microseconds). */
161 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
164 * Device parameter to configure the total data buffer size for a single
165 * hairpin queue (logarithm value).
167 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
169 /* Flow memory reclaim mode. */
170 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
172 /* The default memory allocator used in PMD. */
173 #define MLX5_SYS_MEM_EN "sys_mem_en"
174 /* Decap will be used or not. */
175 #define MLX5_DECAP_EN "decap_en"
177 /* Shared memory between primary and secondary processes. */
178 struct mlx5_shared_data *mlx5_shared_data;
180 /** Driver-specific log messages type. */
183 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
184 LIST_HEAD_INITIALIZER();
185 static pthread_mutex_t mlx5_dev_ctx_list_mutex = PTHREAD_MUTEX_INITIALIZER;
187 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
188 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
190 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
196 .malloc = mlx5_malloc,
198 .type = "mlx5_encap_decap_ipool",
201 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
207 .malloc = mlx5_malloc,
209 .type = "mlx5_push_vlan_ipool",
212 .size = sizeof(struct mlx5_flow_dv_tag_resource),
218 .malloc = mlx5_malloc,
220 .type = "mlx5_tag_ipool",
223 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
229 .malloc = mlx5_malloc,
231 .type = "mlx5_port_id_ipool",
234 .size = sizeof(struct mlx5_flow_tbl_data_entry),
240 .malloc = mlx5_malloc,
242 .type = "mlx5_jump_ipool",
245 .size = sizeof(struct mlx5_flow_dv_sample_resource),
251 .malloc = mlx5_malloc,
253 .type = "mlx5_sample_ipool",
256 .size = sizeof(struct mlx5_flow_dv_dest_array_resource),
262 .malloc = mlx5_malloc,
264 .type = "mlx5_dest_array_ipool",
268 .size = sizeof(struct mlx5_flow_meter),
274 .malloc = mlx5_malloc,
276 .type = "mlx5_meter_ipool",
279 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
285 .malloc = mlx5_malloc,
287 .type = "mlx5_mcp_ipool",
290 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
296 .malloc = mlx5_malloc,
298 .type = "mlx5_hrxq_ipool",
302 * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
303 * It set in run time according to PCI function configuration.
311 .malloc = mlx5_malloc,
313 .type = "mlx5_flow_handle_ipool",
316 .size = sizeof(struct rte_flow),
320 .malloc = mlx5_malloc,
322 .type = "rte_flow_ipool",
327 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
328 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
330 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
333 * Allocate ID pool structure.
336 * The maximum id can be allocated from the pool.
339 * Pointer to pool object, NULL value otherwise.
341 struct mlx5_flow_id_pool *
342 mlx5_flow_id_pool_alloc(uint32_t max_id)
344 struct mlx5_flow_id_pool *pool;
347 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool),
348 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
350 DRV_LOG(ERR, "can't allocate id pool");
354 mem = mlx5_malloc(MLX5_MEM_ZERO,
355 MLX5_FLOW_MIN_ID_POOL_SIZE * sizeof(uint32_t),
356 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
358 DRV_LOG(ERR, "can't allocate mem for id pool");
362 pool->free_arr = mem;
363 pool->curr = pool->free_arr;
364 pool->last = pool->free_arr + MLX5_FLOW_MIN_ID_POOL_SIZE;
365 pool->base_index = 0;
366 pool->max_id = max_id;
374 * Release ID pool structure.
377 * Pointer to flow id pool object to free.
380 mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool)
382 mlx5_free(pool->free_arr);
390 * Pointer to flow id pool.
395 * 0 on success, error value otherwise.
398 mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id)
400 if (pool->curr == pool->free_arr) {
401 if (pool->base_index == pool->max_id) {
403 DRV_LOG(ERR, "no free id");
406 *id = ++pool->base_index;
409 *id = *(--pool->curr);
417 * Pointer to flow id pool.
422 * 0 on success, error value otherwise.
425 mlx5_flow_id_release(struct mlx5_flow_id_pool *pool, uint32_t id)
431 if (pool->curr == pool->last) {
432 size = pool->curr - pool->free_arr;
433 size2 = size * MLX5_ID_GENERATION_ARRAY_FACTOR;
434 MLX5_ASSERT(size2 > size);
435 mem = mlx5_malloc(0, size2 * sizeof(uint32_t), 0,
438 DRV_LOG(ERR, "can't allocate mem for id pool");
442 memcpy(mem, pool->free_arr, size * sizeof(uint32_t));
443 mlx5_free(pool->free_arr);
444 pool->free_arr = mem;
445 pool->curr = pool->free_arr + size;
446 pool->last = pool->free_arr + size2;
454 * Initialize the shared aging list information per port.
457 * Pointer to mlx5_dev_ctx_shared object.
460 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
463 struct mlx5_age_info *age_info;
465 for (i = 0; i < sh->max_port; i++) {
466 age_info = &sh->port[i].age_info;
468 TAILQ_INIT(&age_info->aged_counters);
469 rte_spinlock_init(&age_info->aged_sl);
470 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
475 * Initialize the counters management structure.
478 * Pointer to mlx5_dev_ctx_shared object to free
481 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
485 memset(&sh->cmng, 0, sizeof(sh->cmng));
486 TAILQ_INIT(&sh->cmng.flow_counters);
487 for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
488 sh->cmng.ccont[i].min_id = MLX5_CNT_BATCH_OFFSET;
489 sh->cmng.ccont[i].max_id = -1;
490 sh->cmng.ccont[i].last_pool_idx = POOL_IDX_INVALID;
491 TAILQ_INIT(&sh->cmng.ccont[i].pool_list);
492 rte_spinlock_init(&sh->cmng.ccont[i].resize_sl);
493 TAILQ_INIT(&sh->cmng.ccont[i].counters);
494 rte_spinlock_init(&sh->cmng.ccont[i].csl);
499 * Destroy all the resources allocated for a counter memory management.
502 * Pointer to the memory management structure.
505 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
507 uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
509 LIST_REMOVE(mng, next);
510 claim_zero(mlx5_devx_cmd_destroy(mng->dm));
511 claim_zero(mlx5_glue->devx_umem_dereg(mng->umem));
516 * Close and release all the resources of the counters management.
519 * Pointer to mlx5_dev_ctx_shared object to free.
522 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
524 struct mlx5_counter_stats_mem_mng *mng;
531 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
532 if (rte_errno != EINPROGRESS)
536 for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
537 struct mlx5_flow_counter_pool *pool;
538 uint32_t batch = !!(i > 1);
540 if (!sh->cmng.ccont[i].pools)
542 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
544 if (batch && pool->min_dcs)
545 claim_zero(mlx5_devx_cmd_destroy
547 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
548 if (MLX5_POOL_GET_CNT(pool, j)->action)
550 (mlx5_glue->destroy_flow_action
553 if (!batch && MLX5_GET_POOL_CNT_EXT
555 claim_zero(mlx5_devx_cmd_destroy
556 (MLX5_GET_POOL_CNT_EXT
559 TAILQ_REMOVE(&sh->cmng.ccont[i].pool_list, pool, next);
561 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
563 mlx5_free(sh->cmng.ccont[i].pools);
565 mng = LIST_FIRST(&sh->cmng.mem_mngs);
567 mlx5_flow_destroy_counter_stat_mem_mng(mng);
568 mng = LIST_FIRST(&sh->cmng.mem_mngs);
570 memset(&sh->cmng, 0, sizeof(sh->cmng));
574 * Initialize the flow resources' indexed mempool.
577 * Pointer to mlx5_dev_ctx_shared object.
579 * Pointer to user dev config.
582 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
583 const struct mlx5_dev_config *config)
586 struct mlx5_indexed_pool_config cfg;
588 for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
589 cfg = mlx5_ipool_cfg[i];
594 * Set MLX5_IPOOL_MLX5_FLOW ipool size
595 * according to PCI function flow configuration.
597 case MLX5_IPOOL_MLX5_FLOW:
598 cfg.size = config->dv_flow_en ?
599 sizeof(struct mlx5_flow_handle) :
600 MLX5_FLOW_HANDLE_VERBS_SIZE;
603 if (config->reclaim_mode)
604 cfg.release_mem_en = 1;
605 sh->ipool[i] = mlx5_ipool_create(&cfg);
610 * Release the flow resources' indexed mempool.
613 * Pointer to mlx5_dev_ctx_shared object.
616 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
620 for (i = 0; i < MLX5_IPOOL_MAX; ++i)
621 mlx5_ipool_destroy(sh->ipool[i]);
625 * Check if dynamic flex parser for eCPRI already exists.
628 * Pointer to Ethernet device structure.
631 * true on exists, false on not.
634 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
636 struct mlx5_priv *priv = dev->data->dev_private;
637 struct mlx5_flex_parser_profiles *prf =
638 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
644 * Allocation of a flex parser for eCPRI. Once created, this parser related
645 * resources will be held until the device is closed.
648 * Pointer to Ethernet device structure.
651 * 0 on success, a negative errno value otherwise and rte_errno is set.
654 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
656 struct mlx5_priv *priv = dev->data->dev_private;
657 struct mlx5_flex_parser_profiles *prf =
658 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
659 struct mlx5_devx_graph_node_attr node = {
660 .modify_field_select = 0,
665 if (!priv->config.hca_attr.parse_graph_flex_node) {
666 DRV_LOG(ERR, "Dynamic flex parser is not supported "
667 "for device %s.", priv->dev_data->name);
670 node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED;
671 /* 8 bytes now: 4B common header + 4B message body header. */
672 node.header_length_base_value = 0x8;
673 /* After MAC layer: Ether / VLAN. */
674 node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC;
675 /* Type of compared condition should be 0xAEFE in the L2 layer. */
676 node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI;
677 /* Sample #0: type in common header. */
678 node.sample[0].flow_match_sample_en = 1;
680 node.sample[0].flow_match_sample_offset_mode = 0x0;
681 /* Only the 2nd byte will be used. */
682 node.sample[0].flow_match_sample_field_base_offset = 0x0;
683 /* Sample #1: message payload. */
684 node.sample[1].flow_match_sample_en = 1;
686 node.sample[1].flow_match_sample_offset_mode = 0x0;
688 * Only the first two bytes will be used right now, and its offset will
689 * start after the common header that with the length of a DW(u32).
691 node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);
692 prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->ctx, &node);
694 DRV_LOG(ERR, "Failed to create flex parser node object.");
695 return (rte_errno == 0) ? -ENODEV : -rte_errno;
698 ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num);
700 DRV_LOG(ERR, "Failed to query sample IDs.");
701 return (rte_errno == 0) ? -ENODEV : -rte_errno;
703 prf->offset[0] = 0x0;
704 prf->offset[1] = sizeof(uint32_t);
705 prf->ids[0] = ids[0];
706 prf->ids[1] = ids[1];
711 * Destroy the flex parser node, including the parser itself, input / output
712 * arcs and DW samples. Resources could be reused then.
715 * Pointer to Ethernet device structure.
718 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
720 struct mlx5_priv *priv = dev->data->dev_private;
721 struct mlx5_flex_parser_profiles *prf =
722 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
725 mlx5_devx_cmd_destroy(prf->obj);
730 * Allocate Rx and Tx UARs in robust fashion.
731 * This routine handles the following UAR allocation issues:
733 * - tries to allocate the UAR with the most appropriate memory
734 * mapping type from the ones supported by the host
736 * - tries to allocate the UAR with non-NULL base address
737 * OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as
738 * UAR base address if UAR was not the first object in the UAR page.
739 * It caused the PMD failure and we should try to get another UAR
740 * till we get the first one with non-NULL base address returned.
743 mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh,
744 const struct mlx5_dev_config *config)
746 uint32_t uar_mapping, retry;
750 for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
751 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
752 /* Control the mapping type according to the settings. */
753 uar_mapping = (config->dbnc == MLX5_TXDB_NCACHED) ?
754 MLX5DV_UAR_ALLOC_TYPE_NC :
755 MLX5DV_UAR_ALLOC_TYPE_BF;
757 RTE_SET_USED(config);
759 * It seems we have no way to control the memory mapping type
760 * for the UAR, the default "Write-Combining" type is supposed.
761 * The UAR initialization on queue creation queries the
762 * actual mapping type done by Verbs/kernel and setups the
763 * PMD datapath accordingly.
767 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->ctx, uar_mapping);
768 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
770 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
771 if (config->dbnc == MLX5_TXDB_CACHED ||
772 config->dbnc == MLX5_TXDB_HEURISTIC)
773 DRV_LOG(WARNING, "Devarg tx_db_nc setting "
774 "is not supported by DevX");
776 * In some environments like virtual machine
777 * the Write Combining mapped might be not supported
778 * and UAR allocation fails. We try "Non-Cached"
779 * mapping for the case. The tx_burst routines take
780 * the UAR mapping type into account on UAR setup
783 DRV_LOG(WARNING, "Failed to allocate Tx DevX UAR (BF)");
784 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
785 sh->tx_uar = mlx5_glue->devx_alloc_uar
786 (sh->ctx, uar_mapping);
787 } else if (!sh->tx_uar &&
788 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_NC) {
789 if (config->dbnc == MLX5_TXDB_NCACHED)
790 DRV_LOG(WARNING, "Devarg tx_db_nc settings "
791 "is not supported by DevX");
793 * If Verbs/kernel does not support "Non-Cached"
794 * try the "Write-Combining".
796 DRV_LOG(WARNING, "Failed to allocate Tx DevX UAR (NC)");
797 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_BF;
798 sh->tx_uar = mlx5_glue->devx_alloc_uar
799 (sh->ctx, uar_mapping);
803 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (BF/NC)");
807 base_addr = mlx5_os_get_devx_uar_base_addr(sh->tx_uar);
811 * The UARs are allocated by rdma_core within the
812 * IB device context, on context closure all UARs
813 * will be freed, should be no memory/object leakage.
815 DRV_LOG(WARNING, "Retrying to allocate Tx DevX UAR");
818 /* Check whether we finally succeeded with valid UAR allocation. */
820 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (NULL base)");
824 for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
826 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
827 (sh->ctx, uar_mapping);
828 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
829 if (!sh->devx_rx_uar &&
830 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
832 * Rx UAR is used to control interrupts only,
833 * should be no datapath noticeable impact,
834 * can try "Non-Cached" mapping safely.
836 DRV_LOG(WARNING, "Failed to allocate Rx DevX UAR (BF)");
837 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
838 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
839 (sh->ctx, uar_mapping);
842 if (!sh->devx_rx_uar) {
843 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (BF/NC)");
847 base_addr = mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar);
851 * The UARs are allocated by rdma_core within the
852 * IB device context, on context closure all UARs
853 * will be freed, should be no memory/object leakage.
855 DRV_LOG(WARNING, "Retrying to allocate Rx DevX UAR");
856 sh->devx_rx_uar = NULL;
858 /* Check whether we finally succeeded with valid UAR allocation. */
859 if (!sh->devx_rx_uar) {
860 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (NULL base)");
868 * Allocate shared device context. If there is multiport device the
869 * master and representors will share this context, if there is single
870 * port dedicated device, the context will be used by only given
871 * port due to unification.
873 * Routine first searches the context for the specified device name,
874 * if found the shared context assumed and reference counter is incremented.
875 * If no context found the new one is created and initialized with specified
876 * device context and parameters.
879 * Pointer to the device attributes (name, port, etc).
881 * Pointer to device configuration structure.
884 * Pointer to mlx5_dev_ctx_shared object on success,
885 * otherwise NULL and rte_errno is set.
887 struct mlx5_dev_ctx_shared *
888 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
889 const struct mlx5_dev_config *config)
891 struct mlx5_dev_ctx_shared *sh;
894 struct mlx5_devx_tis_attr tis_attr = { 0 };
897 /* Secondary process should not create the shared context. */
898 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
899 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
900 /* Search for IB context by device name. */
901 LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
902 if (!strcmp(sh->ibdev_name,
903 mlx5_os_get_dev_device_name(spawn->phys_dev))) {
908 /* No device found, we have to create new shared context. */
909 MLX5_ASSERT(spawn->max_port);
910 sh = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
911 sizeof(struct mlx5_dev_ctx_shared) +
913 sizeof(struct mlx5_dev_shared_port),
914 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
916 DRV_LOG(ERR, "shared context allocation failure");
920 err = mlx5_os_open_device(spawn, config, sh);
923 err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
925 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
929 sh->max_port = spawn->max_port;
930 strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
931 sizeof(sh->ibdev_name) - 1);
932 strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
933 sizeof(sh->ibdev_path) - 1);
935 * Setting port_id to max unallowed value means
936 * there is no interrupt subhandler installed for
937 * the given port index i.
939 for (i = 0; i < sh->max_port; i++) {
940 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
941 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
943 sh->pd = mlx5_glue->alloc_pd(sh->ctx);
944 if (sh->pd == NULL) {
945 DRV_LOG(ERR, "PD allocation failure");
950 /* Query the EQN for this core. */
951 err = mlx5_glue->devx_query_eqn(sh->ctx, 0, &sh->eqn);
954 DRV_LOG(ERR, "Failed to query event queue number %d.",
958 err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
960 DRV_LOG(ERR, "Fail to extract pdn from PD");
963 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
965 DRV_LOG(ERR, "TD allocation failure");
969 tis_attr.transport_domain = sh->td->id;
970 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
972 DRV_LOG(ERR, "TIS allocation failure");
976 err = mlx5_alloc_rxtx_uars(sh, config);
979 MLX5_ASSERT(sh->tx_uar);
980 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->tx_uar));
982 MLX5_ASSERT(sh->devx_rx_uar);
983 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar));
985 sh->flow_id_pool = mlx5_flow_id_pool_alloc
986 ((1 << HAIRPIN_FLOW_ID_BITS) - 1);
987 if (!sh->flow_id_pool) {
988 DRV_LOG(ERR, "can't create flow id pool");
993 /* Initialize UAR access locks for 32bit implementations. */
994 rte_spinlock_init(&sh->uar_lock_cq);
995 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
996 rte_spinlock_init(&sh->uar_lock[i]);
999 * Once the device is added to the list of memory event
1000 * callback, its global MR cache table cannot be expanded
1001 * on the fly because of deadlock. If it overflows, lookup
1002 * should be done by searching MR list linearly, which is slow.
1004 * At this point the device is not added to the memory
1005 * event list yet, context is just being created.
1007 err = mlx5_mr_btree_init(&sh->share_cache.cache,
1008 MLX5_MR_BTREE_CACHE_N * 2,
1009 spawn->pci_dev->device.numa_node);
1014 mlx5_os_set_reg_mr_cb(&sh->share_cache.reg_mr_cb,
1015 &sh->share_cache.dereg_mr_cb);
1016 mlx5_os_dev_shared_handler_install(sh);
1017 sh->cnt_id_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_DWORD);
1018 if (!sh->cnt_id_tbl) {
1022 mlx5_flow_aging_init(sh);
1023 mlx5_flow_counters_mng_init(sh);
1024 mlx5_flow_ipool_create(sh, config);
1025 /* Add device to memory callback list. */
1026 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1027 LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
1029 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1030 /* Add context to the global device list. */
1031 LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
1033 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1036 pthread_mutex_destroy(&sh->txpp.mutex);
1037 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1040 mlx5_l3t_destroy(sh->cnt_id_tbl);
1042 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1044 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1045 if (sh->devx_rx_uar)
1046 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1048 mlx5_glue->devx_free_uar(sh->tx_uar);
1050 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
1052 claim_zero(mlx5_glue->close_device(sh->ctx));
1053 if (sh->flow_id_pool)
1054 mlx5_flow_id_pool_release(sh->flow_id_pool);
1056 MLX5_ASSERT(err > 0);
1062 * Free shared IB device context. Decrement counter and if zero free
1063 * all allocated resources and close handles.
1066 * Pointer to mlx5_dev_ctx_shared object to free
1069 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
1071 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1072 #ifdef RTE_LIBRTE_MLX5_DEBUG
1073 /* Check the object presence in the list. */
1074 struct mlx5_dev_ctx_shared *lctx;
1076 LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
1081 DRV_LOG(ERR, "Freeing non-existing shared IB context");
1086 MLX5_ASSERT(sh->refcnt);
1087 /* Secondary process should not free the shared context. */
1088 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1091 /* Remove from memory callback device list. */
1092 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1093 LIST_REMOVE(sh, mem_event_cb);
1094 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1095 /* Release created Memory Regions. */
1096 mlx5_mr_release_cache(&sh->share_cache);
1097 /* Remove context from the global device list. */
1098 LIST_REMOVE(sh, next);
1099 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1101 * Ensure there is no async event handler installed.
1102 * Only primary process handles async device events.
1104 mlx5_flow_counters_mng_close(sh);
1105 mlx5_flow_ipool_destroy(sh);
1106 mlx5_os_dev_shared_handler_uninstall(sh);
1107 if (sh->cnt_id_tbl) {
1108 mlx5_l3t_destroy(sh->cnt_id_tbl);
1109 sh->cnt_id_tbl = NULL;
1112 mlx5_glue->devx_free_uar(sh->tx_uar);
1116 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
1118 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1120 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1121 if (sh->devx_rx_uar)
1122 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1124 claim_zero(mlx5_glue->close_device(sh->ctx));
1125 if (sh->flow_id_pool)
1126 mlx5_flow_id_pool_release(sh->flow_id_pool);
1127 pthread_mutex_destroy(&sh->txpp.mutex);
1131 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1135 * Destroy table hash list and all the root entries per domain.
1138 * Pointer to the private device data structure.
1141 mlx5_free_table_hash_list(struct mlx5_priv *priv)
1143 struct mlx5_dev_ctx_shared *sh = priv->sh;
1144 struct mlx5_flow_tbl_data_entry *tbl_data;
1145 union mlx5_flow_tbl_key table_key = {
1153 struct mlx5_hlist_entry *pos;
1157 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
1159 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
1161 MLX5_ASSERT(tbl_data);
1162 mlx5_hlist_remove(sh->flow_tbls, pos);
1163 mlx5_free(tbl_data);
1165 table_key.direction = 1;
1166 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
1168 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
1170 MLX5_ASSERT(tbl_data);
1171 mlx5_hlist_remove(sh->flow_tbls, pos);
1172 mlx5_free(tbl_data);
1174 table_key.direction = 0;
1175 table_key.domain = 1;
1176 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
1178 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
1180 MLX5_ASSERT(tbl_data);
1181 mlx5_hlist_remove(sh->flow_tbls, pos);
1182 mlx5_free(tbl_data);
1184 mlx5_hlist_destroy(sh->flow_tbls, NULL, NULL);
1188 * Initialize flow table hash list and create the root tables entry
1192 * Pointer to the private device data structure.
1195 * Zero on success, positive error code otherwise.
1198 mlx5_alloc_table_hash_list(struct mlx5_priv *priv)
1200 struct mlx5_dev_ctx_shared *sh = priv->sh;
1201 char s[MLX5_HLIST_NAMESIZE];
1205 snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1206 sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE);
1207 if (!sh->flow_tbls) {
1208 DRV_LOG(ERR, "flow tables with hash creation failed.");
1212 #ifndef HAVE_MLX5DV_DR
1214 * In case we have not DR support, the zero tables should be created
1215 * because DV expect to see them even if they cannot be created by
1218 union mlx5_flow_tbl_key table_key = {
1226 struct mlx5_flow_tbl_data_entry *tbl_data = mlx5_malloc(MLX5_MEM_ZERO,
1227 sizeof(*tbl_data), 0,
1234 tbl_data->entry.key = table_key.v64;
1235 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1238 rte_atomic32_init(&tbl_data->tbl.refcnt);
1239 rte_atomic32_inc(&tbl_data->tbl.refcnt);
1240 table_key.direction = 1;
1241 tbl_data = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tbl_data), 0,
1247 tbl_data->entry.key = table_key.v64;
1248 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1251 rte_atomic32_init(&tbl_data->tbl.refcnt);
1252 rte_atomic32_inc(&tbl_data->tbl.refcnt);
1253 table_key.direction = 0;
1254 table_key.domain = 1;
1255 tbl_data = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tbl_data), 0,
1261 tbl_data->entry.key = table_key.v64;
1262 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1265 rte_atomic32_init(&tbl_data->tbl.refcnt);
1266 rte_atomic32_inc(&tbl_data->tbl.refcnt);
1269 mlx5_free_table_hash_list(priv);
1270 #endif /* HAVE_MLX5DV_DR */
1275 * Retrieve integer value from environment variable.
1278 * Environment variable name.
1281 * Integer value, 0 if the variable is not set.
1284 mlx5_getenv_int(const char *name)
1286 const char *val = getenv(name);
1294 * DPDK callback to add udp tunnel port
1297 * A pointer to eth_dev
1298 * @param[in] udp_tunnel
1299 * A pointer to udp tunnel
1302 * 0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1305 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1306 struct rte_eth_udp_tunnel *udp_tunnel)
1308 MLX5_ASSERT(udp_tunnel != NULL);
1309 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1310 udp_tunnel->udp_port == 4789)
1312 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1313 udp_tunnel->udp_port == 4790)
1319 * Initialize process private data structure.
1322 * Pointer to Ethernet device structure.
1325 * 0 on success, a negative errno value otherwise and rte_errno is set.
1328 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1330 struct mlx5_priv *priv = dev->data->dev_private;
1331 struct mlx5_proc_priv *ppriv;
1335 * UAR register table follows the process private structure. BlueFlame
1336 * registers for Tx queues are stored in the table.
1339 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1340 ppriv = mlx5_malloc(MLX5_MEM_RTE, ppriv_size, RTE_CACHE_LINE_SIZE,
1341 dev->device->numa_node);
1346 ppriv->uar_table_sz = ppriv_size;
1347 dev->process_private = ppriv;
1352 * Un-initialize process private data structure.
1355 * Pointer to Ethernet device structure.
1358 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1360 if (!dev->process_private)
1362 mlx5_free(dev->process_private);
1363 dev->process_private = NULL;
1367 * DPDK callback to close the device.
1369 * Destroy all queues and objects, free memory.
1372 * Pointer to Ethernet device structure.
1375 mlx5_dev_close(struct rte_eth_dev *dev)
1377 struct mlx5_priv *priv = dev->data->dev_private;
1381 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1382 /* Check if process_private released. */
1383 if (!dev->process_private)
1385 mlx5_tx_uar_uninit_secondary(dev);
1386 mlx5_proc_priv_uninit(dev);
1387 rte_eth_dev_release_port(dev);
1392 DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1394 ((priv->sh->ctx != NULL) ?
1395 mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
1397 * If default mreg copy action is removed at the stop stage,
1398 * the search will return none and nothing will be done anymore.
1400 mlx5_flow_stop_default(dev);
1401 mlx5_traffic_disable(dev);
1403 * If all the flows are already flushed in the device stop stage,
1404 * then this will return directly without any action.
1406 mlx5_flow_list_flush(dev, &priv->flows, true);
1407 mlx5_flow_meter_flush(dev, NULL);
1408 /* Free the intermediate buffers for flow creation. */
1409 mlx5_flow_free_intermediate(dev);
1410 /* Prevent crashes when queues are still in use. */
1411 dev->rx_pkt_burst = removed_rx_burst;
1412 dev->tx_pkt_burst = removed_tx_burst;
1414 /* Disable datapath on secondary process. */
1415 mlx5_mp_os_req_stop_rxtx(dev);
1416 /* Free the eCPRI flex parser resource. */
1417 mlx5_flex_parser_ecpri_release(dev);
1418 if (priv->rxqs != NULL) {
1419 /* XXX race condition if mlx5_rx_burst() is still running. */
1421 for (i = 0; (i != priv->rxqs_n); ++i)
1422 mlx5_rxq_release(dev, i);
1426 if (priv->txqs != NULL) {
1427 /* XXX race condition if mlx5_tx_burst() is still running. */
1429 for (i = 0; (i != priv->txqs_n); ++i)
1430 mlx5_txq_release(dev, i);
1434 mlx5_proc_priv_uninit(dev);
1435 if (priv->mreg_cp_tbl)
1436 mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
1437 mlx5_mprq_free_mp(dev);
1438 mlx5_os_free_shared_dr(priv);
1439 if (priv->rss_conf.rss_key != NULL)
1440 mlx5_free(priv->rss_conf.rss_key);
1441 if (priv->reta_idx != NULL)
1442 mlx5_free(priv->reta_idx);
1443 if (priv->config.vf)
1444 mlx5_os_mac_addr_flush(dev);
1445 if (priv->nl_socket_route >= 0)
1446 close(priv->nl_socket_route);
1447 if (priv->nl_socket_rdma >= 0)
1448 close(priv->nl_socket_rdma);
1449 if (priv->vmwa_context)
1450 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1451 ret = mlx5_hrxq_verify(dev);
1453 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1454 dev->data->port_id);
1455 ret = mlx5_ind_table_obj_verify(dev);
1457 DRV_LOG(WARNING, "port %u some indirection table still remain",
1458 dev->data->port_id);
1459 ret = mlx5_rxq_obj_verify(dev);
1461 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1462 dev->data->port_id);
1463 ret = mlx5_rxq_verify(dev);
1465 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1466 dev->data->port_id);
1467 ret = mlx5_txq_obj_verify(dev);
1469 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1470 dev->data->port_id);
1471 ret = mlx5_txq_verify(dev);
1473 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1474 dev->data->port_id);
1475 ret = mlx5_flow_verify(dev);
1477 DRV_LOG(WARNING, "port %u some flows still remain",
1478 dev->data->port_id);
1480 * Free the shared context in last turn, because the cleanup
1481 * routines above may use some shared fields, like
1482 * mlx5_os_mac_addr_flush() uses ibdev_path for retrieveing
1483 * ifindex if Netlink fails.
1485 mlx5_free_shared_dev_ctx(priv->sh);
1486 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1490 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1491 struct mlx5_priv *opriv =
1492 rte_eth_devices[port_id].data->dev_private;
1495 opriv->domain_id != priv->domain_id ||
1496 &rte_eth_devices[port_id] == dev)
1502 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1504 memset(priv, 0, sizeof(*priv));
1505 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1507 * Reset mac_addrs to NULL such that it is not freed as part of
1508 * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1509 * it is freed when dev_private is freed.
1511 dev->data->mac_addrs = NULL;
1516 * Verify and store value for device argument.
1519 * Key argument to verify.
1521 * Value associated with key.
1526 * 0 on success, a negative errno value otherwise and rte_errno is set.
1529 mlx5_args_check(const char *key, const char *val, void *opaque)
1531 struct mlx5_dev_config *config = opaque;
1535 /* No-op, port representors are processed in mlx5_dev_spawn(). */
1536 if (!strcmp(MLX5_REPRESENTOR, key))
1539 tmp = strtol(val, NULL, 0);
1542 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1545 if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
1546 /* Negative values are acceptable for some keys only. */
1548 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
1551 mod = tmp >= 0 ? tmp : -tmp;
1552 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1553 config->cqe_comp = !!tmp;
1554 } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
1555 config->cqe_pad = !!tmp;
1556 } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1557 config->hw_padding = !!tmp;
1558 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1559 config->mprq.enabled = !!tmp;
1560 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1561 config->mprq.stride_num_n = tmp;
1562 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1563 config->mprq.stride_size_n = tmp;
1564 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1565 config->mprq.max_memcpy_len = tmp;
1566 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1567 config->mprq.min_rxqs_num = tmp;
1568 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1569 DRV_LOG(WARNING, "%s: deprecated parameter,"
1570 " converted to txq_inline_max", key);
1571 config->txq_inline_max = tmp;
1572 } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1573 config->txq_inline_max = tmp;
1574 } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1575 config->txq_inline_min = tmp;
1576 } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1577 config->txq_inline_mpw = tmp;
1578 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1579 config->txqs_inline = tmp;
1580 } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1581 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1582 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1583 config->mps = !!tmp;
1584 } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1585 if (tmp != MLX5_TXDB_CACHED &&
1586 tmp != MLX5_TXDB_NCACHED &&
1587 tmp != MLX5_TXDB_HEURISTIC) {
1588 DRV_LOG(ERR, "invalid Tx doorbell "
1589 "mapping parameter");
1594 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1595 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1596 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1597 DRV_LOG(WARNING, "%s: deprecated parameter,"
1598 " converted to txq_inline_mpw", key);
1599 config->txq_inline_mpw = tmp;
1600 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1601 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1602 } else if (strcmp(MLX5_TX_PP, key) == 0) {
1604 DRV_LOG(ERR, "Zero Tx packet pacing parameter");
1608 config->tx_pp = tmp;
1609 } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
1610 config->tx_skew = tmp;
1611 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1612 config->rx_vec_en = !!tmp;
1613 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1614 config->l3_vxlan_en = !!tmp;
1615 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1616 config->vf_nl_en = !!tmp;
1617 } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1618 config->dv_esw_en = !!tmp;
1619 } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1620 config->dv_flow_en = !!tmp;
1621 } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1622 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1623 tmp != MLX5_XMETA_MODE_META16 &&
1624 tmp != MLX5_XMETA_MODE_META32) {
1625 DRV_LOG(ERR, "invalid extensive "
1626 "metadata parameter");
1630 config->dv_xmeta_en = tmp;
1631 } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
1632 config->lacp_by_user = !!tmp;
1633 } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1634 config->mr_ext_memseg_en = !!tmp;
1635 } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1636 config->max_dump_files_num = tmp;
1637 } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1638 config->lro.timeout = tmp;
1639 } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1640 DRV_LOG(DEBUG, "class argument is %s.", val);
1641 } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1642 config->log_hp_size = tmp;
1643 } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1644 if (tmp != MLX5_RCM_NONE &&
1645 tmp != MLX5_RCM_LIGHT &&
1646 tmp != MLX5_RCM_AGGR) {
1647 DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1651 config->reclaim_mode = tmp;
1652 } else if (strcmp(MLX5_SYS_MEM_EN, key) == 0) {
1653 config->sys_mem_en = !!tmp;
1654 } else if (strcmp(MLX5_DECAP_EN, key) == 0) {
1655 config->decap_en = !!tmp;
1657 DRV_LOG(WARNING, "%s: unknown parameter", key);
1665 * Parse device parameters.
1668 * Pointer to device configuration structure.
1670 * Device arguments structure.
1673 * 0 on success, a negative errno value otherwise and rte_errno is set.
1676 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1678 const char **params = (const char *[]){
1679 MLX5_RXQ_CQE_COMP_EN,
1680 MLX5_RXQ_CQE_PAD_EN,
1681 MLX5_RXQ_PKT_PAD_EN,
1683 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1684 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1685 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1688 MLX5_TXQ_INLINE_MIN,
1689 MLX5_TXQ_INLINE_MAX,
1690 MLX5_TXQ_INLINE_MPW,
1691 MLX5_TXQS_MIN_INLINE,
1694 MLX5_TXQ_MPW_HDR_DSEG_EN,
1695 MLX5_TXQ_MAX_INLINE_LEN,
1707 MLX5_MR_EXT_MEMSEG_EN,
1709 MLX5_MAX_DUMP_FILES_NUM,
1710 MLX5_LRO_TIMEOUT_USEC,
1711 MLX5_CLASS_ARG_NAME,
1718 struct rte_kvargs *kvlist;
1722 if (devargs == NULL)
1724 /* Following UGLY cast is done to pass checkpatch. */
1725 kvlist = rte_kvargs_parse(devargs->args, params);
1726 if (kvlist == NULL) {
1730 /* Process parameters. */
1731 for (i = 0; (params[i] != NULL); ++i) {
1732 if (rte_kvargs_count(kvlist, params[i])) {
1733 ret = rte_kvargs_process(kvlist, params[i],
1734 mlx5_args_check, config);
1737 rte_kvargs_free(kvlist);
1742 rte_kvargs_free(kvlist);
1747 * Configures the minimal amount of data to inline into WQE
1748 * while sending packets.
1750 * - the txq_inline_min has the maximal priority, if this
1751 * key is specified in devargs
1752 * - if DevX is enabled the inline mode is queried from the
1753 * device (HCA attributes and NIC vport context if needed).
1754 * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1755 * and none (0 bytes) for other NICs
1758 * Verbs device parameters (name, port, switch_info) to spawn.
1760 * Device configuration parameters.
1763 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1764 struct mlx5_dev_config *config)
1766 if (config->txq_inline_min != MLX5_ARG_UNSET) {
1767 /* Application defines size of inlined data explicitly. */
1768 switch (spawn->pci_dev->id.device_id) {
1769 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1770 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1771 if (config->txq_inline_min <
1772 (int)MLX5_INLINE_HSIZE_L2) {
1774 "txq_inline_mix aligned to minimal"
1775 " ConnectX-4 required value %d",
1776 (int)MLX5_INLINE_HSIZE_L2);
1777 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1783 if (config->hca_attr.eth_net_offloads) {
1784 /* We have DevX enabled, inline mode queried successfully. */
1785 switch (config->hca_attr.wqe_inline_mode) {
1786 case MLX5_CAP_INLINE_MODE_L2:
1787 /* outer L2 header must be inlined. */
1788 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1790 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1791 /* No inline data are required by NIC. */
1792 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1793 config->hw_vlan_insert =
1794 config->hca_attr.wqe_vlan_insert;
1795 DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1797 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1798 /* inline mode is defined by NIC vport context. */
1799 if (!config->hca_attr.eth_virt)
1801 switch (config->hca_attr.vport_inline_mode) {
1802 case MLX5_INLINE_MODE_NONE:
1803 config->txq_inline_min =
1804 MLX5_INLINE_HSIZE_NONE;
1806 case MLX5_INLINE_MODE_L2:
1807 config->txq_inline_min =
1808 MLX5_INLINE_HSIZE_L2;
1810 case MLX5_INLINE_MODE_IP:
1811 config->txq_inline_min =
1812 MLX5_INLINE_HSIZE_L3;
1814 case MLX5_INLINE_MODE_TCP_UDP:
1815 config->txq_inline_min =
1816 MLX5_INLINE_HSIZE_L4;
1818 case MLX5_INLINE_MODE_INNER_L2:
1819 config->txq_inline_min =
1820 MLX5_INLINE_HSIZE_INNER_L2;
1822 case MLX5_INLINE_MODE_INNER_IP:
1823 config->txq_inline_min =
1824 MLX5_INLINE_HSIZE_INNER_L3;
1826 case MLX5_INLINE_MODE_INNER_TCP_UDP:
1827 config->txq_inline_min =
1828 MLX5_INLINE_HSIZE_INNER_L4;
1834 * We get here if we are unable to deduce
1835 * inline data size with DevX. Try PCI ID
1836 * to determine old NICs.
1838 switch (spawn->pci_dev->id.device_id) {
1839 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1840 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1841 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
1842 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1843 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1844 config->hw_vlan_insert = 0;
1846 case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
1847 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1848 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
1849 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1851 * These NICs support VLAN insertion from WQE and
1852 * report the wqe_vlan_insert flag. But there is the bug
1853 * and PFC control may be broken, so disable feature.
1855 config->hw_vlan_insert = 0;
1856 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1859 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1863 DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
1867 * Configures the metadata mask fields in the shared context.
1870 * Pointer to Ethernet device.
1873 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
1875 struct mlx5_priv *priv = dev->data->dev_private;
1876 struct mlx5_dev_ctx_shared *sh = priv->sh;
1877 uint32_t meta, mark, reg_c0;
1879 reg_c0 = ~priv->vport_meta_mask;
1880 switch (priv->config.dv_xmeta_en) {
1881 case MLX5_XMETA_MODE_LEGACY:
1883 mark = MLX5_FLOW_MARK_MASK;
1885 case MLX5_XMETA_MODE_META16:
1886 meta = reg_c0 >> rte_bsf32(reg_c0);
1887 mark = MLX5_FLOW_MARK_MASK;
1889 case MLX5_XMETA_MODE_META32:
1891 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
1899 if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
1900 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
1901 sh->dv_mark_mask, mark);
1903 sh->dv_mark_mask = mark;
1904 if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
1905 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
1906 sh->dv_meta_mask, meta);
1908 sh->dv_meta_mask = meta;
1909 if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
1910 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
1911 sh->dv_meta_mask, reg_c0);
1913 sh->dv_regc0_mask = reg_c0;
1914 DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
1915 DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
1916 DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
1917 DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
1921 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
1923 static const char *const dynf_names[] = {
1924 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
1925 RTE_MBUF_DYNFLAG_METADATA_NAME,
1926 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
1930 if (n < RTE_DIM(dynf_names))
1932 for (i = 0; i < RTE_DIM(dynf_names); i++) {
1933 if (names[i] == NULL)
1935 strcpy(names[i], dynf_names[i]);
1937 return RTE_DIM(dynf_names);
1941 * Comparison callback to sort device data.
1943 * This is meant to be used with qsort().
1946 * Pointer to pointer to first data object.
1948 * Pointer to pointer to second data object.
1951 * 0 if both objects are equal, less than 0 if the first argument is less
1952 * than the second, greater than 0 otherwise.
1955 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
1956 struct mlx5_dev_config *config)
1958 struct mlx5_dev_ctx_shared *sh = priv->sh;
1959 struct mlx5_dev_config *sh_conf = NULL;
1963 /* Nothing to compare for the single/first device. */
1964 if (sh->refcnt == 1)
1966 /* Find the device with shared context. */
1967 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1968 struct mlx5_priv *opriv =
1969 rte_eth_devices[port_id].data->dev_private;
1971 if (opriv && opriv != priv && opriv->sh == sh) {
1972 sh_conf = &opriv->config;
1978 if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
1979 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
1980 " for shared %s context", sh->ibdev_name);
1984 if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
1985 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
1986 " for shared %s context", sh->ibdev_name);
1994 * Look for the ethernet device belonging to mlx5 driver.
1996 * @param[in] port_id
1997 * port_id to start looking for device.
1998 * @param[in] pci_dev
1999 * Pointer to the hint PCI device. When device is being probed
2000 * the its siblings (master and preceding representors might
2001 * not have assigned driver yet (because the mlx5_os_pci_probe()
2002 * is not completed yet, for this case match on hint PCI
2003 * device may be used to detect sibling device.
2006 * port_id of found device, RTE_MAX_ETHPORT if not found.
2009 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
2011 while (port_id < RTE_MAX_ETHPORTS) {
2012 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
2014 if (dev->state != RTE_ETH_DEV_UNUSED &&
2016 (dev->device == &pci_dev->device ||
2017 (dev->device->driver &&
2018 dev->device->driver->name &&
2019 !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
2023 if (port_id >= RTE_MAX_ETHPORTS)
2024 return RTE_MAX_ETHPORTS;
2029 * DPDK callback to remove a PCI device.
2031 * This function removes all Ethernet devices belong to a given PCI device.
2033 * @param[in] pci_dev
2034 * Pointer to the PCI device.
2037 * 0 on success, the function cannot fail.
2040 mlx5_pci_remove(struct rte_pci_device *pci_dev)
2045 RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
2047 * mlx5_dev_close() is not registered to secondary process,
2048 * call the close function explicitly for secondary process.
2050 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
2051 ret |= mlx5_dev_close(&rte_eth_devices[port_id]);
2053 ret |= rte_eth_dev_close(port_id);
2055 return ret == 0 ? 0 : -EIO;
2058 static const struct rte_pci_id mlx5_pci_id_map[] = {
2060 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2061 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
2064 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2065 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
2068 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2069 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
2072 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2073 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
2076 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2077 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
2080 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2081 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
2084 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2085 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
2088 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2089 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
2092 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2093 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
2096 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2097 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
2100 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2101 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
2104 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2105 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
2108 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2109 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
2112 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2113 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF)
2116 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2117 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
2120 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2121 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
2128 static struct mlx5_pci_driver mlx5_driver = {
2129 .driver_class = MLX5_CLASS_NET,
2132 .name = MLX5_DRIVER_NAME,
2134 .id_table = mlx5_pci_id_map,
2135 .probe = mlx5_os_pci_probe,
2136 .remove = mlx5_pci_remove,
2137 .dma_map = mlx5_dma_map,
2138 .dma_unmap = mlx5_dma_unmap,
2139 .drv_flags = PCI_DRV_FLAGS,
2143 /* Initialize driver log type. */
2144 RTE_LOG_REGISTER(mlx5_logtype, pmd.net.mlx5, NOTICE)
2147 * Driver initialization routine.
2149 RTE_INIT(rte_mlx5_pmd_init)
2152 /* Build the static tables for Verbs conversion. */
2153 mlx5_set_ptype_table();
2154 mlx5_set_cksum_table();
2155 mlx5_set_swp_types_table();
2157 mlx5_pci_driver_register(&mlx5_driver);
2160 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
2161 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
2162 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");