4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
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8 * modification, are permitted provided that the following conditions
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44 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
46 #pragma GCC diagnostic ignored "-Wpedantic"
48 #include <infiniband/verbs.h>
50 #pragma GCC diagnostic error "-Wpedantic"
53 #include <rte_malloc.h>
54 #include <rte_ethdev.h>
55 #include <rte_ethdev_pci.h>
57 #include <rte_common.h>
58 #include <rte_kvargs.h>
61 #include "mlx5_utils.h"
62 #include "mlx5_rxtx.h"
63 #include "mlx5_autoconf.h"
64 #include "mlx5_defs.h"
66 /* Device parameter to enable RX completion queue compression. */
67 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
69 /* Device parameter to configure inline send. */
70 #define MLX5_TXQ_INLINE "txq_inline"
73 * Device parameter to configure the number of TX queues threshold for
74 * enabling inline send.
76 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
78 /* Device parameter to enable multi-packet send WQEs. */
79 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
81 /* Device parameter to include 2 dsegs in the title WQEBB. */
82 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
84 /* Device parameter to limit the size of inlining packet. */
85 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
87 /* Device parameter to enable hardware TSO offload. */
88 #define MLX5_TSO "tso"
90 /* Device parameter to enable hardware Tx vector. */
91 #define MLX5_TX_VEC_EN "tx_vec_en"
93 /* Device parameter to enable hardware Rx vector. */
94 #define MLX5_RX_VEC_EN "rx_vec_en"
96 /* Default PMD specific parameter value. */
97 #define MLX5_ARG_UNSET (-1)
99 #ifndef HAVE_IBV_MLX5_MOD_MPW
100 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2)
101 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3)
110 int inline_max_packet_sz;
116 * Retrieve integer value from environment variable.
119 * Environment variable name.
122 * Integer value, 0 if the variable is not set.
125 mlx5_getenv_int(const char *name)
127 const char *val = getenv(name);
135 * Verbs callback to allocate a memory. This function should allocate the space
136 * according to the size provided residing inside a huge page.
137 * Please note that all allocation must respect the alignment from libmlx5
138 * (i.e. currently sysconf(_SC_PAGESIZE)).
141 * The size in bytes of the memory to allocate.
143 * A pointer to the callback data.
146 * a pointer to the allocate space.
149 mlx5_alloc_verbs_buf(size_t size, void *data)
151 struct priv *priv = data;
153 size_t alignment = sysconf(_SC_PAGESIZE);
155 assert(data != NULL);
156 assert(!mlx5_is_secondary());
157 ret = rte_malloc_socket(__func__, size, alignment,
158 priv->dev->device->numa_node);
159 DEBUG("Extern alloc size: %lu, align: %lu: %p", size, alignment, ret);
164 * Verbs callback to free a memory.
167 * A pointer to the memory to free.
169 * A pointer to the callback data.
172 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused)
174 assert(data != NULL);
175 assert(!mlx5_is_secondary());
176 DEBUG("Extern free request: %p", ptr);
181 * DPDK callback to close the device.
183 * Destroy all queues and objects, free memory.
186 * Pointer to Ethernet device structure.
189 mlx5_dev_close(struct rte_eth_dev *dev)
191 struct priv *priv = mlx5_get_priv(dev);
195 DEBUG("%p: closing device \"%s\"",
197 ((priv->ctx != NULL) ? priv->ctx->device->name : ""));
198 /* In case mlx5_dev_stop() has not been called. */
199 priv_dev_interrupt_handler_uninstall(priv, dev);
200 priv_special_flow_disable_all(priv);
201 priv_mac_addrs_disable(priv);
202 priv_destroy_hash_rxqs(priv);
204 /* Prevent crashes when queues are still in use. */
205 dev->rx_pkt_burst = removed_rx_burst;
206 dev->tx_pkt_burst = removed_tx_burst;
207 if (priv->rxqs != NULL) {
208 /* XXX race condition if mlx5_rx_burst() is still running. */
210 for (i = 0; (i != priv->rxqs_n); ++i) {
211 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
212 struct mlx5_rxq_ctrl *rxq_ctrl;
216 rxq_ctrl = container_of(rxq, struct mlx5_rxq_ctrl, rxq);
217 (*priv->rxqs)[i] = NULL;
218 mlx5_rxq_cleanup(rxq_ctrl);
224 if (priv->txqs != NULL) {
225 /* XXX race condition if mlx5_tx_burst() is still running. */
227 for (i = 0; (i != priv->txqs_n); ++i) {
228 struct mlx5_txq_data *txq = (*priv->txqs)[i];
229 struct mlx5_txq_ctrl *txq_ctrl;
233 txq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq);
234 (*priv->txqs)[i] = NULL;
235 mlx5_txq_cleanup(txq_ctrl);
241 if (priv->pd != NULL) {
242 assert(priv->ctx != NULL);
243 claim_zero(ibv_dealloc_pd(priv->pd));
244 claim_zero(ibv_close_device(priv->ctx));
246 assert(priv->ctx == NULL);
247 if (priv->rss_conf != NULL) {
248 for (i = 0; (i != hash_rxq_init_n); ++i)
249 rte_free((*priv->rss_conf)[i]);
250 rte_free(priv->rss_conf);
252 if (priv->reta_idx != NULL)
253 rte_free(priv->reta_idx);
254 priv_socket_uninit(priv);
256 memset(priv, 0, sizeof(*priv));
259 static const struct eth_dev_ops mlx5_dev_ops = {
260 .dev_configure = mlx5_dev_configure,
261 .dev_start = mlx5_dev_start,
262 .dev_stop = mlx5_dev_stop,
263 .dev_set_link_down = mlx5_set_link_down,
264 .dev_set_link_up = mlx5_set_link_up,
265 .dev_close = mlx5_dev_close,
266 .promiscuous_enable = mlx5_promiscuous_enable,
267 .promiscuous_disable = mlx5_promiscuous_disable,
268 .allmulticast_enable = mlx5_allmulticast_enable,
269 .allmulticast_disable = mlx5_allmulticast_disable,
270 .link_update = mlx5_link_update,
271 .stats_get = mlx5_stats_get,
272 .stats_reset = mlx5_stats_reset,
273 .xstats_get = mlx5_xstats_get,
274 .xstats_reset = mlx5_xstats_reset,
275 .xstats_get_names = mlx5_xstats_get_names,
276 .dev_infos_get = mlx5_dev_infos_get,
277 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
278 .vlan_filter_set = mlx5_vlan_filter_set,
279 .rx_queue_setup = mlx5_rx_queue_setup,
280 .tx_queue_setup = mlx5_tx_queue_setup,
281 .rx_queue_release = mlx5_rx_queue_release,
282 .tx_queue_release = mlx5_tx_queue_release,
283 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
284 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
285 .mac_addr_remove = mlx5_mac_addr_remove,
286 .mac_addr_add = mlx5_mac_addr_add,
287 .mac_addr_set = mlx5_mac_addr_set,
288 .mtu_set = mlx5_dev_set_mtu,
289 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
290 .vlan_offload_set = mlx5_vlan_offload_set,
291 .reta_update = mlx5_dev_rss_reta_update,
292 .reta_query = mlx5_dev_rss_reta_query,
293 .rss_hash_update = mlx5_rss_hash_update,
294 .rss_hash_conf_get = mlx5_rss_hash_conf_get,
295 .filter_ctrl = mlx5_dev_filter_ctrl,
296 .rx_descriptor_status = mlx5_rx_descriptor_status,
297 .tx_descriptor_status = mlx5_tx_descriptor_status,
298 .rx_queue_intr_enable = mlx5_rx_intr_enable,
299 .rx_queue_intr_disable = mlx5_rx_intr_disable,
303 static const struct eth_dev_ops mlx5_dev_sec_ops = {
304 .stats_get = mlx5_stats_get,
305 .stats_reset = mlx5_stats_reset,
306 .xstats_get = mlx5_xstats_get,
307 .xstats_reset = mlx5_xstats_reset,
308 .xstats_get_names = mlx5_xstats_get_names,
309 .dev_infos_get = mlx5_dev_infos_get,
310 .rx_descriptor_status = mlx5_rx_descriptor_status,
311 .tx_descriptor_status = mlx5_tx_descriptor_status,
315 struct rte_pci_addr pci_addr; /* associated PCI address */
316 uint32_t ports; /* physical ports bitfield. */
320 * Get device index in mlx5_dev[] from PCI bus address.
322 * @param[in] pci_addr
323 * PCI bus address to look for.
326 * mlx5_dev[] index on success, -1 on failure.
329 mlx5_dev_idx(struct rte_pci_addr *pci_addr)
334 assert(pci_addr != NULL);
335 for (i = 0; (i != RTE_DIM(mlx5_dev)); ++i) {
336 if ((mlx5_dev[i].pci_addr.domain == pci_addr->domain) &&
337 (mlx5_dev[i].pci_addr.bus == pci_addr->bus) &&
338 (mlx5_dev[i].pci_addr.devid == pci_addr->devid) &&
339 (mlx5_dev[i].pci_addr.function == pci_addr->function))
341 if ((mlx5_dev[i].ports == 0) && (ret == -1))
348 * Verify and store value for device argument.
351 * Key argument to verify.
353 * Value associated with key.
358 * 0 on success, negative errno value on failure.
361 mlx5_args_check(const char *key, const char *val, void *opaque)
363 struct mlx5_args *args = opaque;
367 tmp = strtoul(val, NULL, 0);
369 WARN("%s: \"%s\" is not a valid integer", key, val);
372 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
373 args->cqe_comp = !!tmp;
374 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
375 args->txq_inline = tmp;
376 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
377 args->txqs_inline = tmp;
378 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
380 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
381 args->mpw_hdr_dseg = !!tmp;
382 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
383 args->inline_max_packet_sz = tmp;
384 } else if (strcmp(MLX5_TSO, key) == 0) {
386 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
387 args->tx_vec_en = !!tmp;
388 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
389 args->rx_vec_en = !!tmp;
391 WARN("%s: unknown parameter", key);
398 * Parse device parameters.
401 * Pointer to private structure.
403 * Device arguments structure.
406 * 0 on success, errno value on failure.
409 mlx5_args(struct mlx5_args *args, struct rte_devargs *devargs)
411 const char **params = (const char *[]){
412 MLX5_RXQ_CQE_COMP_EN,
414 MLX5_TXQS_MIN_INLINE,
416 MLX5_TXQ_MPW_HDR_DSEG_EN,
417 MLX5_TXQ_MAX_INLINE_LEN,
423 struct rte_kvargs *kvlist;
429 /* Following UGLY cast is done to pass checkpatch. */
430 kvlist = rte_kvargs_parse(devargs->args, params);
433 /* Process parameters. */
434 for (i = 0; (params[i] != NULL); ++i) {
435 if (rte_kvargs_count(kvlist, params[i])) {
436 ret = rte_kvargs_process(kvlist, params[i],
437 mlx5_args_check, args);
439 rte_kvargs_free(kvlist);
444 rte_kvargs_free(kvlist);
448 static struct rte_pci_driver mlx5_driver;
451 * Assign parameters from args into priv, only non default
452 * values are considered.
455 * Pointer to private structure.
457 * Pointer to args values.
460 mlx5_args_assign(struct priv *priv, struct mlx5_args *args)
462 if (args->cqe_comp != MLX5_ARG_UNSET)
463 priv->cqe_comp = args->cqe_comp;
464 if (args->txq_inline != MLX5_ARG_UNSET)
465 priv->txq_inline = args->txq_inline;
466 if (args->txqs_inline != MLX5_ARG_UNSET)
467 priv->txqs_inline = args->txqs_inline;
468 if (args->mps != MLX5_ARG_UNSET)
469 priv->mps = args->mps ? priv->mps : 0;
470 if (args->mpw_hdr_dseg != MLX5_ARG_UNSET)
471 priv->mpw_hdr_dseg = args->mpw_hdr_dseg;
472 if (args->inline_max_packet_sz != MLX5_ARG_UNSET)
473 priv->inline_max_packet_sz = args->inline_max_packet_sz;
474 if (args->tso != MLX5_ARG_UNSET)
475 priv->tso = args->tso;
476 if (args->tx_vec_en != MLX5_ARG_UNSET)
477 priv->tx_vec_en = args->tx_vec_en;
478 if (args->rx_vec_en != MLX5_ARG_UNSET)
479 priv->rx_vec_en = args->rx_vec_en;
483 * DPDK callback to register a PCI device.
485 * This function creates an Ethernet device for each port of a given
489 * PCI driver structure (mlx5_driver).
491 * PCI device information.
494 * 0 on success, negative errno value on failure.
497 mlx5_pci_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
499 struct ibv_device **list;
500 struct ibv_device *ibv_dev;
502 struct ibv_context *attr_ctx = NULL;
503 struct ibv_device_attr_ex device_attr;
506 unsigned int tunnel_en = 0;
509 struct mlx5dv_context attrs_out;
512 assert(pci_drv == &mlx5_driver);
513 /* Get mlx5_dev[] index. */
514 idx = mlx5_dev_idx(&pci_dev->addr);
516 ERROR("this driver cannot support any more adapters");
519 DEBUG("using driver device index %d", idx);
521 /* Save PCI address. */
522 mlx5_dev[idx].pci_addr = pci_dev->addr;
523 list = ibv_get_device_list(&i);
527 ERROR("cannot list devices, is ib_uverbs loaded?");
532 * For each listed device, check related sysfs entry against
533 * the provided PCI ID.
536 struct rte_pci_addr pci_addr;
539 DEBUG("checking device \"%s\"", list[i]->name);
540 if (mlx5_ibv_device_to_pci_addr(list[i], &pci_addr))
542 if ((pci_dev->addr.domain != pci_addr.domain) ||
543 (pci_dev->addr.bus != pci_addr.bus) ||
544 (pci_dev->addr.devid != pci_addr.devid) ||
545 (pci_dev->addr.function != pci_addr.function))
547 sriov = ((pci_dev->id.device_id ==
548 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF) ||
549 (pci_dev->id.device_id ==
550 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF) ||
551 (pci_dev->id.device_id ==
552 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF) ||
553 (pci_dev->id.device_id ==
554 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF));
555 switch (pci_dev->id.device_id) {
556 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
559 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
560 case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
561 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
562 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
563 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
569 INFO("PCI information matches, using device \"%s\""
572 sriov ? "true" : "false");
573 attr_ctx = ibv_open_device(list[i]);
577 if (attr_ctx == NULL) {
578 ibv_free_device_list(list);
581 ERROR("cannot access device, is mlx5_ib loaded?");
584 ERROR("cannot use device, are drivers up to date?");
592 DEBUG("device opened");
594 * Multi-packet send is supported by ConnectX-4 Lx PF as well
595 * as all ConnectX-5 devices.
597 mlx5dv_query_device(attr_ctx, &attrs_out);
598 if (attrs_out.flags & (MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW |
599 MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED)) {
600 INFO("Enhanced MPW is detected\n");
601 mps = MLX5_MPW_ENHANCED;
602 } else if (attrs_out.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
603 INFO("MPW is detected\n");
606 INFO("MPW is disabled\n");
607 mps = MLX5_MPW_DISABLED;
609 if (ibv_query_device_ex(attr_ctx, NULL, &device_attr))
611 INFO("%u port(s) detected", device_attr.orig_attr.phys_port_cnt);
613 for (i = 0; i < device_attr.orig_attr.phys_port_cnt; i++) {
614 uint32_t port = i + 1; /* ports are indexed from one */
615 uint32_t test = (1 << i);
616 struct ibv_context *ctx = NULL;
617 struct ibv_port_attr port_attr;
618 struct ibv_pd *pd = NULL;
619 struct priv *priv = NULL;
620 struct rte_eth_dev *eth_dev;
621 struct ibv_device_attr_ex device_attr_ex;
622 struct ether_addr mac;
623 uint16_t num_vfs = 0;
624 struct mlx5_args args = {
625 .cqe_comp = MLX5_ARG_UNSET,
626 .txq_inline = MLX5_ARG_UNSET,
627 .txqs_inline = MLX5_ARG_UNSET,
628 .mps = MLX5_ARG_UNSET,
629 .mpw_hdr_dseg = MLX5_ARG_UNSET,
630 .inline_max_packet_sz = MLX5_ARG_UNSET,
631 .tso = MLX5_ARG_UNSET,
632 .tx_vec_en = MLX5_ARG_UNSET,
633 .rx_vec_en = MLX5_ARG_UNSET,
636 mlx5_dev[idx].ports |= test;
638 if (mlx5_is_secondary()) {
639 /* from rte_ethdev.c */
640 char name[RTE_ETH_NAME_MAX_LEN];
642 snprintf(name, sizeof(name), "%s port %u",
643 ibv_get_device_name(ibv_dev), port);
644 eth_dev = rte_eth_dev_attach_secondary(name);
645 if (eth_dev == NULL) {
646 ERROR("can not attach rte ethdev");
650 eth_dev->device = &pci_dev->device;
651 eth_dev->dev_ops = &mlx5_dev_sec_ops;
652 priv = eth_dev->data->dev_private;
653 /* Receive command fd from primary process */
654 err = priv_socket_connect(priv);
659 /* Remap UAR for Tx queues. */
660 err = priv_tx_uar_remap(priv, err);
665 priv_dev_select_rx_function(priv, eth_dev);
666 priv_dev_select_tx_function(priv, eth_dev);
670 DEBUG("using port %u (%08" PRIx32 ")", port, test);
672 ctx = ibv_open_device(ibv_dev);
678 /* Check port status. */
679 err = ibv_query_port(ctx, port, &port_attr);
681 ERROR("port query failed: %s", strerror(err));
685 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
686 ERROR("port %d is not configured in Ethernet mode",
692 if (port_attr.state != IBV_PORT_ACTIVE)
693 DEBUG("port %d is not active: \"%s\" (%d)",
694 port, ibv_port_state_str(port_attr.state),
697 /* Allocate protection domain. */
698 pd = ibv_alloc_pd(ctx);
700 ERROR("PD allocation failure");
705 mlx5_dev[idx].ports |= test;
707 /* from rte_ethdev.c */
708 priv = rte_zmalloc("ethdev private structure",
710 RTE_CACHE_LINE_SIZE);
712 ERROR("priv allocation failure");
718 strncpy(priv->ibdev_path, priv->ctx->device->ibdev_path,
719 sizeof(priv->ibdev_path));
720 priv->device_attr = device_attr;
723 priv->mtu = ETHER_MTU;
724 priv->mps = mps; /* Enable MPW by default if supported. */
725 priv->cqe_comp = 1; /* Enable compression by default. */
726 priv->tunnel_en = tunnel_en;
727 /* Enable vector by default if supported. */
730 err = mlx5_args(&args, pci_dev->device.devargs);
732 ERROR("failed to process device arguments: %s",
736 mlx5_args_assign(priv, &args);
737 if (ibv_query_device_ex(ctx, NULL, &device_attr_ex)) {
738 ERROR("ibv_query_device_ex() failed");
743 !!(device_attr_ex.device_cap_flags_ex &
744 IBV_DEVICE_RAW_IP_CSUM);
745 DEBUG("checksum offloading is %ssupported",
746 (priv->hw_csum ? "" : "not "));
748 #ifdef HAVE_IBV_DEVICE_VXLAN_SUPPORT
749 priv->hw_csum_l2tun = !!(exp_device_attr.exp_device_cap_flags &
750 IBV_DEVICE_VXLAN_SUPPORT);
752 DEBUG("L2 tunnel checksum offloads are %ssupported",
753 (priv->hw_csum_l2tun ? "" : "not "));
755 priv->ind_table_max_size =
756 device_attr_ex.rss_caps.max_rwq_indirection_table_size;
757 /* Remove this check once DPDK supports larger/variable
758 * indirection tables. */
759 if (priv->ind_table_max_size >
760 (unsigned int)ETH_RSS_RETA_SIZE_512)
761 priv->ind_table_max_size = ETH_RSS_RETA_SIZE_512;
762 DEBUG("maximum RX indirection table size is %u",
763 priv->ind_table_max_size);
764 priv->hw_vlan_strip = !!(device_attr_ex.raw_packet_caps &
765 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
766 DEBUG("VLAN stripping is %ssupported",
767 (priv->hw_vlan_strip ? "" : "not "));
770 !!(device_attr_ex.orig_attr.device_cap_flags &
771 IBV_WQ_FLAGS_SCATTER_FCS);
772 DEBUG("FCS stripping configuration is %ssupported",
773 (priv->hw_fcs_strip ? "" : "not "));
775 #ifdef HAVE_IBV_WQ_FLAG_RX_END_PADDING
776 priv->hw_padding = !!device_attr_ex.rx_pad_end_addr_align;
778 DEBUG("hardware RX end alignment padding is %ssupported",
779 (priv->hw_padding ? "" : "not "));
781 priv_get_num_vfs(priv, &num_vfs);
782 priv->sriov = (num_vfs || sriov);
783 priv->tso = ((priv->tso) &&
784 (device_attr_ex.tso_caps.max_tso > 0) &&
785 (device_attr_ex.tso_caps.supported_qpts &
786 (1 << IBV_QPT_RAW_PACKET)));
788 priv->max_tso_payload_sz =
789 device_attr_ex.tso_caps.max_tso;
790 if (priv->mps && !mps) {
791 ERROR("multi-packet send not supported on this device"
792 " (" MLX5_TXQ_MPW_EN ")");
795 } else if (priv->mps && priv->tso) {
796 WARN("multi-packet send not supported in conjunction "
797 "with TSO. MPS disabled");
801 priv->mps == MLX5_MPW_ENHANCED ? "Enhanced " : "",
802 priv->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled");
803 /* Set default values for Enhanced MPW, a.k.a MPWv2. */
804 if (priv->mps == MLX5_MPW_ENHANCED) {
805 if (args.txqs_inline == MLX5_ARG_UNSET)
806 priv->txqs_inline = MLX5_EMPW_MIN_TXQS;
807 if (args.inline_max_packet_sz == MLX5_ARG_UNSET)
808 priv->inline_max_packet_sz =
809 MLX5_EMPW_MAX_INLINE_LEN;
810 if (args.txq_inline == MLX5_ARG_UNSET)
811 priv->txq_inline = MLX5_WQE_SIZE_MAX -
814 /* Allocate and register default RSS hash keys. */
815 priv->rss_conf = rte_calloc(__func__, hash_rxq_init_n,
816 sizeof((*priv->rss_conf)[0]), 0);
817 if (priv->rss_conf == NULL) {
821 err = rss_hash_rss_conf_new_key(priv,
822 rss_hash_default_key,
823 rss_hash_default_key_len,
827 /* Configure the first MAC address by default. */
828 if (priv_get_mac(priv, &mac.addr_bytes)) {
829 ERROR("cannot get MAC address, is mlx5_en loaded?"
830 " (errno: %s)", strerror(errno));
834 INFO("port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x",
836 mac.addr_bytes[0], mac.addr_bytes[1],
837 mac.addr_bytes[2], mac.addr_bytes[3],
838 mac.addr_bytes[4], mac.addr_bytes[5]);
839 /* Register MAC address. */
840 claim_zero(priv_mac_addr_add(priv, 0,
841 (const uint8_t (*)[ETHER_ADDR_LEN])
845 char ifname[IF_NAMESIZE];
847 if (priv_get_ifname(priv, &ifname) == 0)
848 DEBUG("port %u ifname is \"%s\"",
851 DEBUG("port %u ifname is unknown", priv->port);
854 /* Get actual MTU if possible. */
855 priv_get_mtu(priv, &priv->mtu);
856 DEBUG("port %u MTU is %u", priv->port, priv->mtu);
858 /* from rte_ethdev.c */
860 char name[RTE_ETH_NAME_MAX_LEN];
862 snprintf(name, sizeof(name), "%s port %u",
863 ibv_get_device_name(ibv_dev), port);
864 eth_dev = rte_eth_dev_allocate(name);
866 if (eth_dev == NULL) {
867 ERROR("can not allocate rte ethdev");
871 eth_dev->data->dev_private = priv;
872 eth_dev->data->mac_addrs = priv->mac;
873 eth_dev->device = &pci_dev->device;
874 rte_eth_copy_pci_info(eth_dev, pci_dev);
875 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
876 eth_dev->device->driver = &mlx5_driver.driver;
878 eth_dev->dev_ops = &mlx5_dev_ops;
879 TAILQ_INIT(&priv->flows);
881 /* Hint libmlx5 to use PMD allocator for data plane resources */
882 struct mlx5dv_ctx_allocators alctr = {
883 .alloc = &mlx5_alloc_verbs_buf,
884 .free = &mlx5_free_verbs_buf,
887 mlx5dv_set_context_attr(ctx, MLX5DV_CTX_ATTR_BUF_ALLOCATORS,
888 (void *)((uintptr_t)&alctr));
890 /* Bring Ethernet device up. */
891 DEBUG("forcing Ethernet interface up");
892 priv_set_flags(priv, ~IFF_UP, IFF_UP);
893 mlx5_link_update(priv->dev, 1);
898 rte_free(priv->rss_conf);
902 claim_zero(ibv_dealloc_pd(pd));
904 claim_zero(ibv_close_device(ctx));
909 * XXX if something went wrong in the loop above, there is a resource
910 * leak (ctx, pd, priv, dpdk ethdev) but we can do nothing about it as
911 * long as the dpdk does not provide a way to deallocate a ethdev and a
912 * way to enumerate the registered ethdevs to free the previous ones.
915 /* no port found, complain */
916 if (!mlx5_dev[idx].ports) {
923 claim_zero(ibv_close_device(attr_ctx));
925 ibv_free_device_list(list);
930 static const struct rte_pci_id mlx5_pci_id_map[] = {
932 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
933 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
936 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
937 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
940 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
941 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
944 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
945 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
948 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
949 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
952 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
953 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
956 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
957 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
960 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
961 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
968 static struct rte_pci_driver mlx5_driver = {
970 .name = MLX5_DRIVER_NAME
972 .id_table = mlx5_pci_id_map,
973 .probe = mlx5_pci_probe,
974 .drv_flags = RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV,
978 * Driver initialization routine.
980 RTE_INIT(rte_mlx5_pmd_init);
982 rte_mlx5_pmd_init(void)
984 /* Build the static table for ptype conversion. */
985 mlx5_set_ptype_table();
987 * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use
988 * huge pages. Calling ibv_fork_init() during init allows
989 * applications to use fork() safely for purposes other than
990 * using this PMD, which is not supported in forked processes.
992 setenv("RDMAV_HUGEPAGES_SAFE", "1", 1);
993 /* Don't map UAR to WC if BlueFlame is not used.*/
994 setenv("MLX5_SHUT_UP_BF", "1", 1);
996 rte_pci_register(&mlx5_driver);
999 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
1000 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
1001 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");