drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <stdint.h>
  10 #include <stdlib.h>
  11 #include <errno.h>
  12
  13 #include <rte_malloc.h>
  14 #include <ethdev_driver.h>
  15 #include <rte_pci.h>
  16 #include <rte_bus_pci.h>
  17 #include <rte_common.h>
  18 #include <rte_kvargs.h>
  19 #include <rte_rwlock.h>
  20 #include <rte_spinlock.h>
  21 #include <rte_string_fns.h>
  22 #include <rte_alarm.h>
  23 #include <rte_cycles.h>
  24
  25 #include <mlx5_glue.h>
  26 #include <mlx5_devx_cmds.h>
  27 #include <mlx5_common.h>
  28 #include <mlx5_common_os.h>
  29 #include <mlx5_common_mp.h>
  30 #include <mlx5_malloc.h>
  31
  32 #include "mlx5_defs.h"
  33 #include "mlx5.h"
  34 #include "mlx5_utils.h"
  35 #include "mlx5_rxtx.h"
  36 #include "mlx5_rx.h"
  37 #include "mlx5_tx.h"
  38 #include "mlx5_autoconf.h"
  39 #include "mlx5_mr.h"
  40 #include "mlx5_flow.h"
  41 #include "mlx5_flow_os.h"
  42 #include "rte_pmd_mlx5.h"
  43
  44 #define MLX5_ETH_DRIVER_NAME mlx5_eth
  45
  46 /* Driver type key for new device global syntax. */
  47 #define MLX5_DRIVER_KEY "driver"
  48
  49 /* Device parameter to enable RX completion queue compression. */
  50 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  51
  52 /* Device parameter to enable padding Rx packet to cacheline size. */
  53 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
  54
  55 /* Device parameter to enable Multi-Packet Rx queue. */
  56 #define MLX5_RX_MPRQ_EN "mprq_en"
  57
  58 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
  59 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
  60
  61 /* Device parameter to configure log 2 of the stride size for MPRQ. */
  62 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
  63
  64 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
  65 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
  66
  67 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
  68 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
  69
  70 /* Device parameter to configure inline send. Deprecated, ignored.*/
  71 #define MLX5_TXQ_INLINE "txq_inline"
  72
  73 /* Device parameter to limit packet size to inline with ordinary SEND. */
  74 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
  75
  76 /* Device parameter to configure minimal data size to inline. */
  77 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
  78
  79 /* Device parameter to limit packet size to inline with Enhanced MPW. */
  80 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
  81
  82 /*
  83  * Device parameter to configure the number of TX queues threshold for
  84  * enabling inline send.
  85  */
  86 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  87
  88 /*
  89  * Device parameter to configure the number of TX queues threshold for
  90  * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
  91  */
  92 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
  93
  94 /* Device parameter to enable multi-packet send WQEs. */
  95 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
  96
  97 /*
  98  * Device parameter to force doorbell register mapping
  99  * to non-cahed region eliminating the extra write memory barrier.
 100  */
 101 #define MLX5_TX_DB_NC "tx_db_nc"
 102
 103 /*
 104  * Device parameter to include 2 dsegs in the title WQEBB.
 105  * Deprecated, ignored.
 106  */
 107 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
 108
 109 /*
 110  * Device parameter to limit the size of inlining packet.
 111  * Deprecated, ignored.
 112  */
 113 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
 114
 115 /*
 116  * Device parameter to enable Tx scheduling on timestamps
 117  * and specify the packet pacing granularity in nanoseconds.
 118  */
 119 #define MLX5_TX_PP "tx_pp"
 120
 121 /*
 122  * Device parameter to specify skew in nanoseconds on Tx datapath,
 123  * it represents the time between SQ start WQE processing and
 124  * appearing actual packet data on the wire.
 125  */
 126 #define MLX5_TX_SKEW "tx_skew"
 127
 128 /*
 129  * Device parameter to enable hardware Tx vector.
 130  * Deprecated, ignored (no vectorized Tx routines anymore).
 131  */
 132 #define MLX5_TX_VEC_EN "tx_vec_en"
 133
 134 /* Device parameter to enable hardware Rx vector. */
 135 #define MLX5_RX_VEC_EN "rx_vec_en"
 136
 137 /* Allow L3 VXLAN flow creation. */
 138 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
 139
 140 /* Activate DV E-Switch flow steering. */
 141 #define MLX5_DV_ESW_EN "dv_esw_en"
 142
 143 /* Activate DV flow steering. */
 144 #define MLX5_DV_FLOW_EN "dv_flow_en"
 145
 146 /* Enable extensive flow metadata support. */
 147 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
 148
 149 /* Device parameter to let the user manage the lacp traffic of bonded device */
 150 #define MLX5_LACP_BY_USER "lacp_by_user"
 151
 152 /* Activate Netlink support in VF mode. */
 153 #define MLX5_VF_NL_EN "vf_nl_en"
 154
 155 /* Enable extending memsegs when creating a MR. */
 156 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
 157
 158 /* Select port representors to instantiate. */
 159 #define MLX5_REPRESENTOR "representor"
 160
 161 /* Device parameter to configure the maximum number of dump files per queue. */
 162 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
 163
 164 /* Configure timeout of LRO session (in microseconds). */
 165 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
 166
 167 /*
 168  * Device parameter to configure the total data buffer size for a single
 169  * hairpin queue (logarithm value).
 170  */
 171 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
 172
 173 /* Flow memory reclaim mode. */
 174 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
 175
 176 /* The default memory allocator used in PMD. */
 177 #define MLX5_SYS_MEM_EN "sys_mem_en"
 178 /* Decap will be used or not. */
 179 #define MLX5_DECAP_EN "decap_en"
 180
 181 /* Device parameter to configure allow or prevent duplicate rules pattern. */
 182 #define MLX5_ALLOW_DUPLICATE_PATTERN "allow_duplicate_pattern"
 183
 184 /* Device parameter to configure implicit registration of mempool memory. */
 185 #define MLX5_MR_MEMPOOL_REG_EN "mr_mempool_reg_en"
 186
 187 /* Shared memory between primary and secondary processes. */
 188 struct mlx5_shared_data *mlx5_shared_data;
 189
 190 /** Driver-specific log messages type. */
 191 int mlx5_logtype;
 192
 193 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
 194                                                 LIST_HEAD_INITIALIZER();
 195 static pthread_mutex_t mlx5_dev_ctx_list_mutex;
 196 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
 197 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
 198         [MLX5_IPOOL_DECAP_ENCAP] = {
 199                 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
 200                 .trunk_size = 64,
 201                 .grow_trunk = 3,
 202                 .grow_shift = 2,
 203                 .need_lock = 1,
 204                 .release_mem_en = 1,
 205                 .malloc = mlx5_malloc,
 206                 .free = mlx5_free,
 207                 .type = "mlx5_encap_decap_ipool",
 208         },
 209         [MLX5_IPOOL_PUSH_VLAN] = {
 210                 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
 211                 .trunk_size = 64,
 212                 .grow_trunk = 3,
 213                 .grow_shift = 2,
 214                 .need_lock = 1,
 215                 .release_mem_en = 1,
 216                 .malloc = mlx5_malloc,
 217                 .free = mlx5_free,
 218                 .type = "mlx5_push_vlan_ipool",
 219         },
 220         [MLX5_IPOOL_TAG] = {
 221                 .size = sizeof(struct mlx5_flow_dv_tag_resource),
 222                 .trunk_size = 64,
 223                 .grow_trunk = 3,
 224                 .grow_shift = 2,
 225                 .need_lock = 1,
 226                 .release_mem_en = 0,
 227                 .per_core_cache = (1 << 16),
 228                 .malloc = mlx5_malloc,
 229                 .free = mlx5_free,
 230                 .type = "mlx5_tag_ipool",
 231         },
 232         [MLX5_IPOOL_PORT_ID] = {
 233                 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
 234                 .trunk_size = 64,
 235                 .grow_trunk = 3,
 236                 .grow_shift = 2,
 237                 .need_lock = 1,
 238                 .release_mem_en = 1,
 239                 .malloc = mlx5_malloc,
 240                 .free = mlx5_free,
 241                 .type = "mlx5_port_id_ipool",
 242         },
 243         [MLX5_IPOOL_JUMP] = {
 244                 .size = sizeof(struct mlx5_flow_tbl_data_entry),
 245                 .trunk_size = 64,
 246                 .grow_trunk = 3,
 247                 .grow_shift = 2,
 248                 .need_lock = 1,
 249                 .release_mem_en = 1,
 250                 .malloc = mlx5_malloc,
 251                 .free = mlx5_free,
 252                 .type = "mlx5_jump_ipool",
 253         },
 254         [MLX5_IPOOL_SAMPLE] = {
 255                 .size = sizeof(struct mlx5_flow_dv_sample_resource),
 256                 .trunk_size = 64,
 257                 .grow_trunk = 3,
 258                 .grow_shift = 2,
 259                 .need_lock = 1,
 260                 .release_mem_en = 1,
 261                 .malloc = mlx5_malloc,
 262                 .free = mlx5_free,
 263                 .type = "mlx5_sample_ipool",
 264         },
 265         [MLX5_IPOOL_DEST_ARRAY] = {
 266                 .size = sizeof(struct mlx5_flow_dv_dest_array_resource),
 267                 .trunk_size = 64,
 268                 .grow_trunk = 3,
 269                 .grow_shift = 2,
 270                 .need_lock = 1,
 271                 .release_mem_en = 1,
 272                 .malloc = mlx5_malloc,
 273                 .free = mlx5_free,
 274                 .type = "mlx5_dest_array_ipool",
 275         },
 276         [MLX5_IPOOL_TUNNEL_ID] = {
 277                 .size = sizeof(struct mlx5_flow_tunnel),
 278                 .trunk_size = MLX5_MAX_TUNNELS,
 279                 .need_lock = 1,
 280                 .release_mem_en = 1,
 281                 .type = "mlx5_tunnel_offload",
 282         },
 283         [MLX5_IPOOL_TNL_TBL_ID] = {
 284                 .size = 0,
 285                 .need_lock = 1,
 286                 .type = "mlx5_flow_tnl_tbl_ipool",
 287         },
 288 #endif
 289         [MLX5_IPOOL_MTR] = {
 290                 /**
 291                  * The ipool index should grow continually from small to big,
 292                  * for meter idx, so not set grow_trunk to avoid meter index
 293                  * not jump continually.
 294                  */
 295                 .size = sizeof(struct mlx5_legacy_flow_meter),
 296                 .trunk_size = 64,
 297                 .need_lock = 1,
 298                 .release_mem_en = 1,
 299                 .malloc = mlx5_malloc,
 300                 .free = mlx5_free,
 301                 .type = "mlx5_meter_ipool",
 302         },
 303         [MLX5_IPOOL_MCP] = {
 304                 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
 305                 .trunk_size = 64,
 306                 .grow_trunk = 3,
 307                 .grow_shift = 2,
 308                 .need_lock = 1,
 309                 .release_mem_en = 1,
 310                 .malloc = mlx5_malloc,
 311                 .free = mlx5_free,
 312                 .type = "mlx5_mcp_ipool",
 313         },
 314         [MLX5_IPOOL_HRXQ] = {
 315                 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
 316                 .trunk_size = 64,
 317                 .grow_trunk = 3,
 318                 .grow_shift = 2,
 319                 .need_lock = 1,
 320                 .release_mem_en = 1,
 321                 .malloc = mlx5_malloc,
 322                 .free = mlx5_free,
 323                 .type = "mlx5_hrxq_ipool",
 324         },
 325         [MLX5_IPOOL_MLX5_FLOW] = {
 326                 /*
 327                  * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
 328                  * It set in run time according to PCI function configuration.
 329                  */
 330                 .size = 0,
 331                 .trunk_size = 64,
 332                 .grow_trunk = 3,
 333                 .grow_shift = 2,
 334                 .need_lock = 1,
 335                 .release_mem_en = 0,
 336                 .per_core_cache = 1 << 19,
 337                 .malloc = mlx5_malloc,
 338                 .free = mlx5_free,
 339                 .type = "mlx5_flow_handle_ipool",
 340         },
 341         [MLX5_IPOOL_RTE_FLOW] = {
 342                 .size = sizeof(struct rte_flow),
 343                 .trunk_size = 4096,
 344                 .need_lock = 1,
 345                 .release_mem_en = 1,
 346                 .malloc = mlx5_malloc,
 347                 .free = mlx5_free,
 348                 .type = "rte_flow_ipool",
 349         },
 350         [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID] = {
 351                 .size = 0,
 352                 .need_lock = 1,
 353                 .type = "mlx5_flow_rss_id_ipool",
 354         },
 355         [MLX5_IPOOL_RSS_SHARED_ACTIONS] = {
 356                 .size = sizeof(struct mlx5_shared_action_rss),
 357                 .trunk_size = 64,
 358                 .grow_trunk = 3,
 359                 .grow_shift = 2,
 360                 .need_lock = 1,
 361                 .release_mem_en = 1,
 362                 .malloc = mlx5_malloc,
 363                 .free = mlx5_free,
 364                 .type = "mlx5_shared_action_rss",
 365         },
 366         [MLX5_IPOOL_MTR_POLICY] = {
 367                 /**
 368                  * The ipool index should grow continually from small to big,
 369                  * for policy idx, so not set grow_trunk to avoid policy index
 370                  * not jump continually.
 371                  */
 372                 .size = sizeof(struct mlx5_flow_meter_sub_policy),
 373                 .trunk_size = 64,
 374                 .need_lock = 1,
 375                 .release_mem_en = 1,
 376                 .malloc = mlx5_malloc,
 377                 .free = mlx5_free,
 378                 .type = "mlx5_meter_policy_ipool",
 379         },
 380 };
 381
 382
 383 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
 384 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
 385
 386 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 1024
 387
 388 /**
 389  * Decide whether representor ID is a HPF(host PF) port on BF2.
 390  *
 391  * @param dev
 392  *   Pointer to Ethernet device structure.
 393  *
 394  * @return
 395  *   Non-zero if HPF, otherwise 0.
 396  */
 397 bool
 398 mlx5_is_hpf(struct rte_eth_dev *dev)
 399 {
 400         struct mlx5_priv *priv = dev->data->dev_private;
 401         uint16_t repr = MLX5_REPRESENTOR_REPR(priv->representor_id);
 402         int type = MLX5_REPRESENTOR_TYPE(priv->representor_id);
 403
 404         return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_VF &&
 405                MLX5_REPRESENTOR_REPR(-1) == repr;
 406 }
 407
 408 /**
 409  * Decide whether representor ID is a SF port representor.
 410  *
 411  * @param dev
 412  *   Pointer to Ethernet device structure.
 413  *
 414  * @return
 415  *   Non-zero if HPF, otherwise 0.
 416  */
 417 bool
 418 mlx5_is_sf_repr(struct rte_eth_dev *dev)
 419 {
 420         struct mlx5_priv *priv = dev->data->dev_private;
 421         int type = MLX5_REPRESENTOR_TYPE(priv->representor_id);
 422
 423         return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_SF;
 424 }
 425
 426 /**
 427  * Initialize the ASO aging management structure.
 428  *
 429  * @param[in] sh
 430  *   Pointer to mlx5_dev_ctx_shared object to free
 431  *
 432  * @return
 433  *   0 on success, a negative errno value otherwise and rte_errno is set.
 434  */
 435 int
 436 mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh)
 437 {
 438         int err;
 439
 440         if (sh->aso_age_mng)
 441                 return 0;
 442         sh->aso_age_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->aso_age_mng),
 443                                       RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 444         if (!sh->aso_age_mng) {
 445                 DRV_LOG(ERR, "aso_age_mng allocation was failed.");
 446                 rte_errno = ENOMEM;
 447                 return -ENOMEM;
 448         }
 449         err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_FLOW_HIT);
 450         if (err) {
 451                 mlx5_free(sh->aso_age_mng);
 452                 return -1;
 453         }
 454         rte_spinlock_init(&sh->aso_age_mng->resize_sl);
 455         rte_spinlock_init(&sh->aso_age_mng->free_sl);
 456         LIST_INIT(&sh->aso_age_mng->free);
 457         return 0;
 458 }
 459
 460 /**
 461  * Close and release all the resources of the ASO aging management structure.
 462  *
 463  * @param[in] sh
 464  *   Pointer to mlx5_dev_ctx_shared object to free.
 465  */
 466 static void
 467 mlx5_flow_aso_age_mng_close(struct mlx5_dev_ctx_shared *sh)
 468 {
 469         int i, j;
 470
 471         mlx5_aso_flow_hit_queue_poll_stop(sh);
 472         mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_FLOW_HIT);
 473         if (sh->aso_age_mng->pools) {
 474                 struct mlx5_aso_age_pool *pool;
 475
 476                 for (i = 0; i < sh->aso_age_mng->next; ++i) {
 477                         pool = sh->aso_age_mng->pools[i];
 478                         claim_zero(mlx5_devx_cmd_destroy
 479                                                 (pool->flow_hit_aso_obj));
 480                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j)
 481                                 if (pool->actions[j].dr_action)
 482                                         claim_zero
 483                                             (mlx5_flow_os_destroy_flow_action
 484                                               (pool->actions[j].dr_action));
 485                         mlx5_free(pool);
 486                 }
 487                 mlx5_free(sh->aso_age_mng->pools);
 488         }
 489         mlx5_free(sh->aso_age_mng);
 490 }
 491
 492 /**
 493  * Initialize the shared aging list information per port.
 494  *
 495  * @param[in] sh
 496  *   Pointer to mlx5_dev_ctx_shared object.
 497  */
 498 static void
 499 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
 500 {
 501         uint32_t i;
 502         struct mlx5_age_info *age_info;
 503
 504         for (i = 0; i < sh->max_port; i++) {
 505                 age_info = &sh->port[i].age_info;
 506                 age_info->flags = 0;
 507                 TAILQ_INIT(&age_info->aged_counters);
 508                 LIST_INIT(&age_info->aged_aso);
 509                 rte_spinlock_init(&age_info->aged_sl);
 510                 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
 511         }
 512 }
 513
 514 /**
 515  * Initialize the counters management structure.
 516  *
 517  * @param[in] sh
 518  *   Pointer to mlx5_dev_ctx_shared object to free
 519  */
 520 static void
 521 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
 522 {
 523         struct mlx5_hca_attr *attr = &sh->cdev->config.hca_attr;
 524         int i;
 525
 526         memset(&sh->cmng, 0, sizeof(sh->cmng));
 527         TAILQ_INIT(&sh->cmng.flow_counters);
 528         sh->cmng.min_id = MLX5_CNT_BATCH_OFFSET;
 529         sh->cmng.max_id = -1;
 530         sh->cmng.last_pool_idx = POOL_IDX_INVALID;
 531         rte_spinlock_init(&sh->cmng.pool_update_sl);
 532         for (i = 0; i < MLX5_COUNTER_TYPE_MAX; i++) {
 533                 TAILQ_INIT(&sh->cmng.counters[i]);
 534                 rte_spinlock_init(&sh->cmng.csl[i]);
 535         }
 536         if (sh->devx && !haswell_broadwell_cpu) {
 537                 sh->cmng.relaxed_ordering_write = attr->relaxed_ordering_write;
 538                 sh->cmng.relaxed_ordering_read = attr->relaxed_ordering_read;
 539         }
 540 }
 541
 542 /**
 543  * Destroy all the resources allocated for a counter memory management.
 544  *
 545  * @param[in] mng
 546  *   Pointer to the memory management structure.
 547  */
 548 static void
 549 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
 550 {
 551         uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
 552
 553         LIST_REMOVE(mng, next);
 554         claim_zero(mlx5_devx_cmd_destroy(mng->dm));
 555         claim_zero(mlx5_os_umem_dereg(mng->umem));
 556         mlx5_free(mem);
 557 }
 558
 559 /**
 560  * Close and release all the resources of the counters management.
 561  *
 562  * @param[in] sh
 563  *   Pointer to mlx5_dev_ctx_shared object to free.
 564  */
 565 static void
 566 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
 567 {
 568         struct mlx5_counter_stats_mem_mng *mng;
 569         int i, j;
 570         int retries = 1024;
 571
 572         rte_errno = 0;
 573         while (--retries) {
 574                 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
 575                 if (rte_errno != EINPROGRESS)
 576                         break;
 577                 rte_pause();
 578         }
 579
 580         if (sh->cmng.pools) {
 581                 struct mlx5_flow_counter_pool *pool;
 582                 uint16_t n_valid = sh->cmng.n_valid;
 583                 bool fallback = sh->cmng.counter_fallback;
 584
 585                 for (i = 0; i < n_valid; ++i) {
 586                         pool = sh->cmng.pools[i];
 587                         if (!fallback && pool->min_dcs)
 588                                 claim_zero(mlx5_devx_cmd_destroy
 589                                                                (pool->min_dcs));
 590                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
 591                                 struct mlx5_flow_counter *cnt =
 592                                                 MLX5_POOL_GET_CNT(pool, j);
 593
 594                                 if (cnt->action)
 595                                         claim_zero
 596                                          (mlx5_flow_os_destroy_flow_action
 597                                           (cnt->action));
 598                                 if (fallback && MLX5_POOL_GET_CNT
 599                                     (pool, j)->dcs_when_free)
 600                                         claim_zero(mlx5_devx_cmd_destroy
 601                                                    (cnt->dcs_when_free));
 602                         }
 603                         mlx5_free(pool);
 604                 }
 605                 mlx5_free(sh->cmng.pools);
 606         }
 607         mng = LIST_FIRST(&sh->cmng.mem_mngs);
 608         while (mng) {
 609                 mlx5_flow_destroy_counter_stat_mem_mng(mng);
 610                 mng = LIST_FIRST(&sh->cmng.mem_mngs);
 611         }
 612         memset(&sh->cmng, 0, sizeof(sh->cmng));
 613 }
 614
 615 /**
 616  * Initialize the aso flow meters management structure.
 617  *
 618  * @param[in] sh
 619  *   Pointer to mlx5_dev_ctx_shared object to free
 620  */
 621 int
 622 mlx5_aso_flow_mtrs_mng_init(struct mlx5_dev_ctx_shared *sh)
 623 {
 624         if (!sh->mtrmng) {
 625                 sh->mtrmng = mlx5_malloc(MLX5_MEM_ZERO,
 626                         sizeof(*sh->mtrmng),
 627                         RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 628                 if (!sh->mtrmng) {
 629                         DRV_LOG(ERR,
 630                         "meter management allocation was failed.");
 631                         rte_errno = ENOMEM;
 632                         return -ENOMEM;
 633                 }
 634                 if (sh->meter_aso_en) {
 635                         rte_spinlock_init(&sh->mtrmng->pools_mng.mtrsl);
 636                         LIST_INIT(&sh->mtrmng->pools_mng.meters);
 637                 }
 638                 sh->mtrmng->def_policy_id = MLX5_INVALID_POLICY_ID;
 639         }
 640         return 0;
 641 }
 642
 643 /**
 644  * Close and release all the resources of
 645  * the ASO flow meter management structure.
 646  *
 647  * @param[in] sh
 648  *   Pointer to mlx5_dev_ctx_shared object to free.
 649  */
 650 static void
 651 mlx5_aso_flow_mtrs_mng_close(struct mlx5_dev_ctx_shared *sh)
 652 {
 653         struct mlx5_aso_mtr_pool *mtr_pool;
 654         struct mlx5_flow_mtr_mng *mtrmng = sh->mtrmng;
 655         uint32_t idx;
 656 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
 657         struct mlx5_aso_mtr *aso_mtr;
 658         int i;
 659 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
 660
 661         if (sh->meter_aso_en) {
 662                 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_POLICER);
 663                 idx = mtrmng->pools_mng.n_valid;
 664                 while (idx--) {
 665                         mtr_pool = mtrmng->pools_mng.pools[idx];
 666 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
 667                         for (i = 0; i < MLX5_ASO_MTRS_PER_POOL; i++) {
 668                                 aso_mtr = &mtr_pool->mtrs[i];
 669                                 if (aso_mtr->fm.meter_action)
 670                                         claim_zero
 671                                         (mlx5_glue->destroy_flow_action
 672                                         (aso_mtr->fm.meter_action));
 673                         }
 674 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
 675                         claim_zero(mlx5_devx_cmd_destroy
 676                                                 (mtr_pool->devx_obj));
 677                         mtrmng->pools_mng.n_valid--;
 678                         mlx5_free(mtr_pool);
 679                 }
 680                 mlx5_free(sh->mtrmng->pools_mng.pools);
 681         }
 682         mlx5_free(sh->mtrmng);
 683         sh->mtrmng = NULL;
 684 }
 685
 686 /* Send FLOW_AGED event if needed. */
 687 void
 688 mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh)
 689 {
 690         struct mlx5_age_info *age_info;
 691         uint32_t i;
 692
 693         for (i = 0; i < sh->max_port; i++) {
 694                 age_info = &sh->port[i].age_info;
 695                 if (!MLX5_AGE_GET(age_info, MLX5_AGE_EVENT_NEW))
 696                         continue;
 697                 MLX5_AGE_UNSET(age_info, MLX5_AGE_EVENT_NEW);
 698                 if (MLX5_AGE_GET(age_info, MLX5_AGE_TRIGGER)) {
 699                         MLX5_AGE_UNSET(age_info, MLX5_AGE_TRIGGER);
 700                         rte_eth_dev_callback_process
 701                                 (&rte_eth_devices[sh->port[i].devx_ih_port_id],
 702                                 RTE_ETH_EVENT_FLOW_AGED, NULL);
 703                 }
 704         }
 705 }
 706
 707 /*
 708  * Initialize the ASO connection tracking structure.
 709  *
 710  * @param[in] sh
 711  *   Pointer to mlx5_dev_ctx_shared object.
 712  *
 713  * @return
 714  *   0 on success, a negative errno value otherwise and rte_errno is set.
 715  */
 716 int
 717 mlx5_flow_aso_ct_mng_init(struct mlx5_dev_ctx_shared *sh)
 718 {
 719         int err;
 720
 721         if (sh->ct_mng)
 722                 return 0;
 723         sh->ct_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->ct_mng),
 724                                  RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 725         if (!sh->ct_mng) {
 726                 DRV_LOG(ERR, "ASO CT management allocation failed.");
 727                 rte_errno = ENOMEM;
 728                 return -rte_errno;
 729         }
 730         err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_CONNECTION_TRACKING);
 731         if (err) {
 732                 mlx5_free(sh->ct_mng);
 733                 /* rte_errno should be extracted from the failure. */
 734                 rte_errno = EINVAL;
 735                 return -rte_errno;
 736         }
 737         rte_spinlock_init(&sh->ct_mng->ct_sl);
 738         rte_rwlock_init(&sh->ct_mng->resize_rwl);
 739         LIST_INIT(&sh->ct_mng->free_cts);
 740         return 0;
 741 }
 742
 743 /*
 744  * Close and release all the resources of the
 745  * ASO connection tracking management structure.
 746  *
 747  * @param[in] sh
 748  *   Pointer to mlx5_dev_ctx_shared object to free.
 749  */
 750 static void
 751 mlx5_flow_aso_ct_mng_close(struct mlx5_dev_ctx_shared *sh)
 752 {
 753         struct mlx5_aso_ct_pools_mng *mng = sh->ct_mng;
 754         struct mlx5_aso_ct_pool *ct_pool;
 755         struct mlx5_aso_ct_action *ct;
 756         uint32_t idx;
 757         uint32_t val;
 758         uint32_t cnt;
 759         int i;
 760
 761         mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_CONNECTION_TRACKING);
 762         idx = mng->next;
 763         while (idx--) {
 764                 cnt = 0;
 765                 ct_pool = mng->pools[idx];
 766                 for (i = 0; i < MLX5_ASO_CT_ACTIONS_PER_POOL; i++) {
 767                         ct = &ct_pool->actions[i];
 768                         val = __atomic_fetch_sub(&ct->refcnt, 1,
 769                                                  __ATOMIC_RELAXED);
 770                         MLX5_ASSERT(val == 1);
 771                         if (val > 1)
 772                                 cnt++;
 773 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
 774                         if (ct->dr_action_orig)
 775                                 claim_zero(mlx5_glue->destroy_flow_action
 776                                                         (ct->dr_action_orig));
 777                         if (ct->dr_action_rply)
 778                                 claim_zero(mlx5_glue->destroy_flow_action
 779                                                         (ct->dr_action_rply));
 780 #endif
 781                 }
 782                 claim_zero(mlx5_devx_cmd_destroy(ct_pool->devx_obj));
 783                 if (cnt) {
 784                         DRV_LOG(DEBUG, "%u ASO CT objects are being used in the pool %u",
 785                                 cnt, i);
 786                 }
 787                 mlx5_free(ct_pool);
 788                 /* in case of failure. */
 789                 mng->next--;
 790         }
 791         mlx5_free(mng->pools);
 792         mlx5_free(mng);
 793         /* Management structure must be cleared to 0s during allocation. */
 794         sh->ct_mng = NULL;
 795 }
 796
 797 /**
 798  * Initialize the flow resources' indexed mempool.
 799  *
 800  * @param[in] sh
 801  *   Pointer to mlx5_dev_ctx_shared object.
 802  * @param[in] config
 803  *   Pointer to user dev config.
 804  */
 805 static void
 806 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
 807                        const struct mlx5_dev_config *config)
 808 {
 809         uint8_t i;
 810         struct mlx5_indexed_pool_config cfg;
 811
 812         for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
 813                 cfg = mlx5_ipool_cfg[i];
 814                 switch (i) {
 815                 default:
 816                         break;
 817                 /*
 818                  * Set MLX5_IPOOL_MLX5_FLOW ipool size
 819                  * according to PCI function flow configuration.
 820                  */
 821                 case MLX5_IPOOL_MLX5_FLOW:
 822                         cfg.size = config->dv_flow_en ?
 823                                 sizeof(struct mlx5_flow_handle) :
 824                                 MLX5_FLOW_HANDLE_VERBS_SIZE;
 825                         break;
 826                 }
 827                 if (config->reclaim_mode) {
 828                         cfg.release_mem_en = 1;
 829                         cfg.per_core_cache = 0;
 830                 } else {
 831                         cfg.release_mem_en = 0;
 832                 }
 833                 sh->ipool[i] = mlx5_ipool_create(&cfg);
 834         }
 835 }
 836
 837
 838 /**
 839  * Release the flow resources' indexed mempool.
 840  *
 841  * @param[in] sh
 842  *   Pointer to mlx5_dev_ctx_shared object.
 843  */
 844 static void
 845 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
 846 {
 847         uint8_t i;
 848
 849         for (i = 0; i < MLX5_IPOOL_MAX; ++i)
 850                 mlx5_ipool_destroy(sh->ipool[i]);
 851         for (i = 0; i < MLX5_MAX_MODIFY_NUM; ++i)
 852                 if (sh->mdh_ipools[i])
 853                         mlx5_ipool_destroy(sh->mdh_ipools[i]);
 854 }
 855
 856 /*
 857  * Check if dynamic flex parser for eCPRI already exists.
 858  *
 859  * @param dev
 860  *   Pointer to Ethernet device structure.
 861  *
 862  * @return
 863  *   true on exists, false on not.
 864  */
 865 bool
 866 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
 867 {
 868         struct mlx5_priv *priv = dev->data->dev_private;
 869         struct mlx5_flex_parser_profiles *prf =
 870                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 871
 872         return !!prf->obj;
 873 }
 874
 875 /*
 876  * Allocation of a flex parser for eCPRI. Once created, this parser related
 877  * resources will be held until the device is closed.
 878  *
 879  * @param dev
 880  *   Pointer to Ethernet device structure.
 881  *
 882  * @return
 883  *   0 on success, a negative errno value otherwise and rte_errno is set.
 884  */
 885 int
 886 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
 887 {
 888         struct mlx5_priv *priv = dev->data->dev_private;
 889         struct mlx5_flex_parser_profiles *prf =
 890                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 891         struct mlx5_devx_graph_node_attr node = {
 892                 .modify_field_select = 0,
 893         };
 894         uint32_t ids[8];
 895         int ret;
 896
 897         if (!priv->config.hca_attr.parse_graph_flex_node) {
 898                 DRV_LOG(ERR, "Dynamic flex parser is not supported "
 899                         "for device %s.", priv->dev_data->name);
 900                 return -ENOTSUP;
 901         }
 902         node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED;
 903         /* 8 bytes now: 4B common header + 4B message body header. */
 904         node.header_length_base_value = 0x8;
 905         /* After MAC layer: Ether / VLAN. */
 906         node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC;
 907         /* Type of compared condition should be 0xAEFE in the L2 layer. */
 908         node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI;
 909         /* Sample #0: type in common header. */
 910         node.sample[0].flow_match_sample_en = 1;
 911         /* Fixed offset. */
 912         node.sample[0].flow_match_sample_offset_mode = 0x0;
 913         /* Only the 2nd byte will be used. */
 914         node.sample[0].flow_match_sample_field_base_offset = 0x0;
 915         /* Sample #1: message payload. */
 916         node.sample[1].flow_match_sample_en = 1;
 917         /* Fixed offset. */
 918         node.sample[1].flow_match_sample_offset_mode = 0x0;
 919         /*
 920          * Only the first two bytes will be used right now, and its offset will
 921          * start after the common header that with the length of a DW(u32).
 922          */
 923         node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);
 924         prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->cdev->ctx, &node);
 925         if (!prf->obj) {
 926                 DRV_LOG(ERR, "Failed to create flex parser node object.");
 927                 return (rte_errno == 0) ? -ENODEV : -rte_errno;
 928         }
 929         prf->num = 2;
 930         ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num);
 931         if (ret) {
 932                 DRV_LOG(ERR, "Failed to query sample IDs.");
 933                 return (rte_errno == 0) ? -ENODEV : -rte_errno;
 934         }
 935         prf->offset[0] = 0x0;
 936         prf->offset[1] = sizeof(uint32_t);
 937         prf->ids[0] = ids[0];
 938         prf->ids[1] = ids[1];
 939         return 0;
 940 }
 941
 942 /*
 943  * Destroy the flex parser node, including the parser itself, input / output
 944  * arcs and DW samples. Resources could be reused then.
 945  *
 946  * @param dev
 947  *   Pointer to Ethernet device structure.
 948  */
 949 static void
 950 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
 951 {
 952         struct mlx5_priv *priv = dev->data->dev_private;
 953         struct mlx5_flex_parser_profiles *prf =
 954                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 955
 956         if (prf->obj)
 957                 mlx5_devx_cmd_destroy(prf->obj);
 958         prf->obj = NULL;
 959 }
 960
 961 uint32_t
 962 mlx5_get_supported_sw_parsing_offloads(const struct mlx5_hca_attr *attr)
 963 {
 964         uint32_t sw_parsing_offloads = 0;
 965
 966         if (attr->swp) {
 967                 sw_parsing_offloads |= MLX5_SW_PARSING_CAP;
 968                 if (attr->swp_csum)
 969                         sw_parsing_offloads |= MLX5_SW_PARSING_CSUM_CAP;
 970
 971                 if (attr->swp_lso)
 972                         sw_parsing_offloads |= MLX5_SW_PARSING_TSO_CAP;
 973         }
 974         return sw_parsing_offloads;
 975 }
 976
 977 uint32_t
 978 mlx5_get_supported_tunneling_offloads(const struct mlx5_hca_attr *attr)
 979 {
 980         uint32_t tn_offloads = 0;
 981
 982         if (attr->tunnel_stateless_vxlan)
 983                 tn_offloads |= MLX5_TUNNELED_OFFLOADS_VXLAN_CAP;
 984         if (attr->tunnel_stateless_gre)
 985                 tn_offloads |= MLX5_TUNNELED_OFFLOADS_GRE_CAP;
 986         if (attr->tunnel_stateless_geneve_rx)
 987                 tn_offloads |= MLX5_TUNNELED_OFFLOADS_GENEVE_CAP;
 988         return tn_offloads;
 989 }
 990
 991 /*
 992  * Allocate Rx and Tx UARs in robust fashion.
 993  * This routine handles the following UAR allocation issues:
 994  *
 995  *  - tries to allocate the UAR with the most appropriate memory
 996  *    mapping type from the ones supported by the host
 997  *
 998  *  - tries to allocate the UAR with non-NULL base address
 999  *    OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as
1000  *    UAR base address if UAR was not the first object in the UAR page.
1001  *    It caused the PMD failure and we should try to get another UAR
1002  *    till we get the first one with non-NULL base address returned.
1003  */
1004 static int
1005 mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh,
1006                      const struct mlx5_common_dev_config *config)
1007 {
1008         uint32_t uar_mapping, retry;
1009         int err = 0;
1010         void *base_addr;
1011
1012         for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
1013 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
1014                 /* Control the mapping type according to the settings. */
1015                 uar_mapping = (config->dbnc == MLX5_TXDB_NCACHED) ?
1016                               MLX5DV_UAR_ALLOC_TYPE_NC :
1017                               MLX5DV_UAR_ALLOC_TYPE_BF;
1018 #else
1019                 RTE_SET_USED(config);
1020                 /*
1021                  * It seems we have no way to control the memory mapping type
1022                  * for the UAR, the default "Write-Combining" type is supposed.
1023                  * The UAR initialization on queue creation queries the
1024                  * actual mapping type done by Verbs/kernel and setups the
1025                  * PMD datapath accordingly.
1026                  */
1027                 uar_mapping = 0;
1028 #endif
1029                 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->cdev->ctx,
1030                                                        uar_mapping);
1031 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
1032                 if (!sh->tx_uar &&
1033                     uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
1034                         if (config->dbnc == MLX5_TXDB_CACHED ||
1035                             config->dbnc == MLX5_TXDB_HEURISTIC)
1036                                 DRV_LOG(WARNING, "Devarg tx_db_nc setting "
1037                                                  "is not supported by DevX");
1038                         /*
1039                          * In some environments like virtual machine
1040                          * the Write Combining mapped might be not supported
1041                          * and UAR allocation fails. We try "Non-Cached"
1042                          * mapping for the case. The tx_burst routines take
1043                          * the UAR mapping type into account on UAR setup
1044                          * on queue creation.
1045                          */
1046                         DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (BF)");
1047                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
1048                         sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->cdev->ctx,
1049                                                                uar_mapping);
1050                 } else if (!sh->tx_uar &&
1051                            uar_mapping == MLX5DV_UAR_ALLOC_TYPE_NC) {
1052                         if (config->dbnc == MLX5_TXDB_NCACHED)
1053                                 DRV_LOG(WARNING, "Devarg tx_db_nc settings "
1054                                                  "is not supported by DevX");
1055                         /*
1056                          * If Verbs/kernel does not support "Non-Cached"
1057                          * try the "Write-Combining".
1058                          */
1059                         DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (NC)");
1060                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_BF;
1061                         sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->cdev->ctx,
1062                                                                uar_mapping);
1063                 }
1064 #endif
1065                 if (!sh->tx_uar) {
1066                         DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (BF/NC)");
1067                         err = ENOMEM;
1068                         goto exit;
1069                 }
1070                 base_addr = mlx5_os_get_devx_uar_base_addr(sh->tx_uar);
1071                 if (base_addr)
1072                         break;
1073                 /*
1074                  * The UARs are allocated by rdma_core within the
1075                  * IB device context, on context closure all UARs
1076                  * will be freed, should be no memory/object leakage.
1077                  */
1078                 DRV_LOG(DEBUG, "Retrying to allocate Tx DevX UAR");
1079                 sh->tx_uar = NULL;
1080         }
1081         /* Check whether we finally succeeded with valid UAR allocation. */
1082         if (!sh->tx_uar) {
1083                 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (NULL base)");
1084                 err = ENOMEM;
1085                 goto exit;
1086         }
1087         for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
1088                 uar_mapping = 0;
1089                 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar(sh->cdev->ctx,
1090                                                             uar_mapping);
1091 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
1092                 if (!sh->devx_rx_uar &&
1093                     uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
1094                         /*
1095                          * Rx UAR is used to control interrupts only,
1096                          * should be no datapath noticeable impact,
1097                          * can try "Non-Cached" mapping safely.
1098                          */
1099                         DRV_LOG(DEBUG, "Failed to allocate Rx DevX UAR (BF)");
1100                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
1101                         sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
1102                                                    (sh->cdev->ctx, uar_mapping);
1103                 }
1104 #endif
1105                 if (!sh->devx_rx_uar) {
1106                         DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (BF/NC)");
1107                         err = ENOMEM;
1108                         goto exit;
1109                 }
1110                 base_addr = mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar);
1111                 if (base_addr)
1112                         break;
1113                 /*
1114                  * The UARs are allocated by rdma_core within the
1115                  * IB device context, on context closure all UARs
1116                  * will be freed, should be no memory/object leakage.
1117                  */
1118                 DRV_LOG(DEBUG, "Retrying to allocate Rx DevX UAR");
1119                 sh->devx_rx_uar = NULL;
1120         }
1121         /* Check whether we finally succeeded with valid UAR allocation. */
1122         if (!sh->devx_rx_uar) {
1123                 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (NULL base)");
1124                 err = ENOMEM;
1125         }
1126 exit:
1127         return err;
1128 }
1129
1130 /**
1131  * Unregister the mempool from the protection domain.
1132  *
1133  * @param sh
1134  *   Pointer to the device shared context.
1135  * @param mp
1136  *   Mempool being unregistered.
1137  */
1138 static void
1139 mlx5_dev_ctx_shared_mempool_unregister(struct mlx5_dev_ctx_shared *sh,
1140                                        struct rte_mempool *mp)
1141 {
1142         struct mlx5_mp_id mp_id;
1143
1144         mlx5_mp_id_init(&mp_id, 0);
1145         if (mlx5_mr_mempool_unregister(&sh->share_cache, mp, &mp_id) < 0)
1146                 DRV_LOG(WARNING, "Failed to unregister mempool %s for PD %p: %s",
1147                         mp->name, sh->cdev->pd, rte_strerror(rte_errno));
1148 }
1149
1150 /**
1151  * rte_mempool_walk() callback to register mempools
1152  * for the protection domain.
1153  *
1154  * @param mp
1155  *   The mempool being walked.
1156  * @param arg
1157  *   Pointer to the device shared context.
1158  */
1159 static void
1160 mlx5_dev_ctx_shared_mempool_register_cb(struct rte_mempool *mp, void *arg)
1161 {
1162         struct mlx5_dev_ctx_shared *sh = arg;
1163         struct mlx5_mp_id mp_id;
1164         int ret;
1165
1166         mlx5_mp_id_init(&mp_id, 0);
1167         ret = mlx5_mr_mempool_register(&sh->share_cache, sh->cdev->pd, mp,
1168                                        &mp_id);
1169         if (ret < 0 && rte_errno != EEXIST)
1170                 DRV_LOG(ERR, "Failed to register existing mempool %s for PD %p: %s",
1171                         mp->name, sh->cdev->pd, rte_strerror(rte_errno));
1172 }
1173
1174 /**
1175  * rte_mempool_walk() callback to unregister mempools
1176  * from the protection domain.
1177  *
1178  * @param mp
1179  *   The mempool being walked.
1180  * @param arg
1181  *   Pointer to the device shared context.
1182  */
1183 static void
1184 mlx5_dev_ctx_shared_mempool_unregister_cb(struct rte_mempool *mp, void *arg)
1185 {
1186         mlx5_dev_ctx_shared_mempool_unregister
1187                                 ((struct mlx5_dev_ctx_shared *)arg, mp);
1188 }
1189
1190 /**
1191  * Mempool life cycle callback for Ethernet devices.
1192  *
1193  * @param event
1194  *   Mempool life cycle event.
1195  * @param mp
1196  *   Associated mempool.
1197  * @param arg
1198  *   Pointer to a device shared context.
1199  */
1200 static void
1201 mlx5_dev_ctx_shared_mempool_event_cb(enum rte_mempool_event event,
1202                                      struct rte_mempool *mp, void *arg)
1203 {
1204         struct mlx5_dev_ctx_shared *sh = arg;
1205         struct mlx5_mp_id mp_id;
1206
1207         switch (event) {
1208         case RTE_MEMPOOL_EVENT_READY:
1209                 mlx5_mp_id_init(&mp_id, 0);
1210                 if (mlx5_mr_mempool_register(&sh->share_cache, sh->cdev->pd, mp,
1211                                              &mp_id) < 0)
1212                         DRV_LOG(ERR, "Failed to register new mempool %s for PD %p: %s",
1213                                 mp->name, sh->cdev->pd,
1214                                 rte_strerror(rte_errno));
1215                 break;
1216         case RTE_MEMPOOL_EVENT_DESTROY:
1217                 mlx5_dev_ctx_shared_mempool_unregister(sh, mp);
1218                 break;
1219         }
1220 }
1221
1222 /**
1223  * Callback used when implicit mempool registration is disabled
1224  * in order to track Rx mempool destruction.
1225  *
1226  * @param event
1227  *   Mempool life cycle event.
1228  * @param mp
1229  *   An Rx mempool registered explicitly when the port is started.
1230  * @param arg
1231  *   Pointer to a device shared context.
1232  */
1233 static void
1234 mlx5_dev_ctx_shared_rx_mempool_event_cb(enum rte_mempool_event event,
1235                                         struct rte_mempool *mp, void *arg)
1236 {
1237         struct mlx5_dev_ctx_shared *sh = arg;
1238
1239         if (event == RTE_MEMPOOL_EVENT_DESTROY)
1240                 mlx5_dev_ctx_shared_mempool_unregister(sh, mp);
1241 }
1242
1243 int
1244 mlx5_dev_ctx_shared_mempool_subscribe(struct rte_eth_dev *dev)
1245 {
1246         struct mlx5_priv *priv = dev->data->dev_private;
1247         struct mlx5_dev_ctx_shared *sh = priv->sh;
1248         int ret;
1249
1250         /* Check if we only need to track Rx mempool destruction. */
1251         if (!sh->cdev->config.mr_mempool_reg_en) {
1252                 ret = rte_mempool_event_callback_register
1253                                 (mlx5_dev_ctx_shared_rx_mempool_event_cb, sh);
1254                 return ret == 0 || rte_errno == EEXIST ? 0 : ret;
1255         }
1256         /* Callback for this shared context may be already registered. */
1257         ret = rte_mempool_event_callback_register
1258                                 (mlx5_dev_ctx_shared_mempool_event_cb, sh);
1259         if (ret != 0 && rte_errno != EEXIST)
1260                 return ret;
1261         /* Register mempools only once for this shared context. */
1262         if (ret == 0)
1263                 rte_mempool_walk(mlx5_dev_ctx_shared_mempool_register_cb, sh);
1264         return 0;
1265 }
1266
1267 /**
1268  * Allocate shared device context. If there is multiport device the
1269  * master and representors will share this context, if there is single
1270  * port dedicated device, the context will be used by only given
1271  * port due to unification.
1272  *
1273  * Routine first searches the context for the specified device name,
1274  * if found the shared context assumed and reference counter is incremented.
1275  * If no context found the new one is created and initialized with specified
1276  * device context and parameters.
1277  *
1278  * @param[in] spawn
1279  *   Pointer to the device attributes (name, port, etc).
1280  * @param[in] config
1281  *   Pointer to device configuration structure.
1282  *
1283  * @return
1284  *   Pointer to mlx5_dev_ctx_shared object on success,
1285  *   otherwise NULL and rte_errno is set.
1286  */
1287 struct mlx5_dev_ctx_shared *
1288 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
1289                           const struct mlx5_dev_config *config)
1290 {
1291         struct mlx5_dev_ctx_shared *sh;
1292         int err = 0;
1293         uint32_t i;
1294         struct mlx5_devx_tis_attr tis_attr = { 0 };
1295
1296         MLX5_ASSERT(spawn);
1297         /* Secondary process should not create the shared context. */
1298         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1299         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1300         /* Search for IB context by device name. */
1301         LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
1302                 if (!strcmp(sh->ibdev_name, spawn->phys_dev_name)) {
1303                         sh->refcnt++;
1304                         goto exit;
1305                 }
1306         }
1307         /* No device found, we have to create new shared context. */
1308         MLX5_ASSERT(spawn->max_port);
1309         sh = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
1310                          sizeof(struct mlx5_dev_ctx_shared) +
1311                          spawn->max_port *
1312                          sizeof(struct mlx5_dev_shared_port),
1313                          RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
1314         if (!sh) {
1315                 DRV_LOG(ERR, "shared context allocation failure");
1316                 rte_errno  = ENOMEM;
1317                 goto exit;
1318         }
1319         pthread_mutex_init(&sh->txpp.mutex, NULL);
1320         sh->numa_node = spawn->cdev->dev->numa_node;
1321         sh->cdev = spawn->cdev;
1322         sh->devx = sh->cdev->config.devx;
1323         if (spawn->bond_info)
1324                 sh->bond = *spawn->bond_info;
1325         err = mlx5_os_get_dev_attr(sh->cdev, &sh->device_attr);
1326         if (err) {
1327                 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
1328                 goto error;
1329         }
1330         sh->refcnt = 1;
1331         sh->max_port = spawn->max_port;
1332         sh->reclaim_mode = config->reclaim_mode;
1333         strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->cdev->ctx),
1334                 sizeof(sh->ibdev_name) - 1);
1335         strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->cdev->ctx),
1336                 sizeof(sh->ibdev_path) - 1);
1337         /*
1338          * Setting port_id to max unallowed value means
1339          * there is no interrupt subhandler installed for
1340          * the given port index i.
1341          */
1342         for (i = 0; i < sh->max_port; i++) {
1343                 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
1344                 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
1345         }
1346         if (sh->devx) {
1347                 sh->td = mlx5_devx_cmd_create_td(sh->cdev->ctx);
1348                 if (!sh->td) {
1349                         DRV_LOG(ERR, "TD allocation failure");
1350                         err = ENOMEM;
1351                         goto error;
1352                 }
1353                 tis_attr.transport_domain = sh->td->id;
1354                 sh->tis = mlx5_devx_cmd_create_tis(sh->cdev->ctx, &tis_attr);
1355                 if (!sh->tis) {
1356                         DRV_LOG(ERR, "TIS allocation failure");
1357                         err = ENOMEM;
1358                         goto error;
1359                 }
1360                 err = mlx5_alloc_rxtx_uars(sh, &sh->cdev->config);
1361                 if (err)
1362                         goto error;
1363                 MLX5_ASSERT(sh->tx_uar);
1364                 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->tx_uar));
1365
1366                 MLX5_ASSERT(sh->devx_rx_uar);
1367                 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar));
1368         }
1369 #ifndef RTE_ARCH_64
1370         /* Initialize UAR access locks for 32bit implementations. */
1371         rte_spinlock_init(&sh->uar_lock_cq);
1372         for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
1373                 rte_spinlock_init(&sh->uar_lock[i]);
1374 #endif
1375         /*
1376          * Once the device is added to the list of memory event
1377          * callback, its global MR cache table cannot be expanded
1378          * on the fly because of deadlock. If it overflows, lookup
1379          * should be done by searching MR list linearly, which is slow.
1380          *
1381          * At this point the device is not added to the memory
1382          * event list yet, context is just being created.
1383          */
1384         err = mlx5_mr_btree_init(&sh->share_cache.cache,
1385                                  MLX5_MR_BTREE_CACHE_N * 2,
1386                                  sh->numa_node);
1387         if (err) {
1388                 err = rte_errno;
1389                 goto error;
1390         }
1391         mlx5_os_set_reg_mr_cb(&sh->share_cache.reg_mr_cb,
1392                               &sh->share_cache.dereg_mr_cb);
1393         mlx5_os_dev_shared_handler_install(sh);
1394         if (LIST_EMPTY(&mlx5_dev_ctx_list)) {
1395                 err = mlx5_flow_os_init_workspace_once();
1396                 if (err)
1397                         goto error;
1398         }
1399         mlx5_flow_aging_init(sh);
1400         mlx5_flow_counters_mng_init(sh);
1401         mlx5_flow_ipool_create(sh, config);
1402         /* Add device to memory callback list. */
1403         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1404         LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
1405                          sh, mem_event_cb);
1406         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1407         /* Add context to the global device list. */
1408         LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
1409         rte_spinlock_init(&sh->geneve_tlv_opt_sl);
1410 exit:
1411         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1412         return sh;
1413 error:
1414         pthread_mutex_destroy(&sh->txpp.mutex);
1415         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1416         MLX5_ASSERT(sh);
1417         if (sh->share_cache.cache.table)
1418                 mlx5_mr_btree_free(&sh->share_cache.cache);
1419         if (sh->tis)
1420                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1421         if (sh->td)
1422                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1423         if (sh->devx_rx_uar)
1424                 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1425         if (sh->tx_uar)
1426                 mlx5_glue->devx_free_uar(sh->tx_uar);
1427         mlx5_free(sh);
1428         MLX5_ASSERT(err > 0);
1429         rte_errno = err;
1430         return NULL;
1431 }
1432
1433 /**
1434  * Free shared IB device context. Decrement counter and if zero free
1435  * all allocated resources and close handles.
1436  *
1437  * @param[in] sh
1438  *   Pointer to mlx5_dev_ctx_shared object to free
1439  */
1440 void
1441 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
1442 {
1443         int ret;
1444
1445         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1446 #ifdef RTE_LIBRTE_MLX5_DEBUG
1447         /* Check the object presence in the list. */
1448         struct mlx5_dev_ctx_shared *lctx;
1449
1450         LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
1451                 if (lctx == sh)
1452                         break;
1453         MLX5_ASSERT(lctx);
1454         if (lctx != sh) {
1455                 DRV_LOG(ERR, "Freeing non-existing shared IB context");
1456                 goto exit;
1457         }
1458 #endif
1459         MLX5_ASSERT(sh);
1460         MLX5_ASSERT(sh->refcnt);
1461         /* Secondary process should not free the shared context. */
1462         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1463         if (--sh->refcnt)
1464                 goto exit;
1465         /* Stop watching for mempool events and unregister all mempools. */
1466         ret = rte_mempool_event_callback_unregister
1467                                 (mlx5_dev_ctx_shared_mempool_event_cb, sh);
1468         if (ret < 0 && rte_errno == ENOENT)
1469                 ret = rte_mempool_event_callback_unregister
1470                                 (mlx5_dev_ctx_shared_rx_mempool_event_cb, sh);
1471         if (ret == 0)
1472                 rte_mempool_walk(mlx5_dev_ctx_shared_mempool_unregister_cb,
1473                                  sh);
1474         /* Remove from memory callback device list. */
1475         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1476         LIST_REMOVE(sh, mem_event_cb);
1477         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1478         /* Release created Memory Regions. */
1479         mlx5_mr_release_cache(&sh->share_cache);
1480         /* Remove context from the global device list. */
1481         LIST_REMOVE(sh, next);
1482         /* Release flow workspaces objects on the last device. */
1483         if (LIST_EMPTY(&mlx5_dev_ctx_list))
1484                 mlx5_flow_os_release_workspace();
1485         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1486         /*
1487          *  Ensure there is no async event handler installed.
1488          *  Only primary process handles async device events.
1489          **/
1490         mlx5_flow_counters_mng_close(sh);
1491         if (sh->aso_age_mng) {
1492                 mlx5_flow_aso_age_mng_close(sh);
1493                 sh->aso_age_mng = NULL;
1494         }
1495         if (sh->mtrmng)
1496                 mlx5_aso_flow_mtrs_mng_close(sh);
1497         mlx5_flow_ipool_destroy(sh);
1498         mlx5_os_dev_shared_handler_uninstall(sh);
1499         if (sh->tx_uar) {
1500                 mlx5_glue->devx_free_uar(sh->tx_uar);
1501                 sh->tx_uar = NULL;
1502         }
1503         if (sh->tis)
1504                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1505         if (sh->td)
1506                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1507         if (sh->devx_rx_uar)
1508                 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1509         MLX5_ASSERT(sh->geneve_tlv_option_resource == NULL);
1510         pthread_mutex_destroy(&sh->txpp.mutex);
1511         mlx5_free(sh);
1512         return;
1513 exit:
1514         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1515 }
1516
1517 /**
1518  * Destroy table hash list.
1519  *
1520  * @param[in] priv
1521  *   Pointer to the private device data structure.
1522  */
1523 void
1524 mlx5_free_table_hash_list(struct mlx5_priv *priv)
1525 {
1526         struct mlx5_dev_ctx_shared *sh = priv->sh;
1527
1528         if (!sh->flow_tbls)
1529                 return;
1530         mlx5_hlist_destroy(sh->flow_tbls);
1531         sh->flow_tbls = NULL;
1532 }
1533
1534 /**
1535  * Initialize flow table hash list and create the root tables entry
1536  * for each domain.
1537  *
1538  * @param[in] priv
1539  *   Pointer to the private device data structure.
1540  *
1541  * @return
1542  *   Zero on success, positive error code otherwise.
1543  */
1544 int
1545 mlx5_alloc_table_hash_list(struct mlx5_priv *priv __rte_unused)
1546 {
1547         int err = 0;
1548         /* Tables are only used in DV and DR modes. */
1549 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
1550         struct mlx5_dev_ctx_shared *sh = priv->sh;
1551         char s[MLX5_NAME_SIZE];
1552
1553         MLX5_ASSERT(sh);
1554         snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1555         sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE,
1556                                           false, true, sh,
1557                                           flow_dv_tbl_create_cb,
1558                                           flow_dv_tbl_match_cb,
1559                                           flow_dv_tbl_remove_cb,
1560                                           flow_dv_tbl_clone_cb,
1561                                           flow_dv_tbl_clone_free_cb);
1562         if (!sh->flow_tbls) {
1563                 DRV_LOG(ERR, "flow tables with hash creation failed.");
1564                 err = ENOMEM;
1565                 return err;
1566         }
1567 #ifndef HAVE_MLX5DV_DR
1568         struct rte_flow_error error;
1569         struct rte_eth_dev *dev = &rte_eth_devices[priv->dev_data->port_id];
1570
1571         /*
1572          * In case we have not DR support, the zero tables should be created
1573          * because DV expect to see them even if they cannot be created by
1574          * RDMA-CORE.
1575          */
1576         if (!flow_dv_tbl_resource_get(dev, 0, 0, 0, 0,
1577                 NULL, 0, 1, 0, &error) ||
1578             !flow_dv_tbl_resource_get(dev, 0, 1, 0, 0,
1579                 NULL, 0, 1, 0, &error) ||
1580             !flow_dv_tbl_resource_get(dev, 0, 0, 1, 0,
1581                 NULL, 0, 1, 0, &error)) {
1582                 err = ENOMEM;
1583                 goto error;
1584         }
1585         return err;
1586 error:
1587         mlx5_free_table_hash_list(priv);
1588 #endif /* HAVE_MLX5DV_DR */
1589 #endif
1590         return err;
1591 }
1592
1593 /**
1594  * Retrieve integer value from environment variable.
1595  *
1596  * @param[in] name
1597  *   Environment variable name.
1598  *
1599  * @return
1600  *   Integer value, 0 if the variable is not set.
1601  */
1602 int
1603 mlx5_getenv_int(const char *name)
1604 {
1605         const char *val = getenv(name);
1606
1607         if (val == NULL)
1608                 return 0;
1609         return atoi(val);
1610 }
1611
1612 /**
1613  * DPDK callback to add udp tunnel port
1614  *
1615  * @param[in] dev
1616  *   A pointer to eth_dev
1617  * @param[in] udp_tunnel
1618  *   A pointer to udp tunnel
1619  *
1620  * @return
1621  *   0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1622  */
1623 int
1624 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1625                          struct rte_eth_udp_tunnel *udp_tunnel)
1626 {
1627         MLX5_ASSERT(udp_tunnel != NULL);
1628         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1629             udp_tunnel->udp_port == 4789)
1630                 return 0;
1631         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1632             udp_tunnel->udp_port == 4790)
1633                 return 0;
1634         return -ENOTSUP;
1635 }
1636
1637 /**
1638  * Initialize process private data structure.
1639  *
1640  * @param dev
1641  *   Pointer to Ethernet device structure.
1642  *
1643  * @return
1644  *   0 on success, a negative errno value otherwise and rte_errno is set.
1645  */
1646 int
1647 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1648 {
1649         struct mlx5_priv *priv = dev->data->dev_private;
1650         struct mlx5_proc_priv *ppriv;
1651         size_t ppriv_size;
1652
1653         mlx5_proc_priv_uninit(dev);
1654         /*
1655          * UAR register table follows the process private structure. BlueFlame
1656          * registers for Tx queues are stored in the table.
1657          */
1658         ppriv_size =
1659                 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1660         ppriv = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, ppriv_size,
1661                             RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1662         if (!ppriv) {
1663                 rte_errno = ENOMEM;
1664                 return -rte_errno;
1665         }
1666         ppriv->uar_table_sz = priv->txqs_n;
1667         dev->process_private = ppriv;
1668         return 0;
1669 }
1670
1671 /**
1672  * Un-initialize process private data structure.
1673  *
1674  * @param dev
1675  *   Pointer to Ethernet device structure.
1676  */
1677 void
1678 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1679 {
1680         if (!dev->process_private)
1681                 return;
1682         mlx5_free(dev->process_private);
1683         dev->process_private = NULL;
1684 }
1685
1686 /**
1687  * DPDK callback to close the device.
1688  *
1689  * Destroy all queues and objects, free memory.
1690  *
1691  * @param dev
1692  *   Pointer to Ethernet device structure.
1693  */
1694 int
1695 mlx5_dev_close(struct rte_eth_dev *dev)
1696 {
1697         struct mlx5_priv *priv = dev->data->dev_private;
1698         unsigned int i;
1699         int ret;
1700
1701         if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1702                 /* Check if process_private released. */
1703                 if (!dev->process_private)
1704                         return 0;
1705                 mlx5_tx_uar_uninit_secondary(dev);
1706                 mlx5_proc_priv_uninit(dev);
1707                 rte_eth_dev_release_port(dev);
1708                 return 0;
1709         }
1710         if (!priv->sh)
1711                 return 0;
1712         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1713                 dev->data->port_id,
1714                 ((priv->sh->cdev->ctx != NULL) ?
1715                 mlx5_os_get_ctx_device_name(priv->sh->cdev->ctx) : ""));
1716         /*
1717          * If default mreg copy action is removed at the stop stage,
1718          * the search will return none and nothing will be done anymore.
1719          */
1720         mlx5_flow_stop_default(dev);
1721         mlx5_traffic_disable(dev);
1722         /*
1723          * If all the flows are already flushed in the device stop stage,
1724          * then this will return directly without any action.
1725          */
1726         mlx5_flow_list_flush(dev, MLX5_FLOW_TYPE_GEN, true);
1727         mlx5_action_handle_flush(dev);
1728         mlx5_flow_meter_flush(dev, NULL);
1729         /* Prevent crashes when queues are still in use. */
1730         dev->rx_pkt_burst = removed_rx_burst;
1731         dev->tx_pkt_burst = removed_tx_burst;
1732         rte_wmb();
1733         /* Disable datapath on secondary process. */
1734         mlx5_mp_os_req_stop_rxtx(dev);
1735         /* Free the eCPRI flex parser resource. */
1736         mlx5_flex_parser_ecpri_release(dev);
1737         if (priv->rxqs != NULL) {
1738                 /* XXX race condition if mlx5_rx_burst() is still running. */
1739                 rte_delay_us_sleep(1000);
1740                 for (i = 0; (i != priv->rxqs_n); ++i)
1741                         mlx5_rxq_release(dev, i);
1742                 priv->rxqs_n = 0;
1743                 priv->rxqs = NULL;
1744         }
1745         if (priv->representor) {
1746                 /* Each representor has a dedicated interrupts handler */
1747                 mlx5_free(dev->intr_handle);
1748                 dev->intr_handle = NULL;
1749         }
1750         if (priv->txqs != NULL) {
1751                 /* XXX race condition if mlx5_tx_burst() is still running. */
1752                 rte_delay_us_sleep(1000);
1753                 for (i = 0; (i != priv->txqs_n); ++i)
1754                         mlx5_txq_release(dev, i);
1755                 priv->txqs_n = 0;
1756                 priv->txqs = NULL;
1757         }
1758         mlx5_proc_priv_uninit(dev);
1759         if (priv->q_counters) {
1760                 mlx5_devx_cmd_destroy(priv->q_counters);
1761                 priv->q_counters = NULL;
1762         }
1763         if (priv->drop_queue.hrxq)
1764                 mlx5_drop_action_destroy(dev);
1765         if (priv->mreg_cp_tbl)
1766                 mlx5_hlist_destroy(priv->mreg_cp_tbl);
1767         mlx5_mprq_free_mp(dev);
1768         if (priv->sh->ct_mng)
1769                 mlx5_flow_aso_ct_mng_close(priv->sh);
1770         mlx5_os_free_shared_dr(priv);
1771         if (priv->rss_conf.rss_key != NULL)
1772                 mlx5_free(priv->rss_conf.rss_key);
1773         if (priv->reta_idx != NULL)
1774                 mlx5_free(priv->reta_idx);
1775         if (priv->config.vf)
1776                 mlx5_os_mac_addr_flush(dev);
1777         if (priv->nl_socket_route >= 0)
1778                 close(priv->nl_socket_route);
1779         if (priv->nl_socket_rdma >= 0)
1780                 close(priv->nl_socket_rdma);
1781         if (priv->vmwa_context)
1782                 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1783         ret = mlx5_hrxq_verify(dev);
1784         if (ret)
1785                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1786                         dev->data->port_id);
1787         ret = mlx5_ind_table_obj_verify(dev);
1788         if (ret)
1789                 DRV_LOG(WARNING, "port %u some indirection table still remain",
1790                         dev->data->port_id);
1791         ret = mlx5_rxq_obj_verify(dev);
1792         if (ret)
1793                 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1794                         dev->data->port_id);
1795         ret = mlx5_rxq_verify(dev);
1796         if (ret)
1797                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1798                         dev->data->port_id);
1799         ret = mlx5_txq_obj_verify(dev);
1800         if (ret)
1801                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1802                         dev->data->port_id);
1803         ret = mlx5_txq_verify(dev);
1804         if (ret)
1805                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1806                         dev->data->port_id);
1807         ret = mlx5_flow_verify(dev);
1808         if (ret)
1809                 DRV_LOG(WARNING, "port %u some flows still remain",
1810                         dev->data->port_id);
1811         if (priv->hrxqs)
1812                 mlx5_list_destroy(priv->hrxqs);
1813         /*
1814          * Free the shared context in last turn, because the cleanup
1815          * routines above may use some shared fields, like
1816          * mlx5_os_mac_addr_flush() uses ibdev_path for retrieveing
1817          * ifindex if Netlink fails.
1818          */
1819         mlx5_free_shared_dev_ctx(priv->sh);
1820         if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1821                 unsigned int c = 0;
1822                 uint16_t port_id;
1823
1824                 MLX5_ETH_FOREACH_DEV(port_id, dev->device) {
1825                         struct mlx5_priv *opriv =
1826                                 rte_eth_devices[port_id].data->dev_private;
1827
1828                         if (!opriv ||
1829                             opriv->domain_id != priv->domain_id ||
1830                             &rte_eth_devices[port_id] == dev)
1831                                 continue;
1832                         ++c;
1833                         break;
1834                 }
1835                 if (!c)
1836                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1837         }
1838         memset(priv, 0, sizeof(*priv));
1839         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1840         /*
1841          * Reset mac_addrs to NULL such that it is not freed as part of
1842          * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1843          * it is freed when dev_private is freed.
1844          */
1845         dev->data->mac_addrs = NULL;
1846         return 0;
1847 }
1848
1849 const struct eth_dev_ops mlx5_dev_ops = {
1850         .dev_configure = mlx5_dev_configure,
1851         .dev_start = mlx5_dev_start,
1852         .dev_stop = mlx5_dev_stop,
1853         .dev_set_link_down = mlx5_set_link_down,
1854         .dev_set_link_up = mlx5_set_link_up,
1855         .dev_close = mlx5_dev_close,
1856         .promiscuous_enable = mlx5_promiscuous_enable,
1857         .promiscuous_disable = mlx5_promiscuous_disable,
1858         .allmulticast_enable = mlx5_allmulticast_enable,
1859         .allmulticast_disable = mlx5_allmulticast_disable,
1860         .link_update = mlx5_link_update,
1861         .stats_get = mlx5_stats_get,
1862         .stats_reset = mlx5_stats_reset,
1863         .xstats_get = mlx5_xstats_get,
1864         .xstats_reset = mlx5_xstats_reset,
1865         .xstats_get_names = mlx5_xstats_get_names,
1866         .fw_version_get = mlx5_fw_version_get,
1867         .dev_infos_get = mlx5_dev_infos_get,
1868         .representor_info_get = mlx5_representor_info_get,
1869         .read_clock = mlx5_txpp_read_clock,
1870         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1871         .vlan_filter_set = mlx5_vlan_filter_set,
1872         .rx_queue_setup = mlx5_rx_queue_setup,
1873         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1874         .tx_queue_setup = mlx5_tx_queue_setup,
1875         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1876         .rx_queue_release = mlx5_rx_queue_release,
1877         .tx_queue_release = mlx5_tx_queue_release,
1878         .rx_queue_start = mlx5_rx_queue_start,
1879         .rx_queue_stop = mlx5_rx_queue_stop,
1880         .tx_queue_start = mlx5_tx_queue_start,
1881         .tx_queue_stop = mlx5_tx_queue_stop,
1882         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1883         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1884         .mac_addr_remove = mlx5_mac_addr_remove,
1885         .mac_addr_add = mlx5_mac_addr_add,
1886         .mac_addr_set = mlx5_mac_addr_set,
1887         .set_mc_addr_list = mlx5_set_mc_addr_list,
1888         .mtu_set = mlx5_dev_set_mtu,
1889         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1890         .vlan_offload_set = mlx5_vlan_offload_set,
1891         .reta_update = mlx5_dev_rss_reta_update,
1892         .reta_query = mlx5_dev_rss_reta_query,
1893         .rss_hash_update = mlx5_rss_hash_update,
1894         .rss_hash_conf_get = mlx5_rss_hash_conf_get,
1895         .flow_ops_get = mlx5_flow_ops_get,
1896         .rxq_info_get = mlx5_rxq_info_get,
1897         .txq_info_get = mlx5_txq_info_get,
1898         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1899         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1900         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1901         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1902         .is_removed = mlx5_is_removed,
1903         .udp_tunnel_port_add  = mlx5_udp_tunnel_port_add,
1904         .get_module_info = mlx5_get_module_info,
1905         .get_module_eeprom = mlx5_get_module_eeprom,
1906         .hairpin_cap_get = mlx5_hairpin_cap_get,
1907         .mtr_ops_get = mlx5_flow_meter_ops_get,
1908         .hairpin_bind = mlx5_hairpin_bind,
1909         .hairpin_unbind = mlx5_hairpin_unbind,
1910         .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1911         .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1912         .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1913         .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1914         .get_monitor_addr = mlx5_get_monitor_addr,
1915 };
1916
1917 /* Available operations from secondary process. */
1918 const struct eth_dev_ops mlx5_dev_sec_ops = {
1919         .stats_get = mlx5_stats_get,
1920         .stats_reset = mlx5_stats_reset,
1921         .xstats_get = mlx5_xstats_get,
1922         .xstats_reset = mlx5_xstats_reset,
1923         .xstats_get_names = mlx5_xstats_get_names,
1924         .fw_version_get = mlx5_fw_version_get,
1925         .dev_infos_get = mlx5_dev_infos_get,
1926         .representor_info_get = mlx5_representor_info_get,
1927         .read_clock = mlx5_txpp_read_clock,
1928         .rx_queue_start = mlx5_rx_queue_start,
1929         .rx_queue_stop = mlx5_rx_queue_stop,
1930         .tx_queue_start = mlx5_tx_queue_start,
1931         .tx_queue_stop = mlx5_tx_queue_stop,
1932         .rxq_info_get = mlx5_rxq_info_get,
1933         .txq_info_get = mlx5_txq_info_get,
1934         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1935         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1936         .get_module_info = mlx5_get_module_info,
1937         .get_module_eeprom = mlx5_get_module_eeprom,
1938 };
1939
1940 /* Available operations in flow isolated mode. */
1941 const struct eth_dev_ops mlx5_dev_ops_isolate = {
1942         .dev_configure = mlx5_dev_configure,
1943         .dev_start = mlx5_dev_start,
1944         .dev_stop = mlx5_dev_stop,
1945         .dev_set_link_down = mlx5_set_link_down,
1946         .dev_set_link_up = mlx5_set_link_up,
1947         .dev_close = mlx5_dev_close,
1948         .promiscuous_enable = mlx5_promiscuous_enable,
1949         .promiscuous_disable = mlx5_promiscuous_disable,
1950         .allmulticast_enable = mlx5_allmulticast_enable,
1951         .allmulticast_disable = mlx5_allmulticast_disable,
1952         .link_update = mlx5_link_update,
1953         .stats_get = mlx5_stats_get,
1954         .stats_reset = mlx5_stats_reset,
1955         .xstats_get = mlx5_xstats_get,
1956         .xstats_reset = mlx5_xstats_reset,
1957         .xstats_get_names = mlx5_xstats_get_names,
1958         .fw_version_get = mlx5_fw_version_get,
1959         .dev_infos_get = mlx5_dev_infos_get,
1960         .representor_info_get = mlx5_representor_info_get,
1961         .read_clock = mlx5_txpp_read_clock,
1962         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1963         .vlan_filter_set = mlx5_vlan_filter_set,
1964         .rx_queue_setup = mlx5_rx_queue_setup,
1965         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1966         .tx_queue_setup = mlx5_tx_queue_setup,
1967         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1968         .rx_queue_release = mlx5_rx_queue_release,
1969         .tx_queue_release = mlx5_tx_queue_release,
1970         .rx_queue_start = mlx5_rx_queue_start,
1971         .rx_queue_stop = mlx5_rx_queue_stop,
1972         .tx_queue_start = mlx5_tx_queue_start,
1973         .tx_queue_stop = mlx5_tx_queue_stop,
1974         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1975         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1976         .mac_addr_remove = mlx5_mac_addr_remove,
1977         .mac_addr_add = mlx5_mac_addr_add,
1978         .mac_addr_set = mlx5_mac_addr_set,
1979         .set_mc_addr_list = mlx5_set_mc_addr_list,
1980         .mtu_set = mlx5_dev_set_mtu,
1981         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1982         .vlan_offload_set = mlx5_vlan_offload_set,
1983         .flow_ops_get = mlx5_flow_ops_get,
1984         .rxq_info_get = mlx5_rxq_info_get,
1985         .txq_info_get = mlx5_txq_info_get,
1986         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1987         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1988         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1989         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1990         .is_removed = mlx5_is_removed,
1991         .get_module_info = mlx5_get_module_info,
1992         .get_module_eeprom = mlx5_get_module_eeprom,
1993         .hairpin_cap_get = mlx5_hairpin_cap_get,
1994         .mtr_ops_get = mlx5_flow_meter_ops_get,
1995         .hairpin_bind = mlx5_hairpin_bind,
1996         .hairpin_unbind = mlx5_hairpin_unbind,
1997         .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1998         .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1999         .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
2000         .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
2001         .get_monitor_addr = mlx5_get_monitor_addr,
2002 };
2003
2004 /**
2005  * Verify and store value for device argument.
2006  *
2007  * @param[in] key
2008  *   Key argument to verify.
2009  * @param[in] val
2010  *   Value associated with key.
2011  * @param opaque
2012  *   User data.
2013  *
2014  * @return
2015  *   0 on success, a negative errno value otherwise and rte_errno is set.
2016  */
2017 static int
2018 mlx5_args_check(const char *key, const char *val, void *opaque)
2019 {
2020         struct mlx5_dev_config *config = opaque;
2021         unsigned long mod;
2022         signed long tmp;
2023
2024         /* No-op, port representors are processed in mlx5_dev_spawn(). */
2025         if (!strcmp(MLX5_DRIVER_KEY, key) || !strcmp(MLX5_REPRESENTOR, key) ||
2026             !strcmp(MLX5_SYS_MEM_EN, key) || !strcmp(MLX5_TX_DB_NC, key) ||
2027             !strcmp(MLX5_MR_MEMPOOL_REG_EN, key) ||
2028             !strcmp(MLX5_MR_EXT_MEMSEG_EN, key))
2029                 return 0;
2030         errno = 0;
2031         tmp = strtol(val, NULL, 0);
2032         if (errno) {
2033                 rte_errno = errno;
2034                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
2035                 return -rte_errno;
2036         }
2037         if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
2038                 /* Negative values are acceptable for some keys only. */
2039                 rte_errno = EINVAL;
2040                 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
2041                 return -rte_errno;
2042         }
2043         mod = tmp >= 0 ? tmp : -tmp;
2044         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
2045                 if (tmp > MLX5_CQE_RESP_FORMAT_L34H_STRIDX) {
2046                         DRV_LOG(ERR, "invalid CQE compression "
2047                                      "format parameter");
2048                         rte_errno = EINVAL;
2049                         return -rte_errno;
2050                 }
2051                 config->cqe_comp = !!tmp;
2052                 config->cqe_comp_fmt = tmp;
2053         } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
2054                 config->hw_padding = !!tmp;
2055         } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
2056                 config->mprq.enabled = !!tmp;
2057         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
2058                 config->mprq.stride_num_n = tmp;
2059         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
2060                 config->mprq.stride_size_n = tmp;
2061         } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
2062                 config->mprq.max_memcpy_len = tmp;
2063         } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
2064                 config->mprq.min_rxqs_num = tmp;
2065         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
2066                 DRV_LOG(WARNING, "%s: deprecated parameter,"
2067                                  " converted to txq_inline_max", key);
2068                 config->txq_inline_max = tmp;
2069         } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
2070                 config->txq_inline_max = tmp;
2071         } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
2072                 config->txq_inline_min = tmp;
2073         } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
2074                 config->txq_inline_mpw = tmp;
2075         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
2076                 config->txqs_inline = tmp;
2077         } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
2078                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
2079         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
2080                 config->mps = !!tmp;
2081         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
2082                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
2083         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
2084                 DRV_LOG(WARNING, "%s: deprecated parameter,"
2085                                  " converted to txq_inline_mpw", key);
2086                 config->txq_inline_mpw = tmp;
2087         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
2088                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
2089         } else if (strcmp(MLX5_TX_PP, key) == 0) {
2090                 if (!mod) {
2091                         DRV_LOG(ERR, "Zero Tx packet pacing parameter");
2092                         rte_errno = EINVAL;
2093                         return -rte_errno;
2094                 }
2095                 config->tx_pp = tmp;
2096         } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
2097                 config->tx_skew = tmp;
2098         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
2099                 config->rx_vec_en = !!tmp;
2100         } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
2101                 config->l3_vxlan_en = !!tmp;
2102         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
2103                 config->vf_nl_en = !!tmp;
2104         } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
2105                 config->dv_esw_en = !!tmp;
2106         } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
2107                 config->dv_flow_en = !!tmp;
2108         } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
2109                 if (tmp != MLX5_XMETA_MODE_LEGACY &&
2110                     tmp != MLX5_XMETA_MODE_META16 &&
2111                     tmp != MLX5_XMETA_MODE_META32 &&
2112                     tmp != MLX5_XMETA_MODE_MISS_INFO) {
2113                         DRV_LOG(ERR, "invalid extensive "
2114                                      "metadata parameter");
2115                         rte_errno = EINVAL;
2116                         return -rte_errno;
2117                 }
2118                 if (tmp != MLX5_XMETA_MODE_MISS_INFO)
2119                         config->dv_xmeta_en = tmp;
2120                 else
2121                         config->dv_miss_info = 1;
2122         } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
2123                 config->lacp_by_user = !!tmp;
2124         } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
2125                 config->max_dump_files_num = tmp;
2126         } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
2127                 config->lro.timeout = tmp;
2128         } else if (strcmp(RTE_DEVARGS_KEY_CLASS, key) == 0) {
2129                 DRV_LOG(DEBUG, "class argument is %s.", val);
2130         } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
2131                 config->log_hp_size = tmp;
2132         } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
2133                 if (tmp != MLX5_RCM_NONE &&
2134                     tmp != MLX5_RCM_LIGHT &&
2135                     tmp != MLX5_RCM_AGGR) {
2136                         DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
2137                         rte_errno = EINVAL;
2138                         return -rte_errno;
2139                 }
2140                 config->reclaim_mode = tmp;
2141         } else if (strcmp(MLX5_DECAP_EN, key) == 0) {
2142                 config->decap_en = !!tmp;
2143         } else if (strcmp(MLX5_ALLOW_DUPLICATE_PATTERN, key) == 0) {
2144                 config->allow_duplicate_pattern = !!tmp;
2145         } else {
2146                 DRV_LOG(WARNING, "%s: unknown parameter", key);
2147                 rte_errno = EINVAL;
2148                 return -rte_errno;
2149         }
2150         return 0;
2151 }
2152
2153 /**
2154  * Parse device parameters.
2155  *
2156  * @param config
2157  *   Pointer to device configuration structure.
2158  * @param devargs
2159  *   Device arguments structure.
2160  *
2161  * @return
2162  *   0 on success, a negative errno value otherwise and rte_errno is set.
2163  */
2164 int
2165 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
2166 {
2167         const char **params = (const char *[]){
2168                 MLX5_DRIVER_KEY,
2169                 MLX5_RXQ_CQE_COMP_EN,
2170                 MLX5_RXQ_PKT_PAD_EN,
2171                 MLX5_RX_MPRQ_EN,
2172                 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
2173                 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
2174                 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
2175                 MLX5_RXQS_MIN_MPRQ,
2176                 MLX5_TXQ_INLINE,
2177                 MLX5_TXQ_INLINE_MIN,
2178                 MLX5_TXQ_INLINE_MAX,
2179                 MLX5_TXQ_INLINE_MPW,
2180                 MLX5_TXQS_MIN_INLINE,
2181                 MLX5_TXQS_MAX_VEC,
2182                 MLX5_TXQ_MPW_EN,
2183                 MLX5_TXQ_MPW_HDR_DSEG_EN,
2184                 MLX5_TXQ_MAX_INLINE_LEN,
2185                 MLX5_TX_DB_NC,
2186                 MLX5_TX_PP,
2187                 MLX5_TX_SKEW,
2188                 MLX5_TX_VEC_EN,
2189                 MLX5_RX_VEC_EN,
2190                 MLX5_L3_VXLAN_EN,
2191                 MLX5_VF_NL_EN,
2192                 MLX5_DV_ESW_EN,
2193                 MLX5_DV_FLOW_EN,
2194                 MLX5_DV_XMETA_EN,
2195                 MLX5_LACP_BY_USER,
2196                 MLX5_MR_EXT_MEMSEG_EN,
2197                 MLX5_REPRESENTOR,
2198                 MLX5_MAX_DUMP_FILES_NUM,
2199                 MLX5_LRO_TIMEOUT_USEC,
2200                 RTE_DEVARGS_KEY_CLASS,
2201                 MLX5_HP_BUF_SIZE,
2202                 MLX5_RECLAIM_MEM,
2203                 MLX5_SYS_MEM_EN,
2204                 MLX5_DECAP_EN,
2205                 MLX5_ALLOW_DUPLICATE_PATTERN,
2206                 MLX5_MR_MEMPOOL_REG_EN,
2207                 NULL,
2208         };
2209         struct rte_kvargs *kvlist;
2210         int ret = 0;
2211         int i;
2212
2213         if (devargs == NULL)
2214                 return 0;
2215         /* Following UGLY cast is done to pass checkpatch. */
2216         kvlist = rte_kvargs_parse(devargs->args, params);
2217         if (kvlist == NULL) {
2218                 rte_errno = EINVAL;
2219                 return -rte_errno;
2220         }
2221         /* Process parameters. */
2222         for (i = 0; (params[i] != NULL); ++i) {
2223                 if (rte_kvargs_count(kvlist, params[i])) {
2224                         ret = rte_kvargs_process(kvlist, params[i],
2225                                                  mlx5_args_check, config);
2226                         if (ret) {
2227                                 rte_errno = EINVAL;
2228                                 rte_kvargs_free(kvlist);
2229                                 return -rte_errno;
2230                         }
2231                 }
2232         }
2233         rte_kvargs_free(kvlist);
2234         return 0;
2235 }
2236
2237 /**
2238  * Configures the minimal amount of data to inline into WQE
2239  * while sending packets.
2240  *
2241  * - the txq_inline_min has the maximal priority, if this
2242  *   key is specified in devargs
2243  * - if DevX is enabled the inline mode is queried from the
2244  *   device (HCA attributes and NIC vport context if needed).
2245  * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
2246  *   and none (0 bytes) for other NICs
2247  *
2248  * @param spawn
2249  *   Verbs device parameters (name, port, switch_info) to spawn.
2250  * @param config
2251  *   Device configuration parameters.
2252  */
2253 void
2254 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
2255                     struct mlx5_dev_config *config)
2256 {
2257         if (config->txq_inline_min != MLX5_ARG_UNSET) {
2258                 /* Application defines size of inlined data explicitly. */
2259                 if (spawn->pci_dev != NULL) {
2260                         switch (spawn->pci_dev->id.device_id) {
2261                         case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2262                         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2263                                 if (config->txq_inline_min <
2264                                                (int)MLX5_INLINE_HSIZE_L2) {
2265                                         DRV_LOG(DEBUG,
2266                                                 "txq_inline_mix aligned to minimal ConnectX-4 required value %d",
2267                                                 (int)MLX5_INLINE_HSIZE_L2);
2268                                         config->txq_inline_min =
2269                                                         MLX5_INLINE_HSIZE_L2;
2270                                 }
2271                                 break;
2272                         }
2273                 }
2274                 goto exit;
2275         }
2276         if (config->hca_attr.eth_net_offloads) {
2277                 /* We have DevX enabled, inline mode queried successfully. */
2278                 switch (config->hca_attr.wqe_inline_mode) {
2279                 case MLX5_CAP_INLINE_MODE_L2:
2280                         /* outer L2 header must be inlined. */
2281                         config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2282                         goto exit;
2283                 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
2284                         /* No inline data are required by NIC. */
2285                         config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2286                         config->hw_vlan_insert =
2287                                 config->hca_attr.wqe_vlan_insert;
2288                         DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
2289                         goto exit;
2290                 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
2291                         /* inline mode is defined by NIC vport context. */
2292                         if (!config->hca_attr.eth_virt)
2293                                 break;
2294                         switch (config->hca_attr.vport_inline_mode) {
2295                         case MLX5_INLINE_MODE_NONE:
2296                                 config->txq_inline_min =
2297                                         MLX5_INLINE_HSIZE_NONE;
2298                                 goto exit;
2299                         case MLX5_INLINE_MODE_L2:
2300                                 config->txq_inline_min =
2301                                         MLX5_INLINE_HSIZE_L2;
2302                                 goto exit;
2303                         case MLX5_INLINE_MODE_IP:
2304                                 config->txq_inline_min =
2305                                         MLX5_INLINE_HSIZE_L3;
2306                                 goto exit;
2307                         case MLX5_INLINE_MODE_TCP_UDP:
2308                                 config->txq_inline_min =
2309                                         MLX5_INLINE_HSIZE_L4;
2310                                 goto exit;
2311                         case MLX5_INLINE_MODE_INNER_L2:
2312                                 config->txq_inline_min =
2313                                         MLX5_INLINE_HSIZE_INNER_L2;
2314                                 goto exit;
2315                         case MLX5_INLINE_MODE_INNER_IP:
2316                                 config->txq_inline_min =
2317                                         MLX5_INLINE_HSIZE_INNER_L3;
2318                                 goto exit;
2319                         case MLX5_INLINE_MODE_INNER_TCP_UDP:
2320                                 config->txq_inline_min =
2321                                         MLX5_INLINE_HSIZE_INNER_L4;
2322                                 goto exit;
2323                         }
2324                 }
2325         }
2326         if (spawn->pci_dev == NULL) {
2327                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2328                 goto exit;
2329         }
2330         /*
2331          * We get here if we are unable to deduce
2332          * inline data size with DevX. Try PCI ID
2333          * to determine old NICs.
2334          */
2335         switch (spawn->pci_dev->id.device_id) {
2336         case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2337         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2338         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
2339         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
2340                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2341                 config->hw_vlan_insert = 0;
2342                 break;
2343         case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
2344         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
2345         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
2346         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
2347                 /*
2348                  * These NICs support VLAN insertion from WQE and
2349                  * report the wqe_vlan_insert flag. But there is the bug
2350                  * and PFC control may be broken, so disable feature.
2351                  */
2352                 config->hw_vlan_insert = 0;
2353                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2354                 break;
2355         default:
2356                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2357                 break;
2358         }
2359 exit:
2360         DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
2361 }
2362
2363 /**
2364  * Configures the metadata mask fields in the shared context.
2365  *
2366  * @param [in] dev
2367  *   Pointer to Ethernet device.
2368  */
2369 void
2370 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
2371 {
2372         struct mlx5_priv *priv = dev->data->dev_private;
2373         struct mlx5_dev_ctx_shared *sh = priv->sh;
2374         uint32_t meta, mark, reg_c0;
2375
2376         reg_c0 = ~priv->vport_meta_mask;
2377         switch (priv->config.dv_xmeta_en) {
2378         case MLX5_XMETA_MODE_LEGACY:
2379                 meta = UINT32_MAX;
2380                 mark = MLX5_FLOW_MARK_MASK;
2381                 break;
2382         case MLX5_XMETA_MODE_META16:
2383                 meta = reg_c0 >> rte_bsf32(reg_c0);
2384                 mark = MLX5_FLOW_MARK_MASK;
2385                 break;
2386         case MLX5_XMETA_MODE_META32:
2387                 meta = UINT32_MAX;
2388                 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
2389                 break;
2390         default:
2391                 meta = 0;
2392                 mark = 0;
2393                 MLX5_ASSERT(false);
2394                 break;
2395         }
2396         if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
2397                 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
2398                                  sh->dv_mark_mask, mark);
2399         else
2400                 sh->dv_mark_mask = mark;
2401         if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
2402                 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
2403                                  sh->dv_meta_mask, meta);
2404         else
2405                 sh->dv_meta_mask = meta;
2406         if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
2407                 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
2408                                  sh->dv_meta_mask, reg_c0);
2409         else
2410                 sh->dv_regc0_mask = reg_c0;
2411         DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
2412         DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
2413         DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
2414         DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
2415 }
2416
2417 int
2418 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
2419 {
2420         static const char *const dynf_names[] = {
2421                 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
2422                 RTE_MBUF_DYNFLAG_METADATA_NAME,
2423                 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
2424         };
2425         unsigned int i;
2426
2427         if (n < RTE_DIM(dynf_names))
2428                 return -ENOMEM;
2429         for (i = 0; i < RTE_DIM(dynf_names); i++) {
2430                 if (names[i] == NULL)
2431                         return -EINVAL;
2432                 strcpy(names[i], dynf_names[i]);
2433         }
2434         return RTE_DIM(dynf_names);
2435 }
2436
2437 /**
2438  * Comparison callback to sort device data.
2439  *
2440  * This is meant to be used with qsort().
2441  *
2442  * @param a[in]
2443  *   Pointer to pointer to first data object.
2444  * @param b[in]
2445  *   Pointer to pointer to second data object.
2446  *
2447  * @return
2448  *   0 if both objects are equal, less than 0 if the first argument is less
2449  *   than the second, greater than 0 otherwise.
2450  */
2451 int
2452 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
2453                               struct mlx5_dev_config *config,
2454                               struct rte_device *dpdk_dev)
2455 {
2456         struct mlx5_dev_ctx_shared *sh = priv->sh;
2457         struct mlx5_dev_config *sh_conf = NULL;
2458         uint16_t port_id;
2459
2460         MLX5_ASSERT(sh);
2461         /* Nothing to compare for the single/first device. */
2462         if (sh->refcnt == 1)
2463                 return 0;
2464         /* Find the device with shared context. */
2465         MLX5_ETH_FOREACH_DEV(port_id, dpdk_dev) {
2466                 struct mlx5_priv *opriv =
2467                         rte_eth_devices[port_id].data->dev_private;
2468
2469                 if (opriv && opriv != priv && opriv->sh == sh) {
2470                         sh_conf = &opriv->config;
2471                         break;
2472                 }
2473         }
2474         if (!sh_conf)
2475                 return 0;
2476         if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
2477                 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
2478                              " for shared %s context", sh->ibdev_name);
2479                 rte_errno = EINVAL;
2480                 return rte_errno;
2481         }
2482         if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
2483                 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
2484                              " for shared %s context", sh->ibdev_name);
2485                 rte_errno = EINVAL;
2486                 return rte_errno;
2487         }
2488         return 0;
2489 }
2490
2491 /**
2492  * Look for the ethernet device belonging to mlx5 driver.
2493  *
2494  * @param[in] port_id
2495  *   port_id to start looking for device.
2496  * @param[in] odev
2497  *   Pointer to the hint device. When device is being probed
2498  *   the its siblings (master and preceding representors might
2499  *   not have assigned driver yet (because the mlx5_os_pci_probe()
2500  *   is not completed yet, for this case match on hint
2501  *   device may be used to detect sibling device.
2502  *
2503  * @return
2504  *   port_id of found device, RTE_MAX_ETHPORT if not found.
2505  */
2506 uint16_t
2507 mlx5_eth_find_next(uint16_t port_id, struct rte_device *odev)
2508 {
2509         while (port_id < RTE_MAX_ETHPORTS) {
2510                 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
2511
2512                 if (dev->state != RTE_ETH_DEV_UNUSED &&
2513                     dev->device &&
2514                     (dev->device == odev ||
2515                      (dev->device->driver &&
2516                      dev->device->driver->name &&
2517                      ((strcmp(dev->device->driver->name,
2518                               MLX5_PCI_DRIVER_NAME) == 0) ||
2519                       (strcmp(dev->device->driver->name,
2520                               MLX5_AUXILIARY_DRIVER_NAME) == 0)))))
2521                         break;
2522                 port_id++;
2523         }
2524         if (port_id >= RTE_MAX_ETHPORTS)
2525                 return RTE_MAX_ETHPORTS;
2526         return port_id;
2527 }
2528
2529 /**
2530  * Callback to remove a device.
2531  *
2532  * This function removes all Ethernet devices belong to a given device.
2533  *
2534  * @param[in] cdev
2535  *   Pointer to the generic device.
2536  *
2537  * @return
2538  *   0 on success, the function cannot fail.
2539  */
2540 int
2541 mlx5_net_remove(struct mlx5_common_device *cdev)
2542 {
2543         uint16_t port_id;
2544         int ret = 0;
2545
2546         RTE_ETH_FOREACH_DEV_OF(port_id, cdev->dev) {
2547                 /*
2548                  * mlx5_dev_close() is not registered to secondary process,
2549                  * call the close function explicitly for secondary process.
2550                  */
2551                 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
2552                         ret |= mlx5_dev_close(&rte_eth_devices[port_id]);
2553                 else
2554                         ret |= rte_eth_dev_close(port_id);
2555         }
2556         return ret == 0 ? 0 : -EIO;
2557 }
2558
2559 static const struct rte_pci_id mlx5_pci_id_map[] = {
2560         {
2561                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2562                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
2563         },
2564         {
2565                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2566                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
2567         },
2568         {
2569                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2570                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
2571         },
2572         {
2573                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2574                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
2575         },
2576         {
2577                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2578                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
2579         },
2580         {
2581                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2582                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
2583         },
2584         {
2585                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2586                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
2587         },
2588         {
2589                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2590                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
2591         },
2592         {
2593                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2594                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
2595         },
2596         {
2597                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2598                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
2599         },
2600         {
2601                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2602                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
2603         },
2604         {
2605                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2606                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
2607         },
2608         {
2609                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2610                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
2611         },
2612         {
2613                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2614                                 PCI_DEVICE_ID_MELLANOX_CONNECTXVF)
2615         },
2616         {
2617                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2618                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
2619         },
2620         {
2621                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2622                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
2623         },
2624         {
2625                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2626                                 PCI_DEVICE_ID_MELLANOX_CONNECTX7)
2627         },
2628         {
2629                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2630                                 PCI_DEVICE_ID_MELLANOX_CONNECTX7BF)
2631         },
2632         {
2633                 .vendor_id = 0
2634         }
2635 };
2636
2637 static struct mlx5_class_driver mlx5_net_driver = {
2638         .drv_class = MLX5_CLASS_ETH,
2639         .name = RTE_STR(MLX5_ETH_DRIVER_NAME),
2640         .id_table = mlx5_pci_id_map,
2641         .probe = mlx5_os_net_probe,
2642         .remove = mlx5_net_remove,
2643         .dma_map = mlx5_net_dma_map,
2644         .dma_unmap = mlx5_net_dma_unmap,
2645         .probe_again = 1,
2646         .intr_lsc = 1,
2647         .intr_rmv = 1,
2648 };
2649
2650 /* Initialize driver log type. */
2651 RTE_LOG_REGISTER_DEFAULT(mlx5_logtype, NOTICE)
2652
2653 /**
2654  * Driver initialization routine.
2655  */
2656 RTE_INIT(rte_mlx5_pmd_init)
2657 {
2658         pthread_mutex_init(&mlx5_dev_ctx_list_mutex, NULL);
2659         mlx5_common_init();
2660         /* Build the static tables for Verbs conversion. */
2661         mlx5_set_ptype_table();
2662         mlx5_set_cksum_table();
2663         mlx5_set_swp_types_table();
2664         if (mlx5_glue)
2665                 mlx5_class_driver_register(&mlx5_net_driver);
2666 }
2667
2668 RTE_PMD_EXPORT_NAME(MLX5_ETH_DRIVER_NAME, __COUNTER__);
2669 RTE_PMD_REGISTER_PCI_TABLE(MLX5_ETH_DRIVER_NAME, mlx5_pci_id_map);
2670 RTE_PMD_REGISTER_KMOD_DEP(MLX5_ETH_DRIVER_NAME, "* ib_uverbs & mlx5_core & mlx5_ib");