4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
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44 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
46 #pragma GCC diagnostic ignored "-Wpedantic"
48 #include <infiniband/verbs.h>
50 #pragma GCC diagnostic error "-Wpedantic"
53 #include <rte_malloc.h>
54 #include <rte_ethdev_driver.h>
55 #include <rte_ethdev_pci.h>
57 #include <rte_bus_pci.h>
58 #include <rte_common.h>
59 #include <rte_kvargs.h>
62 #include "mlx5_utils.h"
63 #include "mlx5_rxtx.h"
64 #include "mlx5_autoconf.h"
65 #include "mlx5_defs.h"
67 /* Device parameter to enable RX completion queue compression. */
68 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
70 /* Device parameter to configure inline send. */
71 #define MLX5_TXQ_INLINE "txq_inline"
74 * Device parameter to configure the number of TX queues threshold for
75 * enabling inline send.
77 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
79 /* Device parameter to enable multi-packet send WQEs. */
80 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
82 /* Device parameter to include 2 dsegs in the title WQEBB. */
83 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
85 /* Device parameter to limit the size of inlining packet. */
86 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
88 /* Device parameter to enable hardware Tx vector. */
89 #define MLX5_TX_VEC_EN "tx_vec_en"
91 /* Device parameter to enable hardware Rx vector. */
92 #define MLX5_RX_VEC_EN "rx_vec_en"
94 #ifndef HAVE_IBV_MLX5_MOD_MPW
95 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2)
96 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3)
99 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP
100 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4)
104 * Retrieve integer value from environment variable.
107 * Environment variable name.
110 * Integer value, 0 if the variable is not set.
113 mlx5_getenv_int(const char *name)
115 const char *val = getenv(name);
123 * Verbs callback to allocate a memory. This function should allocate the space
124 * according to the size provided residing inside a huge page.
125 * Please note that all allocation must respect the alignment from libmlx5
126 * (i.e. currently sysconf(_SC_PAGESIZE)).
129 * The size in bytes of the memory to allocate.
131 * A pointer to the callback data.
134 * a pointer to the allocate space.
137 mlx5_alloc_verbs_buf(size_t size, void *data)
139 struct priv *priv = data;
141 size_t alignment = sysconf(_SC_PAGESIZE);
142 unsigned int socket = SOCKET_ID_ANY;
144 if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) {
145 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
147 socket = ctrl->socket;
148 } else if (priv->verbs_alloc_ctx.type ==
149 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) {
150 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
152 socket = ctrl->socket;
154 assert(data != NULL);
155 ret = rte_malloc_socket(__func__, size, alignment, socket);
156 DEBUG("Extern alloc size: %lu, align: %lu: %p", size, alignment, ret);
161 * Verbs callback to free a memory.
164 * A pointer to the memory to free.
166 * A pointer to the callback data.
169 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused)
171 assert(data != NULL);
172 DEBUG("Extern free request: %p", ptr);
177 * DPDK callback to close the device.
179 * Destroy all queues and objects, free memory.
182 * Pointer to Ethernet device structure.
185 mlx5_dev_close(struct rte_eth_dev *dev)
187 struct priv *priv = dev->data->dev_private;
192 DEBUG("%p: closing device \"%s\"",
194 ((priv->ctx != NULL) ? priv->ctx->device->name : ""));
195 /* In case mlx5_dev_stop() has not been called. */
196 priv_dev_interrupt_handler_uninstall(priv, dev);
197 priv_dev_traffic_disable(priv, dev);
198 /* Prevent crashes when queues are still in use. */
199 dev->rx_pkt_burst = removed_rx_burst;
200 dev->tx_pkt_burst = removed_tx_burst;
201 if (priv->rxqs != NULL) {
202 /* XXX race condition if mlx5_rx_burst() is still running. */
204 for (i = 0; (i != priv->rxqs_n); ++i)
205 mlx5_priv_rxq_release(priv, i);
209 if (priv->txqs != NULL) {
210 /* XXX race condition if mlx5_tx_burst() is still running. */
212 for (i = 0; (i != priv->txqs_n); ++i)
213 mlx5_priv_txq_release(priv, i);
217 if (priv->pd != NULL) {
218 assert(priv->ctx != NULL);
219 claim_zero(ibv_dealloc_pd(priv->pd));
220 claim_zero(ibv_close_device(priv->ctx));
222 assert(priv->ctx == NULL);
223 if (priv->rss_conf.rss_key != NULL)
224 rte_free(priv->rss_conf.rss_key);
225 if (priv->reta_idx != NULL)
226 rte_free(priv->reta_idx);
227 priv_socket_uninit(priv);
228 ret = mlx5_priv_hrxq_ibv_verify(priv);
230 WARN("%p: some Hash Rx queue still remain", (void *)priv);
231 ret = mlx5_priv_ind_table_ibv_verify(priv);
233 WARN("%p: some Indirection table still remain", (void *)priv);
234 ret = mlx5_priv_rxq_ibv_verify(priv);
236 WARN("%p: some Verbs Rx queue still remain", (void *)priv);
237 ret = mlx5_priv_rxq_verify(priv);
239 WARN("%p: some Rx Queues still remain", (void *)priv);
240 ret = mlx5_priv_txq_ibv_verify(priv);
242 WARN("%p: some Verbs Tx queue still remain", (void *)priv);
243 ret = mlx5_priv_txq_verify(priv);
245 WARN("%p: some Tx Queues still remain", (void *)priv);
246 ret = priv_flow_verify(priv);
248 WARN("%p: some flows still remain", (void *)priv);
249 ret = priv_mr_verify(priv);
251 WARN("%p: some Memory Region still remain", (void *)priv);
253 memset(priv, 0, sizeof(*priv));
256 const struct eth_dev_ops mlx5_dev_ops = {
257 .dev_configure = mlx5_dev_configure,
258 .dev_start = mlx5_dev_start,
259 .dev_stop = mlx5_dev_stop,
260 .dev_set_link_down = mlx5_set_link_down,
261 .dev_set_link_up = mlx5_set_link_up,
262 .dev_close = mlx5_dev_close,
263 .promiscuous_enable = mlx5_promiscuous_enable,
264 .promiscuous_disable = mlx5_promiscuous_disable,
265 .allmulticast_enable = mlx5_allmulticast_enable,
266 .allmulticast_disable = mlx5_allmulticast_disable,
267 .link_update = mlx5_link_update,
268 .stats_get = mlx5_stats_get,
269 .stats_reset = mlx5_stats_reset,
270 .xstats_get = mlx5_xstats_get,
271 .xstats_reset = mlx5_xstats_reset,
272 .xstats_get_names = mlx5_xstats_get_names,
273 .dev_infos_get = mlx5_dev_infos_get,
274 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
275 .vlan_filter_set = mlx5_vlan_filter_set,
276 .rx_queue_setup = mlx5_rx_queue_setup,
277 .tx_queue_setup = mlx5_tx_queue_setup,
278 .rx_queue_release = mlx5_rx_queue_release,
279 .tx_queue_release = mlx5_tx_queue_release,
280 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
281 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
282 .mac_addr_remove = mlx5_mac_addr_remove,
283 .mac_addr_add = mlx5_mac_addr_add,
284 .mac_addr_set = mlx5_mac_addr_set,
285 .mtu_set = mlx5_dev_set_mtu,
286 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
287 .vlan_offload_set = mlx5_vlan_offload_set,
288 .reta_update = mlx5_dev_rss_reta_update,
289 .reta_query = mlx5_dev_rss_reta_query,
290 .rss_hash_update = mlx5_rss_hash_update,
291 .rss_hash_conf_get = mlx5_rss_hash_conf_get,
292 .filter_ctrl = mlx5_dev_filter_ctrl,
293 .rx_descriptor_status = mlx5_rx_descriptor_status,
294 .tx_descriptor_status = mlx5_tx_descriptor_status,
295 .rx_queue_intr_enable = mlx5_rx_intr_enable,
296 .rx_queue_intr_disable = mlx5_rx_intr_disable,
297 .is_removed = mlx5_is_removed,
300 static const struct eth_dev_ops mlx5_dev_sec_ops = {
301 .stats_get = mlx5_stats_get,
302 .stats_reset = mlx5_stats_reset,
303 .xstats_get = mlx5_xstats_get,
304 .xstats_reset = mlx5_xstats_reset,
305 .xstats_get_names = mlx5_xstats_get_names,
306 .dev_infos_get = mlx5_dev_infos_get,
307 .rx_descriptor_status = mlx5_rx_descriptor_status,
308 .tx_descriptor_status = mlx5_tx_descriptor_status,
311 /* Available operators in flow isolated mode. */
312 const struct eth_dev_ops mlx5_dev_ops_isolate = {
313 .dev_configure = mlx5_dev_configure,
314 .dev_start = mlx5_dev_start,
315 .dev_stop = mlx5_dev_stop,
316 .dev_set_link_down = mlx5_set_link_down,
317 .dev_set_link_up = mlx5_set_link_up,
318 .dev_close = mlx5_dev_close,
319 .link_update = mlx5_link_update,
320 .stats_get = mlx5_stats_get,
321 .stats_reset = mlx5_stats_reset,
322 .xstats_get = mlx5_xstats_get,
323 .xstats_reset = mlx5_xstats_reset,
324 .xstats_get_names = mlx5_xstats_get_names,
325 .dev_infos_get = mlx5_dev_infos_get,
326 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
327 .vlan_filter_set = mlx5_vlan_filter_set,
328 .rx_queue_setup = mlx5_rx_queue_setup,
329 .tx_queue_setup = mlx5_tx_queue_setup,
330 .rx_queue_release = mlx5_rx_queue_release,
331 .tx_queue_release = mlx5_tx_queue_release,
332 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
333 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
334 .mac_addr_remove = mlx5_mac_addr_remove,
335 .mac_addr_add = mlx5_mac_addr_add,
336 .mac_addr_set = mlx5_mac_addr_set,
337 .mtu_set = mlx5_dev_set_mtu,
338 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
339 .vlan_offload_set = mlx5_vlan_offload_set,
340 .filter_ctrl = mlx5_dev_filter_ctrl,
341 .rx_descriptor_status = mlx5_rx_descriptor_status,
342 .tx_descriptor_status = mlx5_tx_descriptor_status,
343 .rx_queue_intr_enable = mlx5_rx_intr_enable,
344 .rx_queue_intr_disable = mlx5_rx_intr_disable,
345 .is_removed = mlx5_is_removed,
349 struct rte_pci_addr pci_addr; /* associated PCI address */
350 uint32_t ports; /* physical ports bitfield. */
354 * Get device index in mlx5_dev[] from PCI bus address.
356 * @param[in] pci_addr
357 * PCI bus address to look for.
360 * mlx5_dev[] index on success, -1 on failure.
363 mlx5_dev_idx(struct rte_pci_addr *pci_addr)
368 assert(pci_addr != NULL);
369 for (i = 0; (i != RTE_DIM(mlx5_dev)); ++i) {
370 if ((mlx5_dev[i].pci_addr.domain == pci_addr->domain) &&
371 (mlx5_dev[i].pci_addr.bus == pci_addr->bus) &&
372 (mlx5_dev[i].pci_addr.devid == pci_addr->devid) &&
373 (mlx5_dev[i].pci_addr.function == pci_addr->function))
375 if ((mlx5_dev[i].ports == 0) && (ret == -1))
382 * Verify and store value for device argument.
385 * Key argument to verify.
387 * Value associated with key.
392 * 0 on success, negative errno value on failure.
395 mlx5_args_check(const char *key, const char *val, void *opaque)
397 struct mlx5_dev_config *config = opaque;
401 tmp = strtoul(val, NULL, 0);
403 WARN("%s: \"%s\" is not a valid integer", key, val);
406 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
407 config->cqe_comp = !!tmp;
408 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
409 config->txq_inline = tmp;
410 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
411 config->txqs_inline = tmp;
412 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
413 config->mps = !!tmp ? config->mps : 0;
414 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
415 config->mpw_hdr_dseg = !!tmp;
416 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
417 config->inline_max_packet_sz = tmp;
418 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
419 config->tx_vec_en = !!tmp;
420 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
421 config->rx_vec_en = !!tmp;
423 WARN("%s: unknown parameter", key);
430 * Parse device parameters.
433 * Pointer to device configuration structure.
435 * Device arguments structure.
438 * 0 on success, errno value on failure.
441 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
443 const char **params = (const char *[]){
444 MLX5_RXQ_CQE_COMP_EN,
446 MLX5_TXQS_MIN_INLINE,
448 MLX5_TXQ_MPW_HDR_DSEG_EN,
449 MLX5_TXQ_MAX_INLINE_LEN,
454 struct rte_kvargs *kvlist;
460 /* Following UGLY cast is done to pass checkpatch. */
461 kvlist = rte_kvargs_parse(devargs->args, params);
464 /* Process parameters. */
465 for (i = 0; (params[i] != NULL); ++i) {
466 if (rte_kvargs_count(kvlist, params[i])) {
467 ret = rte_kvargs_process(kvlist, params[i],
468 mlx5_args_check, config);
470 rte_kvargs_free(kvlist);
475 rte_kvargs_free(kvlist);
479 static struct rte_pci_driver mlx5_driver;
482 * DPDK callback to register a PCI device.
484 * This function creates an Ethernet device for each port of a given
488 * PCI driver structure (mlx5_driver).
490 * PCI device information.
493 * 0 on success, negative errno value on failure.
496 mlx5_pci_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
498 struct ibv_device **list;
499 struct ibv_device *ibv_dev;
501 struct ibv_context *attr_ctx = NULL;
502 struct ibv_device_attr_ex device_attr;
505 unsigned int cqe_comp;
506 unsigned int tunnel_en = 0;
509 struct mlx5dv_context attrs_out;
510 #ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT
511 struct ibv_counter_set_description cs_desc;
515 assert(pci_drv == &mlx5_driver);
516 /* Get mlx5_dev[] index. */
517 idx = mlx5_dev_idx(&pci_dev->addr);
519 ERROR("this driver cannot support any more adapters");
522 DEBUG("using driver device index %d", idx);
524 /* Save PCI address. */
525 mlx5_dev[idx].pci_addr = pci_dev->addr;
526 list = ibv_get_device_list(&i);
530 ERROR("cannot list devices, is ib_uverbs loaded?");
535 * For each listed device, check related sysfs entry against
536 * the provided PCI ID.
539 struct rte_pci_addr pci_addr;
542 DEBUG("checking device \"%s\"", list[i]->name);
543 if (mlx5_ibv_device_to_pci_addr(list[i], &pci_addr))
545 if ((pci_dev->addr.domain != pci_addr.domain) ||
546 (pci_dev->addr.bus != pci_addr.bus) ||
547 (pci_dev->addr.devid != pci_addr.devid) ||
548 (pci_dev->addr.function != pci_addr.function))
550 sriov = ((pci_dev->id.device_id ==
551 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF) ||
552 (pci_dev->id.device_id ==
553 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF) ||
554 (pci_dev->id.device_id ==
555 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF) ||
556 (pci_dev->id.device_id ==
557 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF));
558 switch (pci_dev->id.device_id) {
559 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
562 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
563 case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
564 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
565 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
566 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
572 INFO("PCI information matches, using device \"%s\""
575 sriov ? "true" : "false");
576 attr_ctx = ibv_open_device(list[i]);
580 if (attr_ctx == NULL) {
581 ibv_free_device_list(list);
584 ERROR("cannot access device, is mlx5_ib loaded?");
587 ERROR("cannot use device, are drivers up to date?");
595 DEBUG("device opened");
597 * Multi-packet send is supported by ConnectX-4 Lx PF as well
598 * as all ConnectX-5 devices.
600 mlx5dv_query_device(attr_ctx, &attrs_out);
601 if (attrs_out.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
602 if (attrs_out.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) {
603 DEBUG("Enhanced MPW is supported");
604 mps = MLX5_MPW_ENHANCED;
606 DEBUG("MPW is supported");
610 DEBUG("MPW isn't supported");
611 mps = MLX5_MPW_DISABLED;
613 if (RTE_CACHE_LINE_SIZE == 128 &&
614 !(attrs_out.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP))
618 if (ibv_query_device_ex(attr_ctx, NULL, &device_attr))
620 INFO("%u port(s) detected", device_attr.orig_attr.phys_port_cnt);
622 for (i = 0; i < device_attr.orig_attr.phys_port_cnt; i++) {
623 char name[RTE_ETH_NAME_MAX_LEN];
625 uint32_t port = i + 1; /* ports are indexed from one */
626 uint32_t test = (1 << i);
627 struct ibv_context *ctx = NULL;
628 struct ibv_port_attr port_attr;
629 struct ibv_pd *pd = NULL;
630 struct priv *priv = NULL;
631 struct rte_eth_dev *eth_dev;
632 struct ibv_device_attr_ex device_attr_ex;
633 struct ether_addr mac;
634 uint16_t num_vfs = 0;
635 struct ibv_device_attr_ex device_attr;
636 struct mlx5_dev_config config = {
637 .cqe_comp = cqe_comp,
639 .tunnel_en = tunnel_en,
643 .txq_inline = MLX5_ARG_UNSET,
644 .txqs_inline = MLX5_ARG_UNSET,
645 .inline_max_packet_sz = MLX5_ARG_UNSET,
648 len = snprintf(name, sizeof(name), PCI_PRI_FMT,
649 pci_dev->addr.domain, pci_dev->addr.bus,
650 pci_dev->addr.devid, pci_dev->addr.function);
651 if (device_attr.orig_attr.phys_port_cnt > 1)
652 snprintf(name + len, sizeof(name), " port %u", i);
654 mlx5_dev[idx].ports |= test;
656 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
657 eth_dev = rte_eth_dev_attach_secondary(name);
658 if (eth_dev == NULL) {
659 ERROR("can not attach rte ethdev");
663 eth_dev->device = &pci_dev->device;
664 eth_dev->dev_ops = &mlx5_dev_sec_ops;
665 priv = eth_dev->data->dev_private;
666 /* Receive command fd from primary process */
667 err = priv_socket_connect(priv);
672 /* Remap UAR for Tx queues. */
673 err = priv_tx_uar_remap(priv, err);
679 * Ethdev pointer is still required as input since
680 * the primary device is not accessible from the
683 eth_dev->rx_pkt_burst =
684 priv_select_rx_function(priv, eth_dev);
685 eth_dev->tx_pkt_burst =
686 priv_select_tx_function(priv, eth_dev);
690 DEBUG("using port %u (%08" PRIx32 ")", port, test);
692 ctx = ibv_open_device(ibv_dev);
698 ibv_query_device_ex(ctx, NULL, &device_attr);
699 /* Check port status. */
700 err = ibv_query_port(ctx, port, &port_attr);
702 ERROR("port query failed: %s", strerror(err));
706 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
707 ERROR("port %d is not configured in Ethernet mode",
713 if (port_attr.state != IBV_PORT_ACTIVE)
714 DEBUG("port %d is not active: \"%s\" (%d)",
715 port, ibv_port_state_str(port_attr.state),
718 /* Allocate protection domain. */
719 pd = ibv_alloc_pd(ctx);
721 ERROR("PD allocation failure");
726 mlx5_dev[idx].ports |= test;
728 /* from rte_ethdev.c */
729 priv = rte_zmalloc("ethdev private structure",
731 RTE_CACHE_LINE_SIZE);
733 ERROR("priv allocation failure");
739 strncpy(priv->ibdev_path, priv->ctx->device->ibdev_path,
740 sizeof(priv->ibdev_path));
741 priv->device_attr = device_attr;
744 priv->mtu = ETHER_MTU;
745 err = mlx5_args(&config, pci_dev->device.devargs);
747 ERROR("failed to process device arguments: %s",
751 if (ibv_query_device_ex(ctx, NULL, &device_attr_ex)) {
752 ERROR("ibv_query_device_ex() failed");
756 config.hw_csum = !!(device_attr_ex.device_cap_flags_ex &
757 IBV_DEVICE_RAW_IP_CSUM);
758 DEBUG("checksum offloading is %ssupported",
759 (config.hw_csum ? "" : "not "));
761 #ifdef HAVE_IBV_DEVICE_VXLAN_SUPPORT
762 config.hw_csum_l2tun =
763 !!(exp_device_attr.exp_device_cap_flags &
764 IBV_DEVICE_VXLAN_SUPPORT);
766 DEBUG("Rx L2 tunnel checksum offloads are %ssupported",
767 (config.hw_csum_l2tun ? "" : "not "));
769 #ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT
770 config.flow_counter_en = !!(device_attr.max_counter_sets);
771 ibv_describe_counter_set(ctx, 0, &cs_desc);
772 DEBUG("counter type = %d, num of cs = %ld, attributes = %d",
773 cs_desc.counter_type, cs_desc.num_of_cs,
776 config.ind_table_max_size =
777 device_attr_ex.rss_caps.max_rwq_indirection_table_size;
778 /* Remove this check once DPDK supports larger/variable
779 * indirection tables. */
780 if (config.ind_table_max_size >
781 (unsigned int)ETH_RSS_RETA_SIZE_512)
782 config.ind_table_max_size = ETH_RSS_RETA_SIZE_512;
783 DEBUG("maximum RX indirection table size is %u",
784 config.ind_table_max_size);
785 config.hw_vlan_strip = !!(device_attr_ex.raw_packet_caps &
786 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
787 DEBUG("VLAN stripping is %ssupported",
788 (config.hw_vlan_strip ? "" : "not "));
790 config.hw_fcs_strip =
791 !!(device_attr_ex.orig_attr.device_cap_flags &
792 IBV_WQ_FLAGS_SCATTER_FCS);
793 DEBUG("FCS stripping configuration is %ssupported",
794 (config.hw_fcs_strip ? "" : "not "));
796 #ifdef HAVE_IBV_WQ_FLAG_RX_END_PADDING
797 config.hw_padding = !!device_attr_ex.rx_pad_end_addr_align;
799 DEBUG("hardware RX end alignment padding is %ssupported",
800 (config.hw_padding ? "" : "not "));
802 priv_get_num_vfs(priv, &num_vfs);
803 config.sriov = (num_vfs || sriov);
804 config.tso = ((device_attr_ex.tso_caps.max_tso > 0) &&
805 (device_attr_ex.tso_caps.supported_qpts &
806 (1 << IBV_QPT_RAW_PACKET)));
808 config.tso_max_payload_sz =
809 device_attr_ex.tso_caps.max_tso;
810 if (config.mps && !mps) {
811 ERROR("multi-packet send not supported on this device"
812 " (" MLX5_TXQ_MPW_EN ")");
817 config.mps == MLX5_MPW_ENHANCED ? "Enhanced " : "",
818 config.mps != MLX5_MPW_DISABLED ? "enabled" : "disabled");
819 if (config.cqe_comp && !cqe_comp) {
820 WARN("Rx CQE compression isn't supported");
823 /* Configure the first MAC address by default. */
824 if (priv_get_mac(priv, &mac.addr_bytes)) {
825 ERROR("cannot get MAC address, is mlx5_en loaded?"
826 " (errno: %s)", strerror(errno));
830 INFO("port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x",
832 mac.addr_bytes[0], mac.addr_bytes[1],
833 mac.addr_bytes[2], mac.addr_bytes[3],
834 mac.addr_bytes[4], mac.addr_bytes[5]);
837 char ifname[IF_NAMESIZE];
839 if (priv_get_ifname(priv, &ifname) == 0)
840 DEBUG("port %u ifname is \"%s\"",
843 DEBUG("port %u ifname is unknown", priv->port);
846 /* Get actual MTU if possible. */
847 priv_get_mtu(priv, &priv->mtu);
848 DEBUG("port %u MTU is %u", priv->port, priv->mtu);
850 eth_dev = rte_eth_dev_allocate(name);
851 if (eth_dev == NULL) {
852 ERROR("can not allocate rte ethdev");
856 eth_dev->data->dev_private = priv;
857 eth_dev->data->mac_addrs = priv->mac;
858 eth_dev->device = &pci_dev->device;
859 rte_eth_copy_pci_info(eth_dev, pci_dev);
860 eth_dev->device->driver = &mlx5_driver.driver;
862 * Initialize burst functions to prevent crashes before link-up.
864 eth_dev->rx_pkt_burst = removed_rx_burst;
865 eth_dev->tx_pkt_burst = removed_tx_burst;
867 eth_dev->dev_ops = &mlx5_dev_ops;
868 /* Register MAC address. */
869 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
870 TAILQ_INIT(&priv->flows);
871 TAILQ_INIT(&priv->ctrl_flows);
873 /* Hint libmlx5 to use PMD allocator for data plane resources */
874 struct mlx5dv_ctx_allocators alctr = {
875 .alloc = &mlx5_alloc_verbs_buf,
876 .free = &mlx5_free_verbs_buf,
879 mlx5dv_set_context_attr(ctx, MLX5DV_CTX_ATTR_BUF_ALLOCATORS,
880 (void *)((uintptr_t)&alctr));
882 /* Bring Ethernet device up. */
883 DEBUG("forcing Ethernet interface up");
884 priv_set_flags(priv, ~IFF_UP, IFF_UP);
885 /* Store device configuration on private structure. */
886 priv->config = config;
893 claim_zero(ibv_dealloc_pd(pd));
895 claim_zero(ibv_close_device(ctx));
900 * XXX if something went wrong in the loop above, there is a resource
901 * leak (ctx, pd, priv, dpdk ethdev) but we can do nothing about it as
902 * long as the dpdk does not provide a way to deallocate a ethdev and a
903 * way to enumerate the registered ethdevs to free the previous ones.
906 /* no port found, complain */
907 if (!mlx5_dev[idx].ports) {
914 claim_zero(ibv_close_device(attr_ctx));
916 ibv_free_device_list(list);
921 static const struct rte_pci_id mlx5_pci_id_map[] = {
923 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
924 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
927 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
928 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
931 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
932 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
935 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
936 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
939 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
940 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
943 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
944 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
947 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
948 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
951 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
952 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
959 static struct rte_pci_driver mlx5_driver = {
961 .name = MLX5_DRIVER_NAME
963 .id_table = mlx5_pci_id_map,
964 .probe = mlx5_pci_probe,
965 .drv_flags = RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV,
969 * Driver initialization routine.
971 RTE_INIT(rte_mlx5_pmd_init);
973 rte_mlx5_pmd_init(void)
975 /* Build the static table for ptype conversion. */
976 mlx5_set_ptype_table();
978 * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use
979 * huge pages. Calling ibv_fork_init() during init allows
980 * applications to use fork() safely for purposes other than
981 * using this PMD, which is not supported in forked processes.
983 setenv("RDMAV_HUGEPAGES_SAFE", "1", 1);
984 /* Match the size of Rx completion entry to the size of a cacheline. */
985 if (RTE_CACHE_LINE_SIZE == 128)
986 setenv("MLX5_CQE_SIZE", "128", 0);
988 rte_pci_register(&mlx5_driver);
991 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
992 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
993 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");