1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
16 #include <linux/rtnetlink.h>
19 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
21 #pragma GCC diagnostic ignored "-Wpedantic"
23 #include <infiniband/verbs.h>
25 #pragma GCC diagnostic error "-Wpedantic"
28 #include <rte_malloc.h>
29 #include <rte_ethdev_driver.h>
30 #include <rte_ethdev_pci.h>
32 #include <rte_bus_pci.h>
33 #include <rte_common.h>
34 #include <rte_config.h>
35 #include <rte_eal_memconfig.h>
36 #include <rte_kvargs.h>
39 #include "mlx5_utils.h"
40 #include "mlx5_rxtx.h"
41 #include "mlx5_autoconf.h"
42 #include "mlx5_defs.h"
43 #include "mlx5_glue.h"
46 /* Device parameter to enable RX completion queue compression. */
47 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
49 /* Device parameter to enable Multi-Packet Rx queue. */
50 #define MLX5_RX_MPRQ_EN "mprq_en"
52 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
53 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
55 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
56 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
58 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
59 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
61 /* Device parameter to configure inline send. */
62 #define MLX5_TXQ_INLINE "txq_inline"
65 * Device parameter to configure the number of TX queues threshold for
66 * enabling inline send.
68 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
70 /* Device parameter to enable multi-packet send WQEs. */
71 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
73 /* Device parameter to include 2 dsegs in the title WQEBB. */
74 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
76 /* Device parameter to limit the size of inlining packet. */
77 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
79 /* Device parameter to enable hardware Tx vector. */
80 #define MLX5_TX_VEC_EN "tx_vec_en"
82 /* Device parameter to enable hardware Rx vector. */
83 #define MLX5_RX_VEC_EN "rx_vec_en"
85 /* Allow L3 VXLAN flow creation. */
86 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
88 /* Activate Netlink support in VF mode. */
89 #define MLX5_VF_NL_EN "vf_nl_en"
91 #ifndef HAVE_IBV_MLX5_MOD_MPW
92 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2)
93 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3)
96 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP
97 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4)
100 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
102 /* Shared memory between primary and secondary processes. */
103 struct mlx5_shared_data *mlx5_shared_data;
105 /* Spinlock for mlx5_shared_data allocation. */
106 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
108 /** Driver-specific log messages type. */
112 * Prepare shared data between primary and secondary process.
115 mlx5_prepare_shared_data(void)
117 const struct rte_memzone *mz;
119 rte_spinlock_lock(&mlx5_shared_data_lock);
120 if (mlx5_shared_data == NULL) {
121 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
122 /* Allocate shared memory. */
123 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
124 sizeof(*mlx5_shared_data),
127 /* Lookup allocated shared memory. */
128 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA);
131 rte_panic("Cannot allocate mlx5 shared data\n");
132 mlx5_shared_data = mz->addr;
133 /* Initialize shared data. */
134 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
135 LIST_INIT(&mlx5_shared_data->mem_event_cb_list);
136 rte_rwlock_init(&mlx5_shared_data->mem_event_rwlock);
139 rte_spinlock_unlock(&mlx5_shared_data_lock);
143 * Retrieve integer value from environment variable.
146 * Environment variable name.
149 * Integer value, 0 if the variable is not set.
152 mlx5_getenv_int(const char *name)
154 const char *val = getenv(name);
162 * Verbs callback to allocate a memory. This function should allocate the space
163 * according to the size provided residing inside a huge page.
164 * Please note that all allocation must respect the alignment from libmlx5
165 * (i.e. currently sysconf(_SC_PAGESIZE)).
168 * The size in bytes of the memory to allocate.
170 * A pointer to the callback data.
173 * Allocated buffer, NULL otherwise and rte_errno is set.
176 mlx5_alloc_verbs_buf(size_t size, void *data)
178 struct priv *priv = data;
180 size_t alignment = sysconf(_SC_PAGESIZE);
181 unsigned int socket = SOCKET_ID_ANY;
183 if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) {
184 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
186 socket = ctrl->socket;
187 } else if (priv->verbs_alloc_ctx.type ==
188 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) {
189 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
191 socket = ctrl->socket;
193 assert(data != NULL);
194 ret = rte_malloc_socket(__func__, size, alignment, socket);
201 * Verbs callback to free a memory.
204 * A pointer to the memory to free.
206 * A pointer to the callback data.
209 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused)
211 assert(data != NULL);
216 * DPDK callback to close the device.
218 * Destroy all queues and objects, free memory.
221 * Pointer to Ethernet device structure.
224 mlx5_dev_close(struct rte_eth_dev *dev)
226 struct priv *priv = dev->data->dev_private;
230 DRV_LOG(DEBUG, "port %u closing device \"%s\"",
232 ((priv->ctx != NULL) ? priv->ctx->device->name : ""));
233 /* In case mlx5_dev_stop() has not been called. */
234 mlx5_dev_interrupt_handler_uninstall(dev);
235 mlx5_traffic_disable(dev);
236 /* Prevent crashes when queues are still in use. */
237 dev->rx_pkt_burst = removed_rx_burst;
238 dev->tx_pkt_burst = removed_tx_burst;
239 if (priv->rxqs != NULL) {
240 /* XXX race condition if mlx5_rx_burst() is still running. */
242 for (i = 0; (i != priv->rxqs_n); ++i)
243 mlx5_rxq_release(dev, i);
247 if (priv->txqs != NULL) {
248 /* XXX race condition if mlx5_tx_burst() is still running. */
250 for (i = 0; (i != priv->txqs_n); ++i)
251 mlx5_txq_release(dev, i);
255 mlx5_flow_delete_drop_queue(dev);
256 mlx5_mprq_free_mp(dev);
257 mlx5_mr_release(dev);
258 if (priv->pd != NULL) {
259 assert(priv->ctx != NULL);
260 claim_zero(mlx5_glue->dealloc_pd(priv->pd));
261 claim_zero(mlx5_glue->close_device(priv->ctx));
263 assert(priv->ctx == NULL);
264 if (priv->rss_conf.rss_key != NULL)
265 rte_free(priv->rss_conf.rss_key);
266 if (priv->reta_idx != NULL)
267 rte_free(priv->reta_idx);
268 if (priv->primary_socket)
269 mlx5_socket_uninit(dev);
271 mlx5_nl_mac_addr_flush(dev);
272 if (priv->nl_socket >= 0)
273 close(priv->nl_socket);
274 ret = mlx5_hrxq_ibv_verify(dev);
276 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
278 ret = mlx5_ind_table_ibv_verify(dev);
280 DRV_LOG(WARNING, "port %u some indirection table still remain",
282 ret = mlx5_rxq_ibv_verify(dev);
284 DRV_LOG(WARNING, "port %u some Verbs Rx queue still remain",
286 ret = mlx5_rxq_verify(dev);
288 DRV_LOG(WARNING, "port %u some Rx queues still remain",
290 ret = mlx5_txq_ibv_verify(dev);
292 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
294 ret = mlx5_txq_verify(dev);
296 DRV_LOG(WARNING, "port %u some Tx queues still remain",
298 ret = mlx5_flow_verify(dev);
300 DRV_LOG(WARNING, "port %u some flows still remain",
302 memset(priv, 0, sizeof(*priv));
305 const struct eth_dev_ops mlx5_dev_ops = {
306 .dev_configure = mlx5_dev_configure,
307 .dev_start = mlx5_dev_start,
308 .dev_stop = mlx5_dev_stop,
309 .dev_set_link_down = mlx5_set_link_down,
310 .dev_set_link_up = mlx5_set_link_up,
311 .dev_close = mlx5_dev_close,
312 .promiscuous_enable = mlx5_promiscuous_enable,
313 .promiscuous_disable = mlx5_promiscuous_disable,
314 .allmulticast_enable = mlx5_allmulticast_enable,
315 .allmulticast_disable = mlx5_allmulticast_disable,
316 .link_update = mlx5_link_update,
317 .stats_get = mlx5_stats_get,
318 .stats_reset = mlx5_stats_reset,
319 .xstats_get = mlx5_xstats_get,
320 .xstats_reset = mlx5_xstats_reset,
321 .xstats_get_names = mlx5_xstats_get_names,
322 .dev_infos_get = mlx5_dev_infos_get,
323 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
324 .vlan_filter_set = mlx5_vlan_filter_set,
325 .rx_queue_setup = mlx5_rx_queue_setup,
326 .tx_queue_setup = mlx5_tx_queue_setup,
327 .rx_queue_release = mlx5_rx_queue_release,
328 .tx_queue_release = mlx5_tx_queue_release,
329 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
330 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
331 .mac_addr_remove = mlx5_mac_addr_remove,
332 .mac_addr_add = mlx5_mac_addr_add,
333 .mac_addr_set = mlx5_mac_addr_set,
334 .set_mc_addr_list = mlx5_set_mc_addr_list,
335 .mtu_set = mlx5_dev_set_mtu,
336 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
337 .vlan_offload_set = mlx5_vlan_offload_set,
338 .reta_update = mlx5_dev_rss_reta_update,
339 .reta_query = mlx5_dev_rss_reta_query,
340 .rss_hash_update = mlx5_rss_hash_update,
341 .rss_hash_conf_get = mlx5_rss_hash_conf_get,
342 .filter_ctrl = mlx5_dev_filter_ctrl,
343 .rx_descriptor_status = mlx5_rx_descriptor_status,
344 .tx_descriptor_status = mlx5_tx_descriptor_status,
345 .rx_queue_intr_enable = mlx5_rx_intr_enable,
346 .rx_queue_intr_disable = mlx5_rx_intr_disable,
347 .is_removed = mlx5_is_removed,
350 static const struct eth_dev_ops mlx5_dev_sec_ops = {
351 .stats_get = mlx5_stats_get,
352 .stats_reset = mlx5_stats_reset,
353 .xstats_get = mlx5_xstats_get,
354 .xstats_reset = mlx5_xstats_reset,
355 .xstats_get_names = mlx5_xstats_get_names,
356 .dev_infos_get = mlx5_dev_infos_get,
357 .rx_descriptor_status = mlx5_rx_descriptor_status,
358 .tx_descriptor_status = mlx5_tx_descriptor_status,
361 /* Available operators in flow isolated mode. */
362 const struct eth_dev_ops mlx5_dev_ops_isolate = {
363 .dev_configure = mlx5_dev_configure,
364 .dev_start = mlx5_dev_start,
365 .dev_stop = mlx5_dev_stop,
366 .dev_set_link_down = mlx5_set_link_down,
367 .dev_set_link_up = mlx5_set_link_up,
368 .dev_close = mlx5_dev_close,
369 .link_update = mlx5_link_update,
370 .stats_get = mlx5_stats_get,
371 .stats_reset = mlx5_stats_reset,
372 .xstats_get = mlx5_xstats_get,
373 .xstats_reset = mlx5_xstats_reset,
374 .xstats_get_names = mlx5_xstats_get_names,
375 .dev_infos_get = mlx5_dev_infos_get,
376 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
377 .vlan_filter_set = mlx5_vlan_filter_set,
378 .rx_queue_setup = mlx5_rx_queue_setup,
379 .tx_queue_setup = mlx5_tx_queue_setup,
380 .rx_queue_release = mlx5_rx_queue_release,
381 .tx_queue_release = mlx5_tx_queue_release,
382 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
383 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
384 .mac_addr_remove = mlx5_mac_addr_remove,
385 .mac_addr_add = mlx5_mac_addr_add,
386 .mac_addr_set = mlx5_mac_addr_set,
387 .set_mc_addr_list = mlx5_set_mc_addr_list,
388 .mtu_set = mlx5_dev_set_mtu,
389 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
390 .vlan_offload_set = mlx5_vlan_offload_set,
391 .filter_ctrl = mlx5_dev_filter_ctrl,
392 .rx_descriptor_status = mlx5_rx_descriptor_status,
393 .tx_descriptor_status = mlx5_tx_descriptor_status,
394 .rx_queue_intr_enable = mlx5_rx_intr_enable,
395 .rx_queue_intr_disable = mlx5_rx_intr_disable,
396 .is_removed = mlx5_is_removed,
400 struct rte_pci_addr pci_addr; /* associated PCI address */
401 uint32_t ports; /* physical ports bitfield. */
405 * Get device index in mlx5_dev[] from PCI bus address.
407 * @param[in] pci_addr
408 * PCI bus address to look for.
411 * mlx5_dev[] index on success, -1 on failure.
414 mlx5_dev_idx(struct rte_pci_addr *pci_addr)
419 assert(pci_addr != NULL);
420 for (i = 0; (i != RTE_DIM(mlx5_dev)); ++i) {
421 if ((mlx5_dev[i].pci_addr.domain == pci_addr->domain) &&
422 (mlx5_dev[i].pci_addr.bus == pci_addr->bus) &&
423 (mlx5_dev[i].pci_addr.devid == pci_addr->devid) &&
424 (mlx5_dev[i].pci_addr.function == pci_addr->function))
426 if ((mlx5_dev[i].ports == 0) && (ret == -1))
433 * Verify and store value for device argument.
436 * Key argument to verify.
438 * Value associated with key.
443 * 0 on success, a negative errno value otherwise and rte_errno is set.
446 mlx5_args_check(const char *key, const char *val, void *opaque)
448 struct mlx5_dev_config *config = opaque;
452 tmp = strtoul(val, NULL, 0);
455 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
458 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
459 config->cqe_comp = !!tmp;
460 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
461 config->mprq.enabled = !!tmp;
462 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
463 config->mprq.stride_num_n = tmp;
464 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
465 config->mprq.max_memcpy_len = tmp;
466 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
467 config->mprq.min_rxqs_num = tmp;
468 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
469 config->txq_inline = tmp;
470 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
471 config->txqs_inline = tmp;
472 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
473 config->mps = !!tmp ? config->mps : 0;
474 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
475 config->mpw_hdr_dseg = !!tmp;
476 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
477 config->inline_max_packet_sz = tmp;
478 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
479 config->tx_vec_en = !!tmp;
480 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
481 config->rx_vec_en = !!tmp;
482 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
483 config->l3_vxlan_en = !!tmp;
484 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
485 config->vf_nl_en = !!tmp;
487 DRV_LOG(WARNING, "%s: unknown parameter", key);
495 * Parse device parameters.
498 * Pointer to device configuration structure.
500 * Device arguments structure.
503 * 0 on success, a negative errno value otherwise and rte_errno is set.
506 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
508 const char **params = (const char *[]){
509 MLX5_RXQ_CQE_COMP_EN,
511 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
512 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
515 MLX5_TXQS_MIN_INLINE,
517 MLX5_TXQ_MPW_HDR_DSEG_EN,
518 MLX5_TXQ_MAX_INLINE_LEN,
525 struct rte_kvargs *kvlist;
531 /* Following UGLY cast is done to pass checkpatch. */
532 kvlist = rte_kvargs_parse(devargs->args, params);
535 /* Process parameters. */
536 for (i = 0; (params[i] != NULL); ++i) {
537 if (rte_kvargs_count(kvlist, params[i])) {
538 ret = rte_kvargs_process(kvlist, params[i],
539 mlx5_args_check, config);
542 rte_kvargs_free(kvlist);
547 rte_kvargs_free(kvlist);
551 static struct rte_pci_driver mlx5_driver;
554 * Reserved UAR address space for TXQ UAR(hw doorbell) mapping, process
555 * local resource used by both primary and secondary to avoid duplicate
557 * The space has to be available on both primary and secondary process,
558 * TXQ UAR maps to this area using fixed mmap w/o double check.
560 static void *uar_base;
563 find_lower_va_bound(const struct rte_memseg_list *msl __rte_unused,
564 const struct rte_memseg *ms, void *arg)
571 *addr = RTE_MIN(*addr, ms->addr);
577 * Reserve UAR address space for primary process.
580 * Pointer to Ethernet device.
583 * 0 on success, a negative errno value otherwise and rte_errno is set.
586 mlx5_uar_init_primary(struct rte_eth_dev *dev)
588 struct priv *priv = dev->data->dev_private;
589 void *addr = (void *)0;
591 if (uar_base) { /* UAR address space mapped. */
592 priv->uar_base = uar_base;
595 /* find out lower bound of hugepage segments */
596 rte_memseg_walk(find_lower_va_bound, &addr);
598 /* keep distance to hugepages to minimize potential conflicts. */
599 addr = RTE_PTR_SUB(addr, MLX5_UAR_OFFSET + MLX5_UAR_SIZE);
600 /* anonymous mmap, no real memory consumption. */
601 addr = mmap(addr, MLX5_UAR_SIZE,
602 PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
603 if (addr == MAP_FAILED) {
605 "port %u failed to reserve UAR address space, please"
606 " adjust MLX5_UAR_SIZE or try --base-virtaddr",
611 /* Accept either same addr or a new addr returned from mmap if target
614 DRV_LOG(INFO, "port %u reserved UAR address space: %p",
615 dev->data->port_id, addr);
616 priv->uar_base = addr; /* for primary and secondary UAR re-mmap. */
617 uar_base = addr; /* process local, don't reserve again. */
622 * Reserve UAR address space for secondary process, align with
626 * Pointer to Ethernet device.
629 * 0 on success, a negative errno value otherwise and rte_errno is set.
632 mlx5_uar_init_secondary(struct rte_eth_dev *dev)
634 struct priv *priv = dev->data->dev_private;
637 assert(priv->uar_base);
638 if (uar_base) { /* already reserved. */
639 assert(uar_base == priv->uar_base);
642 /* anonymous mmap, no real memory consumption. */
643 addr = mmap(priv->uar_base, MLX5_UAR_SIZE,
644 PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
645 if (addr == MAP_FAILED) {
646 DRV_LOG(ERR, "port %u UAR mmap failed: %p size: %llu",
647 dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE);
651 if (priv->uar_base != addr) {
653 "port %u UAR address %p size %llu occupied, please"
654 " adjust MLX5_UAR_OFFSET or try EAL parameter"
656 dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE);
660 uar_base = addr; /* process local, don't reserve again */
661 DRV_LOG(INFO, "port %u reserved UAR address space: %p",
662 dev->data->port_id, addr);
667 * DPDK callback to register a PCI device.
669 * This function creates an Ethernet device for each port of a given
673 * PCI driver structure (mlx5_driver).
675 * PCI device information.
678 * 0 on success, a negative errno value otherwise and rte_errno is set.
681 mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
682 struct rte_pci_device *pci_dev)
684 struct ibv_device **list = NULL;
685 struct ibv_device *ibv_dev;
687 struct ibv_context *attr_ctx = NULL;
688 struct ibv_device_attr_ex device_attr;
691 unsigned int cqe_comp;
692 unsigned int tunnel_en = 0;
693 unsigned int swp = 0;
694 unsigned int verb_priorities = 0;
695 unsigned int mprq = 0;
696 unsigned int mprq_min_stride_size_n = 0;
697 unsigned int mprq_max_stride_size_n = 0;
698 unsigned int mprq_min_stride_num_n = 0;
699 unsigned int mprq_max_stride_num_n = 0;
702 struct mlx5dv_context attrs_out = {0};
703 #ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT
704 struct ibv_counter_set_description cs_desc;
707 /* Prepare shared data between primary and secondary process. */
708 mlx5_prepare_shared_data();
709 assert(pci_drv == &mlx5_driver);
710 /* Get mlx5_dev[] index. */
711 idx = mlx5_dev_idx(&pci_dev->addr);
713 DRV_LOG(ERR, "this driver cannot support any more adapters");
717 DRV_LOG(DEBUG, "using driver device index %d", idx);
718 /* Save PCI address. */
719 mlx5_dev[idx].pci_addr = pci_dev->addr;
720 list = mlx5_glue->get_device_list(&i);
726 "cannot list devices, is ib_uverbs loaded?");
731 * For each listed device, check related sysfs entry against
732 * the provided PCI ID.
735 struct rte_pci_addr pci_addr;
738 DRV_LOG(DEBUG, "checking device \"%s\"", list[i]->name);
739 if (mlx5_ibv_device_to_pci_addr(list[i], &pci_addr))
741 if ((pci_dev->addr.domain != pci_addr.domain) ||
742 (pci_dev->addr.bus != pci_addr.bus) ||
743 (pci_dev->addr.devid != pci_addr.devid) ||
744 (pci_dev->addr.function != pci_addr.function))
746 DRV_LOG(INFO, "PCI information matches, using device \"%s\"",
748 vf = ((pci_dev->id.device_id ==
749 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF) ||
750 (pci_dev->id.device_id ==
751 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF) ||
752 (pci_dev->id.device_id ==
753 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF) ||
754 (pci_dev->id.device_id ==
755 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF));
756 attr_ctx = mlx5_glue->open_device(list[i]);
761 if (attr_ctx == NULL) {
765 "cannot access device, is mlx5_ib loaded?");
770 "cannot use device, are drivers up to date?");
776 DRV_LOG(DEBUG, "device opened");
777 #ifdef HAVE_IBV_MLX5_MOD_SWP
778 attrs_out.comp_mask |= MLX5DV_CONTEXT_MASK_SWP;
781 * Multi-packet send is supported by ConnectX-4 Lx PF as well
782 * as all ConnectX-5 devices.
784 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
785 attrs_out.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS;
787 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
788 attrs_out.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ;
790 mlx5_glue->dv_query_device(attr_ctx, &attrs_out);
791 if (attrs_out.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
792 if (attrs_out.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) {
793 DRV_LOG(DEBUG, "enhanced MPW is supported");
794 mps = MLX5_MPW_ENHANCED;
796 DRV_LOG(DEBUG, "MPW is supported");
800 DRV_LOG(DEBUG, "MPW isn't supported");
801 mps = MLX5_MPW_DISABLED;
803 #ifdef HAVE_IBV_MLX5_MOD_SWP
804 if (attrs_out.comp_mask & MLX5DV_CONTEXT_MASK_SWP)
805 swp = attrs_out.sw_parsing_caps.sw_parsing_offloads;
806 DRV_LOG(DEBUG, "SWP support: %u", swp);
808 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
809 if (attrs_out.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) {
810 struct mlx5dv_striding_rq_caps mprq_caps =
811 attrs_out.striding_rq_caps;
813 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d",
814 mprq_caps.min_single_stride_log_num_of_bytes);
815 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d",
816 mprq_caps.max_single_stride_log_num_of_bytes);
817 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d",
818 mprq_caps.min_single_wqe_log_num_of_strides);
819 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d",
820 mprq_caps.max_single_wqe_log_num_of_strides);
821 DRV_LOG(DEBUG, "\tsupported_qpts: %d",
822 mprq_caps.supported_qpts);
823 DRV_LOG(DEBUG, "device supports Multi-Packet RQ");
825 mprq_min_stride_size_n =
826 mprq_caps.min_single_stride_log_num_of_bytes;
827 mprq_max_stride_size_n =
828 mprq_caps.max_single_stride_log_num_of_bytes;
829 mprq_min_stride_num_n =
830 mprq_caps.min_single_wqe_log_num_of_strides;
831 mprq_max_stride_num_n =
832 mprq_caps.max_single_wqe_log_num_of_strides;
835 if (RTE_CACHE_LINE_SIZE == 128 &&
836 !(attrs_out.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP))
840 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
841 if (attrs_out.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) {
842 tunnel_en = ((attrs_out.tunnel_offloads_caps &
843 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) &&
844 (attrs_out.tunnel_offloads_caps &
845 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE));
847 DRV_LOG(DEBUG, "tunnel offloading is %ssupported",
848 tunnel_en ? "" : "not ");
851 "tunnel offloading disabled due to old OFED/rdma-core version");
853 err = mlx5_glue->query_device_ex(attr_ctx, NULL, &device_attr);
855 DEBUG("ibv_query_device_ex() failed");
858 DRV_LOG(INFO, "%u port(s) detected",
859 device_attr.orig_attr.phys_port_cnt);
860 for (i = 0; i < device_attr.orig_attr.phys_port_cnt; i++) {
861 char name[RTE_ETH_NAME_MAX_LEN];
863 uint32_t port = i + 1; /* ports are indexed from one */
864 uint32_t test = (1 << i);
865 struct ibv_context *ctx = NULL;
866 struct ibv_port_attr port_attr;
867 struct ibv_pd *pd = NULL;
868 struct priv *priv = NULL;
869 struct rte_eth_dev *eth_dev = NULL;
870 struct ibv_device_attr_ex device_attr_ex;
871 struct ether_addr mac;
872 struct mlx5_dev_config config = {
873 .cqe_comp = cqe_comp,
875 .tunnel_en = tunnel_en,
879 .txq_inline = MLX5_ARG_UNSET,
880 .txqs_inline = MLX5_ARG_UNSET,
881 .inline_max_packet_sz = MLX5_ARG_UNSET,
885 .enabled = 0, /* Disabled by default. */
886 .stride_num_n = RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,
887 mprq_min_stride_num_n),
888 .max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN,
889 .min_rxqs_num = MLX5_MPRQ_MIN_RXQS,
893 len = snprintf(name, sizeof(name), PCI_PRI_FMT,
894 pci_dev->addr.domain, pci_dev->addr.bus,
895 pci_dev->addr.devid, pci_dev->addr.function);
896 if (device_attr.orig_attr.phys_port_cnt > 1)
897 snprintf(name + len, sizeof(name), " port %u", i);
898 mlx5_dev[idx].ports |= test;
899 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
900 eth_dev = rte_eth_dev_attach_secondary(name);
901 if (eth_dev == NULL) {
902 DRV_LOG(ERR, "can not attach rte ethdev");
907 eth_dev->device = &pci_dev->device;
908 eth_dev->dev_ops = &mlx5_dev_sec_ops;
909 err = mlx5_uar_init_secondary(eth_dev);
914 /* Receive command fd from primary process */
915 err = mlx5_socket_connect(eth_dev);
920 /* Remap UAR for Tx queues. */
921 err = mlx5_tx_uar_remap(eth_dev, err);
927 * Ethdev pointer is still required as input since
928 * the primary device is not accessible from the
931 eth_dev->rx_pkt_burst =
932 mlx5_select_rx_function(eth_dev);
933 eth_dev->tx_pkt_burst =
934 mlx5_select_tx_function(eth_dev);
937 DRV_LOG(DEBUG, "using port %u (%08" PRIx32 ")", port, test);
938 ctx = mlx5_glue->open_device(ibv_dev);
943 /* Check port status. */
944 err = mlx5_glue->query_port(ctx, port, &port_attr);
946 DRV_LOG(ERR, "port query failed: %s", strerror(err));
949 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
951 "port %d is not configured in Ethernet mode",
956 if (port_attr.state != IBV_PORT_ACTIVE)
957 DRV_LOG(DEBUG, "port %d is not active: \"%s\" (%d)",
959 mlx5_glue->port_state_str(port_attr.state),
961 /* Allocate protection domain. */
962 pd = mlx5_glue->alloc_pd(ctx);
964 DRV_LOG(ERR, "PD allocation failure");
968 mlx5_dev[idx].ports |= test;
969 /* from rte_ethdev.c */
970 priv = rte_zmalloc("ethdev private structure",
972 RTE_CACHE_LINE_SIZE);
974 DRV_LOG(ERR, "priv allocation failure");
979 strncpy(priv->ibdev_path, priv->ctx->device->ibdev_path,
980 sizeof(priv->ibdev_path));
981 priv->device_attr = device_attr;
984 priv->mtu = ETHER_MTU;
985 err = mlx5_args(&config, pci_dev->device.devargs);
987 DRV_LOG(ERR, "failed to process device arguments: %s",
992 err = mlx5_glue->query_device_ex(ctx, NULL, &device_attr_ex);
994 DRV_LOG(ERR, "ibv_query_device_ex() failed");
997 config.hw_csum = !!(device_attr_ex.device_cap_flags_ex &
998 IBV_DEVICE_RAW_IP_CSUM);
999 DRV_LOG(DEBUG, "checksum offloading is %ssupported",
1000 (config.hw_csum ? "" : "not "));
1001 #ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT
1002 config.flow_counter_en = !!(device_attr.max_counter_sets);
1003 mlx5_glue->describe_counter_set(ctx, 0, &cs_desc);
1005 "counter type = %d, num of cs = %ld, attributes = %d",
1006 cs_desc.counter_type, cs_desc.num_of_cs,
1007 cs_desc.attributes);
1009 config.ind_table_max_size =
1010 device_attr_ex.rss_caps.max_rwq_indirection_table_size;
1011 /* Remove this check once DPDK supports larger/variable
1012 * indirection tables. */
1013 if (config.ind_table_max_size >
1014 (unsigned int)ETH_RSS_RETA_SIZE_512)
1015 config.ind_table_max_size = ETH_RSS_RETA_SIZE_512;
1016 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u",
1017 config.ind_table_max_size);
1018 config.hw_vlan_strip = !!(device_attr_ex.raw_packet_caps &
1019 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
1020 DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
1021 (config.hw_vlan_strip ? "" : "not "));
1023 config.hw_fcs_strip = !!(device_attr_ex.raw_packet_caps &
1024 IBV_RAW_PACKET_CAP_SCATTER_FCS);
1025 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported",
1026 (config.hw_fcs_strip ? "" : "not "));
1028 #ifdef HAVE_IBV_WQ_FLAG_RX_END_PADDING
1029 config.hw_padding = !!device_attr_ex.rx_pad_end_addr_align;
1032 "hardware Rx end alignment padding is %ssupported",
1033 (config.hw_padding ? "" : "not "));
1035 config.tso = ((device_attr_ex.tso_caps.max_tso > 0) &&
1036 (device_attr_ex.tso_caps.supported_qpts &
1037 (1 << IBV_QPT_RAW_PACKET)));
1039 config.tso_max_payload_sz =
1040 device_attr_ex.tso_caps.max_tso;
1041 if (config.mps && !mps) {
1043 "multi-packet send not supported on this device"
1044 " (" MLX5_TXQ_MPW_EN ")");
1048 DRV_LOG(INFO, "%s MPS is %s",
1049 config.mps == MLX5_MPW_ENHANCED ? "enhanced " : "",
1050 config.mps != MLX5_MPW_DISABLED ? "enabled" :
1052 if (config.cqe_comp && !cqe_comp) {
1053 DRV_LOG(WARNING, "Rx CQE compression isn't supported");
1054 config.cqe_comp = 0;
1056 config.mprq.enabled = config.mprq.enabled && mprq;
1057 if (config.mprq.enabled) {
1058 if (config.mprq.stride_num_n > mprq_max_stride_num_n ||
1059 config.mprq.stride_num_n < mprq_min_stride_num_n) {
1060 config.mprq.stride_num_n =
1061 RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,
1062 mprq_min_stride_num_n);
1064 "the number of strides"
1065 " for Multi-Packet RQ is out of range,"
1066 " setting default value (%u)",
1067 1 << config.mprq.stride_num_n);
1069 config.mprq.min_stride_size_n = mprq_min_stride_size_n;
1070 config.mprq.max_stride_size_n = mprq_max_stride_size_n;
1072 eth_dev = rte_eth_dev_allocate(name);
1073 if (eth_dev == NULL) {
1074 DRV_LOG(ERR, "can not allocate rte ethdev");
1078 eth_dev->data->dev_private = priv;
1079 priv->dev_data = eth_dev->data;
1080 eth_dev->data->mac_addrs = priv->mac;
1081 eth_dev->device = &pci_dev->device;
1082 rte_eth_copy_pci_info(eth_dev, pci_dev);
1083 eth_dev->device->driver = &mlx5_driver.driver;
1084 err = mlx5_uar_init_primary(eth_dev);
1089 /* Configure the first MAC address by default. */
1090 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) {
1092 "port %u cannot get MAC address, is mlx5_en"
1093 " loaded? (errno: %s)",
1094 eth_dev->data->port_id, strerror(errno));
1099 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x",
1100 eth_dev->data->port_id,
1101 mac.addr_bytes[0], mac.addr_bytes[1],
1102 mac.addr_bytes[2], mac.addr_bytes[3],
1103 mac.addr_bytes[4], mac.addr_bytes[5]);
1106 char ifname[IF_NAMESIZE];
1108 if (mlx5_get_ifname(eth_dev, &ifname) == 0)
1109 DRV_LOG(DEBUG, "port %u ifname is \"%s\"",
1110 eth_dev->data->port_id, ifname);
1112 DRV_LOG(DEBUG, "port %u ifname is unknown",
1113 eth_dev->data->port_id);
1116 /* Get actual MTU if possible. */
1117 err = mlx5_get_mtu(eth_dev, &priv->mtu);
1122 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id,
1125 * Initialize burst functions to prevent crashes before link-up.
1127 eth_dev->rx_pkt_burst = removed_rx_burst;
1128 eth_dev->tx_pkt_burst = removed_tx_burst;
1129 eth_dev->dev_ops = &mlx5_dev_ops;
1130 /* Register MAC address. */
1131 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
1132 priv->nl_socket = -1;
1134 if (vf && config.vf_nl_en) {
1135 priv->nl_socket = mlx5_nl_init(RTMGRP_LINK);
1136 if (priv->nl_socket < 0)
1137 priv->nl_socket = -1;
1138 mlx5_nl_mac_addr_sync(eth_dev);
1140 TAILQ_INIT(&priv->flows);
1141 TAILQ_INIT(&priv->ctrl_flows);
1142 /* Hint libmlx5 to use PMD allocator for data plane resources */
1143 struct mlx5dv_ctx_allocators alctr = {
1144 .alloc = &mlx5_alloc_verbs_buf,
1145 .free = &mlx5_free_verbs_buf,
1148 mlx5_glue->dv_set_context_attr(ctx,
1149 MLX5DV_CTX_ATTR_BUF_ALLOCATORS,
1150 (void *)((uintptr_t)&alctr));
1151 /* Bring Ethernet device up. */
1152 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up",
1153 eth_dev->data->port_id);
1154 mlx5_set_link_up(eth_dev);
1156 * Even though the interrupt handler is not installed yet,
1157 * interrupts will still trigger on the asyn_fd from
1158 * Verbs context returned by ibv_open_device().
1160 mlx5_link_update(eth_dev, 0);
1161 /* Store device configuration on private structure. */
1162 priv->config = config;
1163 /* Create drop queue. */
1164 err = mlx5_flow_create_drop_queue(eth_dev);
1166 DRV_LOG(ERR, "port %u drop queue allocation failed: %s",
1167 eth_dev->data->port_id, strerror(rte_errno));
1171 /* Supported Verbs flow priority number detection. */
1172 if (verb_priorities == 0)
1173 verb_priorities = mlx5_get_max_verbs_prio(eth_dev);
1174 if (verb_priorities < MLX5_VERBS_FLOW_PRIO_8) {
1175 DRV_LOG(ERR, "port %u wrong Verbs flow priorities: %u",
1176 eth_dev->data->port_id, verb_priorities);
1179 priv->config.max_verbs_prio = verb_priorities;
1185 claim_zero(mlx5_glue->dealloc_pd(pd));
1187 claim_zero(mlx5_glue->close_device(ctx));
1188 if (eth_dev && rte_eal_process_type() == RTE_PROC_PRIMARY)
1189 rte_eth_dev_release_port(eth_dev);
1193 * XXX if something went wrong in the loop above, there is a resource
1194 * leak (ctx, pd, priv, dpdk ethdev) but we can do nothing about it as
1195 * long as the dpdk does not provide a way to deallocate a ethdev and a
1196 * way to enumerate the registered ethdevs to free the previous ones.
1198 /* no port found, complain */
1199 if (!mlx5_dev[idx].ports) {
1205 claim_zero(mlx5_glue->close_device(attr_ctx));
1207 mlx5_glue->free_device_list(list);
1215 static const struct rte_pci_id mlx5_pci_id_map[] = {
1217 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1218 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
1221 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1222 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
1225 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1226 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
1229 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1230 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
1233 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1234 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
1237 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1238 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
1241 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1242 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
1245 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1246 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
1253 static struct rte_pci_driver mlx5_driver = {
1255 .name = MLX5_DRIVER_NAME
1257 .id_table = mlx5_pci_id_map,
1258 .probe = mlx5_pci_probe,
1259 .drv_flags = RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV,
1262 #ifdef RTE_LIBRTE_MLX5_DLOPEN_DEPS
1265 * Suffix RTE_EAL_PMD_PATH with "-glue".
1267 * This function performs a sanity check on RTE_EAL_PMD_PATH before
1268 * suffixing its last component.
1271 * Output buffer, should be large enough otherwise NULL is returned.
1276 * Pointer to @p buf or @p NULL in case suffix cannot be appended.
1279 mlx5_glue_path(char *buf, size_t size)
1281 static const char *const bad[] = { "/", ".", "..", NULL };
1282 const char *path = RTE_EAL_PMD_PATH;
1283 size_t len = strlen(path);
1287 while (len && path[len - 1] == '/')
1289 for (off = len; off && path[off - 1] != '/'; --off)
1291 for (i = 0; bad[i]; ++i)
1292 if (!strncmp(path + off, bad[i], (int)(len - off)))
1294 i = snprintf(buf, size, "%.*s-glue", (int)len, path);
1295 if (i == -1 || (size_t)i >= size)
1300 "unable to append \"-glue\" to last component of"
1301 " RTE_EAL_PMD_PATH (\"" RTE_EAL_PMD_PATH "\"),"
1302 " please re-configure DPDK");
1307 * Initialization routine for run-time dependency on rdma-core.
1310 mlx5_glue_init(void)
1312 char glue_path[sizeof(RTE_EAL_PMD_PATH) - 1 + sizeof("-glue")];
1313 const char *path[] = {
1315 * A basic security check is necessary before trusting
1316 * MLX5_GLUE_PATH, which may override RTE_EAL_PMD_PATH.
1318 (geteuid() == getuid() && getegid() == getgid() ?
1319 getenv("MLX5_GLUE_PATH") : NULL),
1321 * When RTE_EAL_PMD_PATH is set, use its glue-suffixed
1322 * variant, otherwise let dlopen() look up libraries on its
1325 (*RTE_EAL_PMD_PATH ?
1326 mlx5_glue_path(glue_path, sizeof(glue_path)) : ""),
1329 void *handle = NULL;
1333 while (!handle && i != RTE_DIM(path)) {
1342 end = strpbrk(path[i], ":;");
1344 end = path[i] + strlen(path[i]);
1345 len = end - path[i];
1350 ret = snprintf(name, sizeof(name), "%.*s%s" MLX5_GLUE,
1352 (!len || *(end - 1) == '/') ? "" : "/");
1355 if (sizeof(name) != (size_t)ret + 1)
1357 DRV_LOG(DEBUG, "looking for rdma-core glue as \"%s\"",
1359 handle = dlopen(name, RTLD_LAZY);
1370 DRV_LOG(WARNING, "cannot load glue library: %s", dlmsg);
1373 sym = dlsym(handle, "mlx5_glue");
1374 if (!sym || !*sym) {
1378 DRV_LOG(ERR, "cannot resolve glue symbol: %s", dlmsg);
1387 "cannot initialize PMD due to missing run-time dependency on"
1388 " rdma-core libraries (libibverbs, libmlx5)");
1395 * Driver initialization routine.
1397 RTE_INIT(rte_mlx5_pmd_init);
1399 rte_mlx5_pmd_init(void)
1401 /* Build the static tables for Verbs conversion. */
1402 mlx5_set_ptype_table();
1403 mlx5_set_cksum_table();
1404 mlx5_set_swp_types_table();
1406 * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use
1407 * huge pages. Calling ibv_fork_init() during init allows
1408 * applications to use fork() safely for purposes other than
1409 * using this PMD, which is not supported in forked processes.
1411 setenv("RDMAV_HUGEPAGES_SAFE", "1", 1);
1412 /* Match the size of Rx completion entry to the size of a cacheline. */
1413 if (RTE_CACHE_LINE_SIZE == 128)
1414 setenv("MLX5_CQE_SIZE", "128", 0);
1415 #ifdef RTE_LIBRTE_MLX5_DLOPEN_DEPS
1416 if (mlx5_glue_init())
1421 /* Glue structure must not contain any NULL pointers. */
1425 for (i = 0; i != sizeof(*mlx5_glue) / sizeof(void *); ++i)
1426 assert(((const void *const *)mlx5_glue)[i]);
1429 if (strcmp(mlx5_glue->version, MLX5_GLUE_VERSION)) {
1431 "rdma-core glue \"%s\" mismatch: \"%s\" is required",
1432 mlx5_glue->version, MLX5_GLUE_VERSION);
1435 mlx5_glue->fork_init();
1436 rte_pci_register(&mlx5_driver);
1437 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
1438 mlx5_mr_mem_event_cb, NULL);
1441 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
1442 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
1443 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");
1445 /** Initialize driver log type. */
1446 RTE_INIT(vdev_netvsc_init_log)
1448 mlx5_logtype = rte_log_register("pmd.net.mlx5");
1449 if (mlx5_logtype >= 0)
1450 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE);