1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
13 #include <rte_malloc.h>
14 #include <ethdev_driver.h>
15 #include <ethdev_pci.h>
17 #include <rte_bus_pci.h>
18 #include <rte_common.h>
19 #include <rte_kvargs.h>
20 #include <rte_rwlock.h>
21 #include <rte_spinlock.h>
22 #include <rte_string_fns.h>
23 #include <rte_alarm.h>
24 #include <rte_cycles.h>
26 #include <mlx5_glue.h>
27 #include <mlx5_devx_cmds.h>
28 #include <mlx5_common.h>
29 #include <mlx5_common_os.h>
30 #include <mlx5_common_mp.h>
31 #include <mlx5_common_pci.h>
32 #include <mlx5_malloc.h>
34 #include "mlx5_defs.h"
36 #include "mlx5_utils.h"
37 #include "mlx5_rxtx.h"
40 #include "mlx5_autoconf.h"
42 #include "mlx5_flow.h"
43 #include "mlx5_flow_os.h"
44 #include "rte_pmd_mlx5.h"
46 /* Device parameter to enable RX completion queue compression. */
47 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
49 /* Device parameter to enable padding Rx packet to cacheline size. */
50 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
52 /* Device parameter to enable Multi-Packet Rx queue. */
53 #define MLX5_RX_MPRQ_EN "mprq_en"
55 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
56 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
58 /* Device parameter to configure log 2 of the stride size for MPRQ. */
59 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
61 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
62 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
64 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
65 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
67 /* Device parameter to configure inline send. Deprecated, ignored.*/
68 #define MLX5_TXQ_INLINE "txq_inline"
70 /* Device parameter to limit packet size to inline with ordinary SEND. */
71 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
73 /* Device parameter to configure minimal data size to inline. */
74 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
76 /* Device parameter to limit packet size to inline with Enhanced MPW. */
77 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
80 * Device parameter to configure the number of TX queues threshold for
81 * enabling inline send.
83 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
86 * Device parameter to configure the number of TX queues threshold for
87 * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
89 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
91 /* Device parameter to enable multi-packet send WQEs. */
92 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
95 * Device parameter to force doorbell register mapping
96 * to non-cahed region eliminating the extra write memory barrier.
98 #define MLX5_TX_DB_NC "tx_db_nc"
101 * Device parameter to include 2 dsegs in the title WQEBB.
102 * Deprecated, ignored.
104 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
107 * Device parameter to limit the size of inlining packet.
108 * Deprecated, ignored.
110 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
113 * Device parameter to enable Tx scheduling on timestamps
114 * and specify the packet pacing granularity in nanoseconds.
116 #define MLX5_TX_PP "tx_pp"
119 * Device parameter to specify skew in nanoseconds on Tx datapath,
120 * it represents the time between SQ start WQE processing and
121 * appearing actual packet data on the wire.
123 #define MLX5_TX_SKEW "tx_skew"
126 * Device parameter to enable hardware Tx vector.
127 * Deprecated, ignored (no vectorized Tx routines anymore).
129 #define MLX5_TX_VEC_EN "tx_vec_en"
131 /* Device parameter to enable hardware Rx vector. */
132 #define MLX5_RX_VEC_EN "rx_vec_en"
134 /* Allow L3 VXLAN flow creation. */
135 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
137 /* Activate DV E-Switch flow steering. */
138 #define MLX5_DV_ESW_EN "dv_esw_en"
140 /* Activate DV flow steering. */
141 #define MLX5_DV_FLOW_EN "dv_flow_en"
143 /* Enable extensive flow metadata support. */
144 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
146 /* Device parameter to let the user manage the lacp traffic of bonded device */
147 #define MLX5_LACP_BY_USER "lacp_by_user"
149 /* Activate Netlink support in VF mode. */
150 #define MLX5_VF_NL_EN "vf_nl_en"
152 /* Enable extending memsegs when creating a MR. */
153 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
155 /* Select port representors to instantiate. */
156 #define MLX5_REPRESENTOR "representor"
158 /* Device parameter to configure the maximum number of dump files per queue. */
159 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
161 /* Configure timeout of LRO session (in microseconds). */
162 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
165 * Device parameter to configure the total data buffer size for a single
166 * hairpin queue (logarithm value).
168 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
170 /* Flow memory reclaim mode. */
171 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
173 /* The default memory allocator used in PMD. */
174 #define MLX5_SYS_MEM_EN "sys_mem_en"
175 /* Decap will be used or not. */
176 #define MLX5_DECAP_EN "decap_en"
178 /* Shared memory between primary and secondary processes. */
179 struct mlx5_shared_data *mlx5_shared_data;
181 /** Driver-specific log messages type. */
184 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
185 LIST_HEAD_INITIALIZER();
186 static pthread_mutex_t mlx5_dev_ctx_list_mutex;
187 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
188 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
189 [MLX5_IPOOL_DECAP_ENCAP] = {
190 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
196 .malloc = mlx5_malloc,
198 .type = "mlx5_encap_decap_ipool",
200 [MLX5_IPOOL_PUSH_VLAN] = {
201 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
207 .malloc = mlx5_malloc,
209 .type = "mlx5_push_vlan_ipool",
212 .size = sizeof(struct mlx5_flow_dv_tag_resource),
218 .malloc = mlx5_malloc,
220 .type = "mlx5_tag_ipool",
222 [MLX5_IPOOL_PORT_ID] = {
223 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
229 .malloc = mlx5_malloc,
231 .type = "mlx5_port_id_ipool",
233 [MLX5_IPOOL_JUMP] = {
234 .size = sizeof(struct mlx5_flow_tbl_data_entry),
240 .malloc = mlx5_malloc,
242 .type = "mlx5_jump_ipool",
244 [MLX5_IPOOL_SAMPLE] = {
245 .size = sizeof(struct mlx5_flow_dv_sample_resource),
251 .malloc = mlx5_malloc,
253 .type = "mlx5_sample_ipool",
255 [MLX5_IPOOL_DEST_ARRAY] = {
256 .size = sizeof(struct mlx5_flow_dv_dest_array_resource),
262 .malloc = mlx5_malloc,
264 .type = "mlx5_dest_array_ipool",
266 [MLX5_IPOOL_TUNNEL_ID] = {
267 .size = sizeof(struct mlx5_flow_tunnel),
268 .trunk_size = MLX5_MAX_TUNNELS,
271 .type = "mlx5_tunnel_offload",
273 [MLX5_IPOOL_TNL_TBL_ID] = {
276 .type = "mlx5_flow_tnl_tbl_ipool",
281 * The ipool index should grow continually from small to big,
282 * for meter idx, so not set grow_trunk to avoid meter index
283 * not jump continually.
285 .size = sizeof(struct mlx5_legacy_flow_meter),
289 .malloc = mlx5_malloc,
291 .type = "mlx5_meter_ipool",
294 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
300 .malloc = mlx5_malloc,
302 .type = "mlx5_mcp_ipool",
304 [MLX5_IPOOL_HRXQ] = {
305 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
311 .malloc = mlx5_malloc,
313 .type = "mlx5_hrxq_ipool",
315 [MLX5_IPOOL_MLX5_FLOW] = {
317 * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
318 * It set in run time according to PCI function configuration.
326 .malloc = mlx5_malloc,
328 .type = "mlx5_flow_handle_ipool",
330 [MLX5_IPOOL_RTE_FLOW] = {
331 .size = sizeof(struct rte_flow),
335 .malloc = mlx5_malloc,
337 .type = "rte_flow_ipool",
339 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID] = {
342 .type = "mlx5_flow_rss_id_ipool",
344 [MLX5_IPOOL_RSS_SHARED_ACTIONS] = {
345 .size = sizeof(struct mlx5_shared_action_rss),
351 .malloc = mlx5_malloc,
353 .type = "mlx5_shared_action_rss",
355 [MLX5_IPOOL_MTR_POLICY] = {
357 * The ipool index should grow continually from small to big,
358 * for policy idx, so not set grow_trunk to avoid policy index
359 * not jump continually.
361 .size = sizeof(struct mlx5_flow_meter_sub_policy),
365 .malloc = mlx5_malloc,
367 .type = "mlx5_meter_policy_ipool",
372 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
373 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
375 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
378 * Decide whether representor ID is a HPF(host PF) port on BF2.
381 * Pointer to Ethernet device structure.
384 * Non-zero if HPF, otherwise 0.
387 mlx5_is_hpf(struct rte_eth_dev *dev)
389 struct mlx5_priv *priv = dev->data->dev_private;
390 uint16_t repr = MLX5_REPRESENTOR_REPR(priv->representor_id);
391 int type = MLX5_REPRESENTOR_TYPE(priv->representor_id);
393 return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_VF &&
394 MLX5_REPRESENTOR_REPR(-1) == repr;
398 * Initialize the ASO aging management structure.
401 * Pointer to mlx5_dev_ctx_shared object to free
404 * 0 on success, a negative errno value otherwise and rte_errno is set.
407 mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh)
413 sh->aso_age_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->aso_age_mng),
414 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
415 if (!sh->aso_age_mng) {
416 DRV_LOG(ERR, "aso_age_mng allocation was failed.");
420 err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_FLOW_HIT);
422 mlx5_free(sh->aso_age_mng);
425 rte_spinlock_init(&sh->aso_age_mng->resize_sl);
426 rte_spinlock_init(&sh->aso_age_mng->free_sl);
427 LIST_INIT(&sh->aso_age_mng->free);
432 * Close and release all the resources of the ASO aging management structure.
435 * Pointer to mlx5_dev_ctx_shared object to free.
438 mlx5_flow_aso_age_mng_close(struct mlx5_dev_ctx_shared *sh)
442 mlx5_aso_flow_hit_queue_poll_stop(sh);
443 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_FLOW_HIT);
444 if (sh->aso_age_mng->pools) {
445 struct mlx5_aso_age_pool *pool;
447 for (i = 0; i < sh->aso_age_mng->next; ++i) {
448 pool = sh->aso_age_mng->pools[i];
449 claim_zero(mlx5_devx_cmd_destroy
450 (pool->flow_hit_aso_obj));
451 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j)
452 if (pool->actions[j].dr_action)
454 (mlx5_flow_os_destroy_flow_action
455 (pool->actions[j].dr_action));
458 mlx5_free(sh->aso_age_mng->pools);
460 mlx5_free(sh->aso_age_mng);
464 * Initialize the shared aging list information per port.
467 * Pointer to mlx5_dev_ctx_shared object.
470 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
473 struct mlx5_age_info *age_info;
475 for (i = 0; i < sh->max_port; i++) {
476 age_info = &sh->port[i].age_info;
478 TAILQ_INIT(&age_info->aged_counters);
479 LIST_INIT(&age_info->aged_aso);
480 rte_spinlock_init(&age_info->aged_sl);
481 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
486 * Initialize the counters management structure.
489 * Pointer to mlx5_dev_ctx_shared object to free
492 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
496 memset(&sh->cmng, 0, sizeof(sh->cmng));
497 TAILQ_INIT(&sh->cmng.flow_counters);
498 sh->cmng.min_id = MLX5_CNT_BATCH_OFFSET;
499 sh->cmng.max_id = -1;
500 sh->cmng.last_pool_idx = POOL_IDX_INVALID;
501 rte_spinlock_init(&sh->cmng.pool_update_sl);
502 for (i = 0; i < MLX5_COUNTER_TYPE_MAX; i++) {
503 TAILQ_INIT(&sh->cmng.counters[i]);
504 rte_spinlock_init(&sh->cmng.csl[i]);
509 * Destroy all the resources allocated for a counter memory management.
512 * Pointer to the memory management structure.
515 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
517 uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
519 LIST_REMOVE(mng, next);
520 claim_zero(mlx5_devx_cmd_destroy(mng->dm));
521 claim_zero(mlx5_os_umem_dereg(mng->umem));
526 * Close and release all the resources of the counters management.
529 * Pointer to mlx5_dev_ctx_shared object to free.
532 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
534 struct mlx5_counter_stats_mem_mng *mng;
540 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
541 if (rte_errno != EINPROGRESS)
546 if (sh->cmng.pools) {
547 struct mlx5_flow_counter_pool *pool;
548 uint16_t n_valid = sh->cmng.n_valid;
549 bool fallback = sh->cmng.counter_fallback;
551 for (i = 0; i < n_valid; ++i) {
552 pool = sh->cmng.pools[i];
553 if (!fallback && pool->min_dcs)
554 claim_zero(mlx5_devx_cmd_destroy
556 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
557 struct mlx5_flow_counter *cnt =
558 MLX5_POOL_GET_CNT(pool, j);
562 (mlx5_flow_os_destroy_flow_action
564 if (fallback && MLX5_POOL_GET_CNT
565 (pool, j)->dcs_when_free)
566 claim_zero(mlx5_devx_cmd_destroy
567 (cnt->dcs_when_free));
571 mlx5_free(sh->cmng.pools);
573 mng = LIST_FIRST(&sh->cmng.mem_mngs);
575 mlx5_flow_destroy_counter_stat_mem_mng(mng);
576 mng = LIST_FIRST(&sh->cmng.mem_mngs);
578 memset(&sh->cmng, 0, sizeof(sh->cmng));
582 * Initialize the aso flow meters management structure.
585 * Pointer to mlx5_dev_ctx_shared object to free
588 mlx5_aso_flow_mtrs_mng_init(struct mlx5_dev_ctx_shared *sh)
591 sh->mtrmng = mlx5_malloc(MLX5_MEM_ZERO,
593 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
596 "meter management allocation was failed.");
600 if (sh->meter_aso_en) {
601 rte_spinlock_init(&sh->mtrmng->pools_mng.mtrsl);
602 LIST_INIT(&sh->mtrmng->pools_mng.meters);
603 sh->mtrmng->policy_idx_tbl =
604 mlx5_l3t_create(MLX5_L3T_TYPE_DWORD);
606 sh->mtrmng->def_policy_id = MLX5_INVALID_POLICY_ID;
612 * Close and release all the resources of
613 * the ASO flow meter management structure.
616 * Pointer to mlx5_dev_ctx_shared object to free.
619 mlx5_aso_flow_mtrs_mng_close(struct mlx5_dev_ctx_shared *sh)
621 struct mlx5_aso_mtr_pool *mtr_pool;
622 struct mlx5_flow_mtr_mng *mtrmng = sh->mtrmng;
624 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
625 struct mlx5_aso_mtr *aso_mtr;
627 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
629 if (sh->meter_aso_en) {
630 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_POLICER);
631 idx = mtrmng->pools_mng.n_valid;
633 mtr_pool = mtrmng->pools_mng.pools[idx];
634 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
635 for (i = 0; i < MLX5_ASO_MTRS_PER_POOL; i++) {
636 aso_mtr = &mtr_pool->mtrs[i];
637 if (aso_mtr->fm.meter_action)
639 (mlx5_glue->destroy_flow_action
640 (aso_mtr->fm.meter_action));
642 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
643 claim_zero(mlx5_devx_cmd_destroy
644 (mtr_pool->devx_obj));
645 mtrmng->pools_mng.n_valid--;
648 mlx5_free(sh->mtrmng->pools_mng.pools);
650 mlx5_free(sh->mtrmng);
654 /* Send FLOW_AGED event if needed. */
656 mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh)
658 struct mlx5_age_info *age_info;
661 for (i = 0; i < sh->max_port; i++) {
662 age_info = &sh->port[i].age_info;
663 if (!MLX5_AGE_GET(age_info, MLX5_AGE_EVENT_NEW))
665 MLX5_AGE_UNSET(age_info, MLX5_AGE_EVENT_NEW);
666 if (MLX5_AGE_GET(age_info, MLX5_AGE_TRIGGER)) {
667 MLX5_AGE_UNSET(age_info, MLX5_AGE_TRIGGER);
668 rte_eth_dev_callback_process
669 (&rte_eth_devices[sh->port[i].devx_ih_port_id],
670 RTE_ETH_EVENT_FLOW_AGED, NULL);
676 * Initialize the flow resources' indexed mempool.
679 * Pointer to mlx5_dev_ctx_shared object.
681 * Pointer to user dev config.
684 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
685 const struct mlx5_dev_config *config)
688 struct mlx5_indexed_pool_config cfg;
690 for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
691 cfg = mlx5_ipool_cfg[i];
696 * Set MLX5_IPOOL_MLX5_FLOW ipool size
697 * according to PCI function flow configuration.
699 case MLX5_IPOOL_MLX5_FLOW:
700 cfg.size = config->dv_flow_en ?
701 sizeof(struct mlx5_flow_handle) :
702 MLX5_FLOW_HANDLE_VERBS_SIZE;
705 if (config->reclaim_mode)
706 cfg.release_mem_en = 1;
707 sh->ipool[i] = mlx5_ipool_create(&cfg);
712 * Release the flow resources' indexed mempool.
715 * Pointer to mlx5_dev_ctx_shared object.
718 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
722 for (i = 0; i < MLX5_IPOOL_MAX; ++i)
723 mlx5_ipool_destroy(sh->ipool[i]);
727 * Check if dynamic flex parser for eCPRI already exists.
730 * Pointer to Ethernet device structure.
733 * true on exists, false on not.
736 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
738 struct mlx5_priv *priv = dev->data->dev_private;
739 struct mlx5_flex_parser_profiles *prf =
740 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
746 * Allocation of a flex parser for eCPRI. Once created, this parser related
747 * resources will be held until the device is closed.
750 * Pointer to Ethernet device structure.
753 * 0 on success, a negative errno value otherwise and rte_errno is set.
756 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
758 struct mlx5_priv *priv = dev->data->dev_private;
759 struct mlx5_flex_parser_profiles *prf =
760 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
761 struct mlx5_devx_graph_node_attr node = {
762 .modify_field_select = 0,
767 if (!priv->config.hca_attr.parse_graph_flex_node) {
768 DRV_LOG(ERR, "Dynamic flex parser is not supported "
769 "for device %s.", priv->dev_data->name);
772 node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED;
773 /* 8 bytes now: 4B common header + 4B message body header. */
774 node.header_length_base_value = 0x8;
775 /* After MAC layer: Ether / VLAN. */
776 node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC;
777 /* Type of compared condition should be 0xAEFE in the L2 layer. */
778 node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI;
779 /* Sample #0: type in common header. */
780 node.sample[0].flow_match_sample_en = 1;
782 node.sample[0].flow_match_sample_offset_mode = 0x0;
783 /* Only the 2nd byte will be used. */
784 node.sample[0].flow_match_sample_field_base_offset = 0x0;
785 /* Sample #1: message payload. */
786 node.sample[1].flow_match_sample_en = 1;
788 node.sample[1].flow_match_sample_offset_mode = 0x0;
790 * Only the first two bytes will be used right now, and its offset will
791 * start after the common header that with the length of a DW(u32).
793 node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);
794 prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->ctx, &node);
796 DRV_LOG(ERR, "Failed to create flex parser node object.");
797 return (rte_errno == 0) ? -ENODEV : -rte_errno;
800 ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num);
802 DRV_LOG(ERR, "Failed to query sample IDs.");
803 return (rte_errno == 0) ? -ENODEV : -rte_errno;
805 prf->offset[0] = 0x0;
806 prf->offset[1] = sizeof(uint32_t);
807 prf->ids[0] = ids[0];
808 prf->ids[1] = ids[1];
813 * Destroy the flex parser node, including the parser itself, input / output
814 * arcs and DW samples. Resources could be reused then.
817 * Pointer to Ethernet device structure.
820 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
822 struct mlx5_priv *priv = dev->data->dev_private;
823 struct mlx5_flex_parser_profiles *prf =
824 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
827 mlx5_devx_cmd_destroy(prf->obj);
832 * Allocate Rx and Tx UARs in robust fashion.
833 * This routine handles the following UAR allocation issues:
835 * - tries to allocate the UAR with the most appropriate memory
836 * mapping type from the ones supported by the host
838 * - tries to allocate the UAR with non-NULL base address
839 * OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as
840 * UAR base address if UAR was not the first object in the UAR page.
841 * It caused the PMD failure and we should try to get another UAR
842 * till we get the first one with non-NULL base address returned.
845 mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh,
846 const struct mlx5_dev_config *config)
848 uint32_t uar_mapping, retry;
852 for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
853 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
854 /* Control the mapping type according to the settings. */
855 uar_mapping = (config->dbnc == MLX5_TXDB_NCACHED) ?
856 MLX5DV_UAR_ALLOC_TYPE_NC :
857 MLX5DV_UAR_ALLOC_TYPE_BF;
859 RTE_SET_USED(config);
861 * It seems we have no way to control the memory mapping type
862 * for the UAR, the default "Write-Combining" type is supposed.
863 * The UAR initialization on queue creation queries the
864 * actual mapping type done by Verbs/kernel and setups the
865 * PMD datapath accordingly.
869 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->ctx, uar_mapping);
870 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
872 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
873 if (config->dbnc == MLX5_TXDB_CACHED ||
874 config->dbnc == MLX5_TXDB_HEURISTIC)
875 DRV_LOG(WARNING, "Devarg tx_db_nc setting "
876 "is not supported by DevX");
878 * In some environments like virtual machine
879 * the Write Combining mapped might be not supported
880 * and UAR allocation fails. We try "Non-Cached"
881 * mapping for the case. The tx_burst routines take
882 * the UAR mapping type into account on UAR setup
885 DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (BF)");
886 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
887 sh->tx_uar = mlx5_glue->devx_alloc_uar
888 (sh->ctx, uar_mapping);
889 } else if (!sh->tx_uar &&
890 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_NC) {
891 if (config->dbnc == MLX5_TXDB_NCACHED)
892 DRV_LOG(WARNING, "Devarg tx_db_nc settings "
893 "is not supported by DevX");
895 * If Verbs/kernel does not support "Non-Cached"
896 * try the "Write-Combining".
898 DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (NC)");
899 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_BF;
900 sh->tx_uar = mlx5_glue->devx_alloc_uar
901 (sh->ctx, uar_mapping);
905 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (BF/NC)");
909 base_addr = mlx5_os_get_devx_uar_base_addr(sh->tx_uar);
913 * The UARs are allocated by rdma_core within the
914 * IB device context, on context closure all UARs
915 * will be freed, should be no memory/object leakage.
917 DRV_LOG(DEBUG, "Retrying to allocate Tx DevX UAR");
920 /* Check whether we finally succeeded with valid UAR allocation. */
922 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (NULL base)");
926 for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
928 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
929 (sh->ctx, uar_mapping);
930 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
931 if (!sh->devx_rx_uar &&
932 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
934 * Rx UAR is used to control interrupts only,
935 * should be no datapath noticeable impact,
936 * can try "Non-Cached" mapping safely.
938 DRV_LOG(DEBUG, "Failed to allocate Rx DevX UAR (BF)");
939 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
940 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
941 (sh->ctx, uar_mapping);
944 if (!sh->devx_rx_uar) {
945 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (BF/NC)");
949 base_addr = mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar);
953 * The UARs are allocated by rdma_core within the
954 * IB device context, on context closure all UARs
955 * will be freed, should be no memory/object leakage.
957 DRV_LOG(DEBUG, "Retrying to allocate Rx DevX UAR");
958 sh->devx_rx_uar = NULL;
960 /* Check whether we finally succeeded with valid UAR allocation. */
961 if (!sh->devx_rx_uar) {
962 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (NULL base)");
970 * Allocate shared device context. If there is multiport device the
971 * master and representors will share this context, if there is single
972 * port dedicated device, the context will be used by only given
973 * port due to unification.
975 * Routine first searches the context for the specified device name,
976 * if found the shared context assumed and reference counter is incremented.
977 * If no context found the new one is created and initialized with specified
978 * device context and parameters.
981 * Pointer to the device attributes (name, port, etc).
983 * Pointer to device configuration structure.
986 * Pointer to mlx5_dev_ctx_shared object on success,
987 * otherwise NULL and rte_errno is set.
989 struct mlx5_dev_ctx_shared *
990 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
991 const struct mlx5_dev_config *config)
993 struct mlx5_dev_ctx_shared *sh;
996 struct mlx5_devx_tis_attr tis_attr = { 0 };
999 /* Secondary process should not create the shared context. */
1000 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1001 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1002 /* Search for IB context by device name. */
1003 LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
1004 if (!strcmp(sh->ibdev_name,
1005 mlx5_os_get_dev_device_name(spawn->phys_dev))) {
1010 /* No device found, we have to create new shared context. */
1011 MLX5_ASSERT(spawn->max_port);
1012 sh = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
1013 sizeof(struct mlx5_dev_ctx_shared) +
1015 sizeof(struct mlx5_dev_shared_port),
1016 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
1018 DRV_LOG(ERR, "shared context allocation failure");
1022 if (spawn->bond_info)
1023 sh->bond = *spawn->bond_info;
1024 err = mlx5_os_open_device(spawn, config, sh);
1027 err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
1029 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
1033 sh->max_port = spawn->max_port;
1034 strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
1035 sizeof(sh->ibdev_name) - 1);
1036 strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
1037 sizeof(sh->ibdev_path) - 1);
1039 * Setting port_id to max unallowed value means
1040 * there is no interrupt subhandler installed for
1041 * the given port index i.
1043 for (i = 0; i < sh->max_port; i++) {
1044 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
1045 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
1047 sh->pd = mlx5_os_alloc_pd(sh->ctx);
1048 if (sh->pd == NULL) {
1049 DRV_LOG(ERR, "PD allocation failure");
1054 err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
1056 DRV_LOG(ERR, "Fail to extract pdn from PD");
1059 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
1061 DRV_LOG(ERR, "TD allocation failure");
1065 tis_attr.transport_domain = sh->td->id;
1066 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
1068 DRV_LOG(ERR, "TIS allocation failure");
1072 err = mlx5_alloc_rxtx_uars(sh, config);
1075 MLX5_ASSERT(sh->tx_uar);
1076 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->tx_uar));
1078 MLX5_ASSERT(sh->devx_rx_uar);
1079 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar));
1082 /* Initialize UAR access locks for 32bit implementations. */
1083 rte_spinlock_init(&sh->uar_lock_cq);
1084 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
1085 rte_spinlock_init(&sh->uar_lock[i]);
1088 * Once the device is added to the list of memory event
1089 * callback, its global MR cache table cannot be expanded
1090 * on the fly because of deadlock. If it overflows, lookup
1091 * should be done by searching MR list linearly, which is slow.
1093 * At this point the device is not added to the memory
1094 * event list yet, context is just being created.
1096 err = mlx5_mr_btree_init(&sh->share_cache.cache,
1097 MLX5_MR_BTREE_CACHE_N * 2,
1098 spawn->pci_dev->device.numa_node);
1103 mlx5_os_set_reg_mr_cb(&sh->share_cache.reg_mr_cb,
1104 &sh->share_cache.dereg_mr_cb);
1105 mlx5_os_dev_shared_handler_install(sh);
1106 sh->cnt_id_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_DWORD);
1107 if (!sh->cnt_id_tbl) {
1111 if (LIST_EMPTY(&mlx5_dev_ctx_list)) {
1112 err = mlx5_flow_os_init_workspace_once();
1116 mlx5_flow_aging_init(sh);
1117 mlx5_flow_counters_mng_init(sh);
1118 mlx5_flow_ipool_create(sh, config);
1119 /* Add device to memory callback list. */
1120 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1121 LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
1123 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1124 /* Add context to the global device list. */
1125 LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
1126 rte_spinlock_init(&sh->geneve_tlv_opt_sl);
1128 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1131 pthread_mutex_destroy(&sh->txpp.mutex);
1132 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1135 mlx5_l3t_destroy(sh->cnt_id_tbl);
1137 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1139 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1140 if (sh->devx_rx_uar)
1141 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1143 mlx5_glue->devx_free_uar(sh->tx_uar);
1145 claim_zero(mlx5_os_dealloc_pd(sh->pd));
1147 claim_zero(mlx5_glue->close_device(sh->ctx));
1149 MLX5_ASSERT(err > 0);
1155 * Free shared IB device context. Decrement counter and if zero free
1156 * all allocated resources and close handles.
1159 * Pointer to mlx5_dev_ctx_shared object to free
1162 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
1164 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1165 #ifdef RTE_LIBRTE_MLX5_DEBUG
1166 /* Check the object presence in the list. */
1167 struct mlx5_dev_ctx_shared *lctx;
1169 LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
1174 DRV_LOG(ERR, "Freeing non-existing shared IB context");
1179 MLX5_ASSERT(sh->refcnt);
1180 /* Secondary process should not free the shared context. */
1181 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1184 /* Remove from memory callback device list. */
1185 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1186 LIST_REMOVE(sh, mem_event_cb);
1187 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1188 /* Release created Memory Regions. */
1189 mlx5_mr_release_cache(&sh->share_cache);
1190 /* Remove context from the global device list. */
1191 LIST_REMOVE(sh, next);
1192 /* Release flow workspaces objects on the last device. */
1193 if (LIST_EMPTY(&mlx5_dev_ctx_list))
1194 mlx5_flow_os_release_workspace();
1195 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1197 * Ensure there is no async event handler installed.
1198 * Only primary process handles async device events.
1200 mlx5_flow_counters_mng_close(sh);
1201 if (sh->aso_age_mng) {
1202 mlx5_flow_aso_age_mng_close(sh);
1203 sh->aso_age_mng = NULL;
1206 mlx5_aso_flow_mtrs_mng_close(sh);
1207 mlx5_flow_ipool_destroy(sh);
1208 mlx5_os_dev_shared_handler_uninstall(sh);
1209 if (sh->cnt_id_tbl) {
1210 mlx5_l3t_destroy(sh->cnt_id_tbl);
1211 sh->cnt_id_tbl = NULL;
1214 mlx5_glue->devx_free_uar(sh->tx_uar);
1218 claim_zero(mlx5_os_dealloc_pd(sh->pd));
1220 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1222 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1223 if (sh->devx_rx_uar)
1224 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1226 claim_zero(mlx5_glue->close_device(sh->ctx));
1227 MLX5_ASSERT(sh->geneve_tlv_option_resource == NULL);
1228 pthread_mutex_destroy(&sh->txpp.mutex);
1232 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1236 * Destroy table hash list.
1239 * Pointer to the private device data structure.
1242 mlx5_free_table_hash_list(struct mlx5_priv *priv)
1244 struct mlx5_dev_ctx_shared *sh = priv->sh;
1248 mlx5_hlist_destroy(sh->flow_tbls);
1252 * Initialize flow table hash list and create the root tables entry
1256 * Pointer to the private device data structure.
1259 * Zero on success, positive error code otherwise.
1262 mlx5_alloc_table_hash_list(struct mlx5_priv *priv __rte_unused)
1265 /* Tables are only used in DV and DR modes. */
1266 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
1267 struct mlx5_dev_ctx_shared *sh = priv->sh;
1268 char s[MLX5_HLIST_NAMESIZE];
1271 snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1272 sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE,
1273 0, 0, flow_dv_tbl_create_cb,
1274 flow_dv_tbl_match_cb,
1275 flow_dv_tbl_remove_cb);
1276 if (!sh->flow_tbls) {
1277 DRV_LOG(ERR, "flow tables with hash creation failed.");
1281 sh->flow_tbls->ctx = sh;
1282 #ifndef HAVE_MLX5DV_DR
1283 struct rte_flow_error error;
1284 struct rte_eth_dev *dev = &rte_eth_devices[priv->dev_data->port_id];
1287 * In case we have not DR support, the zero tables should be created
1288 * because DV expect to see them even if they cannot be created by
1291 if (!flow_dv_tbl_resource_get(dev, 0, 0, 0, 0,
1292 NULL, 0, 1, 0, &error) ||
1293 !flow_dv_tbl_resource_get(dev, 0, 1, 0, 0,
1294 NULL, 0, 1, 0, &error) ||
1295 !flow_dv_tbl_resource_get(dev, 0, 0, 1, 0,
1296 NULL, 0, 1, 0, &error)) {
1302 mlx5_free_table_hash_list(priv);
1303 #endif /* HAVE_MLX5DV_DR */
1309 * Retrieve integer value from environment variable.
1312 * Environment variable name.
1315 * Integer value, 0 if the variable is not set.
1318 mlx5_getenv_int(const char *name)
1320 const char *val = getenv(name);
1328 * DPDK callback to add udp tunnel port
1331 * A pointer to eth_dev
1332 * @param[in] udp_tunnel
1333 * A pointer to udp tunnel
1336 * 0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1339 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1340 struct rte_eth_udp_tunnel *udp_tunnel)
1342 MLX5_ASSERT(udp_tunnel != NULL);
1343 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1344 udp_tunnel->udp_port == 4789)
1346 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1347 udp_tunnel->udp_port == 4790)
1353 * Initialize process private data structure.
1356 * Pointer to Ethernet device structure.
1359 * 0 on success, a negative errno value otherwise and rte_errno is set.
1362 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1364 struct mlx5_priv *priv = dev->data->dev_private;
1365 struct mlx5_proc_priv *ppriv;
1369 * UAR register table follows the process private structure. BlueFlame
1370 * registers for Tx queues are stored in the table.
1373 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1374 ppriv = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, ppriv_size,
1375 RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1380 ppriv->uar_table_sz = priv->txqs_n;
1381 dev->process_private = ppriv;
1386 * Un-initialize process private data structure.
1389 * Pointer to Ethernet device structure.
1392 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1394 if (!dev->process_private)
1396 mlx5_free(dev->process_private);
1397 dev->process_private = NULL;
1401 * DPDK callback to close the device.
1403 * Destroy all queues and objects, free memory.
1406 * Pointer to Ethernet device structure.
1409 mlx5_dev_close(struct rte_eth_dev *dev)
1411 struct mlx5_priv *priv = dev->data->dev_private;
1415 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1416 /* Check if process_private released. */
1417 if (!dev->process_private)
1419 mlx5_tx_uar_uninit_secondary(dev);
1420 mlx5_proc_priv_uninit(dev);
1421 rte_eth_dev_release_port(dev);
1426 DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1428 ((priv->sh->ctx != NULL) ?
1429 mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
1431 * If default mreg copy action is removed at the stop stage,
1432 * the search will return none and nothing will be done anymore.
1434 mlx5_flow_stop_default(dev);
1435 mlx5_traffic_disable(dev);
1437 * If all the flows are already flushed in the device stop stage,
1438 * then this will return directly without any action.
1440 mlx5_flow_list_flush(dev, &priv->flows, true);
1441 mlx5_action_handle_flush(dev);
1442 mlx5_flow_meter_flush(dev, NULL);
1443 /* Prevent crashes when queues are still in use. */
1444 dev->rx_pkt_burst = removed_rx_burst;
1445 dev->tx_pkt_burst = removed_tx_burst;
1447 /* Disable datapath on secondary process. */
1448 mlx5_mp_os_req_stop_rxtx(dev);
1449 /* Free the eCPRI flex parser resource. */
1450 mlx5_flex_parser_ecpri_release(dev);
1451 if (priv->rxqs != NULL) {
1452 /* XXX race condition if mlx5_rx_burst() is still running. */
1453 rte_delay_us_sleep(1000);
1454 for (i = 0; (i != priv->rxqs_n); ++i)
1455 mlx5_rxq_release(dev, i);
1459 if (priv->txqs != NULL) {
1460 /* XXX race condition if mlx5_tx_burst() is still running. */
1461 rte_delay_us_sleep(1000);
1462 for (i = 0; (i != priv->txqs_n); ++i)
1463 mlx5_txq_release(dev, i);
1467 mlx5_proc_priv_uninit(dev);
1468 if (priv->q_counters) {
1469 mlx5_devx_cmd_destroy(priv->q_counters);
1470 priv->q_counters = NULL;
1472 if (priv->drop_queue.hrxq)
1473 mlx5_drop_action_destroy(dev);
1474 if (priv->mreg_cp_tbl)
1475 mlx5_hlist_destroy(priv->mreg_cp_tbl);
1476 mlx5_mprq_free_mp(dev);
1477 mlx5_os_free_shared_dr(priv);
1478 if (priv->rss_conf.rss_key != NULL)
1479 mlx5_free(priv->rss_conf.rss_key);
1480 if (priv->reta_idx != NULL)
1481 mlx5_free(priv->reta_idx);
1482 if (priv->config.vf)
1483 mlx5_os_mac_addr_flush(dev);
1484 if (priv->nl_socket_route >= 0)
1485 close(priv->nl_socket_route);
1486 if (priv->nl_socket_rdma >= 0)
1487 close(priv->nl_socket_rdma);
1488 if (priv->vmwa_context)
1489 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1490 ret = mlx5_hrxq_verify(dev);
1492 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1493 dev->data->port_id);
1494 ret = mlx5_ind_table_obj_verify(dev);
1496 DRV_LOG(WARNING, "port %u some indirection table still remain",
1497 dev->data->port_id);
1498 ret = mlx5_rxq_obj_verify(dev);
1500 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1501 dev->data->port_id);
1502 ret = mlx5_rxq_verify(dev);
1504 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1505 dev->data->port_id);
1506 ret = mlx5_txq_obj_verify(dev);
1508 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1509 dev->data->port_id);
1510 ret = mlx5_txq_verify(dev);
1512 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1513 dev->data->port_id);
1514 ret = mlx5_flow_verify(dev);
1516 DRV_LOG(WARNING, "port %u some flows still remain",
1517 dev->data->port_id);
1518 mlx5_cache_list_destroy(&priv->hrxqs);
1520 * Free the shared context in last turn, because the cleanup
1521 * routines above may use some shared fields, like
1522 * mlx5_os_mac_addr_flush() uses ibdev_path for retrieveing
1523 * ifindex if Netlink fails.
1525 mlx5_free_shared_dev_ctx(priv->sh);
1526 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1530 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1531 struct mlx5_priv *opriv =
1532 rte_eth_devices[port_id].data->dev_private;
1535 opriv->domain_id != priv->domain_id ||
1536 &rte_eth_devices[port_id] == dev)
1542 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1544 memset(priv, 0, sizeof(*priv));
1545 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1547 * Reset mac_addrs to NULL such that it is not freed as part of
1548 * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1549 * it is freed when dev_private is freed.
1551 dev->data->mac_addrs = NULL;
1555 const struct eth_dev_ops mlx5_dev_ops = {
1556 .dev_configure = mlx5_dev_configure,
1557 .dev_start = mlx5_dev_start,
1558 .dev_stop = mlx5_dev_stop,
1559 .dev_set_link_down = mlx5_set_link_down,
1560 .dev_set_link_up = mlx5_set_link_up,
1561 .dev_close = mlx5_dev_close,
1562 .promiscuous_enable = mlx5_promiscuous_enable,
1563 .promiscuous_disable = mlx5_promiscuous_disable,
1564 .allmulticast_enable = mlx5_allmulticast_enable,
1565 .allmulticast_disable = mlx5_allmulticast_disable,
1566 .link_update = mlx5_link_update,
1567 .stats_get = mlx5_stats_get,
1568 .stats_reset = mlx5_stats_reset,
1569 .xstats_get = mlx5_xstats_get,
1570 .xstats_reset = mlx5_xstats_reset,
1571 .xstats_get_names = mlx5_xstats_get_names,
1572 .fw_version_get = mlx5_fw_version_get,
1573 .dev_infos_get = mlx5_dev_infos_get,
1574 .representor_info_get = mlx5_representor_info_get,
1575 .read_clock = mlx5_txpp_read_clock,
1576 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1577 .vlan_filter_set = mlx5_vlan_filter_set,
1578 .rx_queue_setup = mlx5_rx_queue_setup,
1579 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1580 .tx_queue_setup = mlx5_tx_queue_setup,
1581 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1582 .rx_queue_release = mlx5_rx_queue_release,
1583 .tx_queue_release = mlx5_tx_queue_release,
1584 .rx_queue_start = mlx5_rx_queue_start,
1585 .rx_queue_stop = mlx5_rx_queue_stop,
1586 .tx_queue_start = mlx5_tx_queue_start,
1587 .tx_queue_stop = mlx5_tx_queue_stop,
1588 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1589 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1590 .mac_addr_remove = mlx5_mac_addr_remove,
1591 .mac_addr_add = mlx5_mac_addr_add,
1592 .mac_addr_set = mlx5_mac_addr_set,
1593 .set_mc_addr_list = mlx5_set_mc_addr_list,
1594 .mtu_set = mlx5_dev_set_mtu,
1595 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1596 .vlan_offload_set = mlx5_vlan_offload_set,
1597 .reta_update = mlx5_dev_rss_reta_update,
1598 .reta_query = mlx5_dev_rss_reta_query,
1599 .rss_hash_update = mlx5_rss_hash_update,
1600 .rss_hash_conf_get = mlx5_rss_hash_conf_get,
1601 .flow_ops_get = mlx5_flow_ops_get,
1602 .rxq_info_get = mlx5_rxq_info_get,
1603 .txq_info_get = mlx5_txq_info_get,
1604 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1605 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1606 .rx_queue_intr_enable = mlx5_rx_intr_enable,
1607 .rx_queue_intr_disable = mlx5_rx_intr_disable,
1608 .is_removed = mlx5_is_removed,
1609 .udp_tunnel_port_add = mlx5_udp_tunnel_port_add,
1610 .get_module_info = mlx5_get_module_info,
1611 .get_module_eeprom = mlx5_get_module_eeprom,
1612 .hairpin_cap_get = mlx5_hairpin_cap_get,
1613 .mtr_ops_get = mlx5_flow_meter_ops_get,
1614 .hairpin_bind = mlx5_hairpin_bind,
1615 .hairpin_unbind = mlx5_hairpin_unbind,
1616 .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1617 .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1618 .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1619 .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1620 .get_monitor_addr = mlx5_get_monitor_addr,
1623 /* Available operations from secondary process. */
1624 const struct eth_dev_ops mlx5_dev_sec_ops = {
1625 .stats_get = mlx5_stats_get,
1626 .stats_reset = mlx5_stats_reset,
1627 .xstats_get = mlx5_xstats_get,
1628 .xstats_reset = mlx5_xstats_reset,
1629 .xstats_get_names = mlx5_xstats_get_names,
1630 .fw_version_get = mlx5_fw_version_get,
1631 .dev_infos_get = mlx5_dev_infos_get,
1632 .read_clock = mlx5_txpp_read_clock,
1633 .rx_queue_start = mlx5_rx_queue_start,
1634 .rx_queue_stop = mlx5_rx_queue_stop,
1635 .tx_queue_start = mlx5_tx_queue_start,
1636 .tx_queue_stop = mlx5_tx_queue_stop,
1637 .rxq_info_get = mlx5_rxq_info_get,
1638 .txq_info_get = mlx5_txq_info_get,
1639 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1640 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1641 .get_module_info = mlx5_get_module_info,
1642 .get_module_eeprom = mlx5_get_module_eeprom,
1645 /* Available operations in flow isolated mode. */
1646 const struct eth_dev_ops mlx5_dev_ops_isolate = {
1647 .dev_configure = mlx5_dev_configure,
1648 .dev_start = mlx5_dev_start,
1649 .dev_stop = mlx5_dev_stop,
1650 .dev_set_link_down = mlx5_set_link_down,
1651 .dev_set_link_up = mlx5_set_link_up,
1652 .dev_close = mlx5_dev_close,
1653 .promiscuous_enable = mlx5_promiscuous_enable,
1654 .promiscuous_disable = mlx5_promiscuous_disable,
1655 .allmulticast_enable = mlx5_allmulticast_enable,
1656 .allmulticast_disable = mlx5_allmulticast_disable,
1657 .link_update = mlx5_link_update,
1658 .stats_get = mlx5_stats_get,
1659 .stats_reset = mlx5_stats_reset,
1660 .xstats_get = mlx5_xstats_get,
1661 .xstats_reset = mlx5_xstats_reset,
1662 .xstats_get_names = mlx5_xstats_get_names,
1663 .fw_version_get = mlx5_fw_version_get,
1664 .dev_infos_get = mlx5_dev_infos_get,
1665 .read_clock = mlx5_txpp_read_clock,
1666 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1667 .vlan_filter_set = mlx5_vlan_filter_set,
1668 .rx_queue_setup = mlx5_rx_queue_setup,
1669 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1670 .tx_queue_setup = mlx5_tx_queue_setup,
1671 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1672 .rx_queue_release = mlx5_rx_queue_release,
1673 .tx_queue_release = mlx5_tx_queue_release,
1674 .rx_queue_start = mlx5_rx_queue_start,
1675 .rx_queue_stop = mlx5_rx_queue_stop,
1676 .tx_queue_start = mlx5_tx_queue_start,
1677 .tx_queue_stop = mlx5_tx_queue_stop,
1678 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1679 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1680 .mac_addr_remove = mlx5_mac_addr_remove,
1681 .mac_addr_add = mlx5_mac_addr_add,
1682 .mac_addr_set = mlx5_mac_addr_set,
1683 .set_mc_addr_list = mlx5_set_mc_addr_list,
1684 .mtu_set = mlx5_dev_set_mtu,
1685 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1686 .vlan_offload_set = mlx5_vlan_offload_set,
1687 .flow_ops_get = mlx5_flow_ops_get,
1688 .rxq_info_get = mlx5_rxq_info_get,
1689 .txq_info_get = mlx5_txq_info_get,
1690 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1691 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1692 .rx_queue_intr_enable = mlx5_rx_intr_enable,
1693 .rx_queue_intr_disable = mlx5_rx_intr_disable,
1694 .is_removed = mlx5_is_removed,
1695 .get_module_info = mlx5_get_module_info,
1696 .get_module_eeprom = mlx5_get_module_eeprom,
1697 .hairpin_cap_get = mlx5_hairpin_cap_get,
1698 .mtr_ops_get = mlx5_flow_meter_ops_get,
1699 .hairpin_bind = mlx5_hairpin_bind,
1700 .hairpin_unbind = mlx5_hairpin_unbind,
1701 .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1702 .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1703 .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1704 .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1705 .get_monitor_addr = mlx5_get_monitor_addr,
1709 * Verify and store value for device argument.
1712 * Key argument to verify.
1714 * Value associated with key.
1719 * 0 on success, a negative errno value otherwise and rte_errno is set.
1722 mlx5_args_check(const char *key, const char *val, void *opaque)
1724 struct mlx5_dev_config *config = opaque;
1728 /* No-op, port representors are processed in mlx5_dev_spawn(). */
1729 if (!strcmp(MLX5_REPRESENTOR, key))
1732 tmp = strtol(val, NULL, 0);
1735 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1738 if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
1739 /* Negative values are acceptable for some keys only. */
1741 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
1744 mod = tmp >= 0 ? tmp : -tmp;
1745 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1746 if (tmp > MLX5_CQE_RESP_FORMAT_L34H_STRIDX) {
1747 DRV_LOG(ERR, "invalid CQE compression "
1748 "format parameter");
1752 config->cqe_comp = !!tmp;
1753 config->cqe_comp_fmt = tmp;
1754 } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1755 config->hw_padding = !!tmp;
1756 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1757 config->mprq.enabled = !!tmp;
1758 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1759 config->mprq.stride_num_n = tmp;
1760 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1761 config->mprq.stride_size_n = tmp;
1762 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1763 config->mprq.max_memcpy_len = tmp;
1764 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1765 config->mprq.min_rxqs_num = tmp;
1766 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1767 DRV_LOG(WARNING, "%s: deprecated parameter,"
1768 " converted to txq_inline_max", key);
1769 config->txq_inline_max = tmp;
1770 } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1771 config->txq_inline_max = tmp;
1772 } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1773 config->txq_inline_min = tmp;
1774 } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1775 config->txq_inline_mpw = tmp;
1776 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1777 config->txqs_inline = tmp;
1778 } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1779 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1780 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1781 config->mps = !!tmp;
1782 } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1783 if (tmp != MLX5_TXDB_CACHED &&
1784 tmp != MLX5_TXDB_NCACHED &&
1785 tmp != MLX5_TXDB_HEURISTIC) {
1786 DRV_LOG(ERR, "invalid Tx doorbell "
1787 "mapping parameter");
1792 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1793 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1794 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1795 DRV_LOG(WARNING, "%s: deprecated parameter,"
1796 " converted to txq_inline_mpw", key);
1797 config->txq_inline_mpw = tmp;
1798 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1799 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1800 } else if (strcmp(MLX5_TX_PP, key) == 0) {
1802 DRV_LOG(ERR, "Zero Tx packet pacing parameter");
1806 config->tx_pp = tmp;
1807 } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
1808 config->tx_skew = tmp;
1809 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1810 config->rx_vec_en = !!tmp;
1811 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1812 config->l3_vxlan_en = !!tmp;
1813 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1814 config->vf_nl_en = !!tmp;
1815 } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1816 config->dv_esw_en = !!tmp;
1817 } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1818 config->dv_flow_en = !!tmp;
1819 } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1820 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1821 tmp != MLX5_XMETA_MODE_META16 &&
1822 tmp != MLX5_XMETA_MODE_META32 &&
1823 tmp != MLX5_XMETA_MODE_MISS_INFO) {
1824 DRV_LOG(ERR, "invalid extensive "
1825 "metadata parameter");
1829 if (tmp != MLX5_XMETA_MODE_MISS_INFO)
1830 config->dv_xmeta_en = tmp;
1832 config->dv_miss_info = 1;
1833 } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
1834 config->lacp_by_user = !!tmp;
1835 } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1836 config->mr_ext_memseg_en = !!tmp;
1837 } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1838 config->max_dump_files_num = tmp;
1839 } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1840 config->lro.timeout = tmp;
1841 } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1842 DRV_LOG(DEBUG, "class argument is %s.", val);
1843 } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1844 config->log_hp_size = tmp;
1845 } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1846 if (tmp != MLX5_RCM_NONE &&
1847 tmp != MLX5_RCM_LIGHT &&
1848 tmp != MLX5_RCM_AGGR) {
1849 DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1853 config->reclaim_mode = tmp;
1854 } else if (strcmp(MLX5_SYS_MEM_EN, key) == 0) {
1855 config->sys_mem_en = !!tmp;
1856 } else if (strcmp(MLX5_DECAP_EN, key) == 0) {
1857 config->decap_en = !!tmp;
1859 DRV_LOG(WARNING, "%s: unknown parameter", key);
1867 * Parse device parameters.
1870 * Pointer to device configuration structure.
1872 * Device arguments structure.
1875 * 0 on success, a negative errno value otherwise and rte_errno is set.
1878 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1880 const char **params = (const char *[]){
1881 MLX5_RXQ_CQE_COMP_EN,
1882 MLX5_RXQ_PKT_PAD_EN,
1884 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1885 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1886 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1889 MLX5_TXQ_INLINE_MIN,
1890 MLX5_TXQ_INLINE_MAX,
1891 MLX5_TXQ_INLINE_MPW,
1892 MLX5_TXQS_MIN_INLINE,
1895 MLX5_TXQ_MPW_HDR_DSEG_EN,
1896 MLX5_TXQ_MAX_INLINE_LEN,
1908 MLX5_MR_EXT_MEMSEG_EN,
1910 MLX5_MAX_DUMP_FILES_NUM,
1911 MLX5_LRO_TIMEOUT_USEC,
1912 MLX5_CLASS_ARG_NAME,
1919 struct rte_kvargs *kvlist;
1923 if (devargs == NULL)
1925 /* Following UGLY cast is done to pass checkpatch. */
1926 kvlist = rte_kvargs_parse(devargs->args, params);
1927 if (kvlist == NULL) {
1931 /* Process parameters. */
1932 for (i = 0; (params[i] != NULL); ++i) {
1933 if (rte_kvargs_count(kvlist, params[i])) {
1934 ret = rte_kvargs_process(kvlist, params[i],
1935 mlx5_args_check, config);
1938 rte_kvargs_free(kvlist);
1943 rte_kvargs_free(kvlist);
1948 * Configures the minimal amount of data to inline into WQE
1949 * while sending packets.
1951 * - the txq_inline_min has the maximal priority, if this
1952 * key is specified in devargs
1953 * - if DevX is enabled the inline mode is queried from the
1954 * device (HCA attributes and NIC vport context if needed).
1955 * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1956 * and none (0 bytes) for other NICs
1959 * Verbs device parameters (name, port, switch_info) to spawn.
1961 * Device configuration parameters.
1964 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1965 struct mlx5_dev_config *config)
1967 if (config->txq_inline_min != MLX5_ARG_UNSET) {
1968 /* Application defines size of inlined data explicitly. */
1969 switch (spawn->pci_dev->id.device_id) {
1970 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1971 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1972 if (config->txq_inline_min <
1973 (int)MLX5_INLINE_HSIZE_L2) {
1975 "txq_inline_mix aligned to minimal"
1976 " ConnectX-4 required value %d",
1977 (int)MLX5_INLINE_HSIZE_L2);
1978 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1984 if (config->hca_attr.eth_net_offloads) {
1985 /* We have DevX enabled, inline mode queried successfully. */
1986 switch (config->hca_attr.wqe_inline_mode) {
1987 case MLX5_CAP_INLINE_MODE_L2:
1988 /* outer L2 header must be inlined. */
1989 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1991 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1992 /* No inline data are required by NIC. */
1993 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1994 config->hw_vlan_insert =
1995 config->hca_attr.wqe_vlan_insert;
1996 DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1998 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1999 /* inline mode is defined by NIC vport context. */
2000 if (!config->hca_attr.eth_virt)
2002 switch (config->hca_attr.vport_inline_mode) {
2003 case MLX5_INLINE_MODE_NONE:
2004 config->txq_inline_min =
2005 MLX5_INLINE_HSIZE_NONE;
2007 case MLX5_INLINE_MODE_L2:
2008 config->txq_inline_min =
2009 MLX5_INLINE_HSIZE_L2;
2011 case MLX5_INLINE_MODE_IP:
2012 config->txq_inline_min =
2013 MLX5_INLINE_HSIZE_L3;
2015 case MLX5_INLINE_MODE_TCP_UDP:
2016 config->txq_inline_min =
2017 MLX5_INLINE_HSIZE_L4;
2019 case MLX5_INLINE_MODE_INNER_L2:
2020 config->txq_inline_min =
2021 MLX5_INLINE_HSIZE_INNER_L2;
2023 case MLX5_INLINE_MODE_INNER_IP:
2024 config->txq_inline_min =
2025 MLX5_INLINE_HSIZE_INNER_L3;
2027 case MLX5_INLINE_MODE_INNER_TCP_UDP:
2028 config->txq_inline_min =
2029 MLX5_INLINE_HSIZE_INNER_L4;
2035 * We get here if we are unable to deduce
2036 * inline data size with DevX. Try PCI ID
2037 * to determine old NICs.
2039 switch (spawn->pci_dev->id.device_id) {
2040 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2041 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2042 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
2043 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
2044 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2045 config->hw_vlan_insert = 0;
2047 case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
2048 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
2049 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
2050 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
2052 * These NICs support VLAN insertion from WQE and
2053 * report the wqe_vlan_insert flag. But there is the bug
2054 * and PFC control may be broken, so disable feature.
2056 config->hw_vlan_insert = 0;
2057 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2060 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2064 DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
2068 * Configures the metadata mask fields in the shared context.
2071 * Pointer to Ethernet device.
2074 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
2076 struct mlx5_priv *priv = dev->data->dev_private;
2077 struct mlx5_dev_ctx_shared *sh = priv->sh;
2078 uint32_t meta, mark, reg_c0;
2080 reg_c0 = ~priv->vport_meta_mask;
2081 switch (priv->config.dv_xmeta_en) {
2082 case MLX5_XMETA_MODE_LEGACY:
2084 mark = MLX5_FLOW_MARK_MASK;
2086 case MLX5_XMETA_MODE_META16:
2087 meta = reg_c0 >> rte_bsf32(reg_c0);
2088 mark = MLX5_FLOW_MARK_MASK;
2090 case MLX5_XMETA_MODE_META32:
2092 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
2100 if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
2101 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
2102 sh->dv_mark_mask, mark);
2104 sh->dv_mark_mask = mark;
2105 if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
2106 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
2107 sh->dv_meta_mask, meta);
2109 sh->dv_meta_mask = meta;
2110 if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
2111 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
2112 sh->dv_meta_mask, reg_c0);
2114 sh->dv_regc0_mask = reg_c0;
2115 DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
2116 DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
2117 DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
2118 DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
2122 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
2124 static const char *const dynf_names[] = {
2125 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
2126 RTE_MBUF_DYNFLAG_METADATA_NAME,
2127 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
2131 if (n < RTE_DIM(dynf_names))
2133 for (i = 0; i < RTE_DIM(dynf_names); i++) {
2134 if (names[i] == NULL)
2136 strcpy(names[i], dynf_names[i]);
2138 return RTE_DIM(dynf_names);
2142 * Comparison callback to sort device data.
2144 * This is meant to be used with qsort().
2147 * Pointer to pointer to first data object.
2149 * Pointer to pointer to second data object.
2152 * 0 if both objects are equal, less than 0 if the first argument is less
2153 * than the second, greater than 0 otherwise.
2156 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
2157 struct mlx5_dev_config *config)
2159 struct mlx5_dev_ctx_shared *sh = priv->sh;
2160 struct mlx5_dev_config *sh_conf = NULL;
2164 /* Nothing to compare for the single/first device. */
2165 if (sh->refcnt == 1)
2167 /* Find the device with shared context. */
2168 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
2169 struct mlx5_priv *opriv =
2170 rte_eth_devices[port_id].data->dev_private;
2172 if (opriv && opriv != priv && opriv->sh == sh) {
2173 sh_conf = &opriv->config;
2179 if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
2180 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
2181 " for shared %s context", sh->ibdev_name);
2185 if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
2186 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
2187 " for shared %s context", sh->ibdev_name);
2195 * Look for the ethernet device belonging to mlx5 driver.
2197 * @param[in] port_id
2198 * port_id to start looking for device.
2199 * @param[in] pci_dev
2200 * Pointer to the hint PCI device. When device is being probed
2201 * the its siblings (master and preceding representors might
2202 * not have assigned driver yet (because the mlx5_os_pci_probe()
2203 * is not completed yet, for this case match on hint PCI
2204 * device may be used to detect sibling device.
2207 * port_id of found device, RTE_MAX_ETHPORT if not found.
2210 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
2212 while (port_id < RTE_MAX_ETHPORTS) {
2213 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
2215 if (dev->state != RTE_ETH_DEV_UNUSED &&
2217 (dev->device == &pci_dev->device ||
2218 (dev->device->driver &&
2219 dev->device->driver->name &&
2220 !strcmp(dev->device->driver->name, MLX5_PCI_DRIVER_NAME))))
2224 if (port_id >= RTE_MAX_ETHPORTS)
2225 return RTE_MAX_ETHPORTS;
2230 * DPDK callback to remove a PCI device.
2232 * This function removes all Ethernet devices belong to a given PCI device.
2234 * @param[in] pci_dev
2235 * Pointer to the PCI device.
2238 * 0 on success, the function cannot fail.
2241 mlx5_pci_remove(struct rte_pci_device *pci_dev)
2246 RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
2248 * mlx5_dev_close() is not registered to secondary process,
2249 * call the close function explicitly for secondary process.
2251 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
2252 ret |= mlx5_dev_close(&rte_eth_devices[port_id]);
2254 ret |= rte_eth_dev_close(port_id);
2256 return ret == 0 ? 0 : -EIO;
2259 static const struct rte_pci_id mlx5_pci_id_map[] = {
2261 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2262 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
2265 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2266 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
2269 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2270 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
2273 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2274 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
2277 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2278 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
2281 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2282 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
2285 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2286 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
2289 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2290 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
2293 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2294 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
2297 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2298 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
2301 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2302 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
2305 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2306 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
2309 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2310 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
2313 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2314 PCI_DEVICE_ID_MELLANOX_CONNECTXVF)
2317 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2318 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
2321 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2322 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
2325 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2326 PCI_DEVICE_ID_MELLANOX_CONNECTX7)
2329 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2330 PCI_DEVICE_ID_MELLANOX_CONNECTX7BF)
2337 static struct mlx5_pci_driver mlx5_driver = {
2338 .driver_class = MLX5_CLASS_NET,
2341 .name = MLX5_PCI_DRIVER_NAME,
2343 .id_table = mlx5_pci_id_map,
2344 .probe = mlx5_os_pci_probe,
2345 .remove = mlx5_pci_remove,
2346 .dma_map = mlx5_dma_map,
2347 .dma_unmap = mlx5_dma_unmap,
2348 .drv_flags = PCI_DRV_FLAGS,
2352 /* Initialize driver log type. */
2353 RTE_LOG_REGISTER(mlx5_logtype, pmd.net.mlx5, NOTICE)
2356 * Driver initialization routine.
2358 RTE_INIT(rte_mlx5_pmd_init)
2360 pthread_mutex_init(&mlx5_dev_ctx_list_mutex, NULL);
2362 /* Build the static tables for Verbs conversion. */
2363 mlx5_set_ptype_table();
2364 mlx5_set_cksum_table();
2365 mlx5_set_swp_types_table();
2367 mlx5_pci_driver_register(&mlx5_driver);
2370 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
2371 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
2372 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");