4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
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8 * modification, are permitted provided that the following conditions
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44 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
46 #pragma GCC diagnostic ignored "-Wpedantic"
48 #include <infiniband/verbs.h>
50 #pragma GCC diagnostic error "-Wpedantic"
53 #include <rte_malloc.h>
54 #include <rte_ethdev.h>
55 #include <rte_ethdev_pci.h>
57 #include <rte_common.h>
58 #include <rte_kvargs.h>
61 #include "mlx5_utils.h"
62 #include "mlx5_rxtx.h"
63 #include "mlx5_autoconf.h"
64 #include "mlx5_defs.h"
66 /* Device parameter to enable RX completion queue compression. */
67 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
69 /* Device parameter to configure inline send. */
70 #define MLX5_TXQ_INLINE "txq_inline"
73 * Device parameter to configure the number of TX queues threshold for
74 * enabling inline send.
76 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
78 /* Device parameter to enable multi-packet send WQEs. */
79 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
81 /* Device parameter to include 2 dsegs in the title WQEBB. */
82 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
84 /* Device parameter to limit the size of inlining packet. */
85 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
87 /* Device parameter to enable hardware TSO offload. */
88 #define MLX5_TSO "tso"
90 /* Device parameter to enable hardware Tx vector. */
91 #define MLX5_TX_VEC_EN "tx_vec_en"
93 /* Device parameter to enable hardware Rx vector. */
94 #define MLX5_RX_VEC_EN "rx_vec_en"
96 /* Default PMD specific parameter value. */
97 #define MLX5_ARG_UNSET (-1)
99 #ifndef HAVE_IBV_MLX5_MOD_MPW
100 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2)
101 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3)
110 int inline_max_packet_sz;
116 * Retrieve integer value from environment variable.
119 * Environment variable name.
122 * Integer value, 0 if the variable is not set.
125 mlx5_getenv_int(const char *name)
127 const char *val = getenv(name);
135 * Verbs callback to allocate a memory. This function should allocate the space
136 * according to the size provided residing inside a huge page.
137 * Please note that all allocation must respect the alignment from libmlx5
138 * (i.e. currently sysconf(_SC_PAGESIZE)).
141 * The size in bytes of the memory to allocate.
143 * A pointer to the callback data.
146 * a pointer to the allocate space.
149 mlx5_alloc_verbs_buf(size_t size, void *data)
151 struct priv *priv = data;
153 size_t alignment = sysconf(_SC_PAGESIZE);
155 assert(data != NULL);
156 assert(!mlx5_is_secondary());
157 ret = rte_malloc_socket(__func__, size, alignment,
158 priv->dev->device->numa_node);
159 DEBUG("Extern alloc size: %lu, align: %lu: %p", size, alignment, ret);
164 * Verbs callback to free a memory.
167 * A pointer to the memory to free.
169 * A pointer to the callback data.
172 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused)
174 assert(data != NULL);
175 assert(!mlx5_is_secondary());
176 DEBUG("Extern free request: %p", ptr);
181 * DPDK callback to close the device.
183 * Destroy all queues and objects, free memory.
186 * Pointer to Ethernet device structure.
189 mlx5_dev_close(struct rte_eth_dev *dev)
191 struct priv *priv = mlx5_get_priv(dev);
195 DEBUG("%p: closing device \"%s\"",
197 ((priv->ctx != NULL) ? priv->ctx->device->name : ""));
198 /* In case mlx5_dev_stop() has not been called. */
199 priv_dev_interrupt_handler_uninstall(priv, dev);
200 priv_special_flow_disable_all(priv);
201 priv_mac_addrs_disable(priv);
202 priv_destroy_hash_rxqs(priv);
204 /* Remove flow director elements. */
205 priv_fdir_disable(priv);
206 priv_fdir_delete_filters_list(priv);
208 /* Prevent crashes when queues are still in use. */
209 dev->rx_pkt_burst = removed_rx_burst;
210 dev->tx_pkt_burst = removed_tx_burst;
211 if (priv->rxqs != NULL) {
212 /* XXX race condition if mlx5_rx_burst() is still running. */
214 for (i = 0; (i != priv->rxqs_n); ++i) {
215 struct rxq *rxq = (*priv->rxqs)[i];
216 struct rxq_ctrl *rxq_ctrl;
220 rxq_ctrl = container_of(rxq, struct rxq_ctrl, rxq);
221 (*priv->rxqs)[i] = NULL;
222 rxq_cleanup(rxq_ctrl);
228 if (priv->txqs != NULL) {
229 /* XXX race condition if mlx5_tx_burst() is still running. */
231 for (i = 0; (i != priv->txqs_n); ++i) {
232 struct txq *txq = (*priv->txqs)[i];
233 struct txq_ctrl *txq_ctrl;
237 txq_ctrl = container_of(txq, struct txq_ctrl, txq);
238 (*priv->txqs)[i] = NULL;
239 txq_cleanup(txq_ctrl);
245 if (priv->pd != NULL) {
246 assert(priv->ctx != NULL);
247 claim_zero(ibv_dealloc_pd(priv->pd));
248 claim_zero(ibv_close_device(priv->ctx));
250 assert(priv->ctx == NULL);
251 if (priv->rss_conf != NULL) {
252 for (i = 0; (i != hash_rxq_init_n); ++i)
253 rte_free((*priv->rss_conf)[i]);
254 rte_free(priv->rss_conf);
256 if (priv->reta_idx != NULL)
257 rte_free(priv->reta_idx);
258 priv_socket_uninit(priv);
260 memset(priv, 0, sizeof(*priv));
263 static const struct eth_dev_ops mlx5_dev_ops = {
264 .dev_configure = mlx5_dev_configure,
265 .dev_start = mlx5_dev_start,
266 .dev_stop = mlx5_dev_stop,
267 .dev_set_link_down = mlx5_set_link_down,
268 .dev_set_link_up = mlx5_set_link_up,
269 .dev_close = mlx5_dev_close,
270 .promiscuous_enable = mlx5_promiscuous_enable,
271 .promiscuous_disable = mlx5_promiscuous_disable,
272 .allmulticast_enable = mlx5_allmulticast_enable,
273 .allmulticast_disable = mlx5_allmulticast_disable,
274 .link_update = mlx5_link_update,
275 .stats_get = mlx5_stats_get,
276 .stats_reset = mlx5_stats_reset,
277 .xstats_get = mlx5_xstats_get,
278 .xstats_reset = mlx5_xstats_reset,
279 .xstats_get_names = mlx5_xstats_get_names,
280 .dev_infos_get = mlx5_dev_infos_get,
281 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
282 .vlan_filter_set = mlx5_vlan_filter_set,
283 .rx_queue_setup = mlx5_rx_queue_setup,
284 .tx_queue_setup = mlx5_tx_queue_setup,
285 .rx_queue_release = mlx5_rx_queue_release,
286 .tx_queue_release = mlx5_tx_queue_release,
287 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
288 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
289 .mac_addr_remove = mlx5_mac_addr_remove,
290 .mac_addr_add = mlx5_mac_addr_add,
291 .mac_addr_set = mlx5_mac_addr_set,
292 .mtu_set = mlx5_dev_set_mtu,
293 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
294 .vlan_offload_set = mlx5_vlan_offload_set,
295 .reta_update = mlx5_dev_rss_reta_update,
296 .reta_query = mlx5_dev_rss_reta_query,
297 .rss_hash_update = mlx5_rss_hash_update,
298 .rss_hash_conf_get = mlx5_rss_hash_conf_get,
299 .filter_ctrl = mlx5_dev_filter_ctrl,
300 .rx_descriptor_status = mlx5_rx_descriptor_status,
301 .tx_descriptor_status = mlx5_tx_descriptor_status,
302 .rx_queue_intr_enable = mlx5_rx_intr_enable,
303 .rx_queue_intr_disable = mlx5_rx_intr_disable,
307 static const struct eth_dev_ops mlx5_dev_sec_ops = {
308 .stats_get = mlx5_stats_get,
309 .stats_reset = mlx5_stats_reset,
310 .xstats_get = mlx5_xstats_get,
311 .xstats_reset = mlx5_xstats_reset,
312 .xstats_get_names = mlx5_xstats_get_names,
313 .dev_infos_get = mlx5_dev_infos_get,
314 .rx_descriptor_status = mlx5_rx_descriptor_status,
315 .tx_descriptor_status = mlx5_tx_descriptor_status,
319 struct rte_pci_addr pci_addr; /* associated PCI address */
320 uint32_t ports; /* physical ports bitfield. */
324 * Get device index in mlx5_dev[] from PCI bus address.
326 * @param[in] pci_addr
327 * PCI bus address to look for.
330 * mlx5_dev[] index on success, -1 on failure.
333 mlx5_dev_idx(struct rte_pci_addr *pci_addr)
338 assert(pci_addr != NULL);
339 for (i = 0; (i != RTE_DIM(mlx5_dev)); ++i) {
340 if ((mlx5_dev[i].pci_addr.domain == pci_addr->domain) &&
341 (mlx5_dev[i].pci_addr.bus == pci_addr->bus) &&
342 (mlx5_dev[i].pci_addr.devid == pci_addr->devid) &&
343 (mlx5_dev[i].pci_addr.function == pci_addr->function))
345 if ((mlx5_dev[i].ports == 0) && (ret == -1))
352 * Verify and store value for device argument.
355 * Key argument to verify.
357 * Value associated with key.
362 * 0 on success, negative errno value on failure.
365 mlx5_args_check(const char *key, const char *val, void *opaque)
367 struct mlx5_args *args = opaque;
371 tmp = strtoul(val, NULL, 0);
373 WARN("%s: \"%s\" is not a valid integer", key, val);
376 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
377 args->cqe_comp = !!tmp;
378 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
379 args->txq_inline = tmp;
380 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
381 args->txqs_inline = tmp;
382 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
384 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
385 args->mpw_hdr_dseg = !!tmp;
386 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
387 args->inline_max_packet_sz = tmp;
388 } else if (strcmp(MLX5_TSO, key) == 0) {
390 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
391 args->tx_vec_en = !!tmp;
392 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
393 args->rx_vec_en = !!tmp;
395 WARN("%s: unknown parameter", key);
402 * Parse device parameters.
405 * Pointer to private structure.
407 * Device arguments structure.
410 * 0 on success, errno value on failure.
413 mlx5_args(struct mlx5_args *args, struct rte_devargs *devargs)
415 const char **params = (const char *[]){
416 MLX5_RXQ_CQE_COMP_EN,
418 MLX5_TXQS_MIN_INLINE,
420 MLX5_TXQ_MPW_HDR_DSEG_EN,
421 MLX5_TXQ_MAX_INLINE_LEN,
427 struct rte_kvargs *kvlist;
433 /* Following UGLY cast is done to pass checkpatch. */
434 kvlist = rte_kvargs_parse(devargs->args, params);
437 /* Process parameters. */
438 for (i = 0; (params[i] != NULL); ++i) {
439 if (rte_kvargs_count(kvlist, params[i])) {
440 ret = rte_kvargs_process(kvlist, params[i],
441 mlx5_args_check, args);
443 rte_kvargs_free(kvlist);
448 rte_kvargs_free(kvlist);
452 static struct rte_pci_driver mlx5_driver;
455 * Assign parameters from args into priv, only non default
456 * values are considered.
459 * Pointer to private structure.
461 * Pointer to args values.
464 mlx5_args_assign(struct priv *priv, struct mlx5_args *args)
466 if (args->cqe_comp != MLX5_ARG_UNSET)
467 priv->cqe_comp = args->cqe_comp;
468 if (args->txq_inline != MLX5_ARG_UNSET)
469 priv->txq_inline = args->txq_inline;
470 if (args->txqs_inline != MLX5_ARG_UNSET)
471 priv->txqs_inline = args->txqs_inline;
472 if (args->mps != MLX5_ARG_UNSET)
473 priv->mps = args->mps ? priv->mps : 0;
474 if (args->mpw_hdr_dseg != MLX5_ARG_UNSET)
475 priv->mpw_hdr_dseg = args->mpw_hdr_dseg;
476 if (args->inline_max_packet_sz != MLX5_ARG_UNSET)
477 priv->inline_max_packet_sz = args->inline_max_packet_sz;
478 if (args->tso != MLX5_ARG_UNSET)
479 priv->tso = args->tso;
480 if (args->tx_vec_en != MLX5_ARG_UNSET)
481 priv->tx_vec_en = args->tx_vec_en;
482 if (args->rx_vec_en != MLX5_ARG_UNSET)
483 priv->rx_vec_en = args->rx_vec_en;
487 * DPDK callback to register a PCI device.
489 * This function creates an Ethernet device for each port of a given
493 * PCI driver structure (mlx5_driver).
495 * PCI device information.
498 * 0 on success, negative errno value on failure.
501 mlx5_pci_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
503 struct ibv_device **list;
504 struct ibv_device *ibv_dev;
506 struct ibv_context *attr_ctx = NULL;
507 struct ibv_device_attr_ex device_attr;
510 unsigned int tunnel_en = 0;
513 struct mlx5dv_context attrs_out;
516 assert(pci_drv == &mlx5_driver);
517 /* Get mlx5_dev[] index. */
518 idx = mlx5_dev_idx(&pci_dev->addr);
520 ERROR("this driver cannot support any more adapters");
523 DEBUG("using driver device index %d", idx);
525 /* Save PCI address. */
526 mlx5_dev[idx].pci_addr = pci_dev->addr;
527 list = ibv_get_device_list(&i);
531 ERROR("cannot list devices, is ib_uverbs loaded?");
536 * For each listed device, check related sysfs entry against
537 * the provided PCI ID.
540 struct rte_pci_addr pci_addr;
543 DEBUG("checking device \"%s\"", list[i]->name);
544 if (mlx5_ibv_device_to_pci_addr(list[i], &pci_addr))
546 if ((pci_dev->addr.domain != pci_addr.domain) ||
547 (pci_dev->addr.bus != pci_addr.bus) ||
548 (pci_dev->addr.devid != pci_addr.devid) ||
549 (pci_dev->addr.function != pci_addr.function))
551 sriov = ((pci_dev->id.device_id ==
552 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF) ||
553 (pci_dev->id.device_id ==
554 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF) ||
555 (pci_dev->id.device_id ==
556 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF) ||
557 (pci_dev->id.device_id ==
558 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF));
559 switch (pci_dev->id.device_id) {
560 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
563 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
564 case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
565 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
566 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
567 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
573 INFO("PCI information matches, using device \"%s\""
576 sriov ? "true" : "false");
577 attr_ctx = ibv_open_device(list[i]);
581 if (attr_ctx == NULL) {
582 ibv_free_device_list(list);
585 ERROR("cannot access device, is mlx5_ib loaded?");
588 ERROR("cannot use device, are drivers up to date?");
596 DEBUG("device opened");
598 * Multi-packet send is supported by ConnectX-4 Lx PF as well
599 * as all ConnectX-5 devices.
601 mlx5dv_query_device(attr_ctx, &attrs_out);
602 if (attrs_out.flags & (MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW |
603 MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED)) {
604 INFO("Enhanced MPW is detected\n");
605 mps = MLX5_MPW_ENHANCED;
606 } else if (attrs_out.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
607 INFO("MPW is detected\n");
610 INFO("MPW is disabled\n");
611 mps = MLX5_MPW_DISABLED;
613 if (ibv_query_device_ex(attr_ctx, NULL, &device_attr))
615 INFO("%u port(s) detected", device_attr.orig_attr.phys_port_cnt);
617 for (i = 0; i < device_attr.orig_attr.phys_port_cnt; i++) {
618 uint32_t port = i + 1; /* ports are indexed from one */
619 uint32_t test = (1 << i);
620 struct ibv_context *ctx = NULL;
621 struct ibv_port_attr port_attr;
622 struct ibv_pd *pd = NULL;
623 struct priv *priv = NULL;
624 struct rte_eth_dev *eth_dev;
625 struct ibv_device_attr_ex device_attr_ex;
626 struct ether_addr mac;
627 uint16_t num_vfs = 0;
628 struct mlx5_args args = {
629 .cqe_comp = MLX5_ARG_UNSET,
630 .txq_inline = MLX5_ARG_UNSET,
631 .txqs_inline = MLX5_ARG_UNSET,
632 .mps = MLX5_ARG_UNSET,
633 .mpw_hdr_dseg = MLX5_ARG_UNSET,
634 .inline_max_packet_sz = MLX5_ARG_UNSET,
635 .tso = MLX5_ARG_UNSET,
636 .tx_vec_en = MLX5_ARG_UNSET,
637 .rx_vec_en = MLX5_ARG_UNSET,
640 mlx5_dev[idx].ports |= test;
642 if (mlx5_is_secondary()) {
643 /* from rte_ethdev.c */
644 char name[RTE_ETH_NAME_MAX_LEN];
646 snprintf(name, sizeof(name), "%s port %u",
647 ibv_get_device_name(ibv_dev), port);
648 eth_dev = rte_eth_dev_attach_secondary(name);
649 if (eth_dev == NULL) {
650 ERROR("can not attach rte ethdev");
654 eth_dev->device = &pci_dev->device;
655 eth_dev->dev_ops = &mlx5_dev_sec_ops;
656 priv = eth_dev->data->dev_private;
657 /* Receive command fd from primary process */
658 err = priv_socket_connect(priv);
663 /* Remap UAR for Tx queues. */
664 err = priv_tx_uar_remap(priv, err);
669 priv_dev_select_rx_function(priv, eth_dev);
670 priv_dev_select_tx_function(priv, eth_dev);
674 DEBUG("using port %u (%08" PRIx32 ")", port, test);
676 ctx = ibv_open_device(ibv_dev);
682 /* Check port status. */
683 err = ibv_query_port(ctx, port, &port_attr);
685 ERROR("port query failed: %s", strerror(err));
689 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
690 ERROR("port %d is not configured in Ethernet mode",
696 if (port_attr.state != IBV_PORT_ACTIVE)
697 DEBUG("port %d is not active: \"%s\" (%d)",
698 port, ibv_port_state_str(port_attr.state),
701 /* Allocate protection domain. */
702 pd = ibv_alloc_pd(ctx);
704 ERROR("PD allocation failure");
709 mlx5_dev[idx].ports |= test;
711 /* from rte_ethdev.c */
712 priv = rte_zmalloc("ethdev private structure",
714 RTE_CACHE_LINE_SIZE);
716 ERROR("priv allocation failure");
722 strncpy(priv->ibdev_path, priv->ctx->device->ibdev_path,
723 sizeof(priv->ibdev_path));
724 priv->device_attr = device_attr;
727 priv->mtu = ETHER_MTU;
728 priv->mps = mps; /* Enable MPW by default if supported. */
729 priv->cqe_comp = 1; /* Enable compression by default. */
730 priv->tunnel_en = tunnel_en;
731 /* Enable vector by default if supported. */
734 err = mlx5_args(&args, pci_dev->device.devargs);
736 ERROR("failed to process device arguments: %s",
740 mlx5_args_assign(priv, &args);
741 if (ibv_query_device_ex(ctx, NULL, &device_attr_ex)) {
742 ERROR("ibv_query_device_ex() failed");
747 !!(device_attr_ex.device_cap_flags_ex &
748 IBV_DEVICE_RAW_IP_CSUM);
749 DEBUG("checksum offloading is %ssupported",
750 (priv->hw_csum ? "" : "not "));
752 #ifdef HAVE_IBV_DEVICE_VXLAN_SUPPORT
753 priv->hw_csum_l2tun = !!(exp_device_attr.exp_device_cap_flags &
754 IBV_DEVICE_VXLAN_SUPPORT);
756 DEBUG("L2 tunnel checksum offloads are %ssupported",
757 (priv->hw_csum_l2tun ? "" : "not "));
759 priv->ind_table_max_size =
760 device_attr_ex.rss_caps.max_rwq_indirection_table_size;
761 /* Remove this check once DPDK supports larger/variable
762 * indirection tables. */
763 if (priv->ind_table_max_size >
764 (unsigned int)ETH_RSS_RETA_SIZE_512)
765 priv->ind_table_max_size = ETH_RSS_RETA_SIZE_512;
766 DEBUG("maximum RX indirection table size is %u",
767 priv->ind_table_max_size);
768 priv->hw_vlan_strip = !!(device_attr_ex.raw_packet_caps &
769 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
770 DEBUG("VLAN stripping is %ssupported",
771 (priv->hw_vlan_strip ? "" : "not "));
774 !!(device_attr_ex.orig_attr.device_cap_flags &
775 IBV_WQ_FLAGS_SCATTER_FCS);
776 DEBUG("FCS stripping configuration is %ssupported",
777 (priv->hw_fcs_strip ? "" : "not "));
779 #ifdef HAVE_IBV_WQ_FLAG_RX_END_PADDING
780 priv->hw_padding = !!device_attr_ex.rx_pad_end_addr_align;
782 DEBUG("hardware RX end alignment padding is %ssupported",
783 (priv->hw_padding ? "" : "not "));
785 priv_get_num_vfs(priv, &num_vfs);
786 priv->sriov = (num_vfs || sriov);
787 priv->tso = ((priv->tso) &&
788 (device_attr_ex.tso_caps.max_tso > 0) &&
789 (device_attr_ex.tso_caps.supported_qpts &
790 (1 << IBV_QPT_RAW_PACKET)));
792 priv->max_tso_payload_sz =
793 device_attr_ex.tso_caps.max_tso;
794 if (priv->mps && !mps) {
795 ERROR("multi-packet send not supported on this device"
796 " (" MLX5_TXQ_MPW_EN ")");
799 } else if (priv->mps && priv->tso) {
800 WARN("multi-packet send not supported in conjunction "
801 "with TSO. MPS disabled");
805 priv->mps == MLX5_MPW_ENHANCED ? "Enhanced " : "",
806 priv->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled");
807 /* Set default values for Enhanced MPW, a.k.a MPWv2. */
808 if (priv->mps == MLX5_MPW_ENHANCED) {
809 if (args.txqs_inline == MLX5_ARG_UNSET)
810 priv->txqs_inline = MLX5_EMPW_MIN_TXQS;
811 if (args.inline_max_packet_sz == MLX5_ARG_UNSET)
812 priv->inline_max_packet_sz =
813 MLX5_EMPW_MAX_INLINE_LEN;
814 if (args.txq_inline == MLX5_ARG_UNSET)
815 priv->txq_inline = MLX5_WQE_SIZE_MAX -
818 /* Allocate and register default RSS hash keys. */
819 priv->rss_conf = rte_calloc(__func__, hash_rxq_init_n,
820 sizeof((*priv->rss_conf)[0]), 0);
821 if (priv->rss_conf == NULL) {
825 err = rss_hash_rss_conf_new_key(priv,
826 rss_hash_default_key,
827 rss_hash_default_key_len,
831 /* Configure the first MAC address by default. */
832 if (priv_get_mac(priv, &mac.addr_bytes)) {
833 ERROR("cannot get MAC address, is mlx5_en loaded?"
834 " (errno: %s)", strerror(errno));
838 INFO("port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x",
840 mac.addr_bytes[0], mac.addr_bytes[1],
841 mac.addr_bytes[2], mac.addr_bytes[3],
842 mac.addr_bytes[4], mac.addr_bytes[5]);
843 /* Register MAC address. */
844 claim_zero(priv_mac_addr_add(priv, 0,
845 (const uint8_t (*)[ETHER_ADDR_LEN])
847 /* Initialize FD filters list. */
848 err = fdir_init_filters_list(priv);
853 char ifname[IF_NAMESIZE];
855 if (priv_get_ifname(priv, &ifname) == 0)
856 DEBUG("port %u ifname is \"%s\"",
859 DEBUG("port %u ifname is unknown", priv->port);
862 /* Get actual MTU if possible. */
863 priv_get_mtu(priv, &priv->mtu);
864 DEBUG("port %u MTU is %u", priv->port, priv->mtu);
866 /* from rte_ethdev.c */
868 char name[RTE_ETH_NAME_MAX_LEN];
870 snprintf(name, sizeof(name), "%s port %u",
871 ibv_get_device_name(ibv_dev), port);
872 eth_dev = rte_eth_dev_allocate(name);
874 if (eth_dev == NULL) {
875 ERROR("can not allocate rte ethdev");
879 eth_dev->data->dev_private = priv;
880 eth_dev->data->mac_addrs = priv->mac;
881 eth_dev->device = &pci_dev->device;
882 rte_eth_copy_pci_info(eth_dev, pci_dev);
883 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
884 eth_dev->device->driver = &mlx5_driver.driver;
886 eth_dev->dev_ops = &mlx5_dev_ops;
887 TAILQ_INIT(&priv->flows);
889 /* Hint libmlx5 to use PMD allocator for data plane resources */
890 struct mlx5dv_ctx_allocators alctr = {
891 .alloc = &mlx5_alloc_verbs_buf,
892 .free = &mlx5_free_verbs_buf,
895 mlx5dv_set_context_attr(ctx, MLX5DV_CTX_ATTR_BUF_ALLOCATORS,
896 (void *)((uintptr_t)&alctr));
898 /* Bring Ethernet device up. */
899 DEBUG("forcing Ethernet interface up");
900 priv_set_flags(priv, ~IFF_UP, IFF_UP);
901 mlx5_link_update(priv->dev, 1);
906 rte_free(priv->rss_conf);
910 claim_zero(ibv_dealloc_pd(pd));
912 claim_zero(ibv_close_device(ctx));
917 * XXX if something went wrong in the loop above, there is a resource
918 * leak (ctx, pd, priv, dpdk ethdev) but we can do nothing about it as
919 * long as the dpdk does not provide a way to deallocate a ethdev and a
920 * way to enumerate the registered ethdevs to free the previous ones.
923 /* no port found, complain */
924 if (!mlx5_dev[idx].ports) {
931 claim_zero(ibv_close_device(attr_ctx));
933 ibv_free_device_list(list);
938 static const struct rte_pci_id mlx5_pci_id_map[] = {
940 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
941 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
944 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
945 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
948 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
949 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
952 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
953 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
956 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
957 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
960 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
961 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
964 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
965 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
968 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
969 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
976 static struct rte_pci_driver mlx5_driver = {
978 .name = MLX5_DRIVER_NAME
980 .id_table = mlx5_pci_id_map,
981 .probe = mlx5_pci_probe,
982 .drv_flags = RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV,
986 * Driver initialization routine.
988 RTE_INIT(rte_mlx5_pmd_init);
990 rte_mlx5_pmd_init(void)
992 /* Build the static table for ptype conversion. */
993 mlx5_set_ptype_table();
995 * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use
996 * huge pages. Calling ibv_fork_init() during init allows
997 * applications to use fork() safely for purposes other than
998 * using this PMD, which is not supported in forked processes.
1000 setenv("RDMAV_HUGEPAGES_SAFE", "1", 1);
1001 /* Don't map UAR to WC if BlueFlame is not used.*/
1002 setenv("MLX5_SHUT_UP_BF", "1", 1);
1004 rte_pci_register(&mlx5_driver);
1007 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
1008 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
1009 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");