drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <stdint.h>
  10 #include <stdlib.h>
  11 #include <errno.h>
  12 #include <net/if.h>
  13 #include <sys/mman.h>
  14 #include <linux/rtnetlink.h>
  15
  16 /* Verbs header. */
  17 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  18 #ifdef PEDANTIC
  19 #pragma GCC diagnostic ignored "-Wpedantic"
  20 #endif
  21 #include <infiniband/verbs.h>
  22 #ifdef PEDANTIC
  23 #pragma GCC diagnostic error "-Wpedantic"
  24 #endif
  25
  26 #include <rte_malloc.h>
  27 #include <rte_ethdev_driver.h>
  28 #include <rte_ethdev_pci.h>
  29 #include <rte_pci.h>
  30 #include <rte_bus_pci.h>
  31 #include <rte_common.h>
  32 #include <rte_kvargs.h>
  33 #include <rte_rwlock.h>
  34 #include <rte_spinlock.h>
  35 #include <rte_string_fns.h>
  36 #include <rte_alarm.h>
  37
  38 #include <mlx5_glue.h>
  39 #include <mlx5_devx_cmds.h>
  40 #include <mlx5_common.h>
  41 #include <mlx5_common_mp.h>
  42
  43 #include "mlx5_defs.h"
  44 #include "mlx5.h"
  45 #include "mlx5_utils.h"
  46 #include "mlx5_rxtx.h"
  47 #include "mlx5_autoconf.h"
  48 #include "mlx5_mr.h"
  49 #include "mlx5_flow.h"
  50 #include "rte_pmd_mlx5.h"
  51
  52 /* Device parameter to enable RX completion queue compression. */
  53 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  54
  55 /* Device parameter to enable RX completion entry padding to 128B. */
  56 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
  57
  58 /* Device parameter to enable padding Rx packet to cacheline size. */
  59 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
  60
  61 /* Device parameter to enable Multi-Packet Rx queue. */
  62 #define MLX5_RX_MPRQ_EN "mprq_en"
  63
  64 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
  65 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
  66
  67 /* Device parameter to configure log 2 of the stride size for MPRQ. */
  68 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
  69
  70 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
  71 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
  72
  73 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
  74 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
  75
  76 /* Device parameter to configure inline send. Deprecated, ignored.*/
  77 #define MLX5_TXQ_INLINE "txq_inline"
  78
  79 /* Device parameter to limit packet size to inline with ordinary SEND. */
  80 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
  81
  82 /* Device parameter to configure minimal data size to inline. */
  83 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
  84
  85 /* Device parameter to limit packet size to inline with Enhanced MPW. */
  86 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
  87
  88 /*
  89  * Device parameter to configure the number of TX queues threshold for
  90  * enabling inline send.
  91  */
  92 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  93
  94 /*
  95  * Device parameter to configure the number of TX queues threshold for
  96  * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
  97  */
  98 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
  99
 100 /* Device parameter to enable multi-packet send WQEs. */
 101 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
 102
 103 /*
 104  * Device parameter to force doorbell register mapping
 105  * to non-cahed region eliminating the extra write memory barrier.
 106  */
 107 #define MLX5_TX_DB_NC "tx_db_nc"
 108
 109 /*
 110  * Device parameter to include 2 dsegs in the title WQEBB.
 111  * Deprecated, ignored.
 112  */
 113 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
 114
 115 /*
 116  * Device parameter to limit the size of inlining packet.
 117  * Deprecated, ignored.
 118  */
 119 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
 120
 121 /*
 122  * Device parameter to enable hardware Tx vector.
 123  * Deprecated, ignored (no vectorized Tx routines anymore).
 124  */
 125 #define MLX5_TX_VEC_EN "tx_vec_en"
 126
 127 /* Device parameter to enable hardware Rx vector. */
 128 #define MLX5_RX_VEC_EN "rx_vec_en"
 129
 130 /* Allow L3 VXLAN flow creation. */
 131 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
 132
 133 /* Activate DV E-Switch flow steering. */
 134 #define MLX5_DV_ESW_EN "dv_esw_en"
 135
 136 /* Activate DV flow steering. */
 137 #define MLX5_DV_FLOW_EN "dv_flow_en"
 138
 139 /* Enable extensive flow metadata support. */
 140 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
 141
 142 /* Activate Netlink support in VF mode. */
 143 #define MLX5_VF_NL_EN "vf_nl_en"
 144
 145 /* Enable extending memsegs when creating a MR. */
 146 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
 147
 148 /* Select port representors to instantiate. */
 149 #define MLX5_REPRESENTOR "representor"
 150
 151 /* Device parameter to configure the maximum number of dump files per queue. */
 152 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
 153
 154 /* Configure timeout of LRO session (in microseconds). */
 155 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
 156
 157 /*
 158  * Device parameter to configure the total data buffer size for a single
 159  * hairpin queue (logarithm value).
 160  */
 161 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
 162
 163 /* Flow memory reclaim mode. */
 164 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
 165
 166 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
 167
 168 /* Shared memory between primary and secondary processes. */
 169 struct mlx5_shared_data *mlx5_shared_data;
 170
 171 /* Spinlock for mlx5_shared_data allocation. */
 172 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
 173
 174 /* Process local data for secondary processes. */
 175 static struct mlx5_local_data mlx5_local_data;
 176 /** Driver-specific log messages type. */
 177 int mlx5_logtype;
 178
 179 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
 180                                                 LIST_HEAD_INITIALIZER();
 181 static pthread_mutex_t mlx5_dev_ctx_list_mutex = PTHREAD_MUTEX_INITIALIZER;
 182
 183 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
 184 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 185         {
 186                 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
 187                 .trunk_size = 64,
 188                 .grow_trunk = 3,
 189                 .grow_shift = 2,
 190                 .need_lock = 0,
 191                 .release_mem_en = 1,
 192                 .malloc = rte_malloc_socket,
 193                 .free = rte_free,
 194                 .type = "mlx5_encap_decap_ipool",
 195         },
 196         {
 197                 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
 198                 .trunk_size = 64,
 199                 .grow_trunk = 3,
 200                 .grow_shift = 2,
 201                 .need_lock = 0,
 202                 .release_mem_en = 1,
 203                 .malloc = rte_malloc_socket,
 204                 .free = rte_free,
 205                 .type = "mlx5_push_vlan_ipool",
 206         },
 207         {
 208                 .size = sizeof(struct mlx5_flow_dv_tag_resource),
 209                 .trunk_size = 64,
 210                 .grow_trunk = 3,
 211                 .grow_shift = 2,
 212                 .need_lock = 0,
 213                 .release_mem_en = 1,
 214                 .malloc = rte_malloc_socket,
 215                 .free = rte_free,
 216                 .type = "mlx5_tag_ipool",
 217         },
 218         {
 219                 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
 220                 .trunk_size = 64,
 221                 .grow_trunk = 3,
 222                 .grow_shift = 2,
 223                 .need_lock = 0,
 224                 .release_mem_en = 1,
 225                 .malloc = rte_malloc_socket,
 226                 .free = rte_free,
 227                 .type = "mlx5_port_id_ipool",
 228         },
 229         {
 230                 .size = sizeof(struct mlx5_flow_tbl_data_entry),
 231                 .trunk_size = 64,
 232                 .grow_trunk = 3,
 233                 .grow_shift = 2,
 234                 .need_lock = 0,
 235                 .release_mem_en = 1,
 236                 .malloc = rte_malloc_socket,
 237                 .free = rte_free,
 238                 .type = "mlx5_jump_ipool",
 239         },
 240 #endif
 241         {
 242                 .size = sizeof(struct mlx5_flow_meter),
 243                 .trunk_size = 64,
 244                 .grow_trunk = 3,
 245                 .grow_shift = 2,
 246                 .need_lock = 0,
 247                 .release_mem_en = 1,
 248                 .malloc = rte_malloc_socket,
 249                 .free = rte_free,
 250                 .type = "mlx5_meter_ipool",
 251         },
 252         {
 253                 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
 254                 .trunk_size = 64,
 255                 .grow_trunk = 3,
 256                 .grow_shift = 2,
 257                 .need_lock = 0,
 258                 .release_mem_en = 1,
 259                 .malloc = rte_malloc_socket,
 260                 .free = rte_free,
 261                 .type = "mlx5_mcp_ipool",
 262         },
 263         {
 264                 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
 265                 .trunk_size = 64,
 266                 .grow_trunk = 3,
 267                 .grow_shift = 2,
 268                 .need_lock = 0,
 269                 .release_mem_en = 1,
 270                 .malloc = rte_malloc_socket,
 271                 .free = rte_free,
 272                 .type = "mlx5_hrxq_ipool",
 273         },
 274         {
 275                 /*
 276                  * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
 277                  * It set in run time according to PCI function configuration.
 278                  */
 279                 .size = 0,
 280                 .trunk_size = 64,
 281                 .grow_trunk = 3,
 282                 .grow_shift = 2,
 283                 .need_lock = 0,
 284                 .release_mem_en = 1,
 285                 .malloc = rte_malloc_socket,
 286                 .free = rte_free,
 287                 .type = "mlx5_flow_handle_ipool",
 288         },
 289         {
 290                 .size = sizeof(struct rte_flow),
 291                 .trunk_size = 4096,
 292                 .need_lock = 1,
 293                 .release_mem_en = 1,
 294                 .malloc = rte_malloc_socket,
 295                 .free = rte_free,
 296                 .type = "rte_flow_ipool",
 297         },
 298 };
 299
 300
 301 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
 302 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
 303
 304 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
 305
 306 /**
 307  * Allocate ID pool structure.
 308  *
 309  * @param[in] max_id
 310  *   The maximum id can be allocated from the pool.
 311  *
 312  * @return
 313  *   Pointer to pool object, NULL value otherwise.
 314  */
 315 struct mlx5_flow_id_pool *
 316 mlx5_flow_id_pool_alloc(uint32_t max_id)
 317 {
 318         struct mlx5_flow_id_pool *pool;
 319         void *mem;
 320
 321         pool = rte_zmalloc("id pool allocation", sizeof(*pool),
 322                            RTE_CACHE_LINE_SIZE);
 323         if (!pool) {
 324                 DRV_LOG(ERR, "can't allocate id pool");
 325                 rte_errno  = ENOMEM;
 326                 return NULL;
 327         }
 328         mem = rte_zmalloc("", MLX5_FLOW_MIN_ID_POOL_SIZE * sizeof(uint32_t),
 329                           RTE_CACHE_LINE_SIZE);
 330         if (!mem) {
 331                 DRV_LOG(ERR, "can't allocate mem for id pool");
 332                 rte_errno  = ENOMEM;
 333                 goto error;
 334         }
 335         pool->free_arr = mem;
 336         pool->curr = pool->free_arr;
 337         pool->last = pool->free_arr + MLX5_FLOW_MIN_ID_POOL_SIZE;
 338         pool->base_index = 0;
 339         pool->max_id = max_id;
 340         return pool;
 341 error:
 342         rte_free(pool);
 343         return NULL;
 344 }
 345
 346 /**
 347  * Release ID pool structure.
 348  *
 349  * @param[in] pool
 350  *   Pointer to flow id pool object to free.
 351  */
 352 void
 353 mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool)
 354 {
 355         rte_free(pool->free_arr);
 356         rte_free(pool);
 357 }
 358
 359 /**
 360  * Generate ID.
 361  *
 362  * @param[in] pool
 363  *   Pointer to flow id pool.
 364  * @param[out] id
 365  *   The generated ID.
 366  *
 367  * @return
 368  *   0 on success, error value otherwise.
 369  */
 370 uint32_t
 371 mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id)
 372 {
 373         if (pool->curr == pool->free_arr) {
 374                 if (pool->base_index == pool->max_id) {
 375                         rte_errno  = ENOMEM;
 376                         DRV_LOG(ERR, "no free id");
 377                         return -rte_errno;
 378                 }
 379                 *id = ++pool->base_index;
 380                 return 0;
 381         }
 382         *id = *(--pool->curr);
 383         return 0;
 384 }
 385
 386 /**
 387  * Release ID.
 388  *
 389  * @param[in] pool
 390  *   Pointer to flow id pool.
 391  * @param[out] id
 392  *   The generated ID.
 393  *
 394  * @return
 395  *   0 on success, error value otherwise.
 396  */
 397 uint32_t
 398 mlx5_flow_id_release(struct mlx5_flow_id_pool *pool, uint32_t id)
 399 {
 400         uint32_t size;
 401         uint32_t size2;
 402         void *mem;
 403
 404         if (pool->curr == pool->last) {
 405                 size = pool->curr - pool->free_arr;
 406                 size2 = size * MLX5_ID_GENERATION_ARRAY_FACTOR;
 407                 MLX5_ASSERT(size2 > size);
 408                 mem = rte_malloc("", size2 * sizeof(uint32_t), 0);
 409                 if (!mem) {
 410                         DRV_LOG(ERR, "can't allocate mem for id pool");
 411                         rte_errno  = ENOMEM;
 412                         return -rte_errno;
 413                 }
 414                 memcpy(mem, pool->free_arr, size * sizeof(uint32_t));
 415                 rte_free(pool->free_arr);
 416                 pool->free_arr = mem;
 417                 pool->curr = pool->free_arr + size;
 418                 pool->last = pool->free_arr + size2;
 419         }
 420         *pool->curr = id;
 421         pool->curr++;
 422         return 0;
 423 }
 424
 425 /**
 426  * Initialize the shared aging list information per port.
 427  *
 428  * @param[in] sh
 429  *   Pointer to mlx5_dev_ctx_shared object.
 430  */
 431 static void
 432 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
 433 {
 434         uint32_t i;
 435         struct mlx5_age_info *age_info;
 436
 437         for (i = 0; i < sh->max_port; i++) {
 438                 age_info = &sh->port[i].age_info;
 439                 age_info->flags = 0;
 440                 TAILQ_INIT(&age_info->aged_counters);
 441                 rte_spinlock_init(&age_info->aged_sl);
 442                 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
 443         }
 444 }
 445
 446 /**
 447  * Initialize the counters management structure.
 448  *
 449  * @param[in] sh
 450  *   Pointer to mlx5_dev_ctx_shared object to free
 451  */
 452 static void
 453 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
 454 {
 455         int i;
 456
 457         memset(&sh->cmng, 0, sizeof(sh->cmng));
 458         TAILQ_INIT(&sh->cmng.flow_counters);
 459         for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
 460                 sh->cmng.ccont[i].min_id = MLX5_CNT_BATCH_OFFSET;
 461                 sh->cmng.ccont[i].max_id = -1;
 462                 sh->cmng.ccont[i].last_pool_idx = POOL_IDX_INVALID;
 463                 TAILQ_INIT(&sh->cmng.ccont[i].pool_list);
 464                 rte_spinlock_init(&sh->cmng.ccont[i].resize_sl);
 465         }
 466 }
 467
 468 /**
 469  * Destroy all the resources allocated for a counter memory management.
 470  *
 471  * @param[in] mng
 472  *   Pointer to the memory management structure.
 473  */
 474 static void
 475 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
 476 {
 477         uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
 478
 479         LIST_REMOVE(mng, next);
 480         claim_zero(mlx5_devx_cmd_destroy(mng->dm));
 481         claim_zero(mlx5_glue->devx_umem_dereg(mng->umem));
 482         rte_free(mem);
 483 }
 484
 485 /**
 486  * Close and release all the resources of the counters management.
 487  *
 488  * @param[in] sh
 489  *   Pointer to mlx5_dev_ctx_shared object to free.
 490  */
 491 static void
 492 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
 493 {
 494         struct mlx5_counter_stats_mem_mng *mng;
 495         int i;
 496         int j;
 497         int retries = 1024;
 498
 499         rte_errno = 0;
 500         while (--retries) {
 501                 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
 502                 if (rte_errno != EINPROGRESS)
 503                         break;
 504                 rte_pause();
 505         }
 506         for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
 507                 struct mlx5_flow_counter_pool *pool;
 508                 uint32_t batch = !!(i > 1);
 509
 510                 if (!sh->cmng.ccont[i].pools)
 511                         continue;
 512                 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
 513                 while (pool) {
 514                         if (batch && pool->min_dcs)
 515                                 claim_zero(mlx5_devx_cmd_destroy
 516                                                                (pool->min_dcs));
 517                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
 518                                 if (MLX5_POOL_GET_CNT(pool, j)->action)
 519                                         claim_zero
 520                                          (mlx5_glue->destroy_flow_action
 521                                           (MLX5_POOL_GET_CNT
 522                                           (pool, j)->action));
 523                                 if (!batch && MLX5_GET_POOL_CNT_EXT
 524                                     (pool, j)->dcs)
 525                                         claim_zero(mlx5_devx_cmd_destroy
 526                                                    (MLX5_GET_POOL_CNT_EXT
 527                                                     (pool, j)->dcs));
 528                         }
 529                         TAILQ_REMOVE(&sh->cmng.ccont[i].pool_list, pool, next);
 530                         rte_free(pool);
 531                         pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
 532                 }
 533                 rte_free(sh->cmng.ccont[i].pools);
 534         }
 535         mng = LIST_FIRST(&sh->cmng.mem_mngs);
 536         while (mng) {
 537                 mlx5_flow_destroy_counter_stat_mem_mng(mng);
 538                 mng = LIST_FIRST(&sh->cmng.mem_mngs);
 539         }
 540         memset(&sh->cmng, 0, sizeof(sh->cmng));
 541 }
 542
 543 /**
 544  * Initialize the flow resources' indexed mempool.
 545  *
 546  * @param[in] sh
 547  *   Pointer to mlx5_dev_ctx_shared object.
 548  * @param[in] sh
 549  *   Pointer to user dev config.
 550  */
 551 static void
 552 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
 553                        const struct mlx5_dev_config *config)
 554 {
 555         uint8_t i;
 556         struct mlx5_indexed_pool_config cfg;
 557
 558         for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
 559                 cfg = mlx5_ipool_cfg[i];
 560                 switch (i) {
 561                 default:
 562                         break;
 563                 /*
 564                  * Set MLX5_IPOOL_MLX5_FLOW ipool size
 565                  * according to PCI function flow configuration.
 566                  */
 567                 case MLX5_IPOOL_MLX5_FLOW:
 568                         cfg.size = config->dv_flow_en ?
 569                                 sizeof(struct mlx5_flow_handle) :
 570                                 MLX5_FLOW_HANDLE_VERBS_SIZE;
 571                         break;
 572                 }
 573                 if (config->reclaim_mode)
 574                         cfg.release_mem_en = 1;
 575                 sh->ipool[i] = mlx5_ipool_create(&cfg);
 576         }
 577 }
 578
 579 /**
 580  * Release the flow resources' indexed mempool.
 581  *
 582  * @param[in] sh
 583  *   Pointer to mlx5_dev_ctx_shared object.
 584  */
 585 static void
 586 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
 587 {
 588         uint8_t i;
 589
 590         for (i = 0; i < MLX5_IPOOL_MAX; ++i)
 591                 mlx5_ipool_destroy(sh->ipool[i]);
 592 }
 593
 594 /**
 595  * Allocate shared device context. If there is multiport device the
 596  * master and representors will share this context, if there is single
 597  * port dedicated device, the context will be used by only given
 598  * port due to unification.
 599  *
 600  * Routine first searches the context for the specified device name,
 601  * if found the shared context assumed and reference counter is incremented.
 602  * If no context found the new one is created and initialized with specified
 603  * device context and parameters.
 604  *
 605  * @param[in] spawn
 606  *   Pointer to the device attributes (name, port, etc).
 607  * @param[in] config
 608  *   Pointer to device configuration structure.
 609  *
 610  * @return
 611  *   Pointer to mlx5_dev_ctx_shared object on success,
 612  *   otherwise NULL and rte_errno is set.
 613  */
 614 struct mlx5_dev_ctx_shared *
 615 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
 616                            const struct mlx5_dev_config *config)
 617 {
 618         struct mlx5_dev_ctx_shared *sh;
 619         int err = 0;
 620         uint32_t i;
 621         struct mlx5_devx_tis_attr tis_attr = { 0 };
 622
 623         MLX5_ASSERT(spawn);
 624         /* Secondary process should not create the shared context. */
 625         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 626         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
 627         /* Search for IB context by device name. */
 628         LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
 629                 if (!strcmp(sh->ibdev_name,
 630                         mlx5_os_get_dev_device_name(spawn->phys_dev))) {
 631                         sh->refcnt++;
 632                         goto exit;
 633                 }
 634         }
 635         /* No device found, we have to create new shared context. */
 636         MLX5_ASSERT(spawn->max_port);
 637         sh = rte_zmalloc("ethdev shared ib context",
 638                          sizeof(struct mlx5_dev_ctx_shared) +
 639                          spawn->max_port *
 640                          sizeof(struct mlx5_dev_shared_port),
 641                          RTE_CACHE_LINE_SIZE);
 642         if (!sh) {
 643                 DRV_LOG(ERR, "shared context allocation failure");
 644                 rte_errno  = ENOMEM;
 645                 goto exit;
 646         }
 647         err = mlx5_os_open_device(spawn, config, sh);
 648         if (!sh->ctx)
 649                 goto error;
 650         err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
 651         if (err) {
 652                 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
 653                 goto error;
 654         }
 655         sh->refcnt = 1;
 656         sh->max_port = spawn->max_port;
 657         strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
 658                 sizeof(sh->ibdev_name) - 1);
 659         strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
 660                 sizeof(sh->ibdev_path) - 1);
 661         /*
 662          * Setting port_id to max unallowed value means
 663          * there is no interrupt subhandler installed for
 664          * the given port index i.
 665          */
 666         for (i = 0; i < sh->max_port; i++) {
 667                 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
 668                 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
 669         }
 670         sh->pd = mlx5_glue->alloc_pd(sh->ctx);
 671         if (sh->pd == NULL) {
 672                 DRV_LOG(ERR, "PD allocation failure");
 673                 err = ENOMEM;
 674                 goto error;
 675         }
 676         if (sh->devx) {
 677                 err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
 678                 if (err) {
 679                         DRV_LOG(ERR, "Fail to extract pdn from PD");
 680                         goto error;
 681                 }
 682                 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
 683                 if (!sh->td) {
 684                         DRV_LOG(ERR, "TD allocation failure");
 685                         err = ENOMEM;
 686                         goto error;
 687                 }
 688                 tis_attr.transport_domain = sh->td->id;
 689                 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
 690                 if (!sh->tis) {
 691                         DRV_LOG(ERR, "TIS allocation failure");
 692                         err = ENOMEM;
 693                         goto error;
 694                 }
 695         }
 696         sh->flow_id_pool = mlx5_flow_id_pool_alloc
 697                                         ((1 << HAIRPIN_FLOW_ID_BITS) - 1);
 698         if (!sh->flow_id_pool) {
 699                 DRV_LOG(ERR, "can't create flow id pool");
 700                 err = ENOMEM;
 701                 goto error;
 702         }
 703         /*
 704          * Once the device is added to the list of memory event
 705          * callback, its global MR cache table cannot be expanded
 706          * on the fly because of deadlock. If it overflows, lookup
 707          * should be done by searching MR list linearly, which is slow.
 708          *
 709          * At this point the device is not added to the memory
 710          * event list yet, context is just being created.
 711          */
 712         err = mlx5_mr_btree_init(&sh->share_cache.cache,
 713                                  MLX5_MR_BTREE_CACHE_N * 2,
 714                                  spawn->pci_dev->device.numa_node);
 715         if (err) {
 716                 err = rte_errno;
 717                 goto error;
 718         }
 719         mlx5_os_set_reg_mr_cb(&sh->share_cache.reg_mr_cb,
 720                               &sh->share_cache.dereg_mr_cb);
 721         mlx5_os_dev_shared_handler_install(sh);
 722         sh->cnt_id_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_DWORD);
 723         if (!sh->cnt_id_tbl) {
 724                 err = rte_errno;
 725                 goto error;
 726         }
 727         mlx5_flow_aging_init(sh);
 728         mlx5_flow_counters_mng_init(sh);
 729         mlx5_flow_ipool_create(sh, config);
 730         /* Add device to memory callback list. */
 731         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
 732         LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
 733                          sh, mem_event_cb);
 734         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
 735         /* Add context to the global device list. */
 736         LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
 737 exit:
 738         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
 739         return sh;
 740 error:
 741         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
 742         MLX5_ASSERT(sh);
 743         if (sh->cnt_id_tbl) {
 744                 mlx5_l3t_destroy(sh->cnt_id_tbl);
 745                 sh->cnt_id_tbl = NULL;
 746         }
 747         if (sh->tis)
 748                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
 749         if (sh->td)
 750                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
 751         if (sh->pd)
 752                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
 753         if (sh->ctx)
 754                 claim_zero(mlx5_glue->close_device(sh->ctx));
 755         if (sh->flow_id_pool)
 756                 mlx5_flow_id_pool_release(sh->flow_id_pool);
 757         rte_free(sh);
 758         MLX5_ASSERT(err > 0);
 759         rte_errno = err;
 760         return NULL;
 761 }
 762
 763 /**
 764  * Free shared IB device context. Decrement counter and if zero free
 765  * all allocated resources and close handles.
 766  *
 767  * @param[in] sh
 768  *   Pointer to mlx5_dev_ctx_shared object to free
 769  */
 770 void
 771 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
 772 {
 773         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
 774 #ifdef RTE_LIBRTE_MLX5_DEBUG
 775         /* Check the object presence in the list. */
 776         struct mlx5_dev_ctx_shared *lctx;
 777
 778         LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
 779                 if (lctx == sh)
 780                         break;
 781         MLX5_ASSERT(lctx);
 782         if (lctx != sh) {
 783                 DRV_LOG(ERR, "Freeing non-existing shared IB context");
 784                 goto exit;
 785         }
 786 #endif
 787         MLX5_ASSERT(sh);
 788         MLX5_ASSERT(sh->refcnt);
 789         /* Secondary process should not free the shared context. */
 790         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 791         if (--sh->refcnt)
 792                 goto exit;
 793         /* Remove from memory callback device list. */
 794         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
 795         LIST_REMOVE(sh, mem_event_cb);
 796         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
 797         /* Release created Memory Regions. */
 798         mlx5_mr_release_cache(&sh->share_cache);
 799         /* Remove context from the global device list. */
 800         LIST_REMOVE(sh, next);
 801         /*
 802          *  Ensure there is no async event handler installed.
 803          *  Only primary process handles async device events.
 804          **/
 805         mlx5_flow_counters_mng_close(sh);
 806         mlx5_flow_ipool_destroy(sh);
 807         mlx5_os_dev_shared_handler_uninstall(sh);
 808         if (sh->cnt_id_tbl) {
 809                 mlx5_l3t_destroy(sh->cnt_id_tbl);
 810                 sh->cnt_id_tbl = NULL;
 811         }
 812         if (sh->pd)
 813                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
 814         if (sh->tis)
 815                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
 816         if (sh->td)
 817                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
 818         if (sh->ctx)
 819                 claim_zero(mlx5_glue->close_device(sh->ctx));
 820         if (sh->flow_id_pool)
 821                 mlx5_flow_id_pool_release(sh->flow_id_pool);
 822         rte_free(sh);
 823 exit:
 824         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
 825 }
 826
 827 /**
 828  * Destroy table hash list and all the root entries per domain.
 829  *
 830  * @param[in] priv
 831  *   Pointer to the private device data structure.
 832  */
 833 void
 834 mlx5_free_table_hash_list(struct mlx5_priv *priv)
 835 {
 836         struct mlx5_dev_ctx_shared *sh = priv->sh;
 837         struct mlx5_flow_tbl_data_entry *tbl_data;
 838         union mlx5_flow_tbl_key table_key = {
 839                 {
 840                         .table_id = 0,
 841                         .reserved = 0,
 842                         .domain = 0,
 843                         .direction = 0,
 844                 }
 845         };
 846         struct mlx5_hlist_entry *pos;
 847
 848         if (!sh->flow_tbls)
 849                 return;
 850         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 851         if (pos) {
 852                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 853                                         entry);
 854                 MLX5_ASSERT(tbl_data);
 855                 mlx5_hlist_remove(sh->flow_tbls, pos);
 856                 rte_free(tbl_data);
 857         }
 858         table_key.direction = 1;
 859         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 860         if (pos) {
 861                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 862                                         entry);
 863                 MLX5_ASSERT(tbl_data);
 864                 mlx5_hlist_remove(sh->flow_tbls, pos);
 865                 rte_free(tbl_data);
 866         }
 867         table_key.direction = 0;
 868         table_key.domain = 1;
 869         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 870         if (pos) {
 871                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 872                                         entry);
 873                 MLX5_ASSERT(tbl_data);
 874                 mlx5_hlist_remove(sh->flow_tbls, pos);
 875                 rte_free(tbl_data);
 876         }
 877         mlx5_hlist_destroy(sh->flow_tbls, NULL, NULL);
 878 }
 879
 880 /**
 881  * Initialize flow table hash list and create the root tables entry
 882  * for each domain.
 883  *
 884  * @param[in] priv
 885  *   Pointer to the private device data structure.
 886  *
 887  * @return
 888  *   Zero on success, positive error code otherwise.
 889  */
 890 int
 891 mlx5_alloc_table_hash_list(struct mlx5_priv *priv)
 892 {
 893         struct mlx5_dev_ctx_shared *sh = priv->sh;
 894         char s[MLX5_HLIST_NAMESIZE];
 895         int err = 0;
 896
 897         MLX5_ASSERT(sh);
 898         snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
 899         sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE);
 900         if (!sh->flow_tbls) {
 901                 DRV_LOG(ERR, "flow tables with hash creation failed.");
 902                 err = ENOMEM;
 903                 return err;
 904         }
 905 #ifndef HAVE_MLX5DV_DR
 906         /*
 907          * In case we have not DR support, the zero tables should be created
 908          * because DV expect to see them even if they cannot be created by
 909          * RDMA-CORE.
 910          */
 911         union mlx5_flow_tbl_key table_key = {
 912                 {
 913                         .table_id = 0,
 914                         .reserved = 0,
 915                         .domain = 0,
 916                         .direction = 0,
 917                 }
 918         };
 919         struct mlx5_flow_tbl_data_entry *tbl_data = rte_zmalloc(NULL,
 920                                                           sizeof(*tbl_data), 0);
 921
 922         if (!tbl_data) {
 923                 err = ENOMEM;
 924                 goto error;
 925         }
 926         tbl_data->entry.key = table_key.v64;
 927         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
 928         if (err)
 929                 goto error;
 930         rte_atomic32_init(&tbl_data->tbl.refcnt);
 931         rte_atomic32_inc(&tbl_data->tbl.refcnt);
 932         table_key.direction = 1;
 933         tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
 934         if (!tbl_data) {
 935                 err = ENOMEM;
 936                 goto error;
 937         }
 938         tbl_data->entry.key = table_key.v64;
 939         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
 940         if (err)
 941                 goto error;
 942         rte_atomic32_init(&tbl_data->tbl.refcnt);
 943         rte_atomic32_inc(&tbl_data->tbl.refcnt);
 944         table_key.direction = 0;
 945         table_key.domain = 1;
 946         tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
 947         if (!tbl_data) {
 948                 err = ENOMEM;
 949                 goto error;
 950         }
 951         tbl_data->entry.key = table_key.v64;
 952         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
 953         if (err)
 954                 goto error;
 955         rte_atomic32_init(&tbl_data->tbl.refcnt);
 956         rte_atomic32_inc(&tbl_data->tbl.refcnt);
 957         return err;
 958 error:
 959         mlx5_free_table_hash_list(priv);
 960 #endif /* HAVE_MLX5DV_DR */
 961         return err;
 962 }
 963
 964 /**
 965  * Initialize shared data between primary and secondary process.
 966  *
 967  * A memzone is reserved by primary process and secondary processes attach to
 968  * the memzone.
 969  *
 970  * @return
 971  *   0 on success, a negative errno value otherwise and rte_errno is set.
 972  */
 973 static int
 974 mlx5_init_shared_data(void)
 975 {
 976         const struct rte_memzone *mz;
 977         int ret = 0;
 978
 979         rte_spinlock_lock(&mlx5_shared_data_lock);
 980         if (mlx5_shared_data == NULL) {
 981                 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
 982                         /* Allocate shared memory. */
 983                         mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
 984                                                  sizeof(*mlx5_shared_data),
 985                                                  SOCKET_ID_ANY, 0);
 986                         if (mz == NULL) {
 987                                 DRV_LOG(ERR,
 988                                         "Cannot allocate mlx5 shared data");
 989                                 ret = -rte_errno;
 990                                 goto error;
 991                         }
 992                         mlx5_shared_data = mz->addr;
 993                         memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data));
 994                         rte_spinlock_init(&mlx5_shared_data->lock);
 995                 } else {
 996                         /* Lookup allocated shared memory. */
 997                         mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA);
 998                         if (mz == NULL) {
 999                                 DRV_LOG(ERR,
1000                                         "Cannot attach mlx5 shared data");
1001                                 ret = -rte_errno;
1002                                 goto error;
1003                         }
1004                         mlx5_shared_data = mz->addr;
1005                         memset(&mlx5_local_data, 0, sizeof(mlx5_local_data));
1006                 }
1007         }
1008 error:
1009         rte_spinlock_unlock(&mlx5_shared_data_lock);
1010         return ret;
1011 }
1012
1013 /**
1014  * Retrieve integer value from environment variable.
1015  *
1016  * @param[in] name
1017  *   Environment variable name.
1018  *
1019  * @return
1020  *   Integer value, 0 if the variable is not set.
1021  */
1022 int
1023 mlx5_getenv_int(const char *name)
1024 {
1025         const char *val = getenv(name);
1026
1027         if (val == NULL)
1028                 return 0;
1029         return atoi(val);
1030 }
1031
1032 /**
1033  * DPDK callback to add udp tunnel port
1034  *
1035  * @param[in] dev
1036  *   A pointer to eth_dev
1037  * @param[in] udp_tunnel
1038  *   A pointer to udp tunnel
1039  *
1040  * @return
1041  *   0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1042  */
1043 int
1044 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1045                          struct rte_eth_udp_tunnel *udp_tunnel)
1046 {
1047         MLX5_ASSERT(udp_tunnel != NULL);
1048         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1049             udp_tunnel->udp_port == 4789)
1050                 return 0;
1051         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1052             udp_tunnel->udp_port == 4790)
1053                 return 0;
1054         return -ENOTSUP;
1055 }
1056
1057 /**
1058  * Initialize process private data structure.
1059  *
1060  * @param dev
1061  *   Pointer to Ethernet device structure.
1062  *
1063  * @return
1064  *   0 on success, a negative errno value otherwise and rte_errno is set.
1065  */
1066 int
1067 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1068 {
1069         struct mlx5_priv *priv = dev->data->dev_private;
1070         struct mlx5_proc_priv *ppriv;
1071         size_t ppriv_size;
1072
1073         /*
1074          * UAR register table follows the process private structure. BlueFlame
1075          * registers for Tx queues are stored in the table.
1076          */
1077         ppriv_size =
1078                 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1079         ppriv = rte_malloc_socket("mlx5_proc_priv", ppriv_size,
1080                                   RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1081         if (!ppriv) {
1082                 rte_errno = ENOMEM;
1083                 return -rte_errno;
1084         }
1085         ppriv->uar_table_sz = ppriv_size;
1086         dev->process_private = ppriv;
1087         return 0;
1088 }
1089
1090 /**
1091  * Un-initialize process private data structure.
1092  *
1093  * @param dev
1094  *   Pointer to Ethernet device structure.
1095  */
1096 static void
1097 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1098 {
1099         if (!dev->process_private)
1100                 return;
1101         rte_free(dev->process_private);
1102         dev->process_private = NULL;
1103 }
1104
1105 /**
1106  * DPDK callback to close the device.
1107  *
1108  * Destroy all queues and objects, free memory.
1109  *
1110  * @param dev
1111  *   Pointer to Ethernet device structure.
1112  */
1113 void
1114 mlx5_dev_close(struct rte_eth_dev *dev)
1115 {
1116         struct mlx5_priv *priv = dev->data->dev_private;
1117         unsigned int i;
1118         int ret;
1119
1120         if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1121                 /* Check if process_private released. */
1122                 if (!dev->process_private)
1123                         return;
1124                 mlx5_tx_uar_uninit_secondary(dev);
1125                 mlx5_proc_priv_uninit(dev);
1126                 rte_eth_dev_release_port(dev);
1127                 return;
1128         }
1129         if (!priv->sh)
1130                 return;
1131         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1132                 dev->data->port_id,
1133                 ((priv->sh->ctx != NULL) ?
1134                 mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
1135         /*
1136          * If default mreg copy action is removed at the stop stage,
1137          * the search will return none and nothing will be done anymore.
1138          */
1139         mlx5_flow_stop_default(dev);
1140         mlx5_traffic_disable(dev);
1141         /*
1142          * If all the flows are already flushed in the device stop stage,
1143          * then this will return directly without any action.
1144          */
1145         mlx5_flow_list_flush(dev, &priv->flows, true);
1146         mlx5_flow_meter_flush(dev, NULL);
1147         /* Free the intermediate buffers for flow creation. */
1148         mlx5_flow_free_intermediate(dev);
1149         /* Prevent crashes when queues are still in use. */
1150         dev->rx_pkt_burst = removed_rx_burst;
1151         dev->tx_pkt_burst = removed_tx_burst;
1152         rte_wmb();
1153         /* Disable datapath on secondary process. */
1154         mlx5_mp_req_stop_rxtx(dev);
1155         if (priv->rxqs != NULL) {
1156                 /* XXX race condition if mlx5_rx_burst() is still running. */
1157                 usleep(1000);
1158                 for (i = 0; (i != priv->rxqs_n); ++i)
1159                         mlx5_rxq_release(dev, i);
1160                 priv->rxqs_n = 0;
1161                 priv->rxqs = NULL;
1162         }
1163         if (priv->txqs != NULL) {
1164                 /* XXX race condition if mlx5_tx_burst() is still running. */
1165                 usleep(1000);
1166                 for (i = 0; (i != priv->txqs_n); ++i)
1167                         mlx5_txq_release(dev, i);
1168                 priv->txqs_n = 0;
1169                 priv->txqs = NULL;
1170         }
1171         mlx5_proc_priv_uninit(dev);
1172         if (priv->mreg_cp_tbl)
1173                 mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
1174         mlx5_mprq_free_mp(dev);
1175         mlx5_os_free_shared_dr(priv);
1176         if (priv->rss_conf.rss_key != NULL)
1177                 rte_free(priv->rss_conf.rss_key);
1178         if (priv->reta_idx != NULL)
1179                 rte_free(priv->reta_idx);
1180         if (priv->config.vf)
1181                 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev),
1182                                        dev->data->mac_addrs,
1183                                        MLX5_MAX_MAC_ADDRESSES, priv->mac_own);
1184         if (priv->nl_socket_route >= 0)
1185                 close(priv->nl_socket_route);
1186         if (priv->nl_socket_rdma >= 0)
1187                 close(priv->nl_socket_rdma);
1188         if (priv->vmwa_context)
1189                 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1190         ret = mlx5_hrxq_verify(dev);
1191         if (ret)
1192                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1193                         dev->data->port_id);
1194         ret = mlx5_ind_table_obj_verify(dev);
1195         if (ret)
1196                 DRV_LOG(WARNING, "port %u some indirection table still remain",
1197                         dev->data->port_id);
1198         ret = mlx5_rxq_obj_verify(dev);
1199         if (ret)
1200                 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1201                         dev->data->port_id);
1202         ret = mlx5_rxq_verify(dev);
1203         if (ret)
1204                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1205                         dev->data->port_id);
1206         ret = mlx5_txq_obj_verify(dev);
1207         if (ret)
1208                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1209                         dev->data->port_id);
1210         ret = mlx5_txq_verify(dev);
1211         if (ret)
1212                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1213                         dev->data->port_id);
1214         ret = mlx5_flow_verify(dev);
1215         if (ret)
1216                 DRV_LOG(WARNING, "port %u some flows still remain",
1217                         dev->data->port_id);
1218         /*
1219          * Free the shared context in last turn, because the cleanup
1220          * routines above may use some shared fields, like
1221          * mlx5_nl_mac_addr_flush() uses ibdev_path for retrieveing
1222          * ifindex if Netlink fails.
1223          */
1224         mlx5_free_shared_dev_ctx(priv->sh);
1225         if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1226                 unsigned int c = 0;
1227                 uint16_t port_id;
1228
1229                 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1230                         struct mlx5_priv *opriv =
1231                                 rte_eth_devices[port_id].data->dev_private;
1232
1233                         if (!opriv ||
1234                             opriv->domain_id != priv->domain_id ||
1235                             &rte_eth_devices[port_id] == dev)
1236                                 continue;
1237                         ++c;
1238                         break;
1239                 }
1240                 if (!c)
1241                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1242         }
1243         memset(priv, 0, sizeof(*priv));
1244         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1245         /*
1246          * Reset mac_addrs to NULL such that it is not freed as part of
1247          * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1248          * it is freed when dev_private is freed.
1249          */
1250         dev->data->mac_addrs = NULL;
1251 }
1252
1253 /**
1254  * Verify and store value for device argument.
1255  *
1256  * @param[in] key
1257  *   Key argument to verify.
1258  * @param[in] val
1259  *   Value associated with key.
1260  * @param opaque
1261  *   User data.
1262  *
1263  * @return
1264  *   0 on success, a negative errno value otherwise and rte_errno is set.
1265  */
1266 static int
1267 mlx5_args_check(const char *key, const char *val, void *opaque)
1268 {
1269         struct mlx5_dev_config *config = opaque;
1270         unsigned long tmp;
1271
1272         /* No-op, port representors are processed in mlx5_dev_spawn(). */
1273         if (!strcmp(MLX5_REPRESENTOR, key))
1274                 return 0;
1275         errno = 0;
1276         tmp = strtoul(val, NULL, 0);
1277         if (errno) {
1278                 rte_errno = errno;
1279                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1280                 return -rte_errno;
1281         }
1282         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1283                 config->cqe_comp = !!tmp;
1284         } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
1285                 config->cqe_pad = !!tmp;
1286         } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1287                 config->hw_padding = !!tmp;
1288         } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1289                 config->mprq.enabled = !!tmp;
1290         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1291                 config->mprq.stride_num_n = tmp;
1292         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1293                 config->mprq.stride_size_n = tmp;
1294         } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1295                 config->mprq.max_memcpy_len = tmp;
1296         } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1297                 config->mprq.min_rxqs_num = tmp;
1298         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1299                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1300                                  " converted to txq_inline_max", key);
1301                 config->txq_inline_max = tmp;
1302         } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1303                 config->txq_inline_max = tmp;
1304         } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1305                 config->txq_inline_min = tmp;
1306         } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1307                 config->txq_inline_mpw = tmp;
1308         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1309                 config->txqs_inline = tmp;
1310         } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1311                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1312         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1313                 config->mps = !!tmp;
1314         } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1315                 if (tmp != MLX5_TXDB_CACHED &&
1316                     tmp != MLX5_TXDB_NCACHED &&
1317                     tmp != MLX5_TXDB_HEURISTIC) {
1318                         DRV_LOG(ERR, "invalid Tx doorbell "
1319                                      "mapping parameter");
1320                         rte_errno = EINVAL;
1321                         return -rte_errno;
1322                 }
1323                 config->dbnc = tmp;
1324         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1325                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1326         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1327                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1328                                  " converted to txq_inline_mpw", key);
1329                 config->txq_inline_mpw = tmp;
1330         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1331                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1332         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1333                 config->rx_vec_en = !!tmp;
1334         } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1335                 config->l3_vxlan_en = !!tmp;
1336         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1337                 config->vf_nl_en = !!tmp;
1338         } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1339                 config->dv_esw_en = !!tmp;
1340         } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1341                 config->dv_flow_en = !!tmp;
1342         } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1343                 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1344                     tmp != MLX5_XMETA_MODE_META16 &&
1345                     tmp != MLX5_XMETA_MODE_META32) {
1346                         DRV_LOG(ERR, "invalid extensive "
1347                                      "metadata parameter");
1348                         rte_errno = EINVAL;
1349                         return -rte_errno;
1350                 }
1351                 config->dv_xmeta_en = tmp;
1352         } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1353                 config->mr_ext_memseg_en = !!tmp;
1354         } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1355                 config->max_dump_files_num = tmp;
1356         } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1357                 config->lro.timeout = tmp;
1358         } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1359                 DRV_LOG(DEBUG, "class argument is %s.", val);
1360         } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1361                 config->log_hp_size = tmp;
1362         } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1363                 if (tmp != MLX5_RCM_NONE &&
1364                     tmp != MLX5_RCM_LIGHT &&
1365                     tmp != MLX5_RCM_AGGR) {
1366                         DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1367                         rte_errno = EINVAL;
1368                         return -rte_errno;
1369                 }
1370                 config->reclaim_mode = tmp;
1371         } else {
1372                 DRV_LOG(WARNING, "%s: unknown parameter", key);
1373                 rte_errno = EINVAL;
1374                 return -rte_errno;
1375         }
1376         return 0;
1377 }
1378
1379 /**
1380  * Parse device parameters.
1381  *
1382  * @param config
1383  *   Pointer to device configuration structure.
1384  * @param devargs
1385  *   Device arguments structure.
1386  *
1387  * @return
1388  *   0 on success, a negative errno value otherwise and rte_errno is set.
1389  */
1390 int
1391 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1392 {
1393         const char **params = (const char *[]){
1394                 MLX5_RXQ_CQE_COMP_EN,
1395                 MLX5_RXQ_CQE_PAD_EN,
1396                 MLX5_RXQ_PKT_PAD_EN,
1397                 MLX5_RX_MPRQ_EN,
1398                 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1399                 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1400                 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1401                 MLX5_RXQS_MIN_MPRQ,
1402                 MLX5_TXQ_INLINE,
1403                 MLX5_TXQ_INLINE_MIN,
1404                 MLX5_TXQ_INLINE_MAX,
1405                 MLX5_TXQ_INLINE_MPW,
1406                 MLX5_TXQS_MIN_INLINE,
1407                 MLX5_TXQS_MAX_VEC,
1408                 MLX5_TXQ_MPW_EN,
1409                 MLX5_TXQ_MPW_HDR_DSEG_EN,
1410                 MLX5_TXQ_MAX_INLINE_LEN,
1411                 MLX5_TX_DB_NC,
1412                 MLX5_TX_VEC_EN,
1413                 MLX5_RX_VEC_EN,
1414                 MLX5_L3_VXLAN_EN,
1415                 MLX5_VF_NL_EN,
1416                 MLX5_DV_ESW_EN,
1417                 MLX5_DV_FLOW_EN,
1418                 MLX5_DV_XMETA_EN,
1419                 MLX5_MR_EXT_MEMSEG_EN,
1420                 MLX5_REPRESENTOR,
1421                 MLX5_MAX_DUMP_FILES_NUM,
1422                 MLX5_LRO_TIMEOUT_USEC,
1423                 MLX5_CLASS_ARG_NAME,
1424                 MLX5_HP_BUF_SIZE,
1425                 MLX5_RECLAIM_MEM,
1426                 NULL,
1427         };
1428         struct rte_kvargs *kvlist;
1429         int ret = 0;
1430         int i;
1431
1432         if (devargs == NULL)
1433                 return 0;
1434         /* Following UGLY cast is done to pass checkpatch. */
1435         kvlist = rte_kvargs_parse(devargs->args, params);
1436         if (kvlist == NULL) {
1437                 rte_errno = EINVAL;
1438                 return -rte_errno;
1439         }
1440         /* Process parameters. */
1441         for (i = 0; (params[i] != NULL); ++i) {
1442                 if (rte_kvargs_count(kvlist, params[i])) {
1443                         ret = rte_kvargs_process(kvlist, params[i],
1444                                                  mlx5_args_check, config);
1445                         if (ret) {
1446                                 rte_errno = EINVAL;
1447                                 rte_kvargs_free(kvlist);
1448                                 return -rte_errno;
1449                         }
1450                 }
1451         }
1452         rte_kvargs_free(kvlist);
1453         return 0;
1454 }
1455
1456 /**
1457  * PMD global initialization.
1458  *
1459  * Independent from individual device, this function initializes global
1460  * per-PMD data structures distinguishing primary and secondary processes.
1461  * Hence, each initialization is called once per a process.
1462  *
1463  * @return
1464  *   0 on success, a negative errno value otherwise and rte_errno is set.
1465  */
1466 int
1467 mlx5_init_once(void)
1468 {
1469         struct mlx5_shared_data *sd;
1470         struct mlx5_local_data *ld = &mlx5_local_data;
1471         int ret = 0;
1472
1473         if (mlx5_init_shared_data())
1474                 return -rte_errno;
1475         sd = mlx5_shared_data;
1476         MLX5_ASSERT(sd);
1477         rte_spinlock_lock(&sd->lock);
1478         switch (rte_eal_process_type()) {
1479         case RTE_PROC_PRIMARY:
1480                 if (sd->init_done)
1481                         break;
1482                 LIST_INIT(&sd->mem_event_cb_list);
1483                 rte_rwlock_init(&sd->mem_event_rwlock);
1484                 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
1485                                                 mlx5_mr_mem_event_cb, NULL);
1486                 ret = mlx5_mp_init_primary(MLX5_MP_NAME,
1487                                            mlx5_mp_primary_handle);
1488                 if (ret)
1489                         goto out;
1490                 sd->init_done = true;
1491                 break;
1492         case RTE_PROC_SECONDARY:
1493                 if (ld->init_done)
1494                         break;
1495                 ret = mlx5_mp_init_secondary(MLX5_MP_NAME,
1496                                              mlx5_mp_secondary_handle);
1497                 if (ret)
1498                         goto out;
1499                 ++sd->secondary_cnt;
1500                 ld->init_done = true;
1501                 break;
1502         default:
1503                 break;
1504         }
1505 out:
1506         rte_spinlock_unlock(&sd->lock);
1507         return ret;
1508 }
1509
1510 /**
1511  * Configures the minimal amount of data to inline into WQE
1512  * while sending packets.
1513  *
1514  * - the txq_inline_min has the maximal priority, if this
1515  *   key is specified in devargs
1516  * - if DevX is enabled the inline mode is queried from the
1517  *   device (HCA attributes and NIC vport context if needed).
1518  * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1519  *   and none (0 bytes) for other NICs
1520  *
1521  * @param spawn
1522  *   Verbs device parameters (name, port, switch_info) to spawn.
1523  * @param config
1524  *   Device configuration parameters.
1525  */
1526 void
1527 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1528                     struct mlx5_dev_config *config)
1529 {
1530         if (config->txq_inline_min != MLX5_ARG_UNSET) {
1531                 /* Application defines size of inlined data explicitly. */
1532                 switch (spawn->pci_dev->id.device_id) {
1533                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1534                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1535                         if (config->txq_inline_min <
1536                                        (int)MLX5_INLINE_HSIZE_L2) {
1537                                 DRV_LOG(DEBUG,
1538                                         "txq_inline_mix aligned to minimal"
1539                                         " ConnectX-4 required value %d",
1540                                         (int)MLX5_INLINE_HSIZE_L2);
1541                                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1542                         }
1543                         break;
1544                 }
1545                 goto exit;
1546         }
1547         if (config->hca_attr.eth_net_offloads) {
1548                 /* We have DevX enabled, inline mode queried successfully. */
1549                 switch (config->hca_attr.wqe_inline_mode) {
1550                 case MLX5_CAP_INLINE_MODE_L2:
1551                         /* outer L2 header must be inlined. */
1552                         config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1553                         goto exit;
1554                 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1555                         /* No inline data are required by NIC. */
1556                         config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1557                         config->hw_vlan_insert =
1558                                 config->hca_attr.wqe_vlan_insert;
1559                         DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1560                         goto exit;
1561                 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1562                         /* inline mode is defined by NIC vport context. */
1563                         if (!config->hca_attr.eth_virt)
1564                                 break;
1565                         switch (config->hca_attr.vport_inline_mode) {
1566                         case MLX5_INLINE_MODE_NONE:
1567                                 config->txq_inline_min =
1568                                         MLX5_INLINE_HSIZE_NONE;
1569                                 goto exit;
1570                         case MLX5_INLINE_MODE_L2:
1571                                 config->txq_inline_min =
1572                                         MLX5_INLINE_HSIZE_L2;
1573                                 goto exit;
1574                         case MLX5_INLINE_MODE_IP:
1575                                 config->txq_inline_min =
1576                                         MLX5_INLINE_HSIZE_L3;
1577                                 goto exit;
1578                         case MLX5_INLINE_MODE_TCP_UDP:
1579                                 config->txq_inline_min =
1580                                         MLX5_INLINE_HSIZE_L4;
1581                                 goto exit;
1582                         case MLX5_INLINE_MODE_INNER_L2:
1583                                 config->txq_inline_min =
1584                                         MLX5_INLINE_HSIZE_INNER_L2;
1585                                 goto exit;
1586                         case MLX5_INLINE_MODE_INNER_IP:
1587                                 config->txq_inline_min =
1588                                         MLX5_INLINE_HSIZE_INNER_L3;
1589                                 goto exit;
1590                         case MLX5_INLINE_MODE_INNER_TCP_UDP:
1591                                 config->txq_inline_min =
1592                                         MLX5_INLINE_HSIZE_INNER_L4;
1593                                 goto exit;
1594                         }
1595                 }
1596         }
1597         /*
1598          * We get here if we are unable to deduce
1599          * inline data size with DevX. Try PCI ID
1600          * to determine old NICs.
1601          */
1602         switch (spawn->pci_dev->id.device_id) {
1603         case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1604         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1605         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
1606         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1607                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1608                 config->hw_vlan_insert = 0;
1609                 break;
1610         case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
1611         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1612         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
1613         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1614                 /*
1615                  * These NICs support VLAN insertion from WQE and
1616                  * report the wqe_vlan_insert flag. But there is the bug
1617                  * and PFC control may be broken, so disable feature.
1618                  */
1619                 config->hw_vlan_insert = 0;
1620                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1621                 break;
1622         default:
1623                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1624                 break;
1625         }
1626 exit:
1627         DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
1628 }
1629
1630 /**
1631  * Configures the metadata mask fields in the shared context.
1632  *
1633  * @param [in] dev
1634  *   Pointer to Ethernet device.
1635  */
1636 void
1637 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
1638 {
1639         struct mlx5_priv *priv = dev->data->dev_private;
1640         struct mlx5_dev_ctx_shared *sh = priv->sh;
1641         uint32_t meta, mark, reg_c0;
1642
1643         reg_c0 = ~priv->vport_meta_mask;
1644         switch (priv->config.dv_xmeta_en) {
1645         case MLX5_XMETA_MODE_LEGACY:
1646                 meta = UINT32_MAX;
1647                 mark = MLX5_FLOW_MARK_MASK;
1648                 break;
1649         case MLX5_XMETA_MODE_META16:
1650                 meta = reg_c0 >> rte_bsf32(reg_c0);
1651                 mark = MLX5_FLOW_MARK_MASK;
1652                 break;
1653         case MLX5_XMETA_MODE_META32:
1654                 meta = UINT32_MAX;
1655                 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
1656                 break;
1657         default:
1658                 meta = 0;
1659                 mark = 0;
1660                 MLX5_ASSERT(false);
1661                 break;
1662         }
1663         if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
1664                 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
1665                                  sh->dv_mark_mask, mark);
1666         else
1667                 sh->dv_mark_mask = mark;
1668         if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
1669                 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
1670                                  sh->dv_meta_mask, meta);
1671         else
1672                 sh->dv_meta_mask = meta;
1673         if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
1674                 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
1675                                  sh->dv_meta_mask, reg_c0);
1676         else
1677                 sh->dv_regc0_mask = reg_c0;
1678         DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
1679         DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
1680         DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
1681         DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
1682 }
1683
1684 /**
1685  * Allocate page of door-bells and register it using DevX API.
1686  *
1687  * @param [in] dev
1688  *   Pointer to Ethernet device.
1689  *
1690  * @return
1691  *   Pointer to new page on success, NULL otherwise.
1692  */
1693 static struct mlx5_devx_dbr_page *
1694 mlx5_alloc_dbr_page(struct rte_eth_dev *dev)
1695 {
1696         struct mlx5_priv *priv = dev->data->dev_private;
1697         struct mlx5_devx_dbr_page *page;
1698
1699         /* Allocate space for door-bell page and management data. */
1700         page = rte_calloc_socket(__func__, 1, sizeof(struct mlx5_devx_dbr_page),
1701                                  RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1702         if (!page) {
1703                 DRV_LOG(ERR, "port %u cannot allocate dbr page",
1704                         dev->data->port_id);
1705                 return NULL;
1706         }
1707         /* Register allocated memory. */
1708         page->umem = mlx5_glue->devx_umem_reg(priv->sh->ctx, page->dbrs,
1709                                               MLX5_DBR_PAGE_SIZE, 0);
1710         if (!page->umem) {
1711                 DRV_LOG(ERR, "port %u cannot umem reg dbr page",
1712                         dev->data->port_id);
1713                 rte_free(page);
1714                 return NULL;
1715         }
1716         return page;
1717 }
1718
1719 /**
1720  * Find the next available door-bell, allocate new page if needed.
1721  *
1722  * @param [in] dev
1723  *   Pointer to Ethernet device.
1724  * @param [out] dbr_page
1725  *   Door-bell page containing the page data.
1726  *
1727  * @return
1728  *   Door-bell address offset on success, a negative error value otherwise.
1729  */
1730 int64_t
1731 mlx5_get_dbr(struct rte_eth_dev *dev, struct mlx5_devx_dbr_page **dbr_page)
1732 {
1733         struct mlx5_priv *priv = dev->data->dev_private;
1734         struct mlx5_devx_dbr_page *page = NULL;
1735         uint32_t i, j;
1736
1737         LIST_FOREACH(page, &priv->dbrpgs, next)
1738                 if (page->dbr_count < MLX5_DBR_PER_PAGE)
1739                         break;
1740         if (!page) { /* No page with free door-bell exists. */
1741                 page = mlx5_alloc_dbr_page(dev);
1742                 if (!page) /* Failed to allocate new page. */
1743                         return (-1);
1744                 LIST_INSERT_HEAD(&priv->dbrpgs, page, next);
1745         }
1746         /* Loop to find bitmap part with clear bit. */
1747         for (i = 0;
1748              i < MLX5_DBR_BITMAP_SIZE && page->dbr_bitmap[i] == UINT64_MAX;
1749              i++)
1750                 ; /* Empty. */
1751         /* Find the first clear bit. */
1752         MLX5_ASSERT(i < MLX5_DBR_BITMAP_SIZE);
1753         j = rte_bsf64(~page->dbr_bitmap[i]);
1754         page->dbr_bitmap[i] |= (UINT64_C(1) << j);
1755         page->dbr_count++;
1756         *dbr_page = page;
1757         return (((i * 64) + j) * sizeof(uint64_t));
1758 }
1759
1760 /**
1761  * Release a door-bell record.
1762  *
1763  * @param [in] dev
1764  *   Pointer to Ethernet device.
1765  * @param [in] umem_id
1766  *   UMEM ID of page containing the door-bell record to release.
1767  * @param [in] offset
1768  *   Offset of door-bell record in page.
1769  *
1770  * @return
1771  *   0 on success, a negative error value otherwise.
1772  */
1773 int32_t
1774 mlx5_release_dbr(struct rte_eth_dev *dev, uint32_t umem_id, uint64_t offset)
1775 {
1776         struct mlx5_priv *priv = dev->data->dev_private;
1777         struct mlx5_devx_dbr_page *page = NULL;
1778         int ret = 0;
1779
1780         LIST_FOREACH(page, &priv->dbrpgs, next)
1781                 /* Find the page this address belongs to. */
1782                 if (mlx5_os_get_umem_id(page->umem) == umem_id)
1783                         break;
1784         if (!page)
1785                 return -EINVAL;
1786         page->dbr_count--;
1787         if (!page->dbr_count) {
1788                 /* Page not used, free it and remove from list. */
1789                 LIST_REMOVE(page, next);
1790                 if (page->umem)
1791                         ret = -mlx5_glue->devx_umem_dereg(page->umem);
1792                 rte_free(page);
1793         } else {
1794                 /* Mark in bitmap that this door-bell is not in use. */
1795                 offset /= MLX5_DBR_SIZE;
1796                 int i = offset / 64;
1797                 int j = offset % 64;
1798
1799                 page->dbr_bitmap[i] &= ~(UINT64_C(1) << j);
1800         }
1801         return ret;
1802 }
1803
1804 int
1805 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
1806 {
1807         static const char *const dynf_names[] = {
1808                 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
1809                 RTE_MBUF_DYNFLAG_METADATA_NAME
1810         };
1811         unsigned int i;
1812
1813         if (n < RTE_DIM(dynf_names))
1814                 return -ENOMEM;
1815         for (i = 0; i < RTE_DIM(dynf_names); i++) {
1816                 if (names[i] == NULL)
1817                         return -EINVAL;
1818                 strcpy(names[i], dynf_names[i]);
1819         }
1820         return RTE_DIM(dynf_names);
1821 }
1822
1823 /**
1824  * Comparison callback to sort device data.
1825  *
1826  * This is meant to be used with qsort().
1827  *
1828  * @param a[in]
1829  *   Pointer to pointer to first data object.
1830  * @param b[in]
1831  *   Pointer to pointer to second data object.
1832  *
1833  * @return
1834  *   0 if both objects are equal, less than 0 if the first argument is less
1835  *   than the second, greater than 0 otherwise.
1836  */
1837 int
1838 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
1839                               struct mlx5_dev_config *config)
1840 {
1841         struct mlx5_dev_ctx_shared *sh = priv->sh;
1842         struct mlx5_dev_config *sh_conf = NULL;
1843         uint16_t port_id;
1844
1845         MLX5_ASSERT(sh);
1846         /* Nothing to compare for the single/first device. */
1847         if (sh->refcnt == 1)
1848                 return 0;
1849         /* Find the device with shared context. */
1850         MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1851                 struct mlx5_priv *opriv =
1852                         rte_eth_devices[port_id].data->dev_private;
1853
1854                 if (opriv && opriv != priv && opriv->sh == sh) {
1855                         sh_conf = &opriv->config;
1856                         break;
1857                 }
1858         }
1859         if (!sh_conf)
1860                 return 0;
1861         if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
1862                 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
1863                              " for shared %s context", sh->ibdev_name);
1864                 rte_errno = EINVAL;
1865                 return rte_errno;
1866         }
1867         if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
1868                 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
1869                              " for shared %s context", sh->ibdev_name);
1870                 rte_errno = EINVAL;
1871                 return rte_errno;
1872         }
1873         return 0;
1874 }
1875
1876 /**
1877  * Look for the ethernet device belonging to mlx5 driver.
1878  *
1879  * @param[in] port_id
1880  *   port_id to start looking for device.
1881  * @param[in] pci_dev
1882  *   Pointer to the hint PCI device. When device is being probed
1883  *   the its siblings (master and preceding representors might
1884  *   not have assigned driver yet (because the mlx5_os_pci_probe()
1885  *   is not completed yet, for this case match on hint PCI
1886  *   device may be used to detect sibling device.
1887  *
1888  * @return
1889  *   port_id of found device, RTE_MAX_ETHPORT if not found.
1890  */
1891 uint16_t
1892 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
1893 {
1894         while (port_id < RTE_MAX_ETHPORTS) {
1895                 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
1896
1897                 if (dev->state != RTE_ETH_DEV_UNUSED &&
1898                     dev->device &&
1899                     (dev->device == &pci_dev->device ||
1900                      (dev->device->driver &&
1901                      dev->device->driver->name &&
1902                      !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
1903                         break;
1904                 port_id++;
1905         }
1906         if (port_id >= RTE_MAX_ETHPORTS)
1907                 return RTE_MAX_ETHPORTS;
1908         return port_id;
1909 }
1910
1911 /**
1912  * DPDK callback to remove a PCI device.
1913  *
1914  * This function removes all Ethernet devices belong to a given PCI device.
1915  *
1916  * @param[in] pci_dev
1917  *   Pointer to the PCI device.
1918  *
1919  * @return
1920  *   0 on success, the function cannot fail.
1921  */
1922 static int
1923 mlx5_pci_remove(struct rte_pci_device *pci_dev)
1924 {
1925         uint16_t port_id;
1926
1927         RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
1928                 /*
1929                  * mlx5_dev_close() is not registered to secondary process,
1930                  * call the close function explicitly for secondary process.
1931                  */
1932                 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
1933                         mlx5_dev_close(&rte_eth_devices[port_id]);
1934                 else
1935                         rte_eth_dev_close(port_id);
1936         }
1937         return 0;
1938 }
1939
1940 static const struct rte_pci_id mlx5_pci_id_map[] = {
1941         {
1942                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1943                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
1944         },
1945         {
1946                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1947                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
1948         },
1949         {
1950                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1951                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
1952         },
1953         {
1954                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1955                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
1956         },
1957         {
1958                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1959                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
1960         },
1961         {
1962                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1963                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
1964         },
1965         {
1966                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1967                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
1968         },
1969         {
1970                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1971                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
1972         },
1973         {
1974                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1975                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
1976         },
1977         {
1978                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1979                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
1980         },
1981         {
1982                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1983                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
1984         },
1985         {
1986                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1987                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
1988         },
1989         {
1990                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1991                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
1992         },
1993         {
1994                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1995                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF)
1996         },
1997         {
1998                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1999                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
2000         },
2001         {
2002                 .vendor_id = 0
2003         }
2004 };
2005
2006 struct rte_pci_driver mlx5_driver = {
2007         .driver = {
2008                 .name = MLX5_DRIVER_NAME
2009         },
2010         .id_table = mlx5_pci_id_map,
2011         .probe = mlx5_os_pci_probe,
2012         .remove = mlx5_pci_remove,
2013         .dma_map = mlx5_dma_map,
2014         .dma_unmap = mlx5_dma_unmap,
2015         .drv_flags = PCI_DRV_FLAGS,
2016 };
2017
2018 /**
2019  * Driver initialization routine.
2020  */
2021 RTE_INIT(rte_mlx5_pmd_init)
2022 {
2023         /* Initialize driver log type. */
2024         mlx5_logtype = rte_log_register("pmd.net.mlx5");
2025         if (mlx5_logtype >= 0)
2026                 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE);
2027
2028         /* Build the static tables for Verbs conversion. */
2029         mlx5_set_ptype_table();
2030         mlx5_set_cksum_table();
2031         mlx5_set_swp_types_table();
2032         if (mlx5_glue)
2033                 rte_pci_register(&mlx5_driver);
2034 }
2035
2036 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
2037 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
2038 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");