drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <stdint.h>
  10 #include <stdlib.h>
  11 #include <errno.h>
  12
  13 #include <rte_malloc.h>
  14 #include <ethdev_driver.h>
  15 #include <rte_pci.h>
  16 #include <rte_bus_pci.h>
  17 #include <rte_common.h>
  18 #include <rte_kvargs.h>
  19 #include <rte_rwlock.h>
  20 #include <rte_spinlock.h>
  21 #include <rte_string_fns.h>
  22 #include <rte_alarm.h>
  23 #include <rte_cycles.h>
  24
  25 #include <mlx5_glue.h>
  26 #include <mlx5_devx_cmds.h>
  27 #include <mlx5_common.h>
  28 #include <mlx5_common_os.h>
  29 #include <mlx5_common_mp.h>
  30 #include <mlx5_malloc.h>
  31
  32 #include "mlx5_defs.h"
  33 #include "mlx5.h"
  34 #include "mlx5_utils.h"
  35 #include "mlx5_rxtx.h"
  36 #include "mlx5_rx.h"
  37 #include "mlx5_tx.h"
  38 #include "mlx5_autoconf.h"
  39 #include "mlx5_flow.h"
  40 #include "mlx5_flow_os.h"
  41 #include "rte_pmd_mlx5.h"
  42
  43 #define MLX5_ETH_DRIVER_NAME mlx5_eth
  44
  45 /* Driver type key for new device global syntax. */
  46 #define MLX5_DRIVER_KEY "driver"
  47
  48 /* Device parameter to enable RX completion queue compression. */
  49 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  50
  51 /* Device parameter to enable padding Rx packet to cacheline size. */
  52 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
  53
  54 /* Device parameter to enable Multi-Packet Rx queue. */
  55 #define MLX5_RX_MPRQ_EN "mprq_en"
  56
  57 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
  58 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
  59
  60 /* Device parameter to configure log 2 of the stride size for MPRQ. */
  61 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
  62
  63 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
  64 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
  65
  66 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
  67 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
  68
  69 /* Device parameter to configure inline send. Deprecated, ignored.*/
  70 #define MLX5_TXQ_INLINE "txq_inline"
  71
  72 /* Device parameter to limit packet size to inline with ordinary SEND. */
  73 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
  74
  75 /* Device parameter to configure minimal data size to inline. */
  76 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
  77
  78 /* Device parameter to limit packet size to inline with Enhanced MPW. */
  79 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
  80
  81 /*
  82  * Device parameter to configure the number of TX queues threshold for
  83  * enabling inline send.
  84  */
  85 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  86
  87 /*
  88  * Device parameter to configure the number of TX queues threshold for
  89  * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
  90  */
  91 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
  92
  93 /* Device parameter to enable multi-packet send WQEs. */
  94 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
  95
  96 /*
  97  * Device parameter to force doorbell register mapping
  98  * to non-cahed region eliminating the extra write memory barrier.
  99  */
 100 #define MLX5_TX_DB_NC "tx_db_nc"
 101
 102 /*
 103  * Device parameter to include 2 dsegs in the title WQEBB.
 104  * Deprecated, ignored.
 105  */
 106 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
 107
 108 /*
 109  * Device parameter to limit the size of inlining packet.
 110  * Deprecated, ignored.
 111  */
 112 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
 113
 114 /*
 115  * Device parameter to enable Tx scheduling on timestamps
 116  * and specify the packet pacing granularity in nanoseconds.
 117  */
 118 #define MLX5_TX_PP "tx_pp"
 119
 120 /*
 121  * Device parameter to specify skew in nanoseconds on Tx datapath,
 122  * it represents the time between SQ start WQE processing and
 123  * appearing actual packet data on the wire.
 124  */
 125 #define MLX5_TX_SKEW "tx_skew"
 126
 127 /*
 128  * Device parameter to enable hardware Tx vector.
 129  * Deprecated, ignored (no vectorized Tx routines anymore).
 130  */
 131 #define MLX5_TX_VEC_EN "tx_vec_en"
 132
 133 /* Device parameter to enable hardware Rx vector. */
 134 #define MLX5_RX_VEC_EN "rx_vec_en"
 135
 136 /* Allow L3 VXLAN flow creation. */
 137 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
 138
 139 /* Activate DV E-Switch flow steering. */
 140 #define MLX5_DV_ESW_EN "dv_esw_en"
 141
 142 /* Activate DV flow steering. */
 143 #define MLX5_DV_FLOW_EN "dv_flow_en"
 144
 145 /* Enable extensive flow metadata support. */
 146 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
 147
 148 /* Device parameter to let the user manage the lacp traffic of bonded device */
 149 #define MLX5_LACP_BY_USER "lacp_by_user"
 150
 151 /* Activate Netlink support in VF mode. */
 152 #define MLX5_VF_NL_EN "vf_nl_en"
 153
 154 /* Enable extending memsegs when creating a MR. */
 155 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
 156
 157 /* Select port representors to instantiate. */
 158 #define MLX5_REPRESENTOR "representor"
 159
 160 /* Device parameter to configure the maximum number of dump files per queue. */
 161 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
 162
 163 /* Configure timeout of LRO session (in microseconds). */
 164 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
 165
 166 /*
 167  * Device parameter to configure the total data buffer size for a single
 168  * hairpin queue (logarithm value).
 169  */
 170 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
 171
 172 /* Flow memory reclaim mode. */
 173 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
 174
 175 /* The default memory allocator used in PMD. */
 176 #define MLX5_SYS_MEM_EN "sys_mem_en"
 177 /* Decap will be used or not. */
 178 #define MLX5_DECAP_EN "decap_en"
 179
 180 /* Device parameter to configure allow or prevent duplicate rules pattern. */
 181 #define MLX5_ALLOW_DUPLICATE_PATTERN "allow_duplicate_pattern"
 182
 183 /* Device parameter to configure implicit registration of mempool memory. */
 184 #define MLX5_MR_MEMPOOL_REG_EN "mr_mempool_reg_en"
 185
 186 /* Device parameter to configure the delay drop when creating Rxqs. */
 187 #define MLX5_DELAY_DROP "delay_drop"
 188
 189 /* Shared memory between primary and secondary processes. */
 190 struct mlx5_shared_data *mlx5_shared_data;
 191
 192 /** Driver-specific log messages type. */
 193 int mlx5_logtype;
 194
 195 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
 196                                                 LIST_HEAD_INITIALIZER();
 197 static pthread_mutex_t mlx5_dev_ctx_list_mutex;
 198 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
 199 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
 200         [MLX5_IPOOL_DECAP_ENCAP] = {
 201                 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
 202                 .trunk_size = 64,
 203                 .grow_trunk = 3,
 204                 .grow_shift = 2,
 205                 .need_lock = 1,
 206                 .release_mem_en = 1,
 207                 .malloc = mlx5_malloc,
 208                 .free = mlx5_free,
 209                 .type = "mlx5_encap_decap_ipool",
 210         },
 211         [MLX5_IPOOL_PUSH_VLAN] = {
 212                 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
 213                 .trunk_size = 64,
 214                 .grow_trunk = 3,
 215                 .grow_shift = 2,
 216                 .need_lock = 1,
 217                 .release_mem_en = 1,
 218                 .malloc = mlx5_malloc,
 219                 .free = mlx5_free,
 220                 .type = "mlx5_push_vlan_ipool",
 221         },
 222         [MLX5_IPOOL_TAG] = {
 223                 .size = sizeof(struct mlx5_flow_dv_tag_resource),
 224                 .trunk_size = 64,
 225                 .grow_trunk = 3,
 226                 .grow_shift = 2,
 227                 .need_lock = 1,
 228                 .release_mem_en = 0,
 229                 .per_core_cache = (1 << 16),
 230                 .malloc = mlx5_malloc,
 231                 .free = mlx5_free,
 232                 .type = "mlx5_tag_ipool",
 233         },
 234         [MLX5_IPOOL_PORT_ID] = {
 235                 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
 236                 .trunk_size = 64,
 237                 .grow_trunk = 3,
 238                 .grow_shift = 2,
 239                 .need_lock = 1,
 240                 .release_mem_en = 1,
 241                 .malloc = mlx5_malloc,
 242                 .free = mlx5_free,
 243                 .type = "mlx5_port_id_ipool",
 244         },
 245         [MLX5_IPOOL_JUMP] = {
 246                 .size = sizeof(struct mlx5_flow_tbl_data_entry),
 247                 .trunk_size = 64,
 248                 .grow_trunk = 3,
 249                 .grow_shift = 2,
 250                 .need_lock = 1,
 251                 .release_mem_en = 1,
 252                 .malloc = mlx5_malloc,
 253                 .free = mlx5_free,
 254                 .type = "mlx5_jump_ipool",
 255         },
 256         [MLX5_IPOOL_SAMPLE] = {
 257                 .size = sizeof(struct mlx5_flow_dv_sample_resource),
 258                 .trunk_size = 64,
 259                 .grow_trunk = 3,
 260                 .grow_shift = 2,
 261                 .need_lock = 1,
 262                 .release_mem_en = 1,
 263                 .malloc = mlx5_malloc,
 264                 .free = mlx5_free,
 265                 .type = "mlx5_sample_ipool",
 266         },
 267         [MLX5_IPOOL_DEST_ARRAY] = {
 268                 .size = sizeof(struct mlx5_flow_dv_dest_array_resource),
 269                 .trunk_size = 64,
 270                 .grow_trunk = 3,
 271                 .grow_shift = 2,
 272                 .need_lock = 1,
 273                 .release_mem_en = 1,
 274                 .malloc = mlx5_malloc,
 275                 .free = mlx5_free,
 276                 .type = "mlx5_dest_array_ipool",
 277         },
 278         [MLX5_IPOOL_TUNNEL_ID] = {
 279                 .size = sizeof(struct mlx5_flow_tunnel),
 280                 .trunk_size = MLX5_MAX_TUNNELS,
 281                 .need_lock = 1,
 282                 .release_mem_en = 1,
 283                 .type = "mlx5_tunnel_offload",
 284         },
 285         [MLX5_IPOOL_TNL_TBL_ID] = {
 286                 .size = 0,
 287                 .need_lock = 1,
 288                 .type = "mlx5_flow_tnl_tbl_ipool",
 289         },
 290 #endif
 291         [MLX5_IPOOL_MTR] = {
 292                 /**
 293                  * The ipool index should grow continually from small to big,
 294                  * for meter idx, so not set grow_trunk to avoid meter index
 295                  * not jump continually.
 296                  */
 297                 .size = sizeof(struct mlx5_legacy_flow_meter),
 298                 .trunk_size = 64,
 299                 .need_lock = 1,
 300                 .release_mem_en = 1,
 301                 .malloc = mlx5_malloc,
 302                 .free = mlx5_free,
 303                 .type = "mlx5_meter_ipool",
 304         },
 305         [MLX5_IPOOL_MCP] = {
 306                 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
 307                 .trunk_size = 64,
 308                 .grow_trunk = 3,
 309                 .grow_shift = 2,
 310                 .need_lock = 1,
 311                 .release_mem_en = 1,
 312                 .malloc = mlx5_malloc,
 313                 .free = mlx5_free,
 314                 .type = "mlx5_mcp_ipool",
 315         },
 316         [MLX5_IPOOL_HRXQ] = {
 317                 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
 318                 .trunk_size = 64,
 319                 .grow_trunk = 3,
 320                 .grow_shift = 2,
 321                 .need_lock = 1,
 322                 .release_mem_en = 1,
 323                 .malloc = mlx5_malloc,
 324                 .free = mlx5_free,
 325                 .type = "mlx5_hrxq_ipool",
 326         },
 327         [MLX5_IPOOL_MLX5_FLOW] = {
 328                 /*
 329                  * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
 330                  * It set in run time according to PCI function configuration.
 331                  */
 332                 .size = 0,
 333                 .trunk_size = 64,
 334                 .grow_trunk = 3,
 335                 .grow_shift = 2,
 336                 .need_lock = 1,
 337                 .release_mem_en = 0,
 338                 .per_core_cache = 1 << 19,
 339                 .malloc = mlx5_malloc,
 340                 .free = mlx5_free,
 341                 .type = "mlx5_flow_handle_ipool",
 342         },
 343         [MLX5_IPOOL_RTE_FLOW] = {
 344                 .size = sizeof(struct rte_flow),
 345                 .trunk_size = 4096,
 346                 .need_lock = 1,
 347                 .release_mem_en = 1,
 348                 .malloc = mlx5_malloc,
 349                 .free = mlx5_free,
 350                 .type = "rte_flow_ipool",
 351         },
 352         [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID] = {
 353                 .size = 0,
 354                 .need_lock = 1,
 355                 .type = "mlx5_flow_rss_id_ipool",
 356         },
 357         [MLX5_IPOOL_RSS_SHARED_ACTIONS] = {
 358                 .size = sizeof(struct mlx5_shared_action_rss),
 359                 .trunk_size = 64,
 360                 .grow_trunk = 3,
 361                 .grow_shift = 2,
 362                 .need_lock = 1,
 363                 .release_mem_en = 1,
 364                 .malloc = mlx5_malloc,
 365                 .free = mlx5_free,
 366                 .type = "mlx5_shared_action_rss",
 367         },
 368         [MLX5_IPOOL_MTR_POLICY] = {
 369                 /**
 370                  * The ipool index should grow continually from small to big,
 371                  * for policy idx, so not set grow_trunk to avoid policy index
 372                  * not jump continually.
 373                  */
 374                 .size = sizeof(struct mlx5_flow_meter_sub_policy),
 375                 .trunk_size = 64,
 376                 .need_lock = 1,
 377                 .release_mem_en = 1,
 378                 .malloc = mlx5_malloc,
 379                 .free = mlx5_free,
 380                 .type = "mlx5_meter_policy_ipool",
 381         },
 382 };
 383
 384 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
 385 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
 386
 387 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 1024
 388
 389 /**
 390  * Decide whether representor ID is a HPF(host PF) port on BF2.
 391  *
 392  * @param dev
 393  *   Pointer to Ethernet device structure.
 394  *
 395  * @return
 396  *   Non-zero if HPF, otherwise 0.
 397  */
 398 bool
 399 mlx5_is_hpf(struct rte_eth_dev *dev)
 400 {
 401         struct mlx5_priv *priv = dev->data->dev_private;
 402         uint16_t repr = MLX5_REPRESENTOR_REPR(priv->representor_id);
 403         int type = MLX5_REPRESENTOR_TYPE(priv->representor_id);
 404
 405         return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_VF &&
 406                MLX5_REPRESENTOR_REPR(-1) == repr;
 407 }
 408
 409 /**
 410  * Decide whether representor ID is a SF port representor.
 411  *
 412  * @param dev
 413  *   Pointer to Ethernet device structure.
 414  *
 415  * @return
 416  *   Non-zero if HPF, otherwise 0.
 417  */
 418 bool
 419 mlx5_is_sf_repr(struct rte_eth_dev *dev)
 420 {
 421         struct mlx5_priv *priv = dev->data->dev_private;
 422         int type = MLX5_REPRESENTOR_TYPE(priv->representor_id);
 423
 424         return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_SF;
 425 }
 426
 427 /**
 428  * Initialize the ASO aging management structure.
 429  *
 430  * @param[in] sh
 431  *   Pointer to mlx5_dev_ctx_shared object to free
 432  *
 433  * @return
 434  *   0 on success, a negative errno value otherwise and rte_errno is set.
 435  */
 436 int
 437 mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh)
 438 {
 439         int err;
 440
 441         if (sh->aso_age_mng)
 442                 return 0;
 443         sh->aso_age_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->aso_age_mng),
 444                                       RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 445         if (!sh->aso_age_mng) {
 446                 DRV_LOG(ERR, "aso_age_mng allocation was failed.");
 447                 rte_errno = ENOMEM;
 448                 return -ENOMEM;
 449         }
 450         err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_FLOW_HIT);
 451         if (err) {
 452                 mlx5_free(sh->aso_age_mng);
 453                 return -1;
 454         }
 455         rte_rwlock_init(&sh->aso_age_mng->resize_rwl);
 456         rte_spinlock_init(&sh->aso_age_mng->free_sl);
 457         LIST_INIT(&sh->aso_age_mng->free);
 458         return 0;
 459 }
 460
 461 /**
 462  * Close and release all the resources of the ASO aging management structure.
 463  *
 464  * @param[in] sh
 465  *   Pointer to mlx5_dev_ctx_shared object to free.
 466  */
 467 static void
 468 mlx5_flow_aso_age_mng_close(struct mlx5_dev_ctx_shared *sh)
 469 {
 470         int i, j;
 471
 472         mlx5_aso_flow_hit_queue_poll_stop(sh);
 473         mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_FLOW_HIT);
 474         if (sh->aso_age_mng->pools) {
 475                 struct mlx5_aso_age_pool *pool;
 476
 477                 for (i = 0; i < sh->aso_age_mng->next; ++i) {
 478                         pool = sh->aso_age_mng->pools[i];
 479                         claim_zero(mlx5_devx_cmd_destroy
 480                                                 (pool->flow_hit_aso_obj));
 481                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j)
 482                                 if (pool->actions[j].dr_action)
 483                                         claim_zero
 484                                             (mlx5_flow_os_destroy_flow_action
 485                                               (pool->actions[j].dr_action));
 486                         mlx5_free(pool);
 487                 }
 488                 mlx5_free(sh->aso_age_mng->pools);
 489         }
 490         mlx5_free(sh->aso_age_mng);
 491 }
 492
 493 /**
 494  * Initialize the shared aging list information per port.
 495  *
 496  * @param[in] sh
 497  *   Pointer to mlx5_dev_ctx_shared object.
 498  */
 499 static void
 500 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
 501 {
 502         uint32_t i;
 503         struct mlx5_age_info *age_info;
 504
 505         for (i = 0; i < sh->max_port; i++) {
 506                 age_info = &sh->port[i].age_info;
 507                 age_info->flags = 0;
 508                 TAILQ_INIT(&age_info->aged_counters);
 509                 LIST_INIT(&age_info->aged_aso);
 510                 rte_spinlock_init(&age_info->aged_sl);
 511                 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
 512         }
 513 }
 514
 515 /**
 516  * Initialize the counters management structure.
 517  *
 518  * @param[in] sh
 519  *   Pointer to mlx5_dev_ctx_shared object to free
 520  */
 521 static void
 522 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
 523 {
 524         struct mlx5_hca_attr *attr = &sh->cdev->config.hca_attr;
 525         int i;
 526
 527         memset(&sh->cmng, 0, sizeof(sh->cmng));
 528         TAILQ_INIT(&sh->cmng.flow_counters);
 529         sh->cmng.min_id = MLX5_CNT_BATCH_OFFSET;
 530         sh->cmng.max_id = -1;
 531         sh->cmng.last_pool_idx = POOL_IDX_INVALID;
 532         rte_spinlock_init(&sh->cmng.pool_update_sl);
 533         for (i = 0; i < MLX5_COUNTER_TYPE_MAX; i++) {
 534                 TAILQ_INIT(&sh->cmng.counters[i]);
 535                 rte_spinlock_init(&sh->cmng.csl[i]);
 536         }
 537         if (sh->devx && !haswell_broadwell_cpu) {
 538                 sh->cmng.relaxed_ordering_write = attr->relaxed_ordering_write;
 539                 sh->cmng.relaxed_ordering_read = attr->relaxed_ordering_read;
 540         }
 541 }
 542
 543 /**
 544  * Destroy all the resources allocated for a counter memory management.
 545  *
 546  * @param[in] mng
 547  *   Pointer to the memory management structure.
 548  */
 549 static void
 550 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
 551 {
 552         uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
 553
 554         LIST_REMOVE(mng, next);
 555         claim_zero(mlx5_devx_cmd_destroy(mng->dm));
 556         claim_zero(mlx5_os_umem_dereg(mng->umem));
 557         mlx5_free(mem);
 558 }
 559
 560 /**
 561  * Close and release all the resources of the counters management.
 562  *
 563  * @param[in] sh
 564  *   Pointer to mlx5_dev_ctx_shared object to free.
 565  */
 566 static void
 567 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
 568 {
 569         struct mlx5_counter_stats_mem_mng *mng;
 570         int i, j;
 571         int retries = 1024;
 572
 573         rte_errno = 0;
 574         while (--retries) {
 575                 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
 576                 if (rte_errno != EINPROGRESS)
 577                         break;
 578                 rte_pause();
 579         }
 580
 581         if (sh->cmng.pools) {
 582                 struct mlx5_flow_counter_pool *pool;
 583                 uint16_t n_valid = sh->cmng.n_valid;
 584                 bool fallback = sh->cmng.counter_fallback;
 585
 586                 for (i = 0; i < n_valid; ++i) {
 587                         pool = sh->cmng.pools[i];
 588                         if (!fallback && pool->min_dcs)
 589                                 claim_zero(mlx5_devx_cmd_destroy
 590                                                                (pool->min_dcs));
 591                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
 592                                 struct mlx5_flow_counter *cnt =
 593                                                 MLX5_POOL_GET_CNT(pool, j);
 594
 595                                 if (cnt->action)
 596                                         claim_zero
 597                                          (mlx5_flow_os_destroy_flow_action
 598                                           (cnt->action));
 599                                 if (fallback && MLX5_POOL_GET_CNT
 600                                     (pool, j)->dcs_when_free)
 601                                         claim_zero(mlx5_devx_cmd_destroy
 602                                                    (cnt->dcs_when_free));
 603                         }
 604                         mlx5_free(pool);
 605                 }
 606                 mlx5_free(sh->cmng.pools);
 607         }
 608         mng = LIST_FIRST(&sh->cmng.mem_mngs);
 609         while (mng) {
 610                 mlx5_flow_destroy_counter_stat_mem_mng(mng);
 611                 mng = LIST_FIRST(&sh->cmng.mem_mngs);
 612         }
 613         memset(&sh->cmng, 0, sizeof(sh->cmng));
 614 }
 615
 616 /**
 617  * Initialize the aso flow meters management structure.
 618  *
 619  * @param[in] sh
 620  *   Pointer to mlx5_dev_ctx_shared object to free
 621  */
 622 int
 623 mlx5_aso_flow_mtrs_mng_init(struct mlx5_dev_ctx_shared *sh)
 624 {
 625         if (!sh->mtrmng) {
 626                 sh->mtrmng = mlx5_malloc(MLX5_MEM_ZERO,
 627                         sizeof(*sh->mtrmng),
 628                         RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 629                 if (!sh->mtrmng) {
 630                         DRV_LOG(ERR,
 631                         "meter management allocation was failed.");
 632                         rte_errno = ENOMEM;
 633                         return -ENOMEM;
 634                 }
 635                 if (sh->meter_aso_en) {
 636                         rte_spinlock_init(&sh->mtrmng->pools_mng.mtrsl);
 637                         rte_rwlock_init(&sh->mtrmng->pools_mng.resize_mtrwl);
 638                         LIST_INIT(&sh->mtrmng->pools_mng.meters);
 639                 }
 640                 sh->mtrmng->def_policy_id = MLX5_INVALID_POLICY_ID;
 641         }
 642         return 0;
 643 }
 644
 645 /**
 646  * Close and release all the resources of
 647  * the ASO flow meter management structure.
 648  *
 649  * @param[in] sh
 650  *   Pointer to mlx5_dev_ctx_shared object to free.
 651  */
 652 static void
 653 mlx5_aso_flow_mtrs_mng_close(struct mlx5_dev_ctx_shared *sh)
 654 {
 655         struct mlx5_aso_mtr_pool *mtr_pool;
 656         struct mlx5_flow_mtr_mng *mtrmng = sh->mtrmng;
 657         uint32_t idx;
 658 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
 659         struct mlx5_aso_mtr *aso_mtr;
 660         int i;
 661 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
 662
 663         if (sh->meter_aso_en) {
 664                 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_POLICER);
 665                 idx = mtrmng->pools_mng.n_valid;
 666                 while (idx--) {
 667                         mtr_pool = mtrmng->pools_mng.pools[idx];
 668 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
 669                         for (i = 0; i < MLX5_ASO_MTRS_PER_POOL; i++) {
 670                                 aso_mtr = &mtr_pool->mtrs[i];
 671                                 if (aso_mtr->fm.meter_action)
 672                                         claim_zero
 673                                         (mlx5_glue->destroy_flow_action
 674                                         (aso_mtr->fm.meter_action));
 675                         }
 676 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
 677                         claim_zero(mlx5_devx_cmd_destroy
 678                                                 (mtr_pool->devx_obj));
 679                         mtrmng->pools_mng.n_valid--;
 680                         mlx5_free(mtr_pool);
 681                 }
 682                 mlx5_free(sh->mtrmng->pools_mng.pools);
 683         }
 684         mlx5_free(sh->mtrmng);
 685         sh->mtrmng = NULL;
 686 }
 687
 688 /* Send FLOW_AGED event if needed. */
 689 void
 690 mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh)
 691 {
 692         struct mlx5_age_info *age_info;
 693         uint32_t i;
 694
 695         for (i = 0; i < sh->max_port; i++) {
 696                 age_info = &sh->port[i].age_info;
 697                 if (!MLX5_AGE_GET(age_info, MLX5_AGE_EVENT_NEW))
 698                         continue;
 699                 MLX5_AGE_UNSET(age_info, MLX5_AGE_EVENT_NEW);
 700                 if (MLX5_AGE_GET(age_info, MLX5_AGE_TRIGGER)) {
 701                         MLX5_AGE_UNSET(age_info, MLX5_AGE_TRIGGER);
 702                         rte_eth_dev_callback_process
 703                                 (&rte_eth_devices[sh->port[i].devx_ih_port_id],
 704                                 RTE_ETH_EVENT_FLOW_AGED, NULL);
 705                 }
 706         }
 707 }
 708
 709 /*
 710  * Initialize the ASO connection tracking structure.
 711  *
 712  * @param[in] sh
 713  *   Pointer to mlx5_dev_ctx_shared object.
 714  *
 715  * @return
 716  *   0 on success, a negative errno value otherwise and rte_errno is set.
 717  */
 718 int
 719 mlx5_flow_aso_ct_mng_init(struct mlx5_dev_ctx_shared *sh)
 720 {
 721         int err;
 722
 723         if (sh->ct_mng)
 724                 return 0;
 725         sh->ct_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->ct_mng),
 726                                  RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 727         if (!sh->ct_mng) {
 728                 DRV_LOG(ERR, "ASO CT management allocation failed.");
 729                 rte_errno = ENOMEM;
 730                 return -rte_errno;
 731         }
 732         err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_CONNECTION_TRACKING);
 733         if (err) {
 734                 mlx5_free(sh->ct_mng);
 735                 /* rte_errno should be extracted from the failure. */
 736                 rte_errno = EINVAL;
 737                 return -rte_errno;
 738         }
 739         rte_spinlock_init(&sh->ct_mng->ct_sl);
 740         rte_rwlock_init(&sh->ct_mng->resize_rwl);
 741         LIST_INIT(&sh->ct_mng->free_cts);
 742         return 0;
 743 }
 744
 745 /*
 746  * Close and release all the resources of the
 747  * ASO connection tracking management structure.
 748  *
 749  * @param[in] sh
 750  *   Pointer to mlx5_dev_ctx_shared object to free.
 751  */
 752 static void
 753 mlx5_flow_aso_ct_mng_close(struct mlx5_dev_ctx_shared *sh)
 754 {
 755         struct mlx5_aso_ct_pools_mng *mng = sh->ct_mng;
 756         struct mlx5_aso_ct_pool *ct_pool;
 757         struct mlx5_aso_ct_action *ct;
 758         uint32_t idx;
 759         uint32_t val;
 760         uint32_t cnt;
 761         int i;
 762
 763         mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_CONNECTION_TRACKING);
 764         idx = mng->next;
 765         while (idx--) {
 766                 cnt = 0;
 767                 ct_pool = mng->pools[idx];
 768                 for (i = 0; i < MLX5_ASO_CT_ACTIONS_PER_POOL; i++) {
 769                         ct = &ct_pool->actions[i];
 770                         val = __atomic_fetch_sub(&ct->refcnt, 1,
 771                                                  __ATOMIC_RELAXED);
 772                         MLX5_ASSERT(val == 1);
 773                         if (val > 1)
 774                                 cnt++;
 775 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
 776                         if (ct->dr_action_orig)
 777                                 claim_zero(mlx5_glue->destroy_flow_action
 778                                                         (ct->dr_action_orig));
 779                         if (ct->dr_action_rply)
 780                                 claim_zero(mlx5_glue->destroy_flow_action
 781                                                         (ct->dr_action_rply));
 782 #endif
 783                 }
 784                 claim_zero(mlx5_devx_cmd_destroy(ct_pool->devx_obj));
 785                 if (cnt) {
 786                         DRV_LOG(DEBUG, "%u ASO CT objects are being used in the pool %u",
 787                                 cnt, i);
 788                 }
 789                 mlx5_free(ct_pool);
 790                 /* in case of failure. */
 791                 mng->next--;
 792         }
 793         mlx5_free(mng->pools);
 794         mlx5_free(mng);
 795         /* Management structure must be cleared to 0s during allocation. */
 796         sh->ct_mng = NULL;
 797 }
 798
 799 /**
 800  * Initialize the flow resources' indexed mempool.
 801  *
 802  * @param[in] sh
 803  *   Pointer to mlx5_dev_ctx_shared object.
 804  * @param[in] config
 805  *   Pointer to user dev config.
 806  */
 807 static void
 808 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
 809                        const struct mlx5_dev_config *config)
 810 {
 811         uint8_t i;
 812         struct mlx5_indexed_pool_config cfg;
 813
 814         for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
 815                 cfg = mlx5_ipool_cfg[i];
 816                 switch (i) {
 817                 default:
 818                         break;
 819                 /*
 820                  * Set MLX5_IPOOL_MLX5_FLOW ipool size
 821                  * according to PCI function flow configuration.
 822                  */
 823                 case MLX5_IPOOL_MLX5_FLOW:
 824                         cfg.size = config->dv_flow_en ?
 825                                 sizeof(struct mlx5_flow_handle) :
 826                                 MLX5_FLOW_HANDLE_VERBS_SIZE;
 827                         break;
 828                 }
 829                 if (config->reclaim_mode) {
 830                         cfg.release_mem_en = 1;
 831                         cfg.per_core_cache = 0;
 832                 } else {
 833                         cfg.release_mem_en = 0;
 834                 }
 835                 sh->ipool[i] = mlx5_ipool_create(&cfg);
 836         }
 837 }
 838
 839
 840 /**
 841  * Release the flow resources' indexed mempool.
 842  *
 843  * @param[in] sh
 844  *   Pointer to mlx5_dev_ctx_shared object.
 845  */
 846 static void
 847 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
 848 {
 849         uint8_t i;
 850
 851         for (i = 0; i < MLX5_IPOOL_MAX; ++i)
 852                 mlx5_ipool_destroy(sh->ipool[i]);
 853         for (i = 0; i < MLX5_MAX_MODIFY_NUM; ++i)
 854                 if (sh->mdh_ipools[i])
 855                         mlx5_ipool_destroy(sh->mdh_ipools[i]);
 856 }
 857
 858 /*
 859  * Check if dynamic flex parser for eCPRI already exists.
 860  *
 861  * @param dev
 862  *   Pointer to Ethernet device structure.
 863  *
 864  * @return
 865  *   true on exists, false on not.
 866  */
 867 bool
 868 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
 869 {
 870         struct mlx5_priv *priv = dev->data->dev_private;
 871         struct mlx5_ecpri_parser_profile *prf = &priv->sh->ecpri_parser;
 872
 873         return !!prf->obj;
 874 }
 875
 876 /*
 877  * Allocation of a flex parser for eCPRI. Once created, this parser related
 878  * resources will be held until the device is closed.
 879  *
 880  * @param dev
 881  *   Pointer to Ethernet device structure.
 882  *
 883  * @return
 884  *   0 on success, a negative errno value otherwise and rte_errno is set.
 885  */
 886 int
 887 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
 888 {
 889         struct mlx5_priv *priv = dev->data->dev_private;
 890         struct mlx5_ecpri_parser_profile *prf = &priv->sh->ecpri_parser;
 891         struct mlx5_devx_graph_node_attr node = {
 892                 .modify_field_select = 0,
 893         };
 894         uint32_t ids[8];
 895         int ret;
 896
 897         if (!priv->config.hca_attr.parse_graph_flex_node) {
 898                 DRV_LOG(ERR, "Dynamic flex parser is not supported "
 899                         "for device %s.", priv->dev_data->name);
 900                 return -ENOTSUP;
 901         }
 902         node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED;
 903         /* 8 bytes now: 4B common header + 4B message body header. */
 904         node.header_length_base_value = 0x8;
 905         /* After MAC layer: Ether / VLAN. */
 906         node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC;
 907         /* Type of compared condition should be 0xAEFE in the L2 layer. */
 908         node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI;
 909         /* Sample #0: type in common header. */
 910         node.sample[0].flow_match_sample_en = 1;
 911         /* Fixed offset. */
 912         node.sample[0].flow_match_sample_offset_mode = 0x0;
 913         /* Only the 2nd byte will be used. */
 914         node.sample[0].flow_match_sample_field_base_offset = 0x0;
 915         /* Sample #1: message payload. */
 916         node.sample[1].flow_match_sample_en = 1;
 917         /* Fixed offset. */
 918         node.sample[1].flow_match_sample_offset_mode = 0x0;
 919         /*
 920          * Only the first two bytes will be used right now, and its offset will
 921          * start after the common header that with the length of a DW(u32).
 922          */
 923         node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);
 924         prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->cdev->ctx, &node);
 925         if (!prf->obj) {
 926                 DRV_LOG(ERR, "Failed to create flex parser node object.");
 927                 return (rte_errno == 0) ? -ENODEV : -rte_errno;
 928         }
 929         prf->num = 2;
 930         ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num);
 931         if (ret) {
 932                 DRV_LOG(ERR, "Failed to query sample IDs.");
 933                 return (rte_errno == 0) ? -ENODEV : -rte_errno;
 934         }
 935         prf->offset[0] = 0x0;
 936         prf->offset[1] = sizeof(uint32_t);
 937         prf->ids[0] = ids[0];
 938         prf->ids[1] = ids[1];
 939         return 0;
 940 }
 941
 942 /*
 943  * Destroy the flex parser node, including the parser itself, input / output
 944  * arcs and DW samples. Resources could be reused then.
 945  *
 946  * @param dev
 947  *   Pointer to Ethernet device structure.
 948  */
 949 static void
 950 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
 951 {
 952         struct mlx5_priv *priv = dev->data->dev_private;
 953         struct mlx5_ecpri_parser_profile *prf = &priv->sh->ecpri_parser;
 954
 955         if (prf->obj)
 956                 mlx5_devx_cmd_destroy(prf->obj);
 957         prf->obj = NULL;
 958 }
 959
 960 uint32_t
 961 mlx5_get_supported_sw_parsing_offloads(const struct mlx5_hca_attr *attr)
 962 {
 963         uint32_t sw_parsing_offloads = 0;
 964
 965         if (attr->swp) {
 966                 sw_parsing_offloads |= MLX5_SW_PARSING_CAP;
 967                 if (attr->swp_csum)
 968                         sw_parsing_offloads |= MLX5_SW_PARSING_CSUM_CAP;
 969
 970                 if (attr->swp_lso)
 971                         sw_parsing_offloads |= MLX5_SW_PARSING_TSO_CAP;
 972         }
 973         return sw_parsing_offloads;
 974 }
 975
 976 uint32_t
 977 mlx5_get_supported_tunneling_offloads(const struct mlx5_hca_attr *attr)
 978 {
 979         uint32_t tn_offloads = 0;
 980
 981         if (attr->tunnel_stateless_vxlan)
 982                 tn_offloads |= MLX5_TUNNELED_OFFLOADS_VXLAN_CAP;
 983         if (attr->tunnel_stateless_gre)
 984                 tn_offloads |= MLX5_TUNNELED_OFFLOADS_GRE_CAP;
 985         if (attr->tunnel_stateless_geneve_rx)
 986                 tn_offloads |= MLX5_TUNNELED_OFFLOADS_GENEVE_CAP;
 987         return tn_offloads;
 988 }
 989
 990 /*
 991  * Allocate Rx and Tx UARs in robust fashion.
 992  * This routine handles the following UAR allocation issues:
 993  *
 994  *  - tries to allocate the UAR with the most appropriate memory
 995  *    mapping type from the ones supported by the host
 996  *
 997  *  - tries to allocate the UAR with non-NULL base address
 998  *    OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as
 999  *    UAR base address if UAR was not the first object in the UAR page.
1000  *    It caused the PMD failure and we should try to get another UAR
1001  *    till we get the first one with non-NULL base address returned.
1002  */
1003 static int
1004 mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh,
1005                      const struct mlx5_common_dev_config *config)
1006 {
1007         uint32_t uar_mapping, retry;
1008         int err = 0;
1009         void *base_addr;
1010
1011         for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
1012 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
1013                 /* Control the mapping type according to the settings. */
1014                 uar_mapping = (config->dbnc == MLX5_TXDB_NCACHED) ?
1015                               MLX5DV_UAR_ALLOC_TYPE_NC :
1016                               MLX5DV_UAR_ALLOC_TYPE_BF;
1017 #else
1018                 RTE_SET_USED(config);
1019                 /*
1020                  * It seems we have no way to control the memory mapping type
1021                  * for the UAR, the default "Write-Combining" type is supposed.
1022                  * The UAR initialization on queue creation queries the
1023                  * actual mapping type done by Verbs/kernel and setups the
1024                  * PMD datapath accordingly.
1025                  */
1026                 uar_mapping = 0;
1027 #endif
1028                 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->cdev->ctx,
1029                                                        uar_mapping);
1030 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
1031                 if (!sh->tx_uar &&
1032                     uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
1033                         if (config->dbnc == MLX5_TXDB_CACHED ||
1034                             config->dbnc == MLX5_TXDB_HEURISTIC)
1035                                 DRV_LOG(WARNING, "Devarg tx_db_nc setting "
1036                                                  "is not supported by DevX");
1037                         /*
1038                          * In some environments like virtual machine
1039                          * the Write Combining mapped might be not supported
1040                          * and UAR allocation fails. We try "Non-Cached"
1041                          * mapping for the case. The tx_burst routines take
1042                          * the UAR mapping type into account on UAR setup
1043                          * on queue creation.
1044                          */
1045                         DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (BF)");
1046                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
1047                         sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->cdev->ctx,
1048                                                                uar_mapping);
1049                 } else if (!sh->tx_uar &&
1050                            uar_mapping == MLX5DV_UAR_ALLOC_TYPE_NC) {
1051                         if (config->dbnc == MLX5_TXDB_NCACHED)
1052                                 DRV_LOG(WARNING, "Devarg tx_db_nc settings "
1053                                                  "is not supported by DevX");
1054                         /*
1055                          * If Verbs/kernel does not support "Non-Cached"
1056                          * try the "Write-Combining".
1057                          */
1058                         DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (NC)");
1059                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_BF;
1060                         sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->cdev->ctx,
1061                                                                uar_mapping);
1062                 }
1063 #endif
1064                 if (!sh->tx_uar) {
1065                         DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (BF/NC)");
1066                         err = ENOMEM;
1067                         goto exit;
1068                 }
1069                 base_addr = mlx5_os_get_devx_uar_base_addr(sh->tx_uar);
1070                 if (base_addr)
1071                         break;
1072                 /*
1073                  * The UARs are allocated by rdma_core within the
1074                  * IB device context, on context closure all UARs
1075                  * will be freed, should be no memory/object leakage.
1076                  */
1077                 DRV_LOG(DEBUG, "Retrying to allocate Tx DevX UAR");
1078                 sh->tx_uar = NULL;
1079         }
1080         /* Check whether we finally succeeded with valid UAR allocation. */
1081         if (!sh->tx_uar) {
1082                 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (NULL base)");
1083                 err = ENOMEM;
1084                 goto exit;
1085         }
1086         for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
1087                 uar_mapping = 0;
1088                 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar(sh->cdev->ctx,
1089                                                             uar_mapping);
1090 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
1091                 if (!sh->devx_rx_uar &&
1092                     uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
1093                         /*
1094                          * Rx UAR is used to control interrupts only,
1095                          * should be no datapath noticeable impact,
1096                          * can try "Non-Cached" mapping safely.
1097                          */
1098                         DRV_LOG(DEBUG, "Failed to allocate Rx DevX UAR (BF)");
1099                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
1100                         sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
1101                                                    (sh->cdev->ctx, uar_mapping);
1102                 }
1103 #endif
1104                 if (!sh->devx_rx_uar) {
1105                         DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (BF/NC)");
1106                         err = ENOMEM;
1107                         goto exit;
1108                 }
1109                 base_addr = mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar);
1110                 if (base_addr)
1111                         break;
1112                 /*
1113                  * The UARs are allocated by rdma_core within the
1114                  * IB device context, on context closure all UARs
1115                  * will be freed, should be no memory/object leakage.
1116                  */
1117                 DRV_LOG(DEBUG, "Retrying to allocate Rx DevX UAR");
1118                 sh->devx_rx_uar = NULL;
1119         }
1120         /* Check whether we finally succeeded with valid UAR allocation. */
1121         if (!sh->devx_rx_uar) {
1122                 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (NULL base)");
1123                 err = ENOMEM;
1124         }
1125 exit:
1126         return err;
1127 }
1128
1129 /**
1130  * rte_mempool_walk() callback to unregister Rx mempools.
1131  * It used when implicit mempool registration is disabled.
1132  *
1133  * @param mp
1134  *   The mempool being walked.
1135  * @param arg
1136  *   Pointer to the device shared context.
1137  */
1138 static void
1139 mlx5_dev_ctx_shared_rx_mempool_unregister_cb(struct rte_mempool *mp, void *arg)
1140 {
1141         struct mlx5_dev_ctx_shared *sh = arg;
1142
1143         mlx5_dev_mempool_unregister(sh->cdev, mp);
1144 }
1145
1146 /**
1147  * Callback used when implicit mempool registration is disabled
1148  * in order to track Rx mempool destruction.
1149  *
1150  * @param event
1151  *   Mempool life cycle event.
1152  * @param mp
1153  *   An Rx mempool registered explicitly when the port is started.
1154  * @param arg
1155  *   Pointer to a device shared context.
1156  */
1157 static void
1158 mlx5_dev_ctx_shared_rx_mempool_event_cb(enum rte_mempool_event event,
1159                                         struct rte_mempool *mp, void *arg)
1160 {
1161         struct mlx5_dev_ctx_shared *sh = arg;
1162
1163         if (event == RTE_MEMPOOL_EVENT_DESTROY)
1164                 mlx5_dev_mempool_unregister(sh->cdev, mp);
1165 }
1166
1167 int
1168 mlx5_dev_ctx_shared_mempool_subscribe(struct rte_eth_dev *dev)
1169 {
1170         struct mlx5_priv *priv = dev->data->dev_private;
1171         struct mlx5_dev_ctx_shared *sh = priv->sh;
1172         int ret;
1173
1174         /* Check if we only need to track Rx mempool destruction. */
1175         if (!sh->cdev->config.mr_mempool_reg_en) {
1176                 ret = rte_mempool_event_callback_register
1177                                 (mlx5_dev_ctx_shared_rx_mempool_event_cb, sh);
1178                 return ret == 0 || rte_errno == EEXIST ? 0 : ret;
1179         }
1180         return mlx5_dev_mempool_subscribe(sh->cdev);
1181 }
1182
1183 /**
1184  * Set up multiple TISs with different affinities according to
1185  * number of bonding ports
1186  *
1187  * @param priv
1188  * Pointer of shared context.
1189  *
1190  * @return
1191  * Zero on success, -1 otherwise.
1192  */
1193 static int
1194 mlx5_setup_tis(struct mlx5_dev_ctx_shared *sh)
1195 {
1196         int i;
1197         struct mlx5_devx_lag_context lag_ctx = { 0 };
1198         struct mlx5_devx_tis_attr tis_attr = { 0 };
1199
1200         tis_attr.transport_domain = sh->td->id;
1201         if (sh->bond.n_port) {
1202                 if (!mlx5_devx_cmd_query_lag(sh->cdev->ctx, &lag_ctx)) {
1203                         sh->lag.tx_remap_affinity[0] =
1204                                 lag_ctx.tx_remap_affinity_1;
1205                         sh->lag.tx_remap_affinity[1] =
1206                                 lag_ctx.tx_remap_affinity_2;
1207                         sh->lag.affinity_mode = lag_ctx.port_select_mode;
1208                 } else {
1209                         DRV_LOG(ERR, "Failed to query lag affinity.");
1210                         return -1;
1211                 }
1212                 if (sh->lag.affinity_mode == MLX5_LAG_MODE_TIS) {
1213                         for (i = 0; i < sh->bond.n_port; i++) {
1214                                 tis_attr.lag_tx_port_affinity =
1215                                         MLX5_IFC_LAG_MAP_TIS_AFFINITY(i,
1216                                                         sh->bond.n_port);
1217                                 sh->tis[i] = mlx5_devx_cmd_create_tis(sh->cdev->ctx,
1218                                                 &tis_attr);
1219                                 if (!sh->tis[i]) {
1220                                         DRV_LOG(ERR, "Failed to TIS %d/%d for bonding device"
1221                                                 " %s.", i, sh->bond.n_port,
1222                                                 sh->ibdev_name);
1223                                         return -1;
1224                                 }
1225                         }
1226                         DRV_LOG(DEBUG, "LAG number of ports : %d, affinity_1 & 2 : pf%d & %d.\n",
1227                                 sh->bond.n_port, lag_ctx.tx_remap_affinity_1,
1228                                 lag_ctx.tx_remap_affinity_2);
1229                         return 0;
1230                 }
1231                 if (sh->lag.affinity_mode == MLX5_LAG_MODE_HASH)
1232                         DRV_LOG(INFO, "Device %s enabled HW hash based LAG.",
1233                                         sh->ibdev_name);
1234         }
1235         tis_attr.lag_tx_port_affinity = 0;
1236         sh->tis[0] = mlx5_devx_cmd_create_tis(sh->cdev->ctx, &tis_attr);
1237         if (!sh->tis[0]) {
1238                 DRV_LOG(ERR, "Failed to TIS 0 for bonding device"
1239                         " %s.", sh->ibdev_name);
1240                 return -1;
1241         }
1242         return 0;
1243 }
1244
1245 /**
1246  * Allocate shared device context. If there is multiport device the
1247  * master and representors will share this context, if there is single
1248  * port dedicated device, the context will be used by only given
1249  * port due to unification.
1250  *
1251  * Routine first searches the context for the specified device name,
1252  * if found the shared context assumed and reference counter is incremented.
1253  * If no context found the new one is created and initialized with specified
1254  * device context and parameters.
1255  *
1256  * @param[in] spawn
1257  *   Pointer to the device attributes (name, port, etc).
1258  * @param[in] config
1259  *   Pointer to device configuration structure.
1260  *
1261  * @return
1262  *   Pointer to mlx5_dev_ctx_shared object on success,
1263  *   otherwise NULL and rte_errno is set.
1264  */
1265 struct mlx5_dev_ctx_shared *
1266 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
1267                           const struct mlx5_dev_config *config)
1268 {
1269         struct mlx5_dev_ctx_shared *sh;
1270         int err = 0;
1271         uint32_t i;
1272
1273         MLX5_ASSERT(spawn);
1274         /* Secondary process should not create the shared context. */
1275         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1276         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1277         /* Search for IB context by device name. */
1278         LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
1279                 if (!strcmp(sh->ibdev_name, spawn->phys_dev_name)) {
1280                         sh->refcnt++;
1281                         goto exit;
1282                 }
1283         }
1284         /* No device found, we have to create new shared context. */
1285         MLX5_ASSERT(spawn->max_port);
1286         sh = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
1287                          sizeof(struct mlx5_dev_ctx_shared) +
1288                          spawn->max_port *
1289                          sizeof(struct mlx5_dev_shared_port),
1290                          RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
1291         if (!sh) {
1292                 DRV_LOG(ERR, "shared context allocation failure");
1293                 rte_errno  = ENOMEM;
1294                 goto exit;
1295         }
1296         pthread_mutex_init(&sh->txpp.mutex, NULL);
1297         sh->numa_node = spawn->cdev->dev->numa_node;
1298         sh->cdev = spawn->cdev;
1299         sh->devx = sh->cdev->config.devx;
1300         if (spawn->bond_info)
1301                 sh->bond = *spawn->bond_info;
1302         err = mlx5_os_get_dev_attr(sh->cdev, &sh->device_attr);
1303         if (err) {
1304                 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
1305                 goto error;
1306         }
1307         sh->refcnt = 1;
1308         sh->max_port = spawn->max_port;
1309         sh->reclaim_mode = config->reclaim_mode;
1310         strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->cdev->ctx),
1311                 sizeof(sh->ibdev_name) - 1);
1312         strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->cdev->ctx),
1313                 sizeof(sh->ibdev_path) - 1);
1314         /*
1315          * Setting port_id to max unallowed value means
1316          * there is no interrupt subhandler installed for
1317          * the given port index i.
1318          */
1319         for (i = 0; i < sh->max_port; i++) {
1320                 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
1321                 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
1322         }
1323         if (sh->devx) {
1324                 sh->td = mlx5_devx_cmd_create_td(sh->cdev->ctx);
1325                 if (!sh->td) {
1326                         DRV_LOG(ERR, "TD allocation failure");
1327                         err = ENOMEM;
1328                         goto error;
1329                 }
1330                 if (mlx5_setup_tis(sh)) {
1331                         DRV_LOG(ERR, "TIS allocation failure");
1332                         err = ENOMEM;
1333                         goto error;
1334                 }
1335                 err = mlx5_alloc_rxtx_uars(sh, &sh->cdev->config);
1336                 if (err)
1337                         goto error;
1338                 MLX5_ASSERT(sh->tx_uar);
1339                 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->tx_uar));
1340
1341                 MLX5_ASSERT(sh->devx_rx_uar);
1342                 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar));
1343         }
1344 #ifndef RTE_ARCH_64
1345         /* Initialize UAR access locks for 32bit implementations. */
1346         rte_spinlock_init(&sh->uar_lock_cq);
1347         for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
1348                 rte_spinlock_init(&sh->uar_lock[i]);
1349 #endif
1350         mlx5_os_dev_shared_handler_install(sh);
1351         if (LIST_EMPTY(&mlx5_dev_ctx_list)) {
1352                 err = mlx5_flow_os_init_workspace_once();
1353                 if (err)
1354                         goto error;
1355         }
1356         mlx5_flow_aging_init(sh);
1357         mlx5_flow_counters_mng_init(sh);
1358         mlx5_flow_ipool_create(sh, config);
1359         /* Add context to the global device list. */
1360         LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
1361         rte_spinlock_init(&sh->geneve_tlv_opt_sl);
1362 exit:
1363         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1364         return sh;
1365 error:
1366         pthread_mutex_destroy(&sh->txpp.mutex);
1367         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1368         MLX5_ASSERT(sh);
1369         if (sh->td)
1370                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1371         i = 0;
1372         do {
1373                 if (sh->tis[i])
1374                         claim_zero(mlx5_devx_cmd_destroy(sh->tis[i]));
1375         } while (++i < (uint32_t)sh->bond.n_port);
1376         if (sh->devx_rx_uar)
1377                 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1378         if (sh->tx_uar)
1379                 mlx5_glue->devx_free_uar(sh->tx_uar);
1380         mlx5_free(sh);
1381         MLX5_ASSERT(err > 0);
1382         rte_errno = err;
1383         return NULL;
1384 }
1385
1386 /**
1387  * Free shared IB device context. Decrement counter and if zero free
1388  * all allocated resources and close handles.
1389  *
1390  * @param[in] sh
1391  *   Pointer to mlx5_dev_ctx_shared object to free
1392  */
1393 void
1394 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
1395 {
1396         int ret;
1397         int i = 0;
1398
1399         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1400 #ifdef RTE_LIBRTE_MLX5_DEBUG
1401         /* Check the object presence in the list. */
1402         struct mlx5_dev_ctx_shared *lctx;
1403
1404         LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
1405                 if (lctx == sh)
1406                         break;
1407         MLX5_ASSERT(lctx);
1408         if (lctx != sh) {
1409                 DRV_LOG(ERR, "Freeing non-existing shared IB context");
1410                 goto exit;
1411         }
1412 #endif
1413         MLX5_ASSERT(sh);
1414         MLX5_ASSERT(sh->refcnt);
1415         /* Secondary process should not free the shared context. */
1416         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1417         if (--sh->refcnt)
1418                 goto exit;
1419         /* Stop watching for mempool events and unregister all mempools. */
1420         if (!sh->cdev->config.mr_mempool_reg_en) {
1421                 ret = rte_mempool_event_callback_unregister
1422                                 (mlx5_dev_ctx_shared_rx_mempool_event_cb, sh);
1423                 if (ret == 0)
1424                         rte_mempool_walk
1425                              (mlx5_dev_ctx_shared_rx_mempool_unregister_cb, sh);
1426         }
1427         /* Remove context from the global device list. */
1428         LIST_REMOVE(sh, next);
1429         /* Release resources on the last device removal. */
1430         if (LIST_EMPTY(&mlx5_dev_ctx_list)) {
1431                 mlx5_os_net_cleanup();
1432                 mlx5_flow_os_release_workspace();
1433         }
1434         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1435         if (sh->flex_parsers_dv) {
1436                 mlx5_list_destroy(sh->flex_parsers_dv);
1437                 sh->flex_parsers_dv = NULL;
1438         }
1439         /*
1440          *  Ensure there is no async event handler installed.
1441          *  Only primary process handles async device events.
1442          **/
1443         mlx5_flow_counters_mng_close(sh);
1444         if (sh->aso_age_mng) {
1445                 mlx5_flow_aso_age_mng_close(sh);
1446                 sh->aso_age_mng = NULL;
1447         }
1448         if (sh->mtrmng)
1449                 mlx5_aso_flow_mtrs_mng_close(sh);
1450         mlx5_flow_ipool_destroy(sh);
1451         mlx5_os_dev_shared_handler_uninstall(sh);
1452         if (sh->tx_uar) {
1453                 mlx5_glue->devx_free_uar(sh->tx_uar);
1454                 sh->tx_uar = NULL;
1455         }
1456         do {
1457                 if (sh->tis[i])
1458                         claim_zero(mlx5_devx_cmd_destroy(sh->tis[i]));
1459         } while (++i < sh->bond.n_port);
1460         if (sh->td)
1461                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1462         if (sh->devx_rx_uar)
1463                 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1464         MLX5_ASSERT(sh->geneve_tlv_option_resource == NULL);
1465         pthread_mutex_destroy(&sh->txpp.mutex);
1466         mlx5_free(sh);
1467         return;
1468 exit:
1469         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1470 }
1471
1472 /**
1473  * Destroy table hash list.
1474  *
1475  * @param[in] priv
1476  *   Pointer to the private device data structure.
1477  */
1478 void
1479 mlx5_free_table_hash_list(struct mlx5_priv *priv)
1480 {
1481         struct mlx5_dev_ctx_shared *sh = priv->sh;
1482
1483         if (!sh->flow_tbls)
1484                 return;
1485         mlx5_hlist_destroy(sh->flow_tbls);
1486         sh->flow_tbls = NULL;
1487 }
1488
1489 /**
1490  * Initialize flow table hash list and create the root tables entry
1491  * for each domain.
1492  *
1493  * @param[in] priv
1494  *   Pointer to the private device data structure.
1495  *
1496  * @return
1497  *   Zero on success, positive error code otherwise.
1498  */
1499 int
1500 mlx5_alloc_table_hash_list(struct mlx5_priv *priv __rte_unused)
1501 {
1502         int err = 0;
1503         /* Tables are only used in DV and DR modes. */
1504 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
1505         struct mlx5_dev_ctx_shared *sh = priv->sh;
1506         char s[MLX5_NAME_SIZE];
1507
1508         MLX5_ASSERT(sh);
1509         snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1510         sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE,
1511                                           false, true, sh,
1512                                           flow_dv_tbl_create_cb,
1513                                           flow_dv_tbl_match_cb,
1514                                           flow_dv_tbl_remove_cb,
1515                                           flow_dv_tbl_clone_cb,
1516                                           flow_dv_tbl_clone_free_cb);
1517         if (!sh->flow_tbls) {
1518                 DRV_LOG(ERR, "flow tables with hash creation failed.");
1519                 err = ENOMEM;
1520                 return err;
1521         }
1522 #ifndef HAVE_MLX5DV_DR
1523         struct rte_flow_error error;
1524         struct rte_eth_dev *dev = &rte_eth_devices[priv->dev_data->port_id];
1525
1526         /*
1527          * In case we have not DR support, the zero tables should be created
1528          * because DV expect to see them even if they cannot be created by
1529          * RDMA-CORE.
1530          */
1531         if (!flow_dv_tbl_resource_get(dev, 0, 0, 0, 0,
1532                 NULL, 0, 1, 0, &error) ||
1533             !flow_dv_tbl_resource_get(dev, 0, 1, 0, 0,
1534                 NULL, 0, 1, 0, &error) ||
1535             !flow_dv_tbl_resource_get(dev, 0, 0, 1, 0,
1536                 NULL, 0, 1, 0, &error)) {
1537                 err = ENOMEM;
1538                 goto error;
1539         }
1540         return err;
1541 error:
1542         mlx5_free_table_hash_list(priv);
1543 #endif /* HAVE_MLX5DV_DR */
1544 #endif
1545         return err;
1546 }
1547
1548 /**
1549  * Retrieve integer value from environment variable.
1550  *
1551  * @param[in] name
1552  *   Environment variable name.
1553  *
1554  * @return
1555  *   Integer value, 0 if the variable is not set.
1556  */
1557 int
1558 mlx5_getenv_int(const char *name)
1559 {
1560         const char *val = getenv(name);
1561
1562         if (val == NULL)
1563                 return 0;
1564         return atoi(val);
1565 }
1566
1567 /**
1568  * DPDK callback to add udp tunnel port
1569  *
1570  * @param[in] dev
1571  *   A pointer to eth_dev
1572  * @param[in] udp_tunnel
1573  *   A pointer to udp tunnel
1574  *
1575  * @return
1576  *   0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1577  */
1578 int
1579 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1580                          struct rte_eth_udp_tunnel *udp_tunnel)
1581 {
1582         MLX5_ASSERT(udp_tunnel != NULL);
1583         if (udp_tunnel->prot_type == RTE_ETH_TUNNEL_TYPE_VXLAN &&
1584             udp_tunnel->udp_port == 4789)
1585                 return 0;
1586         if (udp_tunnel->prot_type == RTE_ETH_TUNNEL_TYPE_VXLAN_GPE &&
1587             udp_tunnel->udp_port == 4790)
1588                 return 0;
1589         return -ENOTSUP;
1590 }
1591
1592 /**
1593  * Initialize process private data structure.
1594  *
1595  * @param dev
1596  *   Pointer to Ethernet device structure.
1597  *
1598  * @return
1599  *   0 on success, a negative errno value otherwise and rte_errno is set.
1600  */
1601 int
1602 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1603 {
1604         struct mlx5_priv *priv = dev->data->dev_private;
1605         struct mlx5_proc_priv *ppriv;
1606         size_t ppriv_size;
1607
1608         mlx5_proc_priv_uninit(dev);
1609         /*
1610          * UAR register table follows the process private structure. BlueFlame
1611          * registers for Tx queues are stored in the table.
1612          */
1613         ppriv_size =
1614                 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1615         ppriv = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, ppriv_size,
1616                             RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1617         if (!ppriv) {
1618                 rte_errno = ENOMEM;
1619                 return -rte_errno;
1620         }
1621         ppriv->uar_table_sz = priv->txqs_n;
1622         dev->process_private = ppriv;
1623         return 0;
1624 }
1625
1626 /**
1627  * Un-initialize process private data structure.
1628  *
1629  * @param dev
1630  *   Pointer to Ethernet device structure.
1631  */
1632 void
1633 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1634 {
1635         if (!dev->process_private)
1636                 return;
1637         mlx5_free(dev->process_private);
1638         dev->process_private = NULL;
1639 }
1640
1641 /**
1642  * DPDK callback to close the device.
1643  *
1644  * Destroy all queues and objects, free memory.
1645  *
1646  * @param dev
1647  *   Pointer to Ethernet device structure.
1648  */
1649 int
1650 mlx5_dev_close(struct rte_eth_dev *dev)
1651 {
1652         struct mlx5_priv *priv = dev->data->dev_private;
1653         unsigned int i;
1654         int ret;
1655
1656         if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1657                 /* Check if process_private released. */
1658                 if (!dev->process_private)
1659                         return 0;
1660                 mlx5_tx_uar_uninit_secondary(dev);
1661                 mlx5_proc_priv_uninit(dev);
1662                 rte_eth_dev_release_port(dev);
1663                 return 0;
1664         }
1665         if (!priv->sh)
1666                 return 0;
1667         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1668                 dev->data->port_id,
1669                 ((priv->sh->cdev->ctx != NULL) ?
1670                 mlx5_os_get_ctx_device_name(priv->sh->cdev->ctx) : ""));
1671         /*
1672          * If default mreg copy action is removed at the stop stage,
1673          * the search will return none and nothing will be done anymore.
1674          */
1675         mlx5_flow_stop_default(dev);
1676         mlx5_traffic_disable(dev);
1677         /*
1678          * If all the flows are already flushed in the device stop stage,
1679          * then this will return directly without any action.
1680          */
1681         mlx5_flow_list_flush(dev, MLX5_FLOW_TYPE_GEN, true);
1682         mlx5_action_handle_flush(dev);
1683         mlx5_flow_meter_flush(dev, NULL);
1684         /* Prevent crashes when queues are still in use. */
1685         dev->rx_pkt_burst = removed_rx_burst;
1686         dev->tx_pkt_burst = removed_tx_burst;
1687         rte_wmb();
1688         /* Disable datapath on secondary process. */
1689         mlx5_mp_os_req_stop_rxtx(dev);
1690         /* Free the eCPRI flex parser resource. */
1691         mlx5_flex_parser_ecpri_release(dev);
1692         mlx5_flex_item_port_cleanup(dev);
1693         if (priv->rxq_privs != NULL) {
1694                 /* XXX race condition if mlx5_rx_burst() is still running. */
1695                 rte_delay_us_sleep(1000);
1696                 for (i = 0; (i != priv->rxqs_n); ++i)
1697                         mlx5_rxq_release(dev, i);
1698                 priv->rxqs_n = 0;
1699                 mlx5_free(priv->rxq_privs);
1700                 priv->rxq_privs = NULL;
1701         }
1702         if (priv->txqs != NULL) {
1703                 /* XXX race condition if mlx5_tx_burst() is still running. */
1704                 rte_delay_us_sleep(1000);
1705                 for (i = 0; (i != priv->txqs_n); ++i)
1706                         mlx5_txq_release(dev, i);
1707                 priv->txqs_n = 0;
1708                 priv->txqs = NULL;
1709         }
1710         mlx5_proc_priv_uninit(dev);
1711         if (priv->q_counters) {
1712                 mlx5_devx_cmd_destroy(priv->q_counters);
1713                 priv->q_counters = NULL;
1714         }
1715         if (priv->drop_queue.hrxq)
1716                 mlx5_drop_action_destroy(dev);
1717         if (priv->mreg_cp_tbl)
1718                 mlx5_hlist_destroy(priv->mreg_cp_tbl);
1719         mlx5_mprq_free_mp(dev);
1720         if (priv->sh->ct_mng)
1721                 mlx5_flow_aso_ct_mng_close(priv->sh);
1722         mlx5_os_free_shared_dr(priv);
1723         if (priv->rss_conf.rss_key != NULL)
1724                 mlx5_free(priv->rss_conf.rss_key);
1725         if (priv->reta_idx != NULL)
1726                 mlx5_free(priv->reta_idx);
1727         if (priv->config.vf)
1728                 mlx5_os_mac_addr_flush(dev);
1729         if (priv->nl_socket_route >= 0)
1730                 close(priv->nl_socket_route);
1731         if (priv->nl_socket_rdma >= 0)
1732                 close(priv->nl_socket_rdma);
1733         if (priv->vmwa_context)
1734                 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1735         ret = mlx5_hrxq_verify(dev);
1736         if (ret)
1737                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1738                         dev->data->port_id);
1739         ret = mlx5_ind_table_obj_verify(dev);
1740         if (ret)
1741                 DRV_LOG(WARNING, "port %u some indirection table still remain",
1742                         dev->data->port_id);
1743         ret = mlx5_rxq_obj_verify(dev);
1744         if (ret)
1745                 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1746                         dev->data->port_id);
1747         ret = mlx5_rxq_verify(dev);
1748         if (ret)
1749                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1750                         dev->data->port_id);
1751         ret = mlx5_txq_obj_verify(dev);
1752         if (ret)
1753                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1754                         dev->data->port_id);
1755         ret = mlx5_txq_verify(dev);
1756         if (ret)
1757                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1758                         dev->data->port_id);
1759         ret = mlx5_flow_verify(dev);
1760         if (ret)
1761                 DRV_LOG(WARNING, "port %u some flows still remain",
1762                         dev->data->port_id);
1763         if (priv->hrxqs)
1764                 mlx5_list_destroy(priv->hrxqs);
1765         /*
1766          * Free the shared context in last turn, because the cleanup
1767          * routines above may use some shared fields, like
1768          * mlx5_os_mac_addr_flush() uses ibdev_path for retrieveing
1769          * ifindex if Netlink fails.
1770          */
1771         mlx5_free_shared_dev_ctx(priv->sh);
1772         if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1773                 unsigned int c = 0;
1774                 uint16_t port_id;
1775
1776                 MLX5_ETH_FOREACH_DEV(port_id, dev->device) {
1777                         struct mlx5_priv *opriv =
1778                                 rte_eth_devices[port_id].data->dev_private;
1779
1780                         if (!opriv ||
1781                             opriv->domain_id != priv->domain_id ||
1782                             &rte_eth_devices[port_id] == dev)
1783                                 continue;
1784                         ++c;
1785                         break;
1786                 }
1787                 if (!c)
1788                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1789         }
1790         memset(priv, 0, sizeof(*priv));
1791         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1792         /*
1793          * Reset mac_addrs to NULL such that it is not freed as part of
1794          * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1795          * it is freed when dev_private is freed.
1796          */
1797         dev->data->mac_addrs = NULL;
1798         return 0;
1799 }
1800
1801 const struct eth_dev_ops mlx5_dev_ops = {
1802         .dev_configure = mlx5_dev_configure,
1803         .dev_start = mlx5_dev_start,
1804         .dev_stop = mlx5_dev_stop,
1805         .dev_set_link_down = mlx5_set_link_down,
1806         .dev_set_link_up = mlx5_set_link_up,
1807         .dev_close = mlx5_dev_close,
1808         .promiscuous_enable = mlx5_promiscuous_enable,
1809         .promiscuous_disable = mlx5_promiscuous_disable,
1810         .allmulticast_enable = mlx5_allmulticast_enable,
1811         .allmulticast_disable = mlx5_allmulticast_disable,
1812         .link_update = mlx5_link_update,
1813         .stats_get = mlx5_stats_get,
1814         .stats_reset = mlx5_stats_reset,
1815         .xstats_get = mlx5_xstats_get,
1816         .xstats_reset = mlx5_xstats_reset,
1817         .xstats_get_names = mlx5_xstats_get_names,
1818         .fw_version_get = mlx5_fw_version_get,
1819         .dev_infos_get = mlx5_dev_infos_get,
1820         .representor_info_get = mlx5_representor_info_get,
1821         .read_clock = mlx5_txpp_read_clock,
1822         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1823         .vlan_filter_set = mlx5_vlan_filter_set,
1824         .rx_queue_setup = mlx5_rx_queue_setup,
1825         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1826         .tx_queue_setup = mlx5_tx_queue_setup,
1827         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1828         .rx_queue_release = mlx5_rx_queue_release,
1829         .tx_queue_release = mlx5_tx_queue_release,
1830         .rx_queue_start = mlx5_rx_queue_start,
1831         .rx_queue_stop = mlx5_rx_queue_stop,
1832         .tx_queue_start = mlx5_tx_queue_start,
1833         .tx_queue_stop = mlx5_tx_queue_stop,
1834         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1835         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1836         .mac_addr_remove = mlx5_mac_addr_remove,
1837         .mac_addr_add = mlx5_mac_addr_add,
1838         .mac_addr_set = mlx5_mac_addr_set,
1839         .set_mc_addr_list = mlx5_set_mc_addr_list,
1840         .mtu_set = mlx5_dev_set_mtu,
1841         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1842         .vlan_offload_set = mlx5_vlan_offload_set,
1843         .reta_update = mlx5_dev_rss_reta_update,
1844         .reta_query = mlx5_dev_rss_reta_query,
1845         .rss_hash_update = mlx5_rss_hash_update,
1846         .rss_hash_conf_get = mlx5_rss_hash_conf_get,
1847         .flow_ops_get = mlx5_flow_ops_get,
1848         .rxq_info_get = mlx5_rxq_info_get,
1849         .txq_info_get = mlx5_txq_info_get,
1850         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1851         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1852         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1853         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1854         .is_removed = mlx5_is_removed,
1855         .udp_tunnel_port_add  = mlx5_udp_tunnel_port_add,
1856         .get_module_info = mlx5_get_module_info,
1857         .get_module_eeprom = mlx5_get_module_eeprom,
1858         .hairpin_cap_get = mlx5_hairpin_cap_get,
1859         .mtr_ops_get = mlx5_flow_meter_ops_get,
1860         .hairpin_bind = mlx5_hairpin_bind,
1861         .hairpin_unbind = mlx5_hairpin_unbind,
1862         .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1863         .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1864         .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1865         .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1866         .get_monitor_addr = mlx5_get_monitor_addr,
1867 };
1868
1869 /* Available operations from secondary process. */
1870 const struct eth_dev_ops mlx5_dev_sec_ops = {
1871         .stats_get = mlx5_stats_get,
1872         .stats_reset = mlx5_stats_reset,
1873         .xstats_get = mlx5_xstats_get,
1874         .xstats_reset = mlx5_xstats_reset,
1875         .xstats_get_names = mlx5_xstats_get_names,
1876         .fw_version_get = mlx5_fw_version_get,
1877         .dev_infos_get = mlx5_dev_infos_get,
1878         .representor_info_get = mlx5_representor_info_get,
1879         .read_clock = mlx5_txpp_read_clock,
1880         .rx_queue_start = mlx5_rx_queue_start,
1881         .rx_queue_stop = mlx5_rx_queue_stop,
1882         .tx_queue_start = mlx5_tx_queue_start,
1883         .tx_queue_stop = mlx5_tx_queue_stop,
1884         .rxq_info_get = mlx5_rxq_info_get,
1885         .txq_info_get = mlx5_txq_info_get,
1886         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1887         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1888         .get_module_info = mlx5_get_module_info,
1889         .get_module_eeprom = mlx5_get_module_eeprom,
1890 };
1891
1892 /* Available operations in flow isolated mode. */
1893 const struct eth_dev_ops mlx5_dev_ops_isolate = {
1894         .dev_configure = mlx5_dev_configure,
1895         .dev_start = mlx5_dev_start,
1896         .dev_stop = mlx5_dev_stop,
1897         .dev_set_link_down = mlx5_set_link_down,
1898         .dev_set_link_up = mlx5_set_link_up,
1899         .dev_close = mlx5_dev_close,
1900         .promiscuous_enable = mlx5_promiscuous_enable,
1901         .promiscuous_disable = mlx5_promiscuous_disable,
1902         .allmulticast_enable = mlx5_allmulticast_enable,
1903         .allmulticast_disable = mlx5_allmulticast_disable,
1904         .link_update = mlx5_link_update,
1905         .stats_get = mlx5_stats_get,
1906         .stats_reset = mlx5_stats_reset,
1907         .xstats_get = mlx5_xstats_get,
1908         .xstats_reset = mlx5_xstats_reset,
1909         .xstats_get_names = mlx5_xstats_get_names,
1910         .fw_version_get = mlx5_fw_version_get,
1911         .dev_infos_get = mlx5_dev_infos_get,
1912         .representor_info_get = mlx5_representor_info_get,
1913         .read_clock = mlx5_txpp_read_clock,
1914         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1915         .vlan_filter_set = mlx5_vlan_filter_set,
1916         .rx_queue_setup = mlx5_rx_queue_setup,
1917         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1918         .tx_queue_setup = mlx5_tx_queue_setup,
1919         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1920         .rx_queue_release = mlx5_rx_queue_release,
1921         .tx_queue_release = mlx5_tx_queue_release,
1922         .rx_queue_start = mlx5_rx_queue_start,
1923         .rx_queue_stop = mlx5_rx_queue_stop,
1924         .tx_queue_start = mlx5_tx_queue_start,
1925         .tx_queue_stop = mlx5_tx_queue_stop,
1926         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1927         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1928         .mac_addr_remove = mlx5_mac_addr_remove,
1929         .mac_addr_add = mlx5_mac_addr_add,
1930         .mac_addr_set = mlx5_mac_addr_set,
1931         .set_mc_addr_list = mlx5_set_mc_addr_list,
1932         .mtu_set = mlx5_dev_set_mtu,
1933         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1934         .vlan_offload_set = mlx5_vlan_offload_set,
1935         .flow_ops_get = mlx5_flow_ops_get,
1936         .rxq_info_get = mlx5_rxq_info_get,
1937         .txq_info_get = mlx5_txq_info_get,
1938         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1939         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1940         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1941         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1942         .is_removed = mlx5_is_removed,
1943         .get_module_info = mlx5_get_module_info,
1944         .get_module_eeprom = mlx5_get_module_eeprom,
1945         .hairpin_cap_get = mlx5_hairpin_cap_get,
1946         .mtr_ops_get = mlx5_flow_meter_ops_get,
1947         .hairpin_bind = mlx5_hairpin_bind,
1948         .hairpin_unbind = mlx5_hairpin_unbind,
1949         .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1950         .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1951         .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1952         .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1953         .get_monitor_addr = mlx5_get_monitor_addr,
1954 };
1955
1956 /**
1957  * Verify and store value for device argument.
1958  *
1959  * @param[in] key
1960  *   Key argument to verify.
1961  * @param[in] val
1962  *   Value associated with key.
1963  * @param opaque
1964  *   User data.
1965  *
1966  * @return
1967  *   0 on success, a negative errno value otherwise and rte_errno is set.
1968  */
1969 static int
1970 mlx5_args_check(const char *key, const char *val, void *opaque)
1971 {
1972         struct mlx5_dev_config *config = opaque;
1973         unsigned long mod;
1974         signed long tmp;
1975
1976         /* No-op, port representors are processed in mlx5_dev_spawn(). */
1977         if (!strcmp(MLX5_DRIVER_KEY, key) || !strcmp(MLX5_REPRESENTOR, key) ||
1978             !strcmp(MLX5_SYS_MEM_EN, key) || !strcmp(MLX5_TX_DB_NC, key) ||
1979             !strcmp(MLX5_MR_MEMPOOL_REG_EN, key) ||
1980             !strcmp(MLX5_MR_EXT_MEMSEG_EN, key))
1981                 return 0;
1982         errno = 0;
1983         tmp = strtol(val, NULL, 0);
1984         if (errno) {
1985                 rte_errno = errno;
1986                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1987                 return -rte_errno;
1988         }
1989         if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
1990                 /* Negative values are acceptable for some keys only. */
1991                 rte_errno = EINVAL;
1992                 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
1993                 return -rte_errno;
1994         }
1995         mod = tmp >= 0 ? tmp : -tmp;
1996         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1997                 if (tmp > MLX5_CQE_RESP_FORMAT_L34H_STRIDX) {
1998                         DRV_LOG(ERR, "invalid CQE compression "
1999                                      "format parameter");
2000                         rte_errno = EINVAL;
2001                         return -rte_errno;
2002                 }
2003                 config->cqe_comp = !!tmp;
2004                 config->cqe_comp_fmt = tmp;
2005         } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
2006                 config->hw_padding = !!tmp;
2007         } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
2008                 config->mprq.enabled = !!tmp;
2009         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
2010                 config->mprq.stride_num_n = tmp;
2011         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
2012                 config->mprq.stride_size_n = tmp;
2013         } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
2014                 config->mprq.max_memcpy_len = tmp;
2015         } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
2016                 config->mprq.min_rxqs_num = tmp;
2017         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
2018                 DRV_LOG(WARNING, "%s: deprecated parameter,"
2019                                  " converted to txq_inline_max", key);
2020                 config->txq_inline_max = tmp;
2021         } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
2022                 config->txq_inline_max = tmp;
2023         } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
2024                 config->txq_inline_min = tmp;
2025         } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
2026                 config->txq_inline_mpw = tmp;
2027         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
2028                 config->txqs_inline = tmp;
2029         } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
2030                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
2031         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
2032                 config->mps = !!tmp;
2033         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
2034                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
2035         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
2036                 DRV_LOG(WARNING, "%s: deprecated parameter,"
2037                                  " converted to txq_inline_mpw", key);
2038                 config->txq_inline_mpw = tmp;
2039         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
2040                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
2041         } else if (strcmp(MLX5_TX_PP, key) == 0) {
2042                 if (!mod) {
2043                         DRV_LOG(ERR, "Zero Tx packet pacing parameter");
2044                         rte_errno = EINVAL;
2045                         return -rte_errno;
2046                 }
2047                 config->tx_pp = tmp;
2048         } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
2049                 config->tx_skew = tmp;
2050         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
2051                 config->rx_vec_en = !!tmp;
2052         } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
2053                 config->l3_vxlan_en = !!tmp;
2054         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
2055                 config->vf_nl_en = !!tmp;
2056         } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
2057                 config->dv_esw_en = !!tmp;
2058         } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
2059                 config->dv_flow_en = !!tmp;
2060         } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
2061                 if (tmp != MLX5_XMETA_MODE_LEGACY &&
2062                     tmp != MLX5_XMETA_MODE_META16 &&
2063                     tmp != MLX5_XMETA_MODE_META32 &&
2064                     tmp != MLX5_XMETA_MODE_MISS_INFO) {
2065                         DRV_LOG(ERR, "invalid extensive "
2066                                      "metadata parameter");
2067                         rte_errno = EINVAL;
2068                         return -rte_errno;
2069                 }
2070                 if (tmp != MLX5_XMETA_MODE_MISS_INFO)
2071                         config->dv_xmeta_en = tmp;
2072                 else
2073                         config->dv_miss_info = 1;
2074         } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
2075                 config->lacp_by_user = !!tmp;
2076         } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
2077                 config->max_dump_files_num = tmp;
2078         } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
2079                 config->lro.timeout = tmp;
2080         } else if (strcmp(RTE_DEVARGS_KEY_CLASS, key) == 0) {
2081                 DRV_LOG(DEBUG, "class argument is %s.", val);
2082         } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
2083                 config->log_hp_size = tmp;
2084         } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
2085                 if (tmp != MLX5_RCM_NONE &&
2086                     tmp != MLX5_RCM_LIGHT &&
2087                     tmp != MLX5_RCM_AGGR) {
2088                         DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
2089                         rte_errno = EINVAL;
2090                         return -rte_errno;
2091                 }
2092                 config->reclaim_mode = tmp;
2093         } else if (strcmp(MLX5_DECAP_EN, key) == 0) {
2094                 config->decap_en = !!tmp;
2095         } else if (strcmp(MLX5_ALLOW_DUPLICATE_PATTERN, key) == 0) {
2096                 config->allow_duplicate_pattern = !!tmp;
2097         } else if (strcmp(MLX5_DELAY_DROP, key) == 0) {
2098                 config->std_delay_drop = tmp & MLX5_DELAY_DROP_STANDARD;
2099                 config->hp_delay_drop = tmp & MLX5_DELAY_DROP_HAIRPIN;
2100         } else {
2101                 DRV_LOG(WARNING, "%s: unknown parameter", key);
2102                 rte_errno = EINVAL;
2103                 return -rte_errno;
2104         }
2105         return 0;
2106 }
2107
2108 /**
2109  * Parse device parameters.
2110  *
2111  * @param config
2112  *   Pointer to device configuration structure.
2113  * @param devargs
2114  *   Device arguments structure.
2115  *
2116  * @return
2117  *   0 on success, a negative errno value otherwise and rte_errno is set.
2118  */
2119 int
2120 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
2121 {
2122         const char **params = (const char *[]){
2123                 MLX5_DRIVER_KEY,
2124                 MLX5_RXQ_CQE_COMP_EN,
2125                 MLX5_RXQ_PKT_PAD_EN,
2126                 MLX5_RX_MPRQ_EN,
2127                 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
2128                 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
2129                 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
2130                 MLX5_RXQS_MIN_MPRQ,
2131                 MLX5_TXQ_INLINE,
2132                 MLX5_TXQ_INLINE_MIN,
2133                 MLX5_TXQ_INLINE_MAX,
2134                 MLX5_TXQ_INLINE_MPW,
2135                 MLX5_TXQS_MIN_INLINE,
2136                 MLX5_TXQS_MAX_VEC,
2137                 MLX5_TXQ_MPW_EN,
2138                 MLX5_TXQ_MPW_HDR_DSEG_EN,
2139                 MLX5_TXQ_MAX_INLINE_LEN,
2140                 MLX5_TX_DB_NC,
2141                 MLX5_TX_PP,
2142                 MLX5_TX_SKEW,
2143                 MLX5_TX_VEC_EN,
2144                 MLX5_RX_VEC_EN,
2145                 MLX5_L3_VXLAN_EN,
2146                 MLX5_VF_NL_EN,
2147                 MLX5_DV_ESW_EN,
2148                 MLX5_DV_FLOW_EN,
2149                 MLX5_DV_XMETA_EN,
2150                 MLX5_LACP_BY_USER,
2151                 MLX5_MR_EXT_MEMSEG_EN,
2152                 MLX5_REPRESENTOR,
2153                 MLX5_MAX_DUMP_FILES_NUM,
2154                 MLX5_LRO_TIMEOUT_USEC,
2155                 RTE_DEVARGS_KEY_CLASS,
2156                 MLX5_HP_BUF_SIZE,
2157                 MLX5_RECLAIM_MEM,
2158                 MLX5_SYS_MEM_EN,
2159                 MLX5_DECAP_EN,
2160                 MLX5_ALLOW_DUPLICATE_PATTERN,
2161                 MLX5_MR_MEMPOOL_REG_EN,
2162                 MLX5_DELAY_DROP,
2163                 NULL,
2164         };
2165         struct rte_kvargs *kvlist;
2166         int ret = 0;
2167         int i;
2168
2169         if (devargs == NULL)
2170                 return 0;
2171         /* Following UGLY cast is done to pass checkpatch. */
2172         kvlist = rte_kvargs_parse(devargs->args, params);
2173         if (kvlist == NULL) {
2174                 rte_errno = EINVAL;
2175                 return -rte_errno;
2176         }
2177         /* Process parameters. */
2178         for (i = 0; (params[i] != NULL); ++i) {
2179                 if (rte_kvargs_count(kvlist, params[i])) {
2180                         ret = rte_kvargs_process(kvlist, params[i],
2181                                                  mlx5_args_check, config);
2182                         if (ret) {
2183                                 rte_errno = EINVAL;
2184                                 rte_kvargs_free(kvlist);
2185                                 return -rte_errno;
2186                         }
2187                 }
2188         }
2189         rte_kvargs_free(kvlist);
2190         return 0;
2191 }
2192
2193 /**
2194  * Configures the minimal amount of data to inline into WQE
2195  * while sending packets.
2196  *
2197  * - the txq_inline_min has the maximal priority, if this
2198  *   key is specified in devargs
2199  * - if DevX is enabled the inline mode is queried from the
2200  *   device (HCA attributes and NIC vport context if needed).
2201  * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
2202  *   and none (0 bytes) for other NICs
2203  *
2204  * @param spawn
2205  *   Verbs device parameters (name, port, switch_info) to spawn.
2206  * @param config
2207  *   Device configuration parameters.
2208  */
2209 void
2210 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
2211                     struct mlx5_dev_config *config)
2212 {
2213         if (config->txq_inline_min != MLX5_ARG_UNSET) {
2214                 /* Application defines size of inlined data explicitly. */
2215                 if (spawn->pci_dev != NULL) {
2216                         switch (spawn->pci_dev->id.device_id) {
2217                         case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2218                         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2219                                 if (config->txq_inline_min <
2220                                                (int)MLX5_INLINE_HSIZE_L2) {
2221                                         DRV_LOG(DEBUG,
2222                                                 "txq_inline_mix aligned to minimal ConnectX-4 required value %d",
2223                                                 (int)MLX5_INLINE_HSIZE_L2);
2224                                         config->txq_inline_min =
2225                                                         MLX5_INLINE_HSIZE_L2;
2226                                 }
2227                                 break;
2228                         }
2229                 }
2230                 goto exit;
2231         }
2232         if (config->hca_attr.eth_net_offloads) {
2233                 /* We have DevX enabled, inline mode queried successfully. */
2234                 switch (config->hca_attr.wqe_inline_mode) {
2235                 case MLX5_CAP_INLINE_MODE_L2:
2236                         /* outer L2 header must be inlined. */
2237                         config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2238                         goto exit;
2239                 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
2240                         /* No inline data are required by NIC. */
2241                         config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2242                         config->hw_vlan_insert =
2243                                 config->hca_attr.wqe_vlan_insert;
2244                         DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
2245                         goto exit;
2246                 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
2247                         /* inline mode is defined by NIC vport context. */
2248                         if (!config->hca_attr.eth_virt)
2249                                 break;
2250                         switch (config->hca_attr.vport_inline_mode) {
2251                         case MLX5_INLINE_MODE_NONE:
2252                                 config->txq_inline_min =
2253                                         MLX5_INLINE_HSIZE_NONE;
2254                                 goto exit;
2255                         case MLX5_INLINE_MODE_L2:
2256                                 config->txq_inline_min =
2257                                         MLX5_INLINE_HSIZE_L2;
2258                                 goto exit;
2259                         case MLX5_INLINE_MODE_IP:
2260                                 config->txq_inline_min =
2261                                         MLX5_INLINE_HSIZE_L3;
2262                                 goto exit;
2263                         case MLX5_INLINE_MODE_TCP_UDP:
2264                                 config->txq_inline_min =
2265                                         MLX5_INLINE_HSIZE_L4;
2266                                 goto exit;
2267                         case MLX5_INLINE_MODE_INNER_L2:
2268                                 config->txq_inline_min =
2269                                         MLX5_INLINE_HSIZE_INNER_L2;
2270                                 goto exit;
2271                         case MLX5_INLINE_MODE_INNER_IP:
2272                                 config->txq_inline_min =
2273                                         MLX5_INLINE_HSIZE_INNER_L3;
2274                                 goto exit;
2275                         case MLX5_INLINE_MODE_INNER_TCP_UDP:
2276                                 config->txq_inline_min =
2277                                         MLX5_INLINE_HSIZE_INNER_L4;
2278                                 goto exit;
2279                         }
2280                 }
2281         }
2282         if (spawn->pci_dev == NULL) {
2283                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2284                 goto exit;
2285         }
2286         /*
2287          * We get here if we are unable to deduce
2288          * inline data size with DevX. Try PCI ID
2289          * to determine old NICs.
2290          */
2291         switch (spawn->pci_dev->id.device_id) {
2292         case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2293         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2294         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
2295         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
2296                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2297                 config->hw_vlan_insert = 0;
2298                 break;
2299         case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
2300         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
2301         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
2302         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
2303                 /*
2304                  * These NICs support VLAN insertion from WQE and
2305                  * report the wqe_vlan_insert flag. But there is the bug
2306                  * and PFC control may be broken, so disable feature.
2307                  */
2308                 config->hw_vlan_insert = 0;
2309                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2310                 break;
2311         default:
2312                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2313                 break;
2314         }
2315 exit:
2316         DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
2317 }
2318
2319 /**
2320  * Configures the metadata mask fields in the shared context.
2321  *
2322  * @param [in] dev
2323  *   Pointer to Ethernet device.
2324  */
2325 void
2326 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
2327 {
2328         struct mlx5_priv *priv = dev->data->dev_private;
2329         struct mlx5_dev_ctx_shared *sh = priv->sh;
2330         uint32_t meta, mark, reg_c0;
2331
2332         reg_c0 = ~priv->vport_meta_mask;
2333         switch (priv->config.dv_xmeta_en) {
2334         case MLX5_XMETA_MODE_LEGACY:
2335                 meta = UINT32_MAX;
2336                 mark = MLX5_FLOW_MARK_MASK;
2337                 break;
2338         case MLX5_XMETA_MODE_META16:
2339                 meta = reg_c0 >> rte_bsf32(reg_c0);
2340                 mark = MLX5_FLOW_MARK_MASK;
2341                 break;
2342         case MLX5_XMETA_MODE_META32:
2343                 meta = UINT32_MAX;
2344                 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
2345                 break;
2346         default:
2347                 meta = 0;
2348                 mark = 0;
2349                 MLX5_ASSERT(false);
2350                 break;
2351         }
2352         if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
2353                 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
2354                                  sh->dv_mark_mask, mark);
2355         else
2356                 sh->dv_mark_mask = mark;
2357         if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
2358                 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
2359                                  sh->dv_meta_mask, meta);
2360         else
2361                 sh->dv_meta_mask = meta;
2362         if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
2363                 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
2364                                  sh->dv_meta_mask, reg_c0);
2365         else
2366                 sh->dv_regc0_mask = reg_c0;
2367         DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
2368         DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
2369         DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
2370         DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
2371 }
2372
2373 int
2374 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
2375 {
2376         static const char *const dynf_names[] = {
2377                 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
2378                 RTE_MBUF_DYNFLAG_METADATA_NAME,
2379                 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
2380         };
2381         unsigned int i;
2382
2383         if (n < RTE_DIM(dynf_names))
2384                 return -ENOMEM;
2385         for (i = 0; i < RTE_DIM(dynf_names); i++) {
2386                 if (names[i] == NULL)
2387                         return -EINVAL;
2388                 strcpy(names[i], dynf_names[i]);
2389         }
2390         return RTE_DIM(dynf_names);
2391 }
2392
2393 /**
2394  * Comparison callback to sort device data.
2395  *
2396  * This is meant to be used with qsort().
2397  *
2398  * @param a[in]
2399  *   Pointer to pointer to first data object.
2400  * @param b[in]
2401  *   Pointer to pointer to second data object.
2402  *
2403  * @return
2404  *   0 if both objects are equal, less than 0 if the first argument is less
2405  *   than the second, greater than 0 otherwise.
2406  */
2407 int
2408 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
2409                               struct mlx5_dev_config *config,
2410                               struct rte_device *dpdk_dev)
2411 {
2412         struct mlx5_dev_ctx_shared *sh = priv->sh;
2413         struct mlx5_dev_config *sh_conf = NULL;
2414         uint16_t port_id;
2415
2416         MLX5_ASSERT(sh);
2417         /* Nothing to compare for the single/first device. */
2418         if (sh->refcnt == 1)
2419                 return 0;
2420         /* Find the device with shared context. */
2421         MLX5_ETH_FOREACH_DEV(port_id, dpdk_dev) {
2422                 struct mlx5_priv *opriv =
2423                         rte_eth_devices[port_id].data->dev_private;
2424
2425                 if (opriv && opriv != priv && opriv->sh == sh) {
2426                         sh_conf = &opriv->config;
2427                         break;
2428                 }
2429         }
2430         if (!sh_conf)
2431                 return 0;
2432         if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
2433                 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
2434                              " for shared %s context", sh->ibdev_name);
2435                 rte_errno = EINVAL;
2436                 return rte_errno;
2437         }
2438         if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
2439                 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
2440                              " for shared %s context", sh->ibdev_name);
2441                 rte_errno = EINVAL;
2442                 return rte_errno;
2443         }
2444         return 0;
2445 }
2446
2447 /**
2448  * Look for the ethernet device belonging to mlx5 driver.
2449  *
2450  * @param[in] port_id
2451  *   port_id to start looking for device.
2452  * @param[in] odev
2453  *   Pointer to the hint device. When device is being probed
2454  *   the its siblings (master and preceding representors might
2455  *   not have assigned driver yet (because the mlx5_os_pci_probe()
2456  *   is not completed yet, for this case match on hint
2457  *   device may be used to detect sibling device.
2458  *
2459  * @return
2460  *   port_id of found device, RTE_MAX_ETHPORT if not found.
2461  */
2462 uint16_t
2463 mlx5_eth_find_next(uint16_t port_id, struct rte_device *odev)
2464 {
2465         while (port_id < RTE_MAX_ETHPORTS) {
2466                 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
2467
2468                 if (dev->state != RTE_ETH_DEV_UNUSED &&
2469                     dev->device &&
2470                     (dev->device == odev ||
2471                      (dev->device->driver &&
2472                      dev->device->driver->name &&
2473                      ((strcmp(dev->device->driver->name,
2474                               MLX5_PCI_DRIVER_NAME) == 0) ||
2475                       (strcmp(dev->device->driver->name,
2476                               MLX5_AUXILIARY_DRIVER_NAME) == 0)))))
2477                         break;
2478                 port_id++;
2479         }
2480         if (port_id >= RTE_MAX_ETHPORTS)
2481                 return RTE_MAX_ETHPORTS;
2482         return port_id;
2483 }
2484
2485 /**
2486  * Callback to remove a device.
2487  *
2488  * This function removes all Ethernet devices belong to a given device.
2489  *
2490  * @param[in] cdev
2491  *   Pointer to the generic device.
2492  *
2493  * @return
2494  *   0 on success, the function cannot fail.
2495  */
2496 int
2497 mlx5_net_remove(struct mlx5_common_device *cdev)
2498 {
2499         uint16_t port_id;
2500         int ret = 0;
2501
2502         RTE_ETH_FOREACH_DEV_OF(port_id, cdev->dev) {
2503                 /*
2504                  * mlx5_dev_close() is not registered to secondary process,
2505                  * call the close function explicitly for secondary process.
2506                  */
2507                 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
2508                         ret |= mlx5_dev_close(&rte_eth_devices[port_id]);
2509                 else
2510                         ret |= rte_eth_dev_close(port_id);
2511         }
2512         return ret == 0 ? 0 : -EIO;
2513 }
2514
2515 static const struct rte_pci_id mlx5_pci_id_map[] = {
2516         {
2517                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2518                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
2519         },
2520         {
2521                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2522                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
2523         },
2524         {
2525                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2526                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
2527         },
2528         {
2529                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2530                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
2531         },
2532         {
2533                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2534                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
2535         },
2536         {
2537                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2538                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
2539         },
2540         {
2541                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2542                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
2543         },
2544         {
2545                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2546                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
2547         },
2548         {
2549                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2550                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
2551         },
2552         {
2553                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2554                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
2555         },
2556         {
2557                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2558                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
2559         },
2560         {
2561                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2562                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
2563         },
2564         {
2565                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2566                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
2567         },
2568         {
2569                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2570                                 PCI_DEVICE_ID_MELLANOX_CONNECTXVF)
2571         },
2572         {
2573                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2574                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
2575         },
2576         {
2577                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2578                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
2579         },
2580         {
2581                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2582                                 PCI_DEVICE_ID_MELLANOX_CONNECTX7)
2583         },
2584         {
2585                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2586                                 PCI_DEVICE_ID_MELLANOX_CONNECTX7BF)
2587         },
2588         {
2589                 .vendor_id = 0
2590         }
2591 };
2592
2593 static struct mlx5_class_driver mlx5_net_driver = {
2594         .drv_class = MLX5_CLASS_ETH,
2595         .name = RTE_STR(MLX5_ETH_DRIVER_NAME),
2596         .id_table = mlx5_pci_id_map,
2597         .probe = mlx5_os_net_probe,
2598         .remove = mlx5_net_remove,
2599         .probe_again = 1,
2600         .intr_lsc = 1,
2601         .intr_rmv = 1,
2602 };
2603
2604 /* Initialize driver log type. */
2605 RTE_LOG_REGISTER_DEFAULT(mlx5_logtype, NOTICE)
2606
2607 /**
2608  * Driver initialization routine.
2609  */
2610 RTE_INIT(rte_mlx5_pmd_init)
2611 {
2612         pthread_mutex_init(&mlx5_dev_ctx_list_mutex, NULL);
2613         mlx5_common_init();
2614         /* Build the static tables for Verbs conversion. */
2615         mlx5_set_ptype_table();
2616         mlx5_set_cksum_table();
2617         mlx5_set_swp_types_table();
2618         if (mlx5_glue)
2619                 mlx5_class_driver_register(&mlx5_net_driver);
2620 }
2621
2622 RTE_PMD_EXPORT_NAME(MLX5_ETH_DRIVER_NAME, __COUNTER__);
2623 RTE_PMD_REGISTER_PCI_TABLE(MLX5_ETH_DRIVER_NAME, mlx5_pci_id_map);
2624 RTE_PMD_REGISTER_KMOD_DEP(MLX5_ETH_DRIVER_NAME, "* ib_uverbs & mlx5_core & mlx5_ib");