1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
13 #include <rte_malloc.h>
14 #include <ethdev_driver.h>
16 #include <rte_bus_pci.h>
17 #include <rte_common.h>
18 #include <rte_kvargs.h>
19 #include <rte_rwlock.h>
20 #include <rte_spinlock.h>
21 #include <rte_string_fns.h>
22 #include <rte_alarm.h>
23 #include <rte_cycles.h>
25 #include <mlx5_glue.h>
26 #include <mlx5_devx_cmds.h>
27 #include <mlx5_common.h>
28 #include <mlx5_common_os.h>
29 #include <mlx5_common_mp.h>
30 #include <mlx5_malloc.h>
32 #include "mlx5_defs.h"
34 #include "mlx5_utils.h"
35 #include "mlx5_rxtx.h"
38 #include "mlx5_autoconf.h"
39 #include "mlx5_flow.h"
40 #include "mlx5_flow_os.h"
41 #include "rte_pmd_mlx5.h"
43 #define MLX5_ETH_DRIVER_NAME mlx5_eth
45 /* Driver type key for new device global syntax. */
46 #define MLX5_DRIVER_KEY "driver"
48 /* Device parameter to enable RX completion queue compression. */
49 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
51 /* Device parameter to enable padding Rx packet to cacheline size. */
52 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
54 /* Device parameter to enable Multi-Packet Rx queue. */
55 #define MLX5_RX_MPRQ_EN "mprq_en"
57 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
58 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
60 /* Device parameter to configure log 2 of the stride size for MPRQ. */
61 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
63 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
64 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
66 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
67 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
69 /* Device parameter to configure inline send. Deprecated, ignored.*/
70 #define MLX5_TXQ_INLINE "txq_inline"
72 /* Device parameter to limit packet size to inline with ordinary SEND. */
73 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
75 /* Device parameter to configure minimal data size to inline. */
76 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
78 /* Device parameter to limit packet size to inline with Enhanced MPW. */
79 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
82 * Device parameter to configure the number of TX queues threshold for
83 * enabling inline send.
85 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
88 * Device parameter to configure the number of TX queues threshold for
89 * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
91 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
93 /* Device parameter to enable multi-packet send WQEs. */
94 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
97 * Device parameter to force doorbell register mapping
98 * to non-cahed region eliminating the extra write memory barrier.
100 #define MLX5_TX_DB_NC "tx_db_nc"
103 * Device parameter to include 2 dsegs in the title WQEBB.
104 * Deprecated, ignored.
106 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
109 * Device parameter to limit the size of inlining packet.
110 * Deprecated, ignored.
112 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
115 * Device parameter to enable Tx scheduling on timestamps
116 * and specify the packet pacing granularity in nanoseconds.
118 #define MLX5_TX_PP "tx_pp"
121 * Device parameter to specify skew in nanoseconds on Tx datapath,
122 * it represents the time between SQ start WQE processing and
123 * appearing actual packet data on the wire.
125 #define MLX5_TX_SKEW "tx_skew"
128 * Device parameter to enable hardware Tx vector.
129 * Deprecated, ignored (no vectorized Tx routines anymore).
131 #define MLX5_TX_VEC_EN "tx_vec_en"
133 /* Device parameter to enable hardware Rx vector. */
134 #define MLX5_RX_VEC_EN "rx_vec_en"
136 /* Allow L3 VXLAN flow creation. */
137 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
139 /* Activate DV E-Switch flow steering. */
140 #define MLX5_DV_ESW_EN "dv_esw_en"
142 /* Activate DV flow steering. */
143 #define MLX5_DV_FLOW_EN "dv_flow_en"
145 /* Enable extensive flow metadata support. */
146 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
148 /* Device parameter to let the user manage the lacp traffic of bonded device */
149 #define MLX5_LACP_BY_USER "lacp_by_user"
151 /* Activate Netlink support in VF mode. */
152 #define MLX5_VF_NL_EN "vf_nl_en"
154 /* Enable extending memsegs when creating a MR. */
155 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
157 /* Select port representors to instantiate. */
158 #define MLX5_REPRESENTOR "representor"
160 /* Device parameter to configure the maximum number of dump files per queue. */
161 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
163 /* Configure timeout of LRO session (in microseconds). */
164 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
167 * Device parameter to configure the total data buffer size for a single
168 * hairpin queue (logarithm value).
170 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
172 /* Flow memory reclaim mode. */
173 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
175 /* The default memory allocator used in PMD. */
176 #define MLX5_SYS_MEM_EN "sys_mem_en"
177 /* Decap will be used or not. */
178 #define MLX5_DECAP_EN "decap_en"
180 /* Device parameter to configure allow or prevent duplicate rules pattern. */
181 #define MLX5_ALLOW_DUPLICATE_PATTERN "allow_duplicate_pattern"
183 /* Device parameter to configure implicit registration of mempool memory. */
184 #define MLX5_MR_MEMPOOL_REG_EN "mr_mempool_reg_en"
186 /* Shared memory between primary and secondary processes. */
187 struct mlx5_shared_data *mlx5_shared_data;
189 /** Driver-specific log messages type. */
192 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
193 LIST_HEAD_INITIALIZER();
194 static pthread_mutex_t mlx5_dev_ctx_list_mutex;
195 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
196 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
197 [MLX5_IPOOL_DECAP_ENCAP] = {
198 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
204 .malloc = mlx5_malloc,
206 .type = "mlx5_encap_decap_ipool",
208 [MLX5_IPOOL_PUSH_VLAN] = {
209 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
215 .malloc = mlx5_malloc,
217 .type = "mlx5_push_vlan_ipool",
220 .size = sizeof(struct mlx5_flow_dv_tag_resource),
226 .per_core_cache = (1 << 16),
227 .malloc = mlx5_malloc,
229 .type = "mlx5_tag_ipool",
231 [MLX5_IPOOL_PORT_ID] = {
232 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
238 .malloc = mlx5_malloc,
240 .type = "mlx5_port_id_ipool",
242 [MLX5_IPOOL_JUMP] = {
243 .size = sizeof(struct mlx5_flow_tbl_data_entry),
249 .malloc = mlx5_malloc,
251 .type = "mlx5_jump_ipool",
253 [MLX5_IPOOL_SAMPLE] = {
254 .size = sizeof(struct mlx5_flow_dv_sample_resource),
260 .malloc = mlx5_malloc,
262 .type = "mlx5_sample_ipool",
264 [MLX5_IPOOL_DEST_ARRAY] = {
265 .size = sizeof(struct mlx5_flow_dv_dest_array_resource),
271 .malloc = mlx5_malloc,
273 .type = "mlx5_dest_array_ipool",
275 [MLX5_IPOOL_TUNNEL_ID] = {
276 .size = sizeof(struct mlx5_flow_tunnel),
277 .trunk_size = MLX5_MAX_TUNNELS,
280 .type = "mlx5_tunnel_offload",
282 [MLX5_IPOOL_TNL_TBL_ID] = {
285 .type = "mlx5_flow_tnl_tbl_ipool",
290 * The ipool index should grow continually from small to big,
291 * for meter idx, so not set grow_trunk to avoid meter index
292 * not jump continually.
294 .size = sizeof(struct mlx5_legacy_flow_meter),
298 .malloc = mlx5_malloc,
300 .type = "mlx5_meter_ipool",
303 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
309 .malloc = mlx5_malloc,
311 .type = "mlx5_mcp_ipool",
313 [MLX5_IPOOL_HRXQ] = {
314 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
320 .malloc = mlx5_malloc,
322 .type = "mlx5_hrxq_ipool",
324 [MLX5_IPOOL_MLX5_FLOW] = {
326 * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
327 * It set in run time according to PCI function configuration.
335 .per_core_cache = 1 << 19,
336 .malloc = mlx5_malloc,
338 .type = "mlx5_flow_handle_ipool",
340 [MLX5_IPOOL_RTE_FLOW] = {
341 .size = sizeof(struct rte_flow),
345 .malloc = mlx5_malloc,
347 .type = "rte_flow_ipool",
349 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID] = {
352 .type = "mlx5_flow_rss_id_ipool",
354 [MLX5_IPOOL_RSS_SHARED_ACTIONS] = {
355 .size = sizeof(struct mlx5_shared_action_rss),
361 .malloc = mlx5_malloc,
363 .type = "mlx5_shared_action_rss",
365 [MLX5_IPOOL_MTR_POLICY] = {
367 * The ipool index should grow continually from small to big,
368 * for policy idx, so not set grow_trunk to avoid policy index
369 * not jump continually.
371 .size = sizeof(struct mlx5_flow_meter_sub_policy),
375 .malloc = mlx5_malloc,
377 .type = "mlx5_meter_policy_ipool",
381 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
382 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
384 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 1024
387 * Decide whether representor ID is a HPF(host PF) port on BF2.
390 * Pointer to Ethernet device structure.
393 * Non-zero if HPF, otherwise 0.
396 mlx5_is_hpf(struct rte_eth_dev *dev)
398 struct mlx5_priv *priv = dev->data->dev_private;
399 uint16_t repr = MLX5_REPRESENTOR_REPR(priv->representor_id);
400 int type = MLX5_REPRESENTOR_TYPE(priv->representor_id);
402 return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_VF &&
403 MLX5_REPRESENTOR_REPR(-1) == repr;
407 * Decide whether representor ID is a SF port representor.
410 * Pointer to Ethernet device structure.
413 * Non-zero if HPF, otherwise 0.
416 mlx5_is_sf_repr(struct rte_eth_dev *dev)
418 struct mlx5_priv *priv = dev->data->dev_private;
419 int type = MLX5_REPRESENTOR_TYPE(priv->representor_id);
421 return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_SF;
425 * Initialize the ASO aging management structure.
428 * Pointer to mlx5_dev_ctx_shared object to free
431 * 0 on success, a negative errno value otherwise and rte_errno is set.
434 mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh)
440 sh->aso_age_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->aso_age_mng),
441 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
442 if (!sh->aso_age_mng) {
443 DRV_LOG(ERR, "aso_age_mng allocation was failed.");
447 err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_FLOW_HIT);
449 mlx5_free(sh->aso_age_mng);
452 rte_rwlock_init(&sh->aso_age_mng->resize_rwl);
453 rte_spinlock_init(&sh->aso_age_mng->free_sl);
454 LIST_INIT(&sh->aso_age_mng->free);
459 * Close and release all the resources of the ASO aging management structure.
462 * Pointer to mlx5_dev_ctx_shared object to free.
465 mlx5_flow_aso_age_mng_close(struct mlx5_dev_ctx_shared *sh)
469 mlx5_aso_flow_hit_queue_poll_stop(sh);
470 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_FLOW_HIT);
471 if (sh->aso_age_mng->pools) {
472 struct mlx5_aso_age_pool *pool;
474 for (i = 0; i < sh->aso_age_mng->next; ++i) {
475 pool = sh->aso_age_mng->pools[i];
476 claim_zero(mlx5_devx_cmd_destroy
477 (pool->flow_hit_aso_obj));
478 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j)
479 if (pool->actions[j].dr_action)
481 (mlx5_flow_os_destroy_flow_action
482 (pool->actions[j].dr_action));
485 mlx5_free(sh->aso_age_mng->pools);
487 mlx5_free(sh->aso_age_mng);
491 * Initialize the shared aging list information per port.
494 * Pointer to mlx5_dev_ctx_shared object.
497 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
500 struct mlx5_age_info *age_info;
502 for (i = 0; i < sh->max_port; i++) {
503 age_info = &sh->port[i].age_info;
505 TAILQ_INIT(&age_info->aged_counters);
506 LIST_INIT(&age_info->aged_aso);
507 rte_spinlock_init(&age_info->aged_sl);
508 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
513 * Initialize the counters management structure.
516 * Pointer to mlx5_dev_ctx_shared object to free
519 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
521 struct mlx5_hca_attr *attr = &sh->cdev->config.hca_attr;
524 memset(&sh->cmng, 0, sizeof(sh->cmng));
525 TAILQ_INIT(&sh->cmng.flow_counters);
526 sh->cmng.min_id = MLX5_CNT_BATCH_OFFSET;
527 sh->cmng.max_id = -1;
528 sh->cmng.last_pool_idx = POOL_IDX_INVALID;
529 rte_spinlock_init(&sh->cmng.pool_update_sl);
530 for (i = 0; i < MLX5_COUNTER_TYPE_MAX; i++) {
531 TAILQ_INIT(&sh->cmng.counters[i]);
532 rte_spinlock_init(&sh->cmng.csl[i]);
534 if (sh->devx && !haswell_broadwell_cpu) {
535 sh->cmng.relaxed_ordering_write = attr->relaxed_ordering_write;
536 sh->cmng.relaxed_ordering_read = attr->relaxed_ordering_read;
541 * Destroy all the resources allocated for a counter memory management.
544 * Pointer to the memory management structure.
547 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
549 uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
551 LIST_REMOVE(mng, next);
552 claim_zero(mlx5_devx_cmd_destroy(mng->dm));
553 claim_zero(mlx5_os_umem_dereg(mng->umem));
558 * Close and release all the resources of the counters management.
561 * Pointer to mlx5_dev_ctx_shared object to free.
564 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
566 struct mlx5_counter_stats_mem_mng *mng;
572 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
573 if (rte_errno != EINPROGRESS)
578 if (sh->cmng.pools) {
579 struct mlx5_flow_counter_pool *pool;
580 uint16_t n_valid = sh->cmng.n_valid;
581 bool fallback = sh->cmng.counter_fallback;
583 for (i = 0; i < n_valid; ++i) {
584 pool = sh->cmng.pools[i];
585 if (!fallback && pool->min_dcs)
586 claim_zero(mlx5_devx_cmd_destroy
588 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
589 struct mlx5_flow_counter *cnt =
590 MLX5_POOL_GET_CNT(pool, j);
594 (mlx5_flow_os_destroy_flow_action
596 if (fallback && MLX5_POOL_GET_CNT
597 (pool, j)->dcs_when_free)
598 claim_zero(mlx5_devx_cmd_destroy
599 (cnt->dcs_when_free));
603 mlx5_free(sh->cmng.pools);
605 mng = LIST_FIRST(&sh->cmng.mem_mngs);
607 mlx5_flow_destroy_counter_stat_mem_mng(mng);
608 mng = LIST_FIRST(&sh->cmng.mem_mngs);
610 memset(&sh->cmng, 0, sizeof(sh->cmng));
614 * Initialize the aso flow meters management structure.
617 * Pointer to mlx5_dev_ctx_shared object to free
620 mlx5_aso_flow_mtrs_mng_init(struct mlx5_dev_ctx_shared *sh)
623 sh->mtrmng = mlx5_malloc(MLX5_MEM_ZERO,
625 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
628 "meter management allocation was failed.");
632 if (sh->meter_aso_en) {
633 rte_spinlock_init(&sh->mtrmng->pools_mng.mtrsl);
634 rte_rwlock_init(&sh->mtrmng->pools_mng.resize_mtrwl);
635 LIST_INIT(&sh->mtrmng->pools_mng.meters);
637 sh->mtrmng->def_policy_id = MLX5_INVALID_POLICY_ID;
643 * Close and release all the resources of
644 * the ASO flow meter management structure.
647 * Pointer to mlx5_dev_ctx_shared object to free.
650 mlx5_aso_flow_mtrs_mng_close(struct mlx5_dev_ctx_shared *sh)
652 struct mlx5_aso_mtr_pool *mtr_pool;
653 struct mlx5_flow_mtr_mng *mtrmng = sh->mtrmng;
655 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
656 struct mlx5_aso_mtr *aso_mtr;
658 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
660 if (sh->meter_aso_en) {
661 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_POLICER);
662 idx = mtrmng->pools_mng.n_valid;
664 mtr_pool = mtrmng->pools_mng.pools[idx];
665 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
666 for (i = 0; i < MLX5_ASO_MTRS_PER_POOL; i++) {
667 aso_mtr = &mtr_pool->mtrs[i];
668 if (aso_mtr->fm.meter_action)
670 (mlx5_glue->destroy_flow_action
671 (aso_mtr->fm.meter_action));
673 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
674 claim_zero(mlx5_devx_cmd_destroy
675 (mtr_pool->devx_obj));
676 mtrmng->pools_mng.n_valid--;
679 mlx5_free(sh->mtrmng->pools_mng.pools);
681 mlx5_free(sh->mtrmng);
685 /* Send FLOW_AGED event if needed. */
687 mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh)
689 struct mlx5_age_info *age_info;
692 for (i = 0; i < sh->max_port; i++) {
693 age_info = &sh->port[i].age_info;
694 if (!MLX5_AGE_GET(age_info, MLX5_AGE_EVENT_NEW))
696 MLX5_AGE_UNSET(age_info, MLX5_AGE_EVENT_NEW);
697 if (MLX5_AGE_GET(age_info, MLX5_AGE_TRIGGER)) {
698 MLX5_AGE_UNSET(age_info, MLX5_AGE_TRIGGER);
699 rte_eth_dev_callback_process
700 (&rte_eth_devices[sh->port[i].devx_ih_port_id],
701 RTE_ETH_EVENT_FLOW_AGED, NULL);
707 * Initialize the ASO connection tracking structure.
710 * Pointer to mlx5_dev_ctx_shared object.
713 * 0 on success, a negative errno value otherwise and rte_errno is set.
716 mlx5_flow_aso_ct_mng_init(struct mlx5_dev_ctx_shared *sh)
722 sh->ct_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->ct_mng),
723 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
725 DRV_LOG(ERR, "ASO CT management allocation failed.");
729 err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_CONNECTION_TRACKING);
731 mlx5_free(sh->ct_mng);
732 /* rte_errno should be extracted from the failure. */
736 rte_spinlock_init(&sh->ct_mng->ct_sl);
737 rte_rwlock_init(&sh->ct_mng->resize_rwl);
738 LIST_INIT(&sh->ct_mng->free_cts);
743 * Close and release all the resources of the
744 * ASO connection tracking management structure.
747 * Pointer to mlx5_dev_ctx_shared object to free.
750 mlx5_flow_aso_ct_mng_close(struct mlx5_dev_ctx_shared *sh)
752 struct mlx5_aso_ct_pools_mng *mng = sh->ct_mng;
753 struct mlx5_aso_ct_pool *ct_pool;
754 struct mlx5_aso_ct_action *ct;
760 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_CONNECTION_TRACKING);
764 ct_pool = mng->pools[idx];
765 for (i = 0; i < MLX5_ASO_CT_ACTIONS_PER_POOL; i++) {
766 ct = &ct_pool->actions[i];
767 val = __atomic_fetch_sub(&ct->refcnt, 1,
769 MLX5_ASSERT(val == 1);
772 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
773 if (ct->dr_action_orig)
774 claim_zero(mlx5_glue->destroy_flow_action
775 (ct->dr_action_orig));
776 if (ct->dr_action_rply)
777 claim_zero(mlx5_glue->destroy_flow_action
778 (ct->dr_action_rply));
781 claim_zero(mlx5_devx_cmd_destroy(ct_pool->devx_obj));
783 DRV_LOG(DEBUG, "%u ASO CT objects are being used in the pool %u",
787 /* in case of failure. */
790 mlx5_free(mng->pools);
792 /* Management structure must be cleared to 0s during allocation. */
797 * Initialize the flow resources' indexed mempool.
800 * Pointer to mlx5_dev_ctx_shared object.
802 * Pointer to user dev config.
805 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
806 const struct mlx5_dev_config *config)
809 struct mlx5_indexed_pool_config cfg;
811 for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
812 cfg = mlx5_ipool_cfg[i];
817 * Set MLX5_IPOOL_MLX5_FLOW ipool size
818 * according to PCI function flow configuration.
820 case MLX5_IPOOL_MLX5_FLOW:
821 cfg.size = config->dv_flow_en ?
822 sizeof(struct mlx5_flow_handle) :
823 MLX5_FLOW_HANDLE_VERBS_SIZE;
826 if (config->reclaim_mode) {
827 cfg.release_mem_en = 1;
828 cfg.per_core_cache = 0;
830 cfg.release_mem_en = 0;
832 sh->ipool[i] = mlx5_ipool_create(&cfg);
838 * Release the flow resources' indexed mempool.
841 * Pointer to mlx5_dev_ctx_shared object.
844 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
848 for (i = 0; i < MLX5_IPOOL_MAX; ++i)
849 mlx5_ipool_destroy(sh->ipool[i]);
850 for (i = 0; i < MLX5_MAX_MODIFY_NUM; ++i)
851 if (sh->mdh_ipools[i])
852 mlx5_ipool_destroy(sh->mdh_ipools[i]);
856 * Check if dynamic flex parser for eCPRI already exists.
859 * Pointer to Ethernet device structure.
862 * true on exists, false on not.
865 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
867 struct mlx5_priv *priv = dev->data->dev_private;
868 struct mlx5_ecpri_parser_profile *prf = &priv->sh->ecpri_parser;
874 * Allocation of a flex parser for eCPRI. Once created, this parser related
875 * resources will be held until the device is closed.
878 * Pointer to Ethernet device structure.
881 * 0 on success, a negative errno value otherwise and rte_errno is set.
884 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
886 struct mlx5_priv *priv = dev->data->dev_private;
887 struct mlx5_ecpri_parser_profile *prf = &priv->sh->ecpri_parser;
888 struct mlx5_devx_graph_node_attr node = {
889 .modify_field_select = 0,
894 if (!priv->config.hca_attr.parse_graph_flex_node) {
895 DRV_LOG(ERR, "Dynamic flex parser is not supported "
896 "for device %s.", priv->dev_data->name);
899 node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED;
900 /* 8 bytes now: 4B common header + 4B message body header. */
901 node.header_length_base_value = 0x8;
902 /* After MAC layer: Ether / VLAN. */
903 node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC;
904 /* Type of compared condition should be 0xAEFE in the L2 layer. */
905 node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI;
906 /* Sample #0: type in common header. */
907 node.sample[0].flow_match_sample_en = 1;
909 node.sample[0].flow_match_sample_offset_mode = 0x0;
910 /* Only the 2nd byte will be used. */
911 node.sample[0].flow_match_sample_field_base_offset = 0x0;
912 /* Sample #1: message payload. */
913 node.sample[1].flow_match_sample_en = 1;
915 node.sample[1].flow_match_sample_offset_mode = 0x0;
917 * Only the first two bytes will be used right now, and its offset will
918 * start after the common header that with the length of a DW(u32).
920 node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);
921 prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->cdev->ctx, &node);
923 DRV_LOG(ERR, "Failed to create flex parser node object.");
924 return (rte_errno == 0) ? -ENODEV : -rte_errno;
927 ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num);
929 DRV_LOG(ERR, "Failed to query sample IDs.");
930 return (rte_errno == 0) ? -ENODEV : -rte_errno;
932 prf->offset[0] = 0x0;
933 prf->offset[1] = sizeof(uint32_t);
934 prf->ids[0] = ids[0];
935 prf->ids[1] = ids[1];
940 * Destroy the flex parser node, including the parser itself, input / output
941 * arcs and DW samples. Resources could be reused then.
944 * Pointer to Ethernet device structure.
947 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
949 struct mlx5_priv *priv = dev->data->dev_private;
950 struct mlx5_ecpri_parser_profile *prf = &priv->sh->ecpri_parser;
953 mlx5_devx_cmd_destroy(prf->obj);
958 mlx5_get_supported_sw_parsing_offloads(const struct mlx5_hca_attr *attr)
960 uint32_t sw_parsing_offloads = 0;
963 sw_parsing_offloads |= MLX5_SW_PARSING_CAP;
965 sw_parsing_offloads |= MLX5_SW_PARSING_CSUM_CAP;
968 sw_parsing_offloads |= MLX5_SW_PARSING_TSO_CAP;
970 return sw_parsing_offloads;
974 mlx5_get_supported_tunneling_offloads(const struct mlx5_hca_attr *attr)
976 uint32_t tn_offloads = 0;
978 if (attr->tunnel_stateless_vxlan)
979 tn_offloads |= MLX5_TUNNELED_OFFLOADS_VXLAN_CAP;
980 if (attr->tunnel_stateless_gre)
981 tn_offloads |= MLX5_TUNNELED_OFFLOADS_GRE_CAP;
982 if (attr->tunnel_stateless_geneve_rx)
983 tn_offloads |= MLX5_TUNNELED_OFFLOADS_GENEVE_CAP;
988 * Allocate Rx and Tx UARs in robust fashion.
989 * This routine handles the following UAR allocation issues:
991 * - tries to allocate the UAR with the most appropriate memory
992 * mapping type from the ones supported by the host
994 * - tries to allocate the UAR with non-NULL base address
995 * OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as
996 * UAR base address if UAR was not the first object in the UAR page.
997 * It caused the PMD failure and we should try to get another UAR
998 * till we get the first one with non-NULL base address returned.
1001 mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh,
1002 const struct mlx5_common_dev_config *config)
1004 uint32_t uar_mapping, retry;
1008 for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
1009 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
1010 /* Control the mapping type according to the settings. */
1011 uar_mapping = (config->dbnc == MLX5_TXDB_NCACHED) ?
1012 MLX5DV_UAR_ALLOC_TYPE_NC :
1013 MLX5DV_UAR_ALLOC_TYPE_BF;
1015 RTE_SET_USED(config);
1017 * It seems we have no way to control the memory mapping type
1018 * for the UAR, the default "Write-Combining" type is supposed.
1019 * The UAR initialization on queue creation queries the
1020 * actual mapping type done by Verbs/kernel and setups the
1021 * PMD datapath accordingly.
1025 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->cdev->ctx,
1027 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
1029 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
1030 if (config->dbnc == MLX5_TXDB_CACHED ||
1031 config->dbnc == MLX5_TXDB_HEURISTIC)
1032 DRV_LOG(WARNING, "Devarg tx_db_nc setting "
1033 "is not supported by DevX");
1035 * In some environments like virtual machine
1036 * the Write Combining mapped might be not supported
1037 * and UAR allocation fails. We try "Non-Cached"
1038 * mapping for the case. The tx_burst routines take
1039 * the UAR mapping type into account on UAR setup
1040 * on queue creation.
1042 DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (BF)");
1043 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
1044 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->cdev->ctx,
1046 } else if (!sh->tx_uar &&
1047 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_NC) {
1048 if (config->dbnc == MLX5_TXDB_NCACHED)
1049 DRV_LOG(WARNING, "Devarg tx_db_nc settings "
1050 "is not supported by DevX");
1052 * If Verbs/kernel does not support "Non-Cached"
1053 * try the "Write-Combining".
1055 DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (NC)");
1056 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_BF;
1057 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->cdev->ctx,
1062 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (BF/NC)");
1066 base_addr = mlx5_os_get_devx_uar_base_addr(sh->tx_uar);
1070 * The UARs are allocated by rdma_core within the
1071 * IB device context, on context closure all UARs
1072 * will be freed, should be no memory/object leakage.
1074 DRV_LOG(DEBUG, "Retrying to allocate Tx DevX UAR");
1077 /* Check whether we finally succeeded with valid UAR allocation. */
1079 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (NULL base)");
1083 for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
1085 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar(sh->cdev->ctx,
1087 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
1088 if (!sh->devx_rx_uar &&
1089 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
1091 * Rx UAR is used to control interrupts only,
1092 * should be no datapath noticeable impact,
1093 * can try "Non-Cached" mapping safely.
1095 DRV_LOG(DEBUG, "Failed to allocate Rx DevX UAR (BF)");
1096 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
1097 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
1098 (sh->cdev->ctx, uar_mapping);
1101 if (!sh->devx_rx_uar) {
1102 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (BF/NC)");
1106 base_addr = mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar);
1110 * The UARs are allocated by rdma_core within the
1111 * IB device context, on context closure all UARs
1112 * will be freed, should be no memory/object leakage.
1114 DRV_LOG(DEBUG, "Retrying to allocate Rx DevX UAR");
1115 sh->devx_rx_uar = NULL;
1117 /* Check whether we finally succeeded with valid UAR allocation. */
1118 if (!sh->devx_rx_uar) {
1119 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (NULL base)");
1127 * rte_mempool_walk() callback to unregister Rx mempools.
1128 * It used when implicit mempool registration is disabled.
1131 * The mempool being walked.
1133 * Pointer to the device shared context.
1136 mlx5_dev_ctx_shared_rx_mempool_unregister_cb(struct rte_mempool *mp, void *arg)
1138 struct mlx5_dev_ctx_shared *sh = arg;
1140 mlx5_dev_mempool_unregister(sh->cdev, mp);
1144 * Callback used when implicit mempool registration is disabled
1145 * in order to track Rx mempool destruction.
1148 * Mempool life cycle event.
1150 * An Rx mempool registered explicitly when the port is started.
1152 * Pointer to a device shared context.
1155 mlx5_dev_ctx_shared_rx_mempool_event_cb(enum rte_mempool_event event,
1156 struct rte_mempool *mp, void *arg)
1158 struct mlx5_dev_ctx_shared *sh = arg;
1160 if (event == RTE_MEMPOOL_EVENT_DESTROY)
1161 mlx5_dev_mempool_unregister(sh->cdev, mp);
1165 mlx5_dev_ctx_shared_mempool_subscribe(struct rte_eth_dev *dev)
1167 struct mlx5_priv *priv = dev->data->dev_private;
1168 struct mlx5_dev_ctx_shared *sh = priv->sh;
1171 /* Check if we only need to track Rx mempool destruction. */
1172 if (!sh->cdev->config.mr_mempool_reg_en) {
1173 ret = rte_mempool_event_callback_register
1174 (mlx5_dev_ctx_shared_rx_mempool_event_cb, sh);
1175 return ret == 0 || rte_errno == EEXIST ? 0 : ret;
1177 return mlx5_dev_mempool_subscribe(sh->cdev);
1181 * Set up multiple TISs with different affinities according to
1182 * number of bonding ports
1185 * Pointer of shared context.
1188 * Zero on success, -1 otherwise.
1191 mlx5_setup_tis(struct mlx5_dev_ctx_shared *sh)
1194 struct mlx5_devx_lag_context lag_ctx = { 0 };
1195 struct mlx5_devx_tis_attr tis_attr = { 0 };
1197 tis_attr.transport_domain = sh->td->id;
1198 if (sh->bond.n_port) {
1199 if (!mlx5_devx_cmd_query_lag(sh->cdev->ctx, &lag_ctx)) {
1200 sh->lag.tx_remap_affinity[0] =
1201 lag_ctx.tx_remap_affinity_1;
1202 sh->lag.tx_remap_affinity[1] =
1203 lag_ctx.tx_remap_affinity_2;
1204 sh->lag.affinity_mode = lag_ctx.port_select_mode;
1206 DRV_LOG(ERR, "Failed to query lag affinity.");
1209 if (sh->lag.affinity_mode == MLX5_LAG_MODE_TIS) {
1210 for (i = 0; i < sh->bond.n_port; i++) {
1211 tis_attr.lag_tx_port_affinity =
1212 MLX5_IFC_LAG_MAP_TIS_AFFINITY(i,
1214 sh->tis[i] = mlx5_devx_cmd_create_tis(sh->cdev->ctx,
1217 DRV_LOG(ERR, "Failed to TIS %d/%d for bonding device"
1218 " %s.", i, sh->bond.n_port,
1223 DRV_LOG(DEBUG, "LAG number of ports : %d, affinity_1 & 2 : pf%d & %d.\n",
1224 sh->bond.n_port, lag_ctx.tx_remap_affinity_1,
1225 lag_ctx.tx_remap_affinity_2);
1228 if (sh->lag.affinity_mode == MLX5_LAG_MODE_HASH)
1229 DRV_LOG(INFO, "Device %s enabled HW hash based LAG.",
1232 tis_attr.lag_tx_port_affinity = 0;
1233 sh->tis[0] = mlx5_devx_cmd_create_tis(sh->cdev->ctx, &tis_attr);
1235 DRV_LOG(ERR, "Failed to TIS 0 for bonding device"
1236 " %s.", sh->ibdev_name);
1243 * Allocate shared device context. If there is multiport device the
1244 * master and representors will share this context, if there is single
1245 * port dedicated device, the context will be used by only given
1246 * port due to unification.
1248 * Routine first searches the context for the specified device name,
1249 * if found the shared context assumed and reference counter is incremented.
1250 * If no context found the new one is created and initialized with specified
1251 * device context and parameters.
1254 * Pointer to the device attributes (name, port, etc).
1256 * Pointer to device configuration structure.
1259 * Pointer to mlx5_dev_ctx_shared object on success,
1260 * otherwise NULL and rte_errno is set.
1262 struct mlx5_dev_ctx_shared *
1263 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
1264 const struct mlx5_dev_config *config)
1266 struct mlx5_dev_ctx_shared *sh;
1271 /* Secondary process should not create the shared context. */
1272 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1273 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1274 /* Search for IB context by device name. */
1275 LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
1276 if (!strcmp(sh->ibdev_name, spawn->phys_dev_name)) {
1281 /* No device found, we have to create new shared context. */
1282 MLX5_ASSERT(spawn->max_port);
1283 sh = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
1284 sizeof(struct mlx5_dev_ctx_shared) +
1286 sizeof(struct mlx5_dev_shared_port),
1287 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
1289 DRV_LOG(ERR, "shared context allocation failure");
1293 pthread_mutex_init(&sh->txpp.mutex, NULL);
1294 sh->numa_node = spawn->cdev->dev->numa_node;
1295 sh->cdev = spawn->cdev;
1296 sh->devx = sh->cdev->config.devx;
1297 if (spawn->bond_info)
1298 sh->bond = *spawn->bond_info;
1299 err = mlx5_os_get_dev_attr(sh->cdev, &sh->device_attr);
1301 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
1305 sh->max_port = spawn->max_port;
1306 sh->reclaim_mode = config->reclaim_mode;
1307 strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->cdev->ctx),
1308 sizeof(sh->ibdev_name) - 1);
1309 strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->cdev->ctx),
1310 sizeof(sh->ibdev_path) - 1);
1312 * Setting port_id to max unallowed value means
1313 * there is no interrupt subhandler installed for
1314 * the given port index i.
1316 for (i = 0; i < sh->max_port; i++) {
1317 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
1318 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
1321 sh->td = mlx5_devx_cmd_create_td(sh->cdev->ctx);
1323 DRV_LOG(ERR, "TD allocation failure");
1327 if (mlx5_setup_tis(sh)) {
1328 DRV_LOG(ERR, "TIS allocation failure");
1332 err = mlx5_alloc_rxtx_uars(sh, &sh->cdev->config);
1335 MLX5_ASSERT(sh->tx_uar);
1336 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->tx_uar));
1338 MLX5_ASSERT(sh->devx_rx_uar);
1339 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar));
1342 /* Initialize UAR access locks for 32bit implementations. */
1343 rte_spinlock_init(&sh->uar_lock_cq);
1344 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
1345 rte_spinlock_init(&sh->uar_lock[i]);
1347 mlx5_os_dev_shared_handler_install(sh);
1348 if (LIST_EMPTY(&mlx5_dev_ctx_list)) {
1349 err = mlx5_flow_os_init_workspace_once();
1353 mlx5_flow_aging_init(sh);
1354 mlx5_flow_counters_mng_init(sh);
1355 mlx5_flow_ipool_create(sh, config);
1356 /* Add context to the global device list. */
1357 LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
1358 rte_spinlock_init(&sh->geneve_tlv_opt_sl);
1360 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1363 pthread_mutex_destroy(&sh->txpp.mutex);
1364 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1367 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1371 claim_zero(mlx5_devx_cmd_destroy(sh->tis[i]));
1372 } while (++i < (uint32_t)sh->bond.n_port);
1373 if (sh->devx_rx_uar)
1374 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1376 mlx5_glue->devx_free_uar(sh->tx_uar);
1378 MLX5_ASSERT(err > 0);
1384 * Free shared IB device context. Decrement counter and if zero free
1385 * all allocated resources and close handles.
1388 * Pointer to mlx5_dev_ctx_shared object to free
1391 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
1396 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1397 #ifdef RTE_LIBRTE_MLX5_DEBUG
1398 /* Check the object presence in the list. */
1399 struct mlx5_dev_ctx_shared *lctx;
1401 LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
1406 DRV_LOG(ERR, "Freeing non-existing shared IB context");
1411 MLX5_ASSERT(sh->refcnt);
1412 /* Secondary process should not free the shared context. */
1413 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1416 /* Stop watching for mempool events and unregister all mempools. */
1417 if (!sh->cdev->config.mr_mempool_reg_en) {
1418 ret = rte_mempool_event_callback_unregister
1419 (mlx5_dev_ctx_shared_rx_mempool_event_cb, sh);
1422 (mlx5_dev_ctx_shared_rx_mempool_unregister_cb, sh);
1424 /* Remove context from the global device list. */
1425 LIST_REMOVE(sh, next);
1426 /* Release resources on the last device removal. */
1427 if (LIST_EMPTY(&mlx5_dev_ctx_list)) {
1428 mlx5_os_net_cleanup();
1429 mlx5_flow_os_release_workspace();
1431 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1433 * Ensure there is no async event handler installed.
1434 * Only primary process handles async device events.
1436 mlx5_flow_counters_mng_close(sh);
1437 if (sh->aso_age_mng) {
1438 mlx5_flow_aso_age_mng_close(sh);
1439 sh->aso_age_mng = NULL;
1442 mlx5_aso_flow_mtrs_mng_close(sh);
1443 mlx5_flow_ipool_destroy(sh);
1444 mlx5_os_dev_shared_handler_uninstall(sh);
1446 mlx5_glue->devx_free_uar(sh->tx_uar);
1451 claim_zero(mlx5_devx_cmd_destroy(sh->tis[i]));
1452 } while (++i < sh->bond.n_port);
1454 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1455 if (sh->devx_rx_uar)
1456 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1457 MLX5_ASSERT(sh->geneve_tlv_option_resource == NULL);
1458 pthread_mutex_destroy(&sh->txpp.mutex);
1462 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1466 * Destroy table hash list.
1469 * Pointer to the private device data structure.
1472 mlx5_free_table_hash_list(struct mlx5_priv *priv)
1474 struct mlx5_dev_ctx_shared *sh = priv->sh;
1478 mlx5_hlist_destroy(sh->flow_tbls);
1479 sh->flow_tbls = NULL;
1483 * Initialize flow table hash list and create the root tables entry
1487 * Pointer to the private device data structure.
1490 * Zero on success, positive error code otherwise.
1493 mlx5_alloc_table_hash_list(struct mlx5_priv *priv __rte_unused)
1496 /* Tables are only used in DV and DR modes. */
1497 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
1498 struct mlx5_dev_ctx_shared *sh = priv->sh;
1499 char s[MLX5_NAME_SIZE];
1502 snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1503 sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE,
1505 flow_dv_tbl_create_cb,
1506 flow_dv_tbl_match_cb,
1507 flow_dv_tbl_remove_cb,
1508 flow_dv_tbl_clone_cb,
1509 flow_dv_tbl_clone_free_cb);
1510 if (!sh->flow_tbls) {
1511 DRV_LOG(ERR, "flow tables with hash creation failed.");
1515 #ifndef HAVE_MLX5DV_DR
1516 struct rte_flow_error error;
1517 struct rte_eth_dev *dev = &rte_eth_devices[priv->dev_data->port_id];
1520 * In case we have not DR support, the zero tables should be created
1521 * because DV expect to see them even if they cannot be created by
1524 if (!flow_dv_tbl_resource_get(dev, 0, 0, 0, 0,
1525 NULL, 0, 1, 0, &error) ||
1526 !flow_dv_tbl_resource_get(dev, 0, 1, 0, 0,
1527 NULL, 0, 1, 0, &error) ||
1528 !flow_dv_tbl_resource_get(dev, 0, 0, 1, 0,
1529 NULL, 0, 1, 0, &error)) {
1535 mlx5_free_table_hash_list(priv);
1536 #endif /* HAVE_MLX5DV_DR */
1542 * Retrieve integer value from environment variable.
1545 * Environment variable name.
1548 * Integer value, 0 if the variable is not set.
1551 mlx5_getenv_int(const char *name)
1553 const char *val = getenv(name);
1561 * DPDK callback to add udp tunnel port
1564 * A pointer to eth_dev
1565 * @param[in] udp_tunnel
1566 * A pointer to udp tunnel
1569 * 0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1572 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1573 struct rte_eth_udp_tunnel *udp_tunnel)
1575 MLX5_ASSERT(udp_tunnel != NULL);
1576 if (udp_tunnel->prot_type == RTE_ETH_TUNNEL_TYPE_VXLAN &&
1577 udp_tunnel->udp_port == 4789)
1579 if (udp_tunnel->prot_type == RTE_ETH_TUNNEL_TYPE_VXLAN_GPE &&
1580 udp_tunnel->udp_port == 4790)
1586 * Initialize process private data structure.
1589 * Pointer to Ethernet device structure.
1592 * 0 on success, a negative errno value otherwise and rte_errno is set.
1595 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1597 struct mlx5_priv *priv = dev->data->dev_private;
1598 struct mlx5_proc_priv *ppriv;
1601 mlx5_proc_priv_uninit(dev);
1603 * UAR register table follows the process private structure. BlueFlame
1604 * registers for Tx queues are stored in the table.
1607 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1608 ppriv = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, ppriv_size,
1609 RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1614 ppriv->uar_table_sz = priv->txqs_n;
1615 dev->process_private = ppriv;
1620 * Un-initialize process private data structure.
1623 * Pointer to Ethernet device structure.
1626 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1628 if (!dev->process_private)
1630 mlx5_free(dev->process_private);
1631 dev->process_private = NULL;
1635 * DPDK callback to close the device.
1637 * Destroy all queues and objects, free memory.
1640 * Pointer to Ethernet device structure.
1643 mlx5_dev_close(struct rte_eth_dev *dev)
1645 struct mlx5_priv *priv = dev->data->dev_private;
1649 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1650 /* Check if process_private released. */
1651 if (!dev->process_private)
1653 mlx5_tx_uar_uninit_secondary(dev);
1654 mlx5_proc_priv_uninit(dev);
1655 rte_eth_dev_release_port(dev);
1660 DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1662 ((priv->sh->cdev->ctx != NULL) ?
1663 mlx5_os_get_ctx_device_name(priv->sh->cdev->ctx) : ""));
1665 * If default mreg copy action is removed at the stop stage,
1666 * the search will return none and nothing will be done anymore.
1668 mlx5_flow_stop_default(dev);
1669 mlx5_traffic_disable(dev);
1671 * If all the flows are already flushed in the device stop stage,
1672 * then this will return directly without any action.
1674 mlx5_flow_list_flush(dev, MLX5_FLOW_TYPE_GEN, true);
1675 mlx5_action_handle_flush(dev);
1676 mlx5_flow_meter_flush(dev, NULL);
1677 /* Prevent crashes when queues are still in use. */
1678 dev->rx_pkt_burst = removed_rx_burst;
1679 dev->tx_pkt_burst = removed_tx_burst;
1681 /* Disable datapath on secondary process. */
1682 mlx5_mp_os_req_stop_rxtx(dev);
1683 /* Free the eCPRI flex parser resource. */
1684 mlx5_flex_parser_ecpri_release(dev);
1685 mlx5_flex_item_port_cleanup(dev);
1686 if (priv->rxqs != NULL) {
1687 /* XXX race condition if mlx5_rx_burst() is still running. */
1688 rte_delay_us_sleep(1000);
1689 for (i = 0; (i != priv->rxqs_n); ++i)
1690 mlx5_rxq_release(dev, i);
1694 if (priv->representor) {
1695 /* Each representor has a dedicated interrupts handler */
1696 mlx5_free(dev->intr_handle);
1697 dev->intr_handle = NULL;
1699 if (priv->txqs != NULL) {
1700 /* XXX race condition if mlx5_tx_burst() is still running. */
1701 rte_delay_us_sleep(1000);
1702 for (i = 0; (i != priv->txqs_n); ++i)
1703 mlx5_txq_release(dev, i);
1707 mlx5_proc_priv_uninit(dev);
1708 if (priv->q_counters) {
1709 mlx5_devx_cmd_destroy(priv->q_counters);
1710 priv->q_counters = NULL;
1712 if (priv->drop_queue.hrxq)
1713 mlx5_drop_action_destroy(dev);
1714 if (priv->mreg_cp_tbl)
1715 mlx5_hlist_destroy(priv->mreg_cp_tbl);
1716 mlx5_mprq_free_mp(dev);
1717 if (priv->sh->ct_mng)
1718 mlx5_flow_aso_ct_mng_close(priv->sh);
1719 mlx5_os_free_shared_dr(priv);
1720 if (priv->rss_conf.rss_key != NULL)
1721 mlx5_free(priv->rss_conf.rss_key);
1722 if (priv->reta_idx != NULL)
1723 mlx5_free(priv->reta_idx);
1724 if (priv->config.vf)
1725 mlx5_os_mac_addr_flush(dev);
1726 if (priv->nl_socket_route >= 0)
1727 close(priv->nl_socket_route);
1728 if (priv->nl_socket_rdma >= 0)
1729 close(priv->nl_socket_rdma);
1730 if (priv->vmwa_context)
1731 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1732 ret = mlx5_hrxq_verify(dev);
1734 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1735 dev->data->port_id);
1736 ret = mlx5_ind_table_obj_verify(dev);
1738 DRV_LOG(WARNING, "port %u some indirection table still remain",
1739 dev->data->port_id);
1740 ret = mlx5_rxq_obj_verify(dev);
1742 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1743 dev->data->port_id);
1744 ret = mlx5_rxq_verify(dev);
1746 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1747 dev->data->port_id);
1748 ret = mlx5_txq_obj_verify(dev);
1750 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1751 dev->data->port_id);
1752 ret = mlx5_txq_verify(dev);
1754 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1755 dev->data->port_id);
1756 ret = mlx5_flow_verify(dev);
1758 DRV_LOG(WARNING, "port %u some flows still remain",
1759 dev->data->port_id);
1761 mlx5_list_destroy(priv->hrxqs);
1763 * Free the shared context in last turn, because the cleanup
1764 * routines above may use some shared fields, like
1765 * mlx5_os_mac_addr_flush() uses ibdev_path for retrieveing
1766 * ifindex if Netlink fails.
1768 mlx5_free_shared_dev_ctx(priv->sh);
1769 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1773 MLX5_ETH_FOREACH_DEV(port_id, dev->device) {
1774 struct mlx5_priv *opriv =
1775 rte_eth_devices[port_id].data->dev_private;
1778 opriv->domain_id != priv->domain_id ||
1779 &rte_eth_devices[port_id] == dev)
1785 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1787 memset(priv, 0, sizeof(*priv));
1788 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1790 * Reset mac_addrs to NULL such that it is not freed as part of
1791 * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1792 * it is freed when dev_private is freed.
1794 dev->data->mac_addrs = NULL;
1798 const struct eth_dev_ops mlx5_dev_ops = {
1799 .dev_configure = mlx5_dev_configure,
1800 .dev_start = mlx5_dev_start,
1801 .dev_stop = mlx5_dev_stop,
1802 .dev_set_link_down = mlx5_set_link_down,
1803 .dev_set_link_up = mlx5_set_link_up,
1804 .dev_close = mlx5_dev_close,
1805 .promiscuous_enable = mlx5_promiscuous_enable,
1806 .promiscuous_disable = mlx5_promiscuous_disable,
1807 .allmulticast_enable = mlx5_allmulticast_enable,
1808 .allmulticast_disable = mlx5_allmulticast_disable,
1809 .link_update = mlx5_link_update,
1810 .stats_get = mlx5_stats_get,
1811 .stats_reset = mlx5_stats_reset,
1812 .xstats_get = mlx5_xstats_get,
1813 .xstats_reset = mlx5_xstats_reset,
1814 .xstats_get_names = mlx5_xstats_get_names,
1815 .fw_version_get = mlx5_fw_version_get,
1816 .dev_infos_get = mlx5_dev_infos_get,
1817 .representor_info_get = mlx5_representor_info_get,
1818 .read_clock = mlx5_txpp_read_clock,
1819 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1820 .vlan_filter_set = mlx5_vlan_filter_set,
1821 .rx_queue_setup = mlx5_rx_queue_setup,
1822 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1823 .tx_queue_setup = mlx5_tx_queue_setup,
1824 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1825 .rx_queue_release = mlx5_rx_queue_release,
1826 .tx_queue_release = mlx5_tx_queue_release,
1827 .rx_queue_start = mlx5_rx_queue_start,
1828 .rx_queue_stop = mlx5_rx_queue_stop,
1829 .tx_queue_start = mlx5_tx_queue_start,
1830 .tx_queue_stop = mlx5_tx_queue_stop,
1831 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1832 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1833 .mac_addr_remove = mlx5_mac_addr_remove,
1834 .mac_addr_add = mlx5_mac_addr_add,
1835 .mac_addr_set = mlx5_mac_addr_set,
1836 .set_mc_addr_list = mlx5_set_mc_addr_list,
1837 .mtu_set = mlx5_dev_set_mtu,
1838 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1839 .vlan_offload_set = mlx5_vlan_offload_set,
1840 .reta_update = mlx5_dev_rss_reta_update,
1841 .reta_query = mlx5_dev_rss_reta_query,
1842 .rss_hash_update = mlx5_rss_hash_update,
1843 .rss_hash_conf_get = mlx5_rss_hash_conf_get,
1844 .flow_ops_get = mlx5_flow_ops_get,
1845 .rxq_info_get = mlx5_rxq_info_get,
1846 .txq_info_get = mlx5_txq_info_get,
1847 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1848 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1849 .rx_queue_intr_enable = mlx5_rx_intr_enable,
1850 .rx_queue_intr_disable = mlx5_rx_intr_disable,
1851 .is_removed = mlx5_is_removed,
1852 .udp_tunnel_port_add = mlx5_udp_tunnel_port_add,
1853 .get_module_info = mlx5_get_module_info,
1854 .get_module_eeprom = mlx5_get_module_eeprom,
1855 .hairpin_cap_get = mlx5_hairpin_cap_get,
1856 .mtr_ops_get = mlx5_flow_meter_ops_get,
1857 .hairpin_bind = mlx5_hairpin_bind,
1858 .hairpin_unbind = mlx5_hairpin_unbind,
1859 .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1860 .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1861 .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1862 .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1863 .get_monitor_addr = mlx5_get_monitor_addr,
1866 /* Available operations from secondary process. */
1867 const struct eth_dev_ops mlx5_dev_sec_ops = {
1868 .stats_get = mlx5_stats_get,
1869 .stats_reset = mlx5_stats_reset,
1870 .xstats_get = mlx5_xstats_get,
1871 .xstats_reset = mlx5_xstats_reset,
1872 .xstats_get_names = mlx5_xstats_get_names,
1873 .fw_version_get = mlx5_fw_version_get,
1874 .dev_infos_get = mlx5_dev_infos_get,
1875 .representor_info_get = mlx5_representor_info_get,
1876 .read_clock = mlx5_txpp_read_clock,
1877 .rx_queue_start = mlx5_rx_queue_start,
1878 .rx_queue_stop = mlx5_rx_queue_stop,
1879 .tx_queue_start = mlx5_tx_queue_start,
1880 .tx_queue_stop = mlx5_tx_queue_stop,
1881 .rxq_info_get = mlx5_rxq_info_get,
1882 .txq_info_get = mlx5_txq_info_get,
1883 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1884 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1885 .get_module_info = mlx5_get_module_info,
1886 .get_module_eeprom = mlx5_get_module_eeprom,
1889 /* Available operations in flow isolated mode. */
1890 const struct eth_dev_ops mlx5_dev_ops_isolate = {
1891 .dev_configure = mlx5_dev_configure,
1892 .dev_start = mlx5_dev_start,
1893 .dev_stop = mlx5_dev_stop,
1894 .dev_set_link_down = mlx5_set_link_down,
1895 .dev_set_link_up = mlx5_set_link_up,
1896 .dev_close = mlx5_dev_close,
1897 .promiscuous_enable = mlx5_promiscuous_enable,
1898 .promiscuous_disable = mlx5_promiscuous_disable,
1899 .allmulticast_enable = mlx5_allmulticast_enable,
1900 .allmulticast_disable = mlx5_allmulticast_disable,
1901 .link_update = mlx5_link_update,
1902 .stats_get = mlx5_stats_get,
1903 .stats_reset = mlx5_stats_reset,
1904 .xstats_get = mlx5_xstats_get,
1905 .xstats_reset = mlx5_xstats_reset,
1906 .xstats_get_names = mlx5_xstats_get_names,
1907 .fw_version_get = mlx5_fw_version_get,
1908 .dev_infos_get = mlx5_dev_infos_get,
1909 .representor_info_get = mlx5_representor_info_get,
1910 .read_clock = mlx5_txpp_read_clock,
1911 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1912 .vlan_filter_set = mlx5_vlan_filter_set,
1913 .rx_queue_setup = mlx5_rx_queue_setup,
1914 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1915 .tx_queue_setup = mlx5_tx_queue_setup,
1916 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1917 .rx_queue_release = mlx5_rx_queue_release,
1918 .tx_queue_release = mlx5_tx_queue_release,
1919 .rx_queue_start = mlx5_rx_queue_start,
1920 .rx_queue_stop = mlx5_rx_queue_stop,
1921 .tx_queue_start = mlx5_tx_queue_start,
1922 .tx_queue_stop = mlx5_tx_queue_stop,
1923 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1924 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1925 .mac_addr_remove = mlx5_mac_addr_remove,
1926 .mac_addr_add = mlx5_mac_addr_add,
1927 .mac_addr_set = mlx5_mac_addr_set,
1928 .set_mc_addr_list = mlx5_set_mc_addr_list,
1929 .mtu_set = mlx5_dev_set_mtu,
1930 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1931 .vlan_offload_set = mlx5_vlan_offload_set,
1932 .flow_ops_get = mlx5_flow_ops_get,
1933 .rxq_info_get = mlx5_rxq_info_get,
1934 .txq_info_get = mlx5_txq_info_get,
1935 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1936 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1937 .rx_queue_intr_enable = mlx5_rx_intr_enable,
1938 .rx_queue_intr_disable = mlx5_rx_intr_disable,
1939 .is_removed = mlx5_is_removed,
1940 .get_module_info = mlx5_get_module_info,
1941 .get_module_eeprom = mlx5_get_module_eeprom,
1942 .hairpin_cap_get = mlx5_hairpin_cap_get,
1943 .mtr_ops_get = mlx5_flow_meter_ops_get,
1944 .hairpin_bind = mlx5_hairpin_bind,
1945 .hairpin_unbind = mlx5_hairpin_unbind,
1946 .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1947 .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1948 .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1949 .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1950 .get_monitor_addr = mlx5_get_monitor_addr,
1954 * Verify and store value for device argument.
1957 * Key argument to verify.
1959 * Value associated with key.
1964 * 0 on success, a negative errno value otherwise and rte_errno is set.
1967 mlx5_args_check(const char *key, const char *val, void *opaque)
1969 struct mlx5_dev_config *config = opaque;
1973 /* No-op, port representors are processed in mlx5_dev_spawn(). */
1974 if (!strcmp(MLX5_DRIVER_KEY, key) || !strcmp(MLX5_REPRESENTOR, key) ||
1975 !strcmp(MLX5_SYS_MEM_EN, key) || !strcmp(MLX5_TX_DB_NC, key) ||
1976 !strcmp(MLX5_MR_MEMPOOL_REG_EN, key) ||
1977 !strcmp(MLX5_MR_EXT_MEMSEG_EN, key))
1980 tmp = strtol(val, NULL, 0);
1983 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1986 if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
1987 /* Negative values are acceptable for some keys only. */
1989 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
1992 mod = tmp >= 0 ? tmp : -tmp;
1993 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1994 if (tmp > MLX5_CQE_RESP_FORMAT_L34H_STRIDX) {
1995 DRV_LOG(ERR, "invalid CQE compression "
1996 "format parameter");
2000 config->cqe_comp = !!tmp;
2001 config->cqe_comp_fmt = tmp;
2002 } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
2003 config->hw_padding = !!tmp;
2004 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
2005 config->mprq.enabled = !!tmp;
2006 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
2007 config->mprq.stride_num_n = tmp;
2008 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
2009 config->mprq.stride_size_n = tmp;
2010 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
2011 config->mprq.max_memcpy_len = tmp;
2012 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
2013 config->mprq.min_rxqs_num = tmp;
2014 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
2015 DRV_LOG(WARNING, "%s: deprecated parameter,"
2016 " converted to txq_inline_max", key);
2017 config->txq_inline_max = tmp;
2018 } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
2019 config->txq_inline_max = tmp;
2020 } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
2021 config->txq_inline_min = tmp;
2022 } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
2023 config->txq_inline_mpw = tmp;
2024 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
2025 config->txqs_inline = tmp;
2026 } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
2027 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
2028 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
2029 config->mps = !!tmp;
2030 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
2031 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
2032 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
2033 DRV_LOG(WARNING, "%s: deprecated parameter,"
2034 " converted to txq_inline_mpw", key);
2035 config->txq_inline_mpw = tmp;
2036 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
2037 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
2038 } else if (strcmp(MLX5_TX_PP, key) == 0) {
2040 DRV_LOG(ERR, "Zero Tx packet pacing parameter");
2044 config->tx_pp = tmp;
2045 } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
2046 config->tx_skew = tmp;
2047 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
2048 config->rx_vec_en = !!tmp;
2049 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
2050 config->l3_vxlan_en = !!tmp;
2051 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
2052 config->vf_nl_en = !!tmp;
2053 } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
2054 config->dv_esw_en = !!tmp;
2055 } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
2056 config->dv_flow_en = !!tmp;
2057 } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
2058 if (tmp != MLX5_XMETA_MODE_LEGACY &&
2059 tmp != MLX5_XMETA_MODE_META16 &&
2060 tmp != MLX5_XMETA_MODE_META32 &&
2061 tmp != MLX5_XMETA_MODE_MISS_INFO) {
2062 DRV_LOG(ERR, "invalid extensive "
2063 "metadata parameter");
2067 if (tmp != MLX5_XMETA_MODE_MISS_INFO)
2068 config->dv_xmeta_en = tmp;
2070 config->dv_miss_info = 1;
2071 } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
2072 config->lacp_by_user = !!tmp;
2073 } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
2074 config->max_dump_files_num = tmp;
2075 } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
2076 config->lro.timeout = tmp;
2077 } else if (strcmp(RTE_DEVARGS_KEY_CLASS, key) == 0) {
2078 DRV_LOG(DEBUG, "class argument is %s.", val);
2079 } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
2080 config->log_hp_size = tmp;
2081 } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
2082 if (tmp != MLX5_RCM_NONE &&
2083 tmp != MLX5_RCM_LIGHT &&
2084 tmp != MLX5_RCM_AGGR) {
2085 DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
2089 config->reclaim_mode = tmp;
2090 } else if (strcmp(MLX5_DECAP_EN, key) == 0) {
2091 config->decap_en = !!tmp;
2092 } else if (strcmp(MLX5_ALLOW_DUPLICATE_PATTERN, key) == 0) {
2093 config->allow_duplicate_pattern = !!tmp;
2095 DRV_LOG(WARNING, "%s: unknown parameter", key);
2103 * Parse device parameters.
2106 * Pointer to device configuration structure.
2108 * Device arguments structure.
2111 * 0 on success, a negative errno value otherwise and rte_errno is set.
2114 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
2116 const char **params = (const char *[]){
2118 MLX5_RXQ_CQE_COMP_EN,
2119 MLX5_RXQ_PKT_PAD_EN,
2121 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
2122 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
2123 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
2126 MLX5_TXQ_INLINE_MIN,
2127 MLX5_TXQ_INLINE_MAX,
2128 MLX5_TXQ_INLINE_MPW,
2129 MLX5_TXQS_MIN_INLINE,
2132 MLX5_TXQ_MPW_HDR_DSEG_EN,
2133 MLX5_TXQ_MAX_INLINE_LEN,
2145 MLX5_MR_EXT_MEMSEG_EN,
2147 MLX5_MAX_DUMP_FILES_NUM,
2148 MLX5_LRO_TIMEOUT_USEC,
2149 RTE_DEVARGS_KEY_CLASS,
2154 MLX5_ALLOW_DUPLICATE_PATTERN,
2155 MLX5_MR_MEMPOOL_REG_EN,
2158 struct rte_kvargs *kvlist;
2162 if (devargs == NULL)
2164 /* Following UGLY cast is done to pass checkpatch. */
2165 kvlist = rte_kvargs_parse(devargs->args, params);
2166 if (kvlist == NULL) {
2170 /* Process parameters. */
2171 for (i = 0; (params[i] != NULL); ++i) {
2172 if (rte_kvargs_count(kvlist, params[i])) {
2173 ret = rte_kvargs_process(kvlist, params[i],
2174 mlx5_args_check, config);
2177 rte_kvargs_free(kvlist);
2182 rte_kvargs_free(kvlist);
2187 * Configures the minimal amount of data to inline into WQE
2188 * while sending packets.
2190 * - the txq_inline_min has the maximal priority, if this
2191 * key is specified in devargs
2192 * - if DevX is enabled the inline mode is queried from the
2193 * device (HCA attributes and NIC vport context if needed).
2194 * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
2195 * and none (0 bytes) for other NICs
2198 * Verbs device parameters (name, port, switch_info) to spawn.
2200 * Device configuration parameters.
2203 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
2204 struct mlx5_dev_config *config)
2206 if (config->txq_inline_min != MLX5_ARG_UNSET) {
2207 /* Application defines size of inlined data explicitly. */
2208 if (spawn->pci_dev != NULL) {
2209 switch (spawn->pci_dev->id.device_id) {
2210 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2211 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2212 if (config->txq_inline_min <
2213 (int)MLX5_INLINE_HSIZE_L2) {
2215 "txq_inline_mix aligned to minimal ConnectX-4 required value %d",
2216 (int)MLX5_INLINE_HSIZE_L2);
2217 config->txq_inline_min =
2218 MLX5_INLINE_HSIZE_L2;
2225 if (config->hca_attr.eth_net_offloads) {
2226 /* We have DevX enabled, inline mode queried successfully. */
2227 switch (config->hca_attr.wqe_inline_mode) {
2228 case MLX5_CAP_INLINE_MODE_L2:
2229 /* outer L2 header must be inlined. */
2230 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2232 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
2233 /* No inline data are required by NIC. */
2234 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2235 config->hw_vlan_insert =
2236 config->hca_attr.wqe_vlan_insert;
2237 DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
2239 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
2240 /* inline mode is defined by NIC vport context. */
2241 if (!config->hca_attr.eth_virt)
2243 switch (config->hca_attr.vport_inline_mode) {
2244 case MLX5_INLINE_MODE_NONE:
2245 config->txq_inline_min =
2246 MLX5_INLINE_HSIZE_NONE;
2248 case MLX5_INLINE_MODE_L2:
2249 config->txq_inline_min =
2250 MLX5_INLINE_HSIZE_L2;
2252 case MLX5_INLINE_MODE_IP:
2253 config->txq_inline_min =
2254 MLX5_INLINE_HSIZE_L3;
2256 case MLX5_INLINE_MODE_TCP_UDP:
2257 config->txq_inline_min =
2258 MLX5_INLINE_HSIZE_L4;
2260 case MLX5_INLINE_MODE_INNER_L2:
2261 config->txq_inline_min =
2262 MLX5_INLINE_HSIZE_INNER_L2;
2264 case MLX5_INLINE_MODE_INNER_IP:
2265 config->txq_inline_min =
2266 MLX5_INLINE_HSIZE_INNER_L3;
2268 case MLX5_INLINE_MODE_INNER_TCP_UDP:
2269 config->txq_inline_min =
2270 MLX5_INLINE_HSIZE_INNER_L4;
2275 if (spawn->pci_dev == NULL) {
2276 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2280 * We get here if we are unable to deduce
2281 * inline data size with DevX. Try PCI ID
2282 * to determine old NICs.
2284 switch (spawn->pci_dev->id.device_id) {
2285 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2286 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2287 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
2288 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
2289 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2290 config->hw_vlan_insert = 0;
2292 case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
2293 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
2294 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
2295 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
2297 * These NICs support VLAN insertion from WQE and
2298 * report the wqe_vlan_insert flag. But there is the bug
2299 * and PFC control may be broken, so disable feature.
2301 config->hw_vlan_insert = 0;
2302 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2305 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2309 DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
2313 * Configures the metadata mask fields in the shared context.
2316 * Pointer to Ethernet device.
2319 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
2321 struct mlx5_priv *priv = dev->data->dev_private;
2322 struct mlx5_dev_ctx_shared *sh = priv->sh;
2323 uint32_t meta, mark, reg_c0;
2325 reg_c0 = ~priv->vport_meta_mask;
2326 switch (priv->config.dv_xmeta_en) {
2327 case MLX5_XMETA_MODE_LEGACY:
2329 mark = MLX5_FLOW_MARK_MASK;
2331 case MLX5_XMETA_MODE_META16:
2332 meta = reg_c0 >> rte_bsf32(reg_c0);
2333 mark = MLX5_FLOW_MARK_MASK;
2335 case MLX5_XMETA_MODE_META32:
2337 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
2345 if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
2346 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
2347 sh->dv_mark_mask, mark);
2349 sh->dv_mark_mask = mark;
2350 if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
2351 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
2352 sh->dv_meta_mask, meta);
2354 sh->dv_meta_mask = meta;
2355 if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
2356 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
2357 sh->dv_meta_mask, reg_c0);
2359 sh->dv_regc0_mask = reg_c0;
2360 DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
2361 DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
2362 DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
2363 DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
2367 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
2369 static const char *const dynf_names[] = {
2370 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
2371 RTE_MBUF_DYNFLAG_METADATA_NAME,
2372 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
2376 if (n < RTE_DIM(dynf_names))
2378 for (i = 0; i < RTE_DIM(dynf_names); i++) {
2379 if (names[i] == NULL)
2381 strcpy(names[i], dynf_names[i]);
2383 return RTE_DIM(dynf_names);
2387 * Comparison callback to sort device data.
2389 * This is meant to be used with qsort().
2392 * Pointer to pointer to first data object.
2394 * Pointer to pointer to second data object.
2397 * 0 if both objects are equal, less than 0 if the first argument is less
2398 * than the second, greater than 0 otherwise.
2401 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
2402 struct mlx5_dev_config *config,
2403 struct rte_device *dpdk_dev)
2405 struct mlx5_dev_ctx_shared *sh = priv->sh;
2406 struct mlx5_dev_config *sh_conf = NULL;
2410 /* Nothing to compare for the single/first device. */
2411 if (sh->refcnt == 1)
2413 /* Find the device with shared context. */
2414 MLX5_ETH_FOREACH_DEV(port_id, dpdk_dev) {
2415 struct mlx5_priv *opriv =
2416 rte_eth_devices[port_id].data->dev_private;
2418 if (opriv && opriv != priv && opriv->sh == sh) {
2419 sh_conf = &opriv->config;
2425 if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
2426 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
2427 " for shared %s context", sh->ibdev_name);
2431 if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
2432 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
2433 " for shared %s context", sh->ibdev_name);
2441 * Look for the ethernet device belonging to mlx5 driver.
2443 * @param[in] port_id
2444 * port_id to start looking for device.
2446 * Pointer to the hint device. When device is being probed
2447 * the its siblings (master and preceding representors might
2448 * not have assigned driver yet (because the mlx5_os_pci_probe()
2449 * is not completed yet, for this case match on hint
2450 * device may be used to detect sibling device.
2453 * port_id of found device, RTE_MAX_ETHPORT if not found.
2456 mlx5_eth_find_next(uint16_t port_id, struct rte_device *odev)
2458 while (port_id < RTE_MAX_ETHPORTS) {
2459 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
2461 if (dev->state != RTE_ETH_DEV_UNUSED &&
2463 (dev->device == odev ||
2464 (dev->device->driver &&
2465 dev->device->driver->name &&
2466 ((strcmp(dev->device->driver->name,
2467 MLX5_PCI_DRIVER_NAME) == 0) ||
2468 (strcmp(dev->device->driver->name,
2469 MLX5_AUXILIARY_DRIVER_NAME) == 0)))))
2473 if (port_id >= RTE_MAX_ETHPORTS)
2474 return RTE_MAX_ETHPORTS;
2479 * Callback to remove a device.
2481 * This function removes all Ethernet devices belong to a given device.
2484 * Pointer to the generic device.
2487 * 0 on success, the function cannot fail.
2490 mlx5_net_remove(struct mlx5_common_device *cdev)
2495 RTE_ETH_FOREACH_DEV_OF(port_id, cdev->dev) {
2497 * mlx5_dev_close() is not registered to secondary process,
2498 * call the close function explicitly for secondary process.
2500 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
2501 ret |= mlx5_dev_close(&rte_eth_devices[port_id]);
2503 ret |= rte_eth_dev_close(port_id);
2505 return ret == 0 ? 0 : -EIO;
2508 static const struct rte_pci_id mlx5_pci_id_map[] = {
2510 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2511 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
2514 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2515 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
2518 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2519 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
2522 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2523 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
2526 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2527 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
2530 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2531 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
2534 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2535 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
2538 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2539 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
2542 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2543 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
2546 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2547 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
2550 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2551 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
2554 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2555 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
2558 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2559 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
2562 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2563 PCI_DEVICE_ID_MELLANOX_CONNECTXVF)
2566 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2567 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
2570 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2571 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
2574 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2575 PCI_DEVICE_ID_MELLANOX_CONNECTX7)
2578 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2579 PCI_DEVICE_ID_MELLANOX_CONNECTX7BF)
2586 static struct mlx5_class_driver mlx5_net_driver = {
2587 .drv_class = MLX5_CLASS_ETH,
2588 .name = RTE_STR(MLX5_ETH_DRIVER_NAME),
2589 .id_table = mlx5_pci_id_map,
2590 .probe = mlx5_os_net_probe,
2591 .remove = mlx5_net_remove,
2597 /* Initialize driver log type. */
2598 RTE_LOG_REGISTER_DEFAULT(mlx5_logtype, NOTICE)
2601 * Driver initialization routine.
2603 RTE_INIT(rte_mlx5_pmd_init)
2605 pthread_mutex_init(&mlx5_dev_ctx_list_mutex, NULL);
2607 /* Build the static tables for Verbs conversion. */
2608 mlx5_set_ptype_table();
2609 mlx5_set_cksum_table();
2610 mlx5_set_swp_types_table();
2612 mlx5_class_driver_register(&mlx5_net_driver);
2615 RTE_PMD_EXPORT_NAME(MLX5_ETH_DRIVER_NAME, __COUNTER__);
2616 RTE_PMD_REGISTER_PCI_TABLE(MLX5_ETH_DRIVER_NAME, mlx5_pci_id_map);
2617 RTE_PMD_REGISTER_KMOD_DEP(MLX5_ETH_DRIVER_NAME, "* ib_uverbs & mlx5_core & mlx5_ib");