4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
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8 * modification, are permitted provided that the following conditions
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44 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
46 #pragma GCC diagnostic ignored "-Wpedantic"
48 #include <infiniband/verbs.h>
50 #pragma GCC diagnostic error "-Wpedantic"
53 #include <rte_malloc.h>
54 #include <rte_ethdev.h>
55 #include <rte_ethdev_pci.h>
57 #include <rte_common.h>
58 #include <rte_kvargs.h>
61 #include "mlx5_utils.h"
62 #include "mlx5_rxtx.h"
63 #include "mlx5_autoconf.h"
64 #include "mlx5_defs.h"
66 /* Device parameter to enable RX completion queue compression. */
67 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
69 /* Device parameter to configure inline send. */
70 #define MLX5_TXQ_INLINE "txq_inline"
73 * Device parameter to configure the number of TX queues threshold for
74 * enabling inline send.
76 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
78 /* Device parameter to enable multi-packet send WQEs. */
79 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
81 /* Device parameter to include 2 dsegs in the title WQEBB. */
82 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
84 /* Device parameter to limit the size of inlining packet. */
85 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
87 /* Device parameter to enable hardware TSO offload. */
88 #define MLX5_TSO "tso"
90 /* Device parameter to enable hardware Tx vector. */
91 #define MLX5_TX_VEC_EN "tx_vec_en"
93 /* Device parameter to enable hardware Rx vector. */
94 #define MLX5_RX_VEC_EN "rx_vec_en"
96 /* Default PMD specific parameter value. */
97 #define MLX5_ARG_UNSET (-1)
99 #ifndef HAVE_IBV_MLX5_MOD_MPW
100 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2)
101 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3)
110 int inline_max_packet_sz;
116 * Retrieve integer value from environment variable.
119 * Environment variable name.
122 * Integer value, 0 if the variable is not set.
125 mlx5_getenv_int(const char *name)
127 const char *val = getenv(name);
135 * DPDK callback to close the device.
137 * Destroy all queues and objects, free memory.
140 * Pointer to Ethernet device structure.
143 mlx5_dev_close(struct rte_eth_dev *dev)
145 struct priv *priv = mlx5_get_priv(dev);
149 DEBUG("%p: closing device \"%s\"",
151 ((priv->ctx != NULL) ? priv->ctx->device->name : ""));
152 /* In case mlx5_dev_stop() has not been called. */
153 priv_dev_interrupt_handler_uninstall(priv, dev);
154 priv_special_flow_disable_all(priv);
155 priv_mac_addrs_disable(priv);
156 priv_destroy_hash_rxqs(priv);
158 /* Remove flow director elements. */
159 priv_fdir_disable(priv);
160 priv_fdir_delete_filters_list(priv);
162 /* Prevent crashes when queues are still in use. */
163 dev->rx_pkt_burst = removed_rx_burst;
164 dev->tx_pkt_burst = removed_tx_burst;
165 if (priv->rxqs != NULL) {
166 /* XXX race condition if mlx5_rx_burst() is still running. */
168 for (i = 0; (i != priv->rxqs_n); ++i) {
169 struct rxq *rxq = (*priv->rxqs)[i];
170 struct rxq_ctrl *rxq_ctrl;
174 rxq_ctrl = container_of(rxq, struct rxq_ctrl, rxq);
175 (*priv->rxqs)[i] = NULL;
176 rxq_cleanup(rxq_ctrl);
182 if (priv->txqs != NULL) {
183 /* XXX race condition if mlx5_tx_burst() is still running. */
185 for (i = 0; (i != priv->txqs_n); ++i) {
186 struct txq *txq = (*priv->txqs)[i];
187 struct txq_ctrl *txq_ctrl;
191 txq_ctrl = container_of(txq, struct txq_ctrl, txq);
192 (*priv->txqs)[i] = NULL;
193 txq_cleanup(txq_ctrl);
199 if (priv->pd != NULL) {
200 assert(priv->ctx != NULL);
201 claim_zero(ibv_dealloc_pd(priv->pd));
202 claim_zero(ibv_close_device(priv->ctx));
204 assert(priv->ctx == NULL);
205 if (priv->rss_conf != NULL) {
206 for (i = 0; (i != hash_rxq_init_n); ++i)
207 rte_free((*priv->rss_conf)[i]);
208 rte_free(priv->rss_conf);
210 if (priv->reta_idx != NULL)
211 rte_free(priv->reta_idx);
213 memset(priv, 0, sizeof(*priv));
216 static const struct eth_dev_ops mlx5_dev_ops = {
217 .dev_configure = mlx5_dev_configure,
218 .dev_start = mlx5_dev_start,
219 .dev_stop = mlx5_dev_stop,
220 .dev_set_link_down = mlx5_set_link_down,
221 .dev_set_link_up = mlx5_set_link_up,
222 .dev_close = mlx5_dev_close,
223 .promiscuous_enable = mlx5_promiscuous_enable,
224 .promiscuous_disable = mlx5_promiscuous_disable,
225 .allmulticast_enable = mlx5_allmulticast_enable,
226 .allmulticast_disable = mlx5_allmulticast_disable,
227 .link_update = mlx5_link_update,
228 .stats_get = mlx5_stats_get,
229 .stats_reset = mlx5_stats_reset,
230 .xstats_get = mlx5_xstats_get,
231 .xstats_reset = mlx5_xstats_reset,
232 .xstats_get_names = mlx5_xstats_get_names,
233 .dev_infos_get = mlx5_dev_infos_get,
234 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
235 .vlan_filter_set = mlx5_vlan_filter_set,
236 .rx_queue_setup = mlx5_rx_queue_setup,
237 .tx_queue_setup = mlx5_tx_queue_setup,
238 .rx_queue_release = mlx5_rx_queue_release,
239 .tx_queue_release = mlx5_tx_queue_release,
240 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
241 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
242 .mac_addr_remove = mlx5_mac_addr_remove,
243 .mac_addr_add = mlx5_mac_addr_add,
244 .mac_addr_set = mlx5_mac_addr_set,
245 .mtu_set = mlx5_dev_set_mtu,
246 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
247 .vlan_offload_set = mlx5_vlan_offload_set,
248 .reta_update = mlx5_dev_rss_reta_update,
249 .reta_query = mlx5_dev_rss_reta_query,
250 .rss_hash_update = mlx5_rss_hash_update,
251 .rss_hash_conf_get = mlx5_rss_hash_conf_get,
252 .filter_ctrl = mlx5_dev_filter_ctrl,
253 .rx_descriptor_status = mlx5_rx_descriptor_status,
254 .tx_descriptor_status = mlx5_tx_descriptor_status,
255 .rx_queue_intr_enable = mlx5_rx_intr_enable,
256 .rx_queue_intr_disable = mlx5_rx_intr_disable,
260 struct rte_pci_addr pci_addr; /* associated PCI address */
261 uint32_t ports; /* physical ports bitfield. */
265 * Get device index in mlx5_dev[] from PCI bus address.
267 * @param[in] pci_addr
268 * PCI bus address to look for.
271 * mlx5_dev[] index on success, -1 on failure.
274 mlx5_dev_idx(struct rte_pci_addr *pci_addr)
279 assert(pci_addr != NULL);
280 for (i = 0; (i != RTE_DIM(mlx5_dev)); ++i) {
281 if ((mlx5_dev[i].pci_addr.domain == pci_addr->domain) &&
282 (mlx5_dev[i].pci_addr.bus == pci_addr->bus) &&
283 (mlx5_dev[i].pci_addr.devid == pci_addr->devid) &&
284 (mlx5_dev[i].pci_addr.function == pci_addr->function))
286 if ((mlx5_dev[i].ports == 0) && (ret == -1))
293 * Verify and store value for device argument.
296 * Key argument to verify.
298 * Value associated with key.
303 * 0 on success, negative errno value on failure.
306 mlx5_args_check(const char *key, const char *val, void *opaque)
308 struct mlx5_args *args = opaque;
312 tmp = strtoul(val, NULL, 0);
314 WARN("%s: \"%s\" is not a valid integer", key, val);
317 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
318 args->cqe_comp = !!tmp;
319 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
320 args->txq_inline = tmp;
321 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
322 args->txqs_inline = tmp;
323 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
325 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
326 args->mpw_hdr_dseg = !!tmp;
327 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
328 args->inline_max_packet_sz = tmp;
329 } else if (strcmp(MLX5_TSO, key) == 0) {
331 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
332 args->tx_vec_en = !!tmp;
333 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
334 args->rx_vec_en = !!tmp;
336 WARN("%s: unknown parameter", key);
343 * Parse device parameters.
346 * Pointer to private structure.
348 * Device arguments structure.
351 * 0 on success, errno value on failure.
354 mlx5_args(struct mlx5_args *args, struct rte_devargs *devargs)
356 const char **params = (const char *[]){
357 MLX5_RXQ_CQE_COMP_EN,
359 MLX5_TXQS_MIN_INLINE,
361 MLX5_TXQ_MPW_HDR_DSEG_EN,
362 MLX5_TXQ_MAX_INLINE_LEN,
368 struct rte_kvargs *kvlist;
374 /* Following UGLY cast is done to pass checkpatch. */
375 kvlist = rte_kvargs_parse(devargs->args, params);
378 /* Process parameters. */
379 for (i = 0; (params[i] != NULL); ++i) {
380 if (rte_kvargs_count(kvlist, params[i])) {
381 ret = rte_kvargs_process(kvlist, params[i],
382 mlx5_args_check, args);
384 rte_kvargs_free(kvlist);
389 rte_kvargs_free(kvlist);
393 static struct rte_pci_driver mlx5_driver;
396 * Assign parameters from args into priv, only non default
397 * values are considered.
400 * Pointer to private structure.
402 * Pointer to args values.
405 mlx5_args_assign(struct priv *priv, struct mlx5_args *args)
407 if (args->cqe_comp != MLX5_ARG_UNSET)
408 priv->cqe_comp = args->cqe_comp;
409 if (args->txq_inline != MLX5_ARG_UNSET)
410 priv->txq_inline = args->txq_inline;
411 if (args->txqs_inline != MLX5_ARG_UNSET)
412 priv->txqs_inline = args->txqs_inline;
413 if (args->mps != MLX5_ARG_UNSET)
414 priv->mps = args->mps ? priv->mps : 0;
415 if (args->mpw_hdr_dseg != MLX5_ARG_UNSET)
416 priv->mpw_hdr_dseg = args->mpw_hdr_dseg;
417 if (args->inline_max_packet_sz != MLX5_ARG_UNSET)
418 priv->inline_max_packet_sz = args->inline_max_packet_sz;
419 if (args->tso != MLX5_ARG_UNSET)
420 priv->tso = args->tso;
421 if (args->tx_vec_en != MLX5_ARG_UNSET)
422 priv->tx_vec_en = args->tx_vec_en;
423 if (args->rx_vec_en != MLX5_ARG_UNSET)
424 priv->rx_vec_en = args->rx_vec_en;
428 * DPDK callback to register a PCI device.
430 * This function creates an Ethernet device for each port of a given
434 * PCI driver structure (mlx5_driver).
436 * PCI device information.
439 * 0 on success, negative errno value on failure.
442 mlx5_pci_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
444 struct ibv_device **list;
445 struct ibv_device *ibv_dev;
447 struct ibv_context *attr_ctx = NULL;
448 struct ibv_device_attr_ex device_attr;
451 unsigned int tunnel_en = 0;
454 struct mlx5dv_context attrs_out;
457 assert(pci_drv == &mlx5_driver);
458 /* Get mlx5_dev[] index. */
459 idx = mlx5_dev_idx(&pci_dev->addr);
461 ERROR("this driver cannot support any more adapters");
464 DEBUG("using driver device index %d", idx);
466 /* Save PCI address. */
467 mlx5_dev[idx].pci_addr = pci_dev->addr;
468 list = ibv_get_device_list(&i);
472 ERROR("cannot list devices, is ib_uverbs loaded?");
477 * For each listed device, check related sysfs entry against
478 * the provided PCI ID.
481 struct rte_pci_addr pci_addr;
484 DEBUG("checking device \"%s\"", list[i]->name);
485 if (mlx5_ibv_device_to_pci_addr(list[i], &pci_addr))
487 if ((pci_dev->addr.domain != pci_addr.domain) ||
488 (pci_dev->addr.bus != pci_addr.bus) ||
489 (pci_dev->addr.devid != pci_addr.devid) ||
490 (pci_dev->addr.function != pci_addr.function))
492 sriov = ((pci_dev->id.device_id ==
493 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF) ||
494 (pci_dev->id.device_id ==
495 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF) ||
496 (pci_dev->id.device_id ==
497 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF) ||
498 (pci_dev->id.device_id ==
499 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF));
500 switch (pci_dev->id.device_id) {
501 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
504 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
505 case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
506 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
507 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
508 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
514 INFO("PCI information matches, using device \"%s\""
517 sriov ? "true" : "false");
518 attr_ctx = ibv_open_device(list[i]);
522 if (attr_ctx == NULL) {
523 ibv_free_device_list(list);
526 ERROR("cannot access device, is mlx5_ib loaded?");
529 ERROR("cannot use device, are drivers up to date?");
537 DEBUG("device opened");
539 * Multi-packet send is supported by ConnectX-4 Lx PF as well
540 * as all ConnectX-5 devices.
542 mlx5dv_query_device(attr_ctx, &attrs_out);
543 if (attrs_out.flags & (MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW |
544 MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED)) {
545 INFO("Enhanced MPW is detected\n");
546 mps = MLX5_MPW_ENHANCED;
547 } else if (attrs_out.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
548 INFO("MPW is detected\n");
551 INFO("MPW is disabled\n");
552 mps = MLX5_MPW_DISABLED;
554 if (ibv_query_device_ex(attr_ctx, NULL, &device_attr))
556 INFO("%u port(s) detected", device_attr.orig_attr.phys_port_cnt);
558 for (i = 0; i < device_attr.orig_attr.phys_port_cnt; i++) {
559 uint32_t port = i + 1; /* ports are indexed from one */
560 uint32_t test = (1 << i);
561 struct ibv_context *ctx = NULL;
562 struct ibv_port_attr port_attr;
563 struct ibv_pd *pd = NULL;
564 struct priv *priv = NULL;
565 struct rte_eth_dev *eth_dev;
566 struct ibv_device_attr_ex device_attr_ex;
567 struct ether_addr mac;
568 uint16_t num_vfs = 0;
569 struct mlx5_args args = {
570 .cqe_comp = MLX5_ARG_UNSET,
571 .txq_inline = MLX5_ARG_UNSET,
572 .txqs_inline = MLX5_ARG_UNSET,
573 .mps = MLX5_ARG_UNSET,
574 .mpw_hdr_dseg = MLX5_ARG_UNSET,
575 .inline_max_packet_sz = MLX5_ARG_UNSET,
576 .tso = MLX5_ARG_UNSET,
577 .tx_vec_en = MLX5_ARG_UNSET,
578 .rx_vec_en = MLX5_ARG_UNSET,
581 DEBUG("using port %u (%08" PRIx32 ")", port, test);
583 ctx = ibv_open_device(ibv_dev);
589 /* Check port status. */
590 err = ibv_query_port(ctx, port, &port_attr);
592 ERROR("port query failed: %s", strerror(err));
596 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
597 ERROR("port %d is not configured in Ethernet mode",
603 if (port_attr.state != IBV_PORT_ACTIVE)
604 DEBUG("port %d is not active: \"%s\" (%d)",
605 port, ibv_port_state_str(port_attr.state),
608 /* Allocate protection domain. */
609 pd = ibv_alloc_pd(ctx);
611 ERROR("PD allocation failure");
616 mlx5_dev[idx].ports |= test;
618 /* from rte_ethdev.c */
619 priv = rte_zmalloc("ethdev private structure",
621 RTE_CACHE_LINE_SIZE);
623 ERROR("priv allocation failure");
629 priv->device_attr = device_attr;
632 priv->mtu = ETHER_MTU;
633 priv->mps = mps; /* Enable MPW by default if supported. */
634 priv->cqe_comp = 1; /* Enable compression by default. */
635 priv->tunnel_en = tunnel_en;
636 /* Enable vector by default if supported. */
639 err = mlx5_args(&args, pci_dev->device.devargs);
641 ERROR("failed to process device arguments: %s",
645 mlx5_args_assign(priv, &args);
646 if (ibv_query_device_ex(ctx, NULL, &device_attr_ex)) {
647 ERROR("ibv_query_device_ex() failed");
652 !!(device_attr_ex.device_cap_flags_ex &
653 IBV_DEVICE_RAW_IP_CSUM);
654 DEBUG("checksum offloading is %ssupported",
655 (priv->hw_csum ? "" : "not "));
657 #ifdef HAVE_IBV_DEVICE_VXLAN_SUPPORT
658 priv->hw_csum_l2tun = !!(exp_device_attr.exp_device_cap_flags &
659 IBV_DEVICE_VXLAN_SUPPORT);
661 DEBUG("L2 tunnel checksum offloads are %ssupported",
662 (priv->hw_csum_l2tun ? "" : "not "));
664 priv->ind_table_max_size =
665 device_attr_ex.rss_caps.max_rwq_indirection_table_size;
666 /* Remove this check once DPDK supports larger/variable
667 * indirection tables. */
668 if (priv->ind_table_max_size >
669 (unsigned int)ETH_RSS_RETA_SIZE_512)
670 priv->ind_table_max_size = ETH_RSS_RETA_SIZE_512;
671 DEBUG("maximum RX indirection table size is %u",
672 priv->ind_table_max_size);
673 priv->hw_vlan_strip = !!(device_attr_ex.raw_packet_caps &
674 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
675 DEBUG("VLAN stripping is %ssupported",
676 (priv->hw_vlan_strip ? "" : "not "));
679 !!(device_attr_ex.orig_attr.device_cap_flags &
680 IBV_WQ_FLAGS_SCATTER_FCS);
681 DEBUG("FCS stripping configuration is %ssupported",
682 (priv->hw_fcs_strip ? "" : "not "));
684 #ifdef HAVE_IBV_WQ_FLAG_RX_END_PADDING
685 priv->hw_padding = !!device_attr_ex.rx_pad_end_addr_align;
687 DEBUG("hardware RX end alignment padding is %ssupported",
688 (priv->hw_padding ? "" : "not "));
690 priv_get_num_vfs(priv, &num_vfs);
691 priv->sriov = (num_vfs || sriov);
692 priv->tso = ((priv->tso) &&
693 (device_attr_ex.tso_caps.max_tso > 0) &&
694 (device_attr_ex.tso_caps.supported_qpts &
695 (1 << IBV_QPT_RAW_PACKET)));
697 priv->max_tso_payload_sz =
698 device_attr_ex.tso_caps.max_tso;
699 if (priv->mps && !mps) {
700 ERROR("multi-packet send not supported on this device"
701 " (" MLX5_TXQ_MPW_EN ")");
704 } else if (priv->mps && priv->tso) {
705 WARN("multi-packet send not supported in conjunction "
706 "with TSO. MPS disabled");
710 priv->mps == MLX5_MPW_ENHANCED ? "Enhanced " : "",
711 priv->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled");
712 /* Set default values for Enhanced MPW, a.k.a MPWv2. */
713 if (priv->mps == MLX5_MPW_ENHANCED) {
714 if (args.txqs_inline == MLX5_ARG_UNSET)
715 priv->txqs_inline = MLX5_EMPW_MIN_TXQS;
716 if (args.inline_max_packet_sz == MLX5_ARG_UNSET)
717 priv->inline_max_packet_sz =
718 MLX5_EMPW_MAX_INLINE_LEN;
719 if (args.txq_inline == MLX5_ARG_UNSET)
720 priv->txq_inline = MLX5_WQE_SIZE_MAX -
723 /* Allocate and register default RSS hash keys. */
724 priv->rss_conf = rte_calloc(__func__, hash_rxq_init_n,
725 sizeof((*priv->rss_conf)[0]), 0);
726 if (priv->rss_conf == NULL) {
730 err = rss_hash_rss_conf_new_key(priv,
731 rss_hash_default_key,
732 rss_hash_default_key_len,
736 /* Configure the first MAC address by default. */
737 if (priv_get_mac(priv, &mac.addr_bytes)) {
738 ERROR("cannot get MAC address, is mlx5_en loaded?"
739 " (errno: %s)", strerror(errno));
743 INFO("port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x",
745 mac.addr_bytes[0], mac.addr_bytes[1],
746 mac.addr_bytes[2], mac.addr_bytes[3],
747 mac.addr_bytes[4], mac.addr_bytes[5]);
748 /* Register MAC address. */
749 claim_zero(priv_mac_addr_add(priv, 0,
750 (const uint8_t (*)[ETHER_ADDR_LEN])
752 /* Initialize FD filters list. */
753 err = fdir_init_filters_list(priv);
758 char ifname[IF_NAMESIZE];
760 if (priv_get_ifname(priv, &ifname) == 0)
761 DEBUG("port %u ifname is \"%s\"",
764 DEBUG("port %u ifname is unknown", priv->port);
767 /* Get actual MTU if possible. */
768 priv_get_mtu(priv, &priv->mtu);
769 DEBUG("port %u MTU is %u", priv->port, priv->mtu);
771 /* from rte_ethdev.c */
773 char name[RTE_ETH_NAME_MAX_LEN];
775 snprintf(name, sizeof(name), "%s port %u",
776 ibv_get_device_name(ibv_dev), port);
777 eth_dev = rte_eth_dev_allocate(name);
779 if (eth_dev == NULL) {
780 ERROR("can not allocate rte ethdev");
784 eth_dev->data->dev_private = priv;
785 eth_dev->data->mac_addrs = priv->mac;
786 eth_dev->device = &pci_dev->device;
787 rte_eth_copy_pci_info(eth_dev, pci_dev);
788 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
789 eth_dev->device->driver = &mlx5_driver.driver;
791 eth_dev->dev_ops = &mlx5_dev_ops;
792 TAILQ_INIT(&priv->flows);
794 /* Bring Ethernet device up. */
795 DEBUG("forcing Ethernet interface up");
796 priv_set_flags(priv, ~IFF_UP, IFF_UP);
797 mlx5_link_update(priv->dev, 1);
802 rte_free(priv->rss_conf);
806 claim_zero(ibv_dealloc_pd(pd));
808 claim_zero(ibv_close_device(ctx));
813 * XXX if something went wrong in the loop above, there is a resource
814 * leak (ctx, pd, priv, dpdk ethdev) but we can do nothing about it as
815 * long as the dpdk does not provide a way to deallocate a ethdev and a
816 * way to enumerate the registered ethdevs to free the previous ones.
819 /* no port found, complain */
820 if (!mlx5_dev[idx].ports) {
827 claim_zero(ibv_close_device(attr_ctx));
829 ibv_free_device_list(list);
834 static const struct rte_pci_id mlx5_pci_id_map[] = {
836 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
837 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
840 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
841 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
844 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
845 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
848 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
849 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
852 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
853 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
856 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
857 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
860 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
861 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
864 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
865 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
872 static struct rte_pci_driver mlx5_driver = {
874 .name = MLX5_DRIVER_NAME
876 .id_table = mlx5_pci_id_map,
877 .probe = mlx5_pci_probe,
878 .drv_flags = RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV,
882 * Driver initialization routine.
884 RTE_INIT(rte_mlx5_pmd_init);
886 rte_mlx5_pmd_init(void)
888 /* Build the static table for ptype conversion. */
889 mlx5_set_ptype_table();
891 * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use
892 * huge pages. Calling ibv_fork_init() during init allows
893 * applications to use fork() safely for purposes other than
894 * using this PMD, which is not supported in forked processes.
896 setenv("RDMAV_HUGEPAGES_SAFE", "1", 1);
897 /* Don't map UAR to WC if BlueFlame is not used.*/
898 setenv("MLX5_SHUT_UP_BF", "1", 1);
900 rte_pci_register(&mlx5_driver);
903 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
904 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
905 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");