drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <stdint.h>
  10 #include <stdlib.h>
  11 #include <errno.h>
  12
  13 #include <rte_malloc.h>
  14 #include <ethdev_driver.h>
  15 #include <rte_pci.h>
  16 #include <rte_bus_pci.h>
  17 #include <rte_common.h>
  18 #include <rte_kvargs.h>
  19 #include <rte_rwlock.h>
  20 #include <rte_spinlock.h>
  21 #include <rte_string_fns.h>
  22 #include <rte_eal_paging.h>
  23 #include <rte_alarm.h>
  24 #include <rte_cycles.h>
  25
  26 #include <mlx5_glue.h>
  27 #include <mlx5_devx_cmds.h>
  28 #include <mlx5_common.h>
  29 #include <mlx5_common_os.h>
  30 #include <mlx5_common_mp.h>
  31 #include <mlx5_malloc.h>
  32
  33 #include "mlx5_defs.h"
  34 #include "mlx5.h"
  35 #include "mlx5_utils.h"
  36 #include "mlx5_rxtx.h"
  37 #include "mlx5_rx.h"
  38 #include "mlx5_tx.h"
  39 #include "mlx5_autoconf.h"
  40 #include "mlx5_flow.h"
  41 #include "mlx5_flow_os.h"
  42 #include "rte_pmd_mlx5.h"
  43
  44 #define MLX5_ETH_DRIVER_NAME mlx5_eth
  45
  46 /* Driver type key for new device global syntax. */
  47 #define MLX5_DRIVER_KEY "driver"
  48
  49 /* Device parameter to enable RX completion queue compression. */
  50 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  51
  52 /* Device parameter to enable padding Rx packet to cacheline size. */
  53 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
  54
  55 /* Device parameter to enable Multi-Packet Rx queue. */
  56 #define MLX5_RX_MPRQ_EN "mprq_en"
  57
  58 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
  59 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
  60
  61 /* Device parameter to configure log 2 of the stride size for MPRQ. */
  62 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
  63
  64 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
  65 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
  66
  67 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
  68 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
  69
  70 /* Device parameter to configure inline send. Deprecated, ignored.*/
  71 #define MLX5_TXQ_INLINE "txq_inline"
  72
  73 /* Device parameter to limit packet size to inline with ordinary SEND. */
  74 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
  75
  76 /* Device parameter to configure minimal data size to inline. */
  77 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
  78
  79 /* Device parameter to limit packet size to inline with Enhanced MPW. */
  80 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
  81
  82 /*
  83  * Device parameter to configure the number of TX queues threshold for
  84  * enabling inline send.
  85  */
  86 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  87
  88 /*
  89  * Device parameter to configure the number of TX queues threshold for
  90  * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
  91  */
  92 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
  93
  94 /* Device parameter to enable multi-packet send WQEs. */
  95 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
  96
  97 /*
  98  * Device parameter to force doorbell register mapping
  99  * to non-cahed region eliminating the extra write memory barrier.
 100  */
 101 #define MLX5_TX_DB_NC "tx_db_nc"
 102
 103 /*
 104  * Device parameter to include 2 dsegs in the title WQEBB.
 105  * Deprecated, ignored.
 106  */
 107 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
 108
 109 /*
 110  * Device parameter to limit the size of inlining packet.
 111  * Deprecated, ignored.
 112  */
 113 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
 114
 115 /*
 116  * Device parameter to enable Tx scheduling on timestamps
 117  * and specify the packet pacing granularity in nanoseconds.
 118  */
 119 #define MLX5_TX_PP "tx_pp"
 120
 121 /*
 122  * Device parameter to specify skew in nanoseconds on Tx datapath,
 123  * it represents the time between SQ start WQE processing and
 124  * appearing actual packet data on the wire.
 125  */
 126 #define MLX5_TX_SKEW "tx_skew"
 127
 128 /*
 129  * Device parameter to enable hardware Tx vector.
 130  * Deprecated, ignored (no vectorized Tx routines anymore).
 131  */
 132 #define MLX5_TX_VEC_EN "tx_vec_en"
 133
 134 /* Device parameter to enable hardware Rx vector. */
 135 #define MLX5_RX_VEC_EN "rx_vec_en"
 136
 137 /* Allow L3 VXLAN flow creation. */
 138 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
 139
 140 /* Activate DV E-Switch flow steering. */
 141 #define MLX5_DV_ESW_EN "dv_esw_en"
 142
 143 /* Activate DV flow steering. */
 144 #define MLX5_DV_FLOW_EN "dv_flow_en"
 145
 146 /* Enable extensive flow metadata support. */
 147 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
 148
 149 /* Device parameter to let the user manage the lacp traffic of bonded device */
 150 #define MLX5_LACP_BY_USER "lacp_by_user"
 151
 152 /* Activate Netlink support in VF mode. */
 153 #define MLX5_VF_NL_EN "vf_nl_en"
 154
 155 /* Enable extending memsegs when creating a MR. */
 156 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
 157
 158 /* Select port representors to instantiate. */
 159 #define MLX5_REPRESENTOR "representor"
 160
 161 /* Device parameter to configure the maximum number of dump files per queue. */
 162 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
 163
 164 /* Configure timeout of LRO session (in microseconds). */
 165 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
 166
 167 /*
 168  * Device parameter to configure the total data buffer size for a single
 169  * hairpin queue (logarithm value).
 170  */
 171 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
 172
 173 /* Flow memory reclaim mode. */
 174 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
 175
 176 /* The default memory allocator used in PMD. */
 177 #define MLX5_SYS_MEM_EN "sys_mem_en"
 178 /* Decap will be used or not. */
 179 #define MLX5_DECAP_EN "decap_en"
 180
 181 /* Device parameter to configure allow or prevent duplicate rules pattern. */
 182 #define MLX5_ALLOW_DUPLICATE_PATTERN "allow_duplicate_pattern"
 183
 184 /* Device parameter to configure implicit registration of mempool memory. */
 185 #define MLX5_MR_MEMPOOL_REG_EN "mr_mempool_reg_en"
 186
 187 /* Device parameter to configure the delay drop when creating Rxqs. */
 188 #define MLX5_DELAY_DROP "delay_drop"
 189
 190 /* Shared memory between primary and secondary processes. */
 191 struct mlx5_shared_data *mlx5_shared_data;
 192
 193 /** Driver-specific log messages type. */
 194 int mlx5_logtype;
 195
 196 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
 197                                                 LIST_HEAD_INITIALIZER();
 198 static pthread_mutex_t mlx5_dev_ctx_list_mutex;
 199 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
 200 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
 201         [MLX5_IPOOL_DECAP_ENCAP] = {
 202                 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
 203                 .trunk_size = 64,
 204                 .grow_trunk = 3,
 205                 .grow_shift = 2,
 206                 .need_lock = 1,
 207                 .release_mem_en = 1,
 208                 .malloc = mlx5_malloc,
 209                 .free = mlx5_free,
 210                 .type = "mlx5_encap_decap_ipool",
 211         },
 212         [MLX5_IPOOL_PUSH_VLAN] = {
 213                 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
 214                 .trunk_size = 64,
 215                 .grow_trunk = 3,
 216                 .grow_shift = 2,
 217                 .need_lock = 1,
 218                 .release_mem_en = 1,
 219                 .malloc = mlx5_malloc,
 220                 .free = mlx5_free,
 221                 .type = "mlx5_push_vlan_ipool",
 222         },
 223         [MLX5_IPOOL_TAG] = {
 224                 .size = sizeof(struct mlx5_flow_dv_tag_resource),
 225                 .trunk_size = 64,
 226                 .grow_trunk = 3,
 227                 .grow_shift = 2,
 228                 .need_lock = 1,
 229                 .release_mem_en = 0,
 230                 .per_core_cache = (1 << 16),
 231                 .malloc = mlx5_malloc,
 232                 .free = mlx5_free,
 233                 .type = "mlx5_tag_ipool",
 234         },
 235         [MLX5_IPOOL_PORT_ID] = {
 236                 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
 237                 .trunk_size = 64,
 238                 .grow_trunk = 3,
 239                 .grow_shift = 2,
 240                 .need_lock = 1,
 241                 .release_mem_en = 1,
 242                 .malloc = mlx5_malloc,
 243                 .free = mlx5_free,
 244                 .type = "mlx5_port_id_ipool",
 245         },
 246         [MLX5_IPOOL_JUMP] = {
 247                 .size = sizeof(struct mlx5_flow_tbl_data_entry),
 248                 .trunk_size = 64,
 249                 .grow_trunk = 3,
 250                 .grow_shift = 2,
 251                 .need_lock = 1,
 252                 .release_mem_en = 1,
 253                 .malloc = mlx5_malloc,
 254                 .free = mlx5_free,
 255                 .type = "mlx5_jump_ipool",
 256         },
 257         [MLX5_IPOOL_SAMPLE] = {
 258                 .size = sizeof(struct mlx5_flow_dv_sample_resource),
 259                 .trunk_size = 64,
 260                 .grow_trunk = 3,
 261                 .grow_shift = 2,
 262                 .need_lock = 1,
 263                 .release_mem_en = 1,
 264                 .malloc = mlx5_malloc,
 265                 .free = mlx5_free,
 266                 .type = "mlx5_sample_ipool",
 267         },
 268         [MLX5_IPOOL_DEST_ARRAY] = {
 269                 .size = sizeof(struct mlx5_flow_dv_dest_array_resource),
 270                 .trunk_size = 64,
 271                 .grow_trunk = 3,
 272                 .grow_shift = 2,
 273                 .need_lock = 1,
 274                 .release_mem_en = 1,
 275                 .malloc = mlx5_malloc,
 276                 .free = mlx5_free,
 277                 .type = "mlx5_dest_array_ipool",
 278         },
 279         [MLX5_IPOOL_TUNNEL_ID] = {
 280                 .size = sizeof(struct mlx5_flow_tunnel),
 281                 .trunk_size = MLX5_MAX_TUNNELS,
 282                 .need_lock = 1,
 283                 .release_mem_en = 1,
 284                 .type = "mlx5_tunnel_offload",
 285         },
 286         [MLX5_IPOOL_TNL_TBL_ID] = {
 287                 .size = 0,
 288                 .need_lock = 1,
 289                 .type = "mlx5_flow_tnl_tbl_ipool",
 290         },
 291 #endif
 292         [MLX5_IPOOL_MTR] = {
 293                 /**
 294                  * The ipool index should grow continually from small to big,
 295                  * for meter idx, so not set grow_trunk to avoid meter index
 296                  * not jump continually.
 297                  */
 298                 .size = sizeof(struct mlx5_legacy_flow_meter),
 299                 .trunk_size = 64,
 300                 .need_lock = 1,
 301                 .release_mem_en = 1,
 302                 .malloc = mlx5_malloc,
 303                 .free = mlx5_free,
 304                 .type = "mlx5_meter_ipool",
 305         },
 306         [MLX5_IPOOL_MCP] = {
 307                 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
 308                 .trunk_size = 64,
 309                 .grow_trunk = 3,
 310                 .grow_shift = 2,
 311                 .need_lock = 1,
 312                 .release_mem_en = 1,
 313                 .malloc = mlx5_malloc,
 314                 .free = mlx5_free,
 315                 .type = "mlx5_mcp_ipool",
 316         },
 317         [MLX5_IPOOL_HRXQ] = {
 318                 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
 319                 .trunk_size = 64,
 320                 .grow_trunk = 3,
 321                 .grow_shift = 2,
 322                 .need_lock = 1,
 323                 .release_mem_en = 1,
 324                 .malloc = mlx5_malloc,
 325                 .free = mlx5_free,
 326                 .type = "mlx5_hrxq_ipool",
 327         },
 328         [MLX5_IPOOL_MLX5_FLOW] = {
 329                 /*
 330                  * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
 331                  * It set in run time according to PCI function configuration.
 332                  */
 333                 .size = 0,
 334                 .trunk_size = 64,
 335                 .grow_trunk = 3,
 336                 .grow_shift = 2,
 337                 .need_lock = 1,
 338                 .release_mem_en = 0,
 339                 .per_core_cache = 1 << 19,
 340                 .malloc = mlx5_malloc,
 341                 .free = mlx5_free,
 342                 .type = "mlx5_flow_handle_ipool",
 343         },
 344         [MLX5_IPOOL_RTE_FLOW] = {
 345                 .size = sizeof(struct rte_flow),
 346                 .trunk_size = 4096,
 347                 .need_lock = 1,
 348                 .release_mem_en = 1,
 349                 .malloc = mlx5_malloc,
 350                 .free = mlx5_free,
 351                 .type = "rte_flow_ipool",
 352         },
 353         [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID] = {
 354                 .size = 0,
 355                 .need_lock = 1,
 356                 .type = "mlx5_flow_rss_id_ipool",
 357         },
 358         [MLX5_IPOOL_RSS_SHARED_ACTIONS] = {
 359                 .size = sizeof(struct mlx5_shared_action_rss),
 360                 .trunk_size = 64,
 361                 .grow_trunk = 3,
 362                 .grow_shift = 2,
 363                 .need_lock = 1,
 364                 .release_mem_en = 1,
 365                 .malloc = mlx5_malloc,
 366                 .free = mlx5_free,
 367                 .type = "mlx5_shared_action_rss",
 368         },
 369         [MLX5_IPOOL_MTR_POLICY] = {
 370                 /**
 371                  * The ipool index should grow continually from small to big,
 372                  * for policy idx, so not set grow_trunk to avoid policy index
 373                  * not jump continually.
 374                  */
 375                 .size = sizeof(struct mlx5_flow_meter_sub_policy),
 376                 .trunk_size = 64,
 377                 .need_lock = 1,
 378                 .release_mem_en = 1,
 379                 .malloc = mlx5_malloc,
 380                 .free = mlx5_free,
 381                 .type = "mlx5_meter_policy_ipool",
 382         },
 383 };
 384
 385 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
 386 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
 387
 388 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 1024
 389
 390 /**
 391  * Decide whether representor ID is a HPF(host PF) port on BF2.
 392  *
 393  * @param dev
 394  *   Pointer to Ethernet device structure.
 395  *
 396  * @return
 397  *   Non-zero if HPF, otherwise 0.
 398  */
 399 bool
 400 mlx5_is_hpf(struct rte_eth_dev *dev)
 401 {
 402         struct mlx5_priv *priv = dev->data->dev_private;
 403         uint16_t repr = MLX5_REPRESENTOR_REPR(priv->representor_id);
 404         int type = MLX5_REPRESENTOR_TYPE(priv->representor_id);
 405
 406         return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_VF &&
 407                MLX5_REPRESENTOR_REPR(-1) == repr;
 408 }
 409
 410 /**
 411  * Decide whether representor ID is a SF port representor.
 412  *
 413  * @param dev
 414  *   Pointer to Ethernet device structure.
 415  *
 416  * @return
 417  *   Non-zero if HPF, otherwise 0.
 418  */
 419 bool
 420 mlx5_is_sf_repr(struct rte_eth_dev *dev)
 421 {
 422         struct mlx5_priv *priv = dev->data->dev_private;
 423         int type = MLX5_REPRESENTOR_TYPE(priv->representor_id);
 424
 425         return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_SF;
 426 }
 427
 428 /**
 429  * Initialize the ASO aging management structure.
 430  *
 431  * @param[in] sh
 432  *   Pointer to mlx5_dev_ctx_shared object to free
 433  *
 434  * @return
 435  *   0 on success, a negative errno value otherwise and rte_errno is set.
 436  */
 437 int
 438 mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh)
 439 {
 440         int err;
 441
 442         if (sh->aso_age_mng)
 443                 return 0;
 444         sh->aso_age_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->aso_age_mng),
 445                                       RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 446         if (!sh->aso_age_mng) {
 447                 DRV_LOG(ERR, "aso_age_mng allocation was failed.");
 448                 rte_errno = ENOMEM;
 449                 return -ENOMEM;
 450         }
 451         err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_FLOW_HIT);
 452         if (err) {
 453                 mlx5_free(sh->aso_age_mng);
 454                 return -1;
 455         }
 456         rte_rwlock_init(&sh->aso_age_mng->resize_rwl);
 457         rte_spinlock_init(&sh->aso_age_mng->free_sl);
 458         LIST_INIT(&sh->aso_age_mng->free);
 459         return 0;
 460 }
 461
 462 /**
 463  * Close and release all the resources of the ASO aging management structure.
 464  *
 465  * @param[in] sh
 466  *   Pointer to mlx5_dev_ctx_shared object to free.
 467  */
 468 static void
 469 mlx5_flow_aso_age_mng_close(struct mlx5_dev_ctx_shared *sh)
 470 {
 471         int i, j;
 472
 473         mlx5_aso_flow_hit_queue_poll_stop(sh);
 474         mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_FLOW_HIT);
 475         if (sh->aso_age_mng->pools) {
 476                 struct mlx5_aso_age_pool *pool;
 477
 478                 for (i = 0; i < sh->aso_age_mng->next; ++i) {
 479                         pool = sh->aso_age_mng->pools[i];
 480                         claim_zero(mlx5_devx_cmd_destroy
 481                                                 (pool->flow_hit_aso_obj));
 482                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j)
 483                                 if (pool->actions[j].dr_action)
 484                                         claim_zero
 485                                             (mlx5_flow_os_destroy_flow_action
 486                                               (pool->actions[j].dr_action));
 487                         mlx5_free(pool);
 488                 }
 489                 mlx5_free(sh->aso_age_mng->pools);
 490         }
 491         mlx5_free(sh->aso_age_mng);
 492 }
 493
 494 /**
 495  * Initialize the shared aging list information per port.
 496  *
 497  * @param[in] sh
 498  *   Pointer to mlx5_dev_ctx_shared object.
 499  */
 500 static void
 501 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
 502 {
 503         uint32_t i;
 504         struct mlx5_age_info *age_info;
 505
 506         for (i = 0; i < sh->max_port; i++) {
 507                 age_info = &sh->port[i].age_info;
 508                 age_info->flags = 0;
 509                 TAILQ_INIT(&age_info->aged_counters);
 510                 LIST_INIT(&age_info->aged_aso);
 511                 rte_spinlock_init(&age_info->aged_sl);
 512                 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
 513         }
 514 }
 515
 516 /**
 517  * Initialize the counters management structure.
 518  *
 519  * @param[in] sh
 520  *   Pointer to mlx5_dev_ctx_shared object to free
 521  */
 522 static void
 523 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
 524 {
 525         int i;
 526
 527         memset(&sh->cmng, 0, sizeof(sh->cmng));
 528         TAILQ_INIT(&sh->cmng.flow_counters);
 529         sh->cmng.min_id = MLX5_CNT_BATCH_OFFSET;
 530         sh->cmng.max_id = -1;
 531         sh->cmng.last_pool_idx = POOL_IDX_INVALID;
 532         rte_spinlock_init(&sh->cmng.pool_update_sl);
 533         for (i = 0; i < MLX5_COUNTER_TYPE_MAX; i++) {
 534                 TAILQ_INIT(&sh->cmng.counters[i]);
 535                 rte_spinlock_init(&sh->cmng.csl[i]);
 536         }
 537 }
 538
 539 /**
 540  * Destroy all the resources allocated for a counter memory management.
 541  *
 542  * @param[in] mng
 543  *   Pointer to the memory management structure.
 544  */
 545 static void
 546 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
 547 {
 548         uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
 549
 550         LIST_REMOVE(mng, next);
 551         mlx5_os_wrapped_mkey_destroy(&mng->wm);
 552         mlx5_free(mem);
 553 }
 554
 555 /**
 556  * Close and release all the resources of the counters management.
 557  *
 558  * @param[in] sh
 559  *   Pointer to mlx5_dev_ctx_shared object to free.
 560  */
 561 static void
 562 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
 563 {
 564         struct mlx5_counter_stats_mem_mng *mng;
 565         int i, j;
 566         int retries = 1024;
 567
 568         rte_errno = 0;
 569         while (--retries) {
 570                 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
 571                 if (rte_errno != EINPROGRESS)
 572                         break;
 573                 rte_pause();
 574         }
 575
 576         if (sh->cmng.pools) {
 577                 struct mlx5_flow_counter_pool *pool;
 578                 uint16_t n_valid = sh->cmng.n_valid;
 579                 bool fallback = sh->cmng.counter_fallback;
 580
 581                 for (i = 0; i < n_valid; ++i) {
 582                         pool = sh->cmng.pools[i];
 583                         if (!fallback && pool->min_dcs)
 584                                 claim_zero(mlx5_devx_cmd_destroy
 585                                                                (pool->min_dcs));
 586                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
 587                                 struct mlx5_flow_counter *cnt =
 588                                                 MLX5_POOL_GET_CNT(pool, j);
 589
 590                                 if (cnt->action)
 591                                         claim_zero
 592                                          (mlx5_flow_os_destroy_flow_action
 593                                           (cnt->action));
 594                                 if (fallback && MLX5_POOL_GET_CNT
 595                                     (pool, j)->dcs_when_free)
 596                                         claim_zero(mlx5_devx_cmd_destroy
 597                                                    (cnt->dcs_when_free));
 598                         }
 599                         mlx5_free(pool);
 600                 }
 601                 mlx5_free(sh->cmng.pools);
 602         }
 603         mng = LIST_FIRST(&sh->cmng.mem_mngs);
 604         while (mng) {
 605                 mlx5_flow_destroy_counter_stat_mem_mng(mng);
 606                 mng = LIST_FIRST(&sh->cmng.mem_mngs);
 607         }
 608         memset(&sh->cmng, 0, sizeof(sh->cmng));
 609 }
 610
 611 /**
 612  * Initialize the aso flow meters management structure.
 613  *
 614  * @param[in] sh
 615  *   Pointer to mlx5_dev_ctx_shared object to free
 616  */
 617 int
 618 mlx5_aso_flow_mtrs_mng_init(struct mlx5_dev_ctx_shared *sh)
 619 {
 620         if (!sh->mtrmng) {
 621                 sh->mtrmng = mlx5_malloc(MLX5_MEM_ZERO,
 622                         sizeof(*sh->mtrmng),
 623                         RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 624                 if (!sh->mtrmng) {
 625                         DRV_LOG(ERR,
 626                         "meter management allocation was failed.");
 627                         rte_errno = ENOMEM;
 628                         return -ENOMEM;
 629                 }
 630                 if (sh->meter_aso_en) {
 631                         rte_spinlock_init(&sh->mtrmng->pools_mng.mtrsl);
 632                         rte_rwlock_init(&sh->mtrmng->pools_mng.resize_mtrwl);
 633                         LIST_INIT(&sh->mtrmng->pools_mng.meters);
 634                 }
 635                 sh->mtrmng->def_policy_id = MLX5_INVALID_POLICY_ID;
 636         }
 637         return 0;
 638 }
 639
 640 /**
 641  * Close and release all the resources of
 642  * the ASO flow meter management structure.
 643  *
 644  * @param[in] sh
 645  *   Pointer to mlx5_dev_ctx_shared object to free.
 646  */
 647 static void
 648 mlx5_aso_flow_mtrs_mng_close(struct mlx5_dev_ctx_shared *sh)
 649 {
 650         struct mlx5_aso_mtr_pool *mtr_pool;
 651         struct mlx5_flow_mtr_mng *mtrmng = sh->mtrmng;
 652         uint32_t idx;
 653 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
 654         struct mlx5_aso_mtr *aso_mtr;
 655         int i;
 656 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
 657
 658         if (sh->meter_aso_en) {
 659                 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_POLICER);
 660                 idx = mtrmng->pools_mng.n_valid;
 661                 while (idx--) {
 662                         mtr_pool = mtrmng->pools_mng.pools[idx];
 663 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
 664                         for (i = 0; i < MLX5_ASO_MTRS_PER_POOL; i++) {
 665                                 aso_mtr = &mtr_pool->mtrs[i];
 666                                 if (aso_mtr->fm.meter_action)
 667                                         claim_zero
 668                                         (mlx5_glue->destroy_flow_action
 669                                         (aso_mtr->fm.meter_action));
 670                         }
 671 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
 672                         claim_zero(mlx5_devx_cmd_destroy
 673                                                 (mtr_pool->devx_obj));
 674                         mtrmng->pools_mng.n_valid--;
 675                         mlx5_free(mtr_pool);
 676                 }
 677                 mlx5_free(sh->mtrmng->pools_mng.pools);
 678         }
 679         mlx5_free(sh->mtrmng);
 680         sh->mtrmng = NULL;
 681 }
 682
 683 /* Send FLOW_AGED event if needed. */
 684 void
 685 mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh)
 686 {
 687         struct mlx5_age_info *age_info;
 688         uint32_t i;
 689
 690         for (i = 0; i < sh->max_port; i++) {
 691                 age_info = &sh->port[i].age_info;
 692                 if (!MLX5_AGE_GET(age_info, MLX5_AGE_EVENT_NEW))
 693                         continue;
 694                 MLX5_AGE_UNSET(age_info, MLX5_AGE_EVENT_NEW);
 695                 if (MLX5_AGE_GET(age_info, MLX5_AGE_TRIGGER)) {
 696                         MLX5_AGE_UNSET(age_info, MLX5_AGE_TRIGGER);
 697                         rte_eth_dev_callback_process
 698                                 (&rte_eth_devices[sh->port[i].devx_ih_port_id],
 699                                 RTE_ETH_EVENT_FLOW_AGED, NULL);
 700                 }
 701         }
 702 }
 703
 704 /*
 705  * Initialize the ASO connection tracking structure.
 706  *
 707  * @param[in] sh
 708  *   Pointer to mlx5_dev_ctx_shared object.
 709  *
 710  * @return
 711  *   0 on success, a negative errno value otherwise and rte_errno is set.
 712  */
 713 int
 714 mlx5_flow_aso_ct_mng_init(struct mlx5_dev_ctx_shared *sh)
 715 {
 716         int err;
 717
 718         if (sh->ct_mng)
 719                 return 0;
 720         sh->ct_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->ct_mng),
 721                                  RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 722         if (!sh->ct_mng) {
 723                 DRV_LOG(ERR, "ASO CT management allocation failed.");
 724                 rte_errno = ENOMEM;
 725                 return -rte_errno;
 726         }
 727         err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_CONNECTION_TRACKING);
 728         if (err) {
 729                 mlx5_free(sh->ct_mng);
 730                 /* rte_errno should be extracted from the failure. */
 731                 rte_errno = EINVAL;
 732                 return -rte_errno;
 733         }
 734         rte_spinlock_init(&sh->ct_mng->ct_sl);
 735         rte_rwlock_init(&sh->ct_mng->resize_rwl);
 736         LIST_INIT(&sh->ct_mng->free_cts);
 737         return 0;
 738 }
 739
 740 /*
 741  * Close and release all the resources of the
 742  * ASO connection tracking management structure.
 743  *
 744  * @param[in] sh
 745  *   Pointer to mlx5_dev_ctx_shared object to free.
 746  */
 747 static void
 748 mlx5_flow_aso_ct_mng_close(struct mlx5_dev_ctx_shared *sh)
 749 {
 750         struct mlx5_aso_ct_pools_mng *mng = sh->ct_mng;
 751         struct mlx5_aso_ct_pool *ct_pool;
 752         struct mlx5_aso_ct_action *ct;
 753         uint32_t idx;
 754         uint32_t val;
 755         uint32_t cnt;
 756         int i;
 757
 758         mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_CONNECTION_TRACKING);
 759         idx = mng->next;
 760         while (idx--) {
 761                 cnt = 0;
 762                 ct_pool = mng->pools[idx];
 763                 for (i = 0; i < MLX5_ASO_CT_ACTIONS_PER_POOL; i++) {
 764                         ct = &ct_pool->actions[i];
 765                         val = __atomic_fetch_sub(&ct->refcnt, 1,
 766                                                  __ATOMIC_RELAXED);
 767                         MLX5_ASSERT(val == 1);
 768                         if (val > 1)
 769                                 cnt++;
 770 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
 771                         if (ct->dr_action_orig)
 772                                 claim_zero(mlx5_glue->destroy_flow_action
 773                                                         (ct->dr_action_orig));
 774                         if (ct->dr_action_rply)
 775                                 claim_zero(mlx5_glue->destroy_flow_action
 776                                                         (ct->dr_action_rply));
 777 #endif
 778                 }
 779                 claim_zero(mlx5_devx_cmd_destroy(ct_pool->devx_obj));
 780                 if (cnt) {
 781                         DRV_LOG(DEBUG, "%u ASO CT objects are being used in the pool %u",
 782                                 cnt, i);
 783                 }
 784                 mlx5_free(ct_pool);
 785                 /* in case of failure. */
 786                 mng->next--;
 787         }
 788         mlx5_free(mng->pools);
 789         mlx5_free(mng);
 790         /* Management structure must be cleared to 0s during allocation. */
 791         sh->ct_mng = NULL;
 792 }
 793
 794 /**
 795  * Initialize the flow resources' indexed mempool.
 796  *
 797  * @param[in] sh
 798  *   Pointer to mlx5_dev_ctx_shared object.
 799  * @param[in] config
 800  *   Pointer to user dev config.
 801  */
 802 static void
 803 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
 804                        const struct mlx5_dev_config *config)
 805 {
 806         uint8_t i;
 807         struct mlx5_indexed_pool_config cfg;
 808
 809         for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
 810                 cfg = mlx5_ipool_cfg[i];
 811                 switch (i) {
 812                 default:
 813                         break;
 814                 /*
 815                  * Set MLX5_IPOOL_MLX5_FLOW ipool size
 816                  * according to PCI function flow configuration.
 817                  */
 818                 case MLX5_IPOOL_MLX5_FLOW:
 819                         cfg.size = config->dv_flow_en ?
 820                                 sizeof(struct mlx5_flow_handle) :
 821                                 MLX5_FLOW_HANDLE_VERBS_SIZE;
 822                         break;
 823                 }
 824                 if (config->reclaim_mode) {
 825                         cfg.release_mem_en = 1;
 826                         cfg.per_core_cache = 0;
 827                 } else {
 828                         cfg.release_mem_en = 0;
 829                 }
 830                 sh->ipool[i] = mlx5_ipool_create(&cfg);
 831         }
 832 }
 833
 834
 835 /**
 836  * Release the flow resources' indexed mempool.
 837  *
 838  * @param[in] sh
 839  *   Pointer to mlx5_dev_ctx_shared object.
 840  */
 841 static void
 842 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
 843 {
 844         uint8_t i;
 845
 846         for (i = 0; i < MLX5_IPOOL_MAX; ++i)
 847                 mlx5_ipool_destroy(sh->ipool[i]);
 848         for (i = 0; i < MLX5_MAX_MODIFY_NUM; ++i)
 849                 if (sh->mdh_ipools[i])
 850                         mlx5_ipool_destroy(sh->mdh_ipools[i]);
 851 }
 852
 853 /*
 854  * Check if dynamic flex parser for eCPRI already exists.
 855  *
 856  * @param dev
 857  *   Pointer to Ethernet device structure.
 858  *
 859  * @return
 860  *   true on exists, false on not.
 861  */
 862 bool
 863 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
 864 {
 865         struct mlx5_priv *priv = dev->data->dev_private;
 866         struct mlx5_ecpri_parser_profile *prf = &priv->sh->ecpri_parser;
 867
 868         return !!prf->obj;
 869 }
 870
 871 /*
 872  * Allocation of a flex parser for eCPRI. Once created, this parser related
 873  * resources will be held until the device is closed.
 874  *
 875  * @param dev
 876  *   Pointer to Ethernet device structure.
 877  *
 878  * @return
 879  *   0 on success, a negative errno value otherwise and rte_errno is set.
 880  */
 881 int
 882 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
 883 {
 884         struct mlx5_priv *priv = dev->data->dev_private;
 885         struct mlx5_ecpri_parser_profile *prf = &priv->sh->ecpri_parser;
 886         struct mlx5_devx_graph_node_attr node = {
 887                 .modify_field_select = 0,
 888         };
 889         uint32_t ids[8];
 890         int ret;
 891
 892         if (!priv->sh->cdev->config.hca_attr.parse_graph_flex_node) {
 893                 DRV_LOG(ERR, "Dynamic flex parser is not supported "
 894                         "for device %s.", priv->dev_data->name);
 895                 return -ENOTSUP;
 896         }
 897         node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED;
 898         /* 8 bytes now: 4B common header + 4B message body header. */
 899         node.header_length_base_value = 0x8;
 900         /* After MAC layer: Ether / VLAN. */
 901         node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC;
 902         /* Type of compared condition should be 0xAEFE in the L2 layer. */
 903         node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI;
 904         /* Sample #0: type in common header. */
 905         node.sample[0].flow_match_sample_en = 1;
 906         /* Fixed offset. */
 907         node.sample[0].flow_match_sample_offset_mode = 0x0;
 908         /* Only the 2nd byte will be used. */
 909         node.sample[0].flow_match_sample_field_base_offset = 0x0;
 910         /* Sample #1: message payload. */
 911         node.sample[1].flow_match_sample_en = 1;
 912         /* Fixed offset. */
 913         node.sample[1].flow_match_sample_offset_mode = 0x0;
 914         /*
 915          * Only the first two bytes will be used right now, and its offset will
 916          * start after the common header that with the length of a DW(u32).
 917          */
 918         node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);
 919         prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->cdev->ctx, &node);
 920         if (!prf->obj) {
 921                 DRV_LOG(ERR, "Failed to create flex parser node object.");
 922                 return (rte_errno == 0) ? -ENODEV : -rte_errno;
 923         }
 924         prf->num = 2;
 925         ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num);
 926         if (ret) {
 927                 DRV_LOG(ERR, "Failed to query sample IDs.");
 928                 return (rte_errno == 0) ? -ENODEV : -rte_errno;
 929         }
 930         prf->offset[0] = 0x0;
 931         prf->offset[1] = sizeof(uint32_t);
 932         prf->ids[0] = ids[0];
 933         prf->ids[1] = ids[1];
 934         return 0;
 935 }
 936
 937 /*
 938  * Destroy the flex parser node, including the parser itself, input / output
 939  * arcs and DW samples. Resources could be reused then.
 940  *
 941  * @param dev
 942  *   Pointer to Ethernet device structure.
 943  */
 944 static void
 945 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
 946 {
 947         struct mlx5_priv *priv = dev->data->dev_private;
 948         struct mlx5_ecpri_parser_profile *prf = &priv->sh->ecpri_parser;
 949
 950         if (prf->obj)
 951                 mlx5_devx_cmd_destroy(prf->obj);
 952         prf->obj = NULL;
 953 }
 954
 955 uint32_t
 956 mlx5_get_supported_sw_parsing_offloads(const struct mlx5_hca_attr *attr)
 957 {
 958         uint32_t sw_parsing_offloads = 0;
 959
 960         if (attr->swp) {
 961                 sw_parsing_offloads |= MLX5_SW_PARSING_CAP;
 962                 if (attr->swp_csum)
 963                         sw_parsing_offloads |= MLX5_SW_PARSING_CSUM_CAP;
 964
 965                 if (attr->swp_lso)
 966                         sw_parsing_offloads |= MLX5_SW_PARSING_TSO_CAP;
 967         }
 968         return sw_parsing_offloads;
 969 }
 970
 971 uint32_t
 972 mlx5_get_supported_tunneling_offloads(const struct mlx5_hca_attr *attr)
 973 {
 974         uint32_t tn_offloads = 0;
 975
 976         if (attr->tunnel_stateless_vxlan)
 977                 tn_offloads |= MLX5_TUNNELED_OFFLOADS_VXLAN_CAP;
 978         if (attr->tunnel_stateless_gre)
 979                 tn_offloads |= MLX5_TUNNELED_OFFLOADS_GRE_CAP;
 980         if (attr->tunnel_stateless_geneve_rx)
 981                 tn_offloads |= MLX5_TUNNELED_OFFLOADS_GENEVE_CAP;
 982         return tn_offloads;
 983 }
 984
 985 /* Fill all fields of UAR structure. */
 986 static int
 987 mlx5_rxtx_uars_prepare(struct mlx5_dev_ctx_shared *sh)
 988 {
 989         int ret;
 990
 991         ret = mlx5_devx_uar_prepare(sh->cdev, &sh->tx_uar);
 992         if (ret) {
 993                 DRV_LOG(ERR, "Failed to prepare Tx DevX UAR.");
 994                 return -rte_errno;
 995         }
 996         MLX5_ASSERT(sh->tx_uar.obj);
 997         MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->tx_uar.obj));
 998         ret = mlx5_devx_uar_prepare(sh->cdev, &sh->rx_uar);
 999         if (ret) {
1000                 DRV_LOG(ERR, "Failed to prepare Rx DevX UAR.");
1001                 mlx5_devx_uar_release(&sh->tx_uar);
1002                 return -rte_errno;
1003         }
1004         MLX5_ASSERT(sh->rx_uar.obj);
1005         MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->rx_uar.obj));
1006         return 0;
1007 }
1008
1009 static void
1010 mlx5_rxtx_uars_release(struct mlx5_dev_ctx_shared *sh)
1011 {
1012         mlx5_devx_uar_release(&sh->rx_uar);
1013         mlx5_devx_uar_release(&sh->tx_uar);
1014 }
1015
1016 /**
1017  * rte_mempool_walk() callback to unregister Rx mempools.
1018  * It used when implicit mempool registration is disabled.
1019  *
1020  * @param mp
1021  *   The mempool being walked.
1022  * @param arg
1023  *   Pointer to the device shared context.
1024  */
1025 static void
1026 mlx5_dev_ctx_shared_rx_mempool_unregister_cb(struct rte_mempool *mp, void *arg)
1027 {
1028         struct mlx5_dev_ctx_shared *sh = arg;
1029
1030         mlx5_dev_mempool_unregister(sh->cdev, mp);
1031 }
1032
1033 /**
1034  * Callback used when implicit mempool registration is disabled
1035  * in order to track Rx mempool destruction.
1036  *
1037  * @param event
1038  *   Mempool life cycle event.
1039  * @param mp
1040  *   An Rx mempool registered explicitly when the port is started.
1041  * @param arg
1042  *   Pointer to a device shared context.
1043  */
1044 static void
1045 mlx5_dev_ctx_shared_rx_mempool_event_cb(enum rte_mempool_event event,
1046                                         struct rte_mempool *mp, void *arg)
1047 {
1048         struct mlx5_dev_ctx_shared *sh = arg;
1049
1050         if (event == RTE_MEMPOOL_EVENT_DESTROY)
1051                 mlx5_dev_mempool_unregister(sh->cdev, mp);
1052 }
1053
1054 int
1055 mlx5_dev_ctx_shared_mempool_subscribe(struct rte_eth_dev *dev)
1056 {
1057         struct mlx5_priv *priv = dev->data->dev_private;
1058         struct mlx5_dev_ctx_shared *sh = priv->sh;
1059         int ret;
1060
1061         /* Check if we only need to track Rx mempool destruction. */
1062         if (!sh->cdev->config.mr_mempool_reg_en) {
1063                 ret = rte_mempool_event_callback_register
1064                                 (mlx5_dev_ctx_shared_rx_mempool_event_cb, sh);
1065                 return ret == 0 || rte_errno == EEXIST ? 0 : ret;
1066         }
1067         return mlx5_dev_mempool_subscribe(sh->cdev);
1068 }
1069
1070 /**
1071  * Set up multiple TISs with different affinities according to
1072  * number of bonding ports
1073  *
1074  * @param priv
1075  * Pointer of shared context.
1076  *
1077  * @return
1078  * Zero on success, -1 otherwise.
1079  */
1080 static int
1081 mlx5_setup_tis(struct mlx5_dev_ctx_shared *sh)
1082 {
1083         int i;
1084         struct mlx5_devx_lag_context lag_ctx = { 0 };
1085         struct mlx5_devx_tis_attr tis_attr = { 0 };
1086
1087         tis_attr.transport_domain = sh->td->id;
1088         if (sh->bond.n_port) {
1089                 if (!mlx5_devx_cmd_query_lag(sh->cdev->ctx, &lag_ctx)) {
1090                         sh->lag.tx_remap_affinity[0] =
1091                                 lag_ctx.tx_remap_affinity_1;
1092                         sh->lag.tx_remap_affinity[1] =
1093                                 lag_ctx.tx_remap_affinity_2;
1094                         sh->lag.affinity_mode = lag_ctx.port_select_mode;
1095                 } else {
1096                         DRV_LOG(ERR, "Failed to query lag affinity.");
1097                         return -1;
1098                 }
1099                 if (sh->lag.affinity_mode == MLX5_LAG_MODE_TIS) {
1100                         for (i = 0; i < sh->bond.n_port; i++) {
1101                                 tis_attr.lag_tx_port_affinity =
1102                                         MLX5_IFC_LAG_MAP_TIS_AFFINITY(i,
1103                                                         sh->bond.n_port);
1104                                 sh->tis[i] = mlx5_devx_cmd_create_tis(sh->cdev->ctx,
1105                                                 &tis_attr);
1106                                 if (!sh->tis[i]) {
1107                                         DRV_LOG(ERR, "Failed to TIS %d/%d for bonding device"
1108                                                 " %s.", i, sh->bond.n_port,
1109                                                 sh->ibdev_name);
1110                                         return -1;
1111                                 }
1112                         }
1113                         DRV_LOG(DEBUG, "LAG number of ports : %d, affinity_1 & 2 : pf%d & %d.\n",
1114                                 sh->bond.n_port, lag_ctx.tx_remap_affinity_1,
1115                                 lag_ctx.tx_remap_affinity_2);
1116                         return 0;
1117                 }
1118                 if (sh->lag.affinity_mode == MLX5_LAG_MODE_HASH)
1119                         DRV_LOG(INFO, "Device %s enabled HW hash based LAG.",
1120                                         sh->ibdev_name);
1121         }
1122         tis_attr.lag_tx_port_affinity = 0;
1123         sh->tis[0] = mlx5_devx_cmd_create_tis(sh->cdev->ctx, &tis_attr);
1124         if (!sh->tis[0]) {
1125                 DRV_LOG(ERR, "Failed to TIS 0 for bonding device"
1126                         " %s.", sh->ibdev_name);
1127                 return -1;
1128         }
1129         return 0;
1130 }
1131
1132 /**
1133  * Allocate shared device context. If there is multiport device the
1134  * master and representors will share this context, if there is single
1135  * port dedicated device, the context will be used by only given
1136  * port due to unification.
1137  *
1138  * Routine first searches the context for the specified device name,
1139  * if found the shared context assumed and reference counter is incremented.
1140  * If no context found the new one is created and initialized with specified
1141  * device context and parameters.
1142  *
1143  * @param[in] spawn
1144  *   Pointer to the device attributes (name, port, etc).
1145  * @param[in] config
1146  *   Pointer to device configuration structure.
1147  *
1148  * @return
1149  *   Pointer to mlx5_dev_ctx_shared object on success,
1150  *   otherwise NULL and rte_errno is set.
1151  */
1152 struct mlx5_dev_ctx_shared *
1153 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
1154                           const struct mlx5_dev_config *config)
1155 {
1156         struct mlx5_dev_ctx_shared *sh;
1157         int err = 0;
1158         uint32_t i;
1159
1160         MLX5_ASSERT(spawn);
1161         /* Secondary process should not create the shared context. */
1162         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1163         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1164         /* Search for IB context by device name. */
1165         LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
1166                 if (!strcmp(sh->ibdev_name, spawn->phys_dev_name)) {
1167                         sh->refcnt++;
1168                         goto exit;
1169                 }
1170         }
1171         /* No device found, we have to create new shared context. */
1172         MLX5_ASSERT(spawn->max_port);
1173         sh = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
1174                          sizeof(struct mlx5_dev_ctx_shared) +
1175                          spawn->max_port * sizeof(struct mlx5_dev_shared_port),
1176                          RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
1177         if (!sh) {
1178                 DRV_LOG(ERR, "Shared context allocation failure.");
1179                 rte_errno = ENOMEM;
1180                 goto exit;
1181         }
1182         pthread_mutex_init(&sh->txpp.mutex, NULL);
1183         sh->numa_node = spawn->cdev->dev->numa_node;
1184         sh->cdev = spawn->cdev;
1185         sh->devx = sh->cdev->config.devx;
1186         if (spawn->bond_info)
1187                 sh->bond = *spawn->bond_info;
1188         err = mlx5_os_get_dev_attr(sh->cdev, &sh->device_attr);
1189         if (err) {
1190                 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
1191                 goto error;
1192         }
1193         sh->refcnt = 1;
1194         sh->max_port = spawn->max_port;
1195         sh->reclaim_mode = config->reclaim_mode;
1196         strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->cdev->ctx),
1197                 sizeof(sh->ibdev_name) - 1);
1198         strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->cdev->ctx),
1199                 sizeof(sh->ibdev_path) - 1);
1200         /*
1201          * Setting port_id to max unallowed value means there is no interrupt
1202          * subhandler installed for the given port index i.
1203          */
1204         for (i = 0; i < sh->max_port; i++) {
1205                 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
1206                 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
1207         }
1208         if (sh->devx) {
1209                 sh->td = mlx5_devx_cmd_create_td(sh->cdev->ctx);
1210                 if (!sh->td) {
1211                         DRV_LOG(ERR, "TD allocation failure");
1212                         rte_errno = ENOMEM;
1213                         goto error;
1214                 }
1215                 if (mlx5_setup_tis(sh)) {
1216                         DRV_LOG(ERR, "TIS allocation failure");
1217                         rte_errno = ENOMEM;
1218                         goto error;
1219                 }
1220                 err = mlx5_rxtx_uars_prepare(sh);
1221                 if (err)
1222                         goto error;
1223 #ifndef RTE_ARCH_64
1224         } else {
1225                 /* Initialize UAR access locks for 32bit implementations. */
1226                 rte_spinlock_init(&sh->uar_lock_cq);
1227                 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
1228                         rte_spinlock_init(&sh->uar_lock[i]);
1229 #endif
1230         }
1231         mlx5_os_dev_shared_handler_install(sh);
1232         if (LIST_EMPTY(&mlx5_dev_ctx_list)) {
1233                 err = mlx5_flow_os_init_workspace_once();
1234                 if (err)
1235                         goto error;
1236         }
1237         mlx5_flow_aging_init(sh);
1238         mlx5_flow_counters_mng_init(sh);
1239         mlx5_flow_ipool_create(sh, config);
1240         /* Add context to the global device list. */
1241         LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
1242         rte_spinlock_init(&sh->geneve_tlv_opt_sl);
1243 exit:
1244         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1245         return sh;
1246 error:
1247         err = rte_errno;
1248         pthread_mutex_destroy(&sh->txpp.mutex);
1249         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1250         MLX5_ASSERT(sh);
1251         mlx5_rxtx_uars_release(sh);
1252         i = 0;
1253         do {
1254                 if (sh->tis[i])
1255                         claim_zero(mlx5_devx_cmd_destroy(sh->tis[i]));
1256         } while (++i < (uint32_t)sh->bond.n_port);
1257         if (sh->td)
1258                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1259         mlx5_free(sh);
1260         rte_errno = err;
1261         return NULL;
1262 }
1263
1264 /**
1265  * Free shared IB device context. Decrement counter and if zero free
1266  * all allocated resources and close handles.
1267  *
1268  * @param[in] sh
1269  *   Pointer to mlx5_dev_ctx_shared object to free
1270  */
1271 void
1272 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
1273 {
1274         int ret;
1275         int i = 0;
1276
1277         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1278 #ifdef RTE_LIBRTE_MLX5_DEBUG
1279         /* Check the object presence in the list. */
1280         struct mlx5_dev_ctx_shared *lctx;
1281
1282         LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
1283                 if (lctx == sh)
1284                         break;
1285         MLX5_ASSERT(lctx);
1286         if (lctx != sh) {
1287                 DRV_LOG(ERR, "Freeing non-existing shared IB context");
1288                 goto exit;
1289         }
1290 #endif
1291         MLX5_ASSERT(sh);
1292         MLX5_ASSERT(sh->refcnt);
1293         /* Secondary process should not free the shared context. */
1294         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1295         if (--sh->refcnt)
1296                 goto exit;
1297         /* Stop watching for mempool events and unregister all mempools. */
1298         if (!sh->cdev->config.mr_mempool_reg_en) {
1299                 ret = rte_mempool_event_callback_unregister
1300                                 (mlx5_dev_ctx_shared_rx_mempool_event_cb, sh);
1301                 if (ret == 0)
1302                         rte_mempool_walk
1303                              (mlx5_dev_ctx_shared_rx_mempool_unregister_cb, sh);
1304         }
1305         /* Remove context from the global device list. */
1306         LIST_REMOVE(sh, next);
1307         /* Release resources on the last device removal. */
1308         if (LIST_EMPTY(&mlx5_dev_ctx_list)) {
1309                 mlx5_os_net_cleanup();
1310                 mlx5_flow_os_release_workspace();
1311         }
1312         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1313         if (sh->flex_parsers_dv) {
1314                 mlx5_list_destroy(sh->flex_parsers_dv);
1315                 sh->flex_parsers_dv = NULL;
1316         }
1317         /*
1318          *  Ensure there is no async event handler installed.
1319          *  Only primary process handles async device events.
1320          **/
1321         mlx5_flow_counters_mng_close(sh);
1322         if (sh->ct_mng)
1323                 mlx5_flow_aso_ct_mng_close(sh);
1324         if (sh->aso_age_mng) {
1325                 mlx5_flow_aso_age_mng_close(sh);
1326                 sh->aso_age_mng = NULL;
1327         }
1328         if (sh->mtrmng)
1329                 mlx5_aso_flow_mtrs_mng_close(sh);
1330         mlx5_flow_ipool_destroy(sh);
1331         mlx5_os_dev_shared_handler_uninstall(sh);
1332         mlx5_rxtx_uars_release(sh);
1333         do {
1334                 if (sh->tis[i])
1335                         claim_zero(mlx5_devx_cmd_destroy(sh->tis[i]));
1336         } while (++i < sh->bond.n_port);
1337         if (sh->td)
1338                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1339         MLX5_ASSERT(sh->geneve_tlv_option_resource == NULL);
1340         pthread_mutex_destroy(&sh->txpp.mutex);
1341         mlx5_free(sh);
1342         return;
1343 exit:
1344         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1345 }
1346
1347 /**
1348  * Destroy table hash list.
1349  *
1350  * @param[in] priv
1351  *   Pointer to the private device data structure.
1352  */
1353 void
1354 mlx5_free_table_hash_list(struct mlx5_priv *priv)
1355 {
1356         struct mlx5_dev_ctx_shared *sh = priv->sh;
1357
1358         if (!sh->flow_tbls)
1359                 return;
1360         mlx5_hlist_destroy(sh->flow_tbls);
1361         sh->flow_tbls = NULL;
1362 }
1363
1364 /**
1365  * Initialize flow table hash list and create the root tables entry
1366  * for each domain.
1367  *
1368  * @param[in] priv
1369  *   Pointer to the private device data structure.
1370  *
1371  * @return
1372  *   Zero on success, positive error code otherwise.
1373  */
1374 int
1375 mlx5_alloc_table_hash_list(struct mlx5_priv *priv __rte_unused)
1376 {
1377         int err = 0;
1378         /* Tables are only used in DV and DR modes. */
1379 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
1380         struct mlx5_dev_ctx_shared *sh = priv->sh;
1381         char s[MLX5_NAME_SIZE];
1382
1383         MLX5_ASSERT(sh);
1384         snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1385         sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE,
1386                                           false, true, sh,
1387                                           flow_dv_tbl_create_cb,
1388                                           flow_dv_tbl_match_cb,
1389                                           flow_dv_tbl_remove_cb,
1390                                           flow_dv_tbl_clone_cb,
1391                                           flow_dv_tbl_clone_free_cb);
1392         if (!sh->flow_tbls) {
1393                 DRV_LOG(ERR, "flow tables with hash creation failed.");
1394                 err = ENOMEM;
1395                 return err;
1396         }
1397 #ifndef HAVE_MLX5DV_DR
1398         struct rte_flow_error error;
1399         struct rte_eth_dev *dev = &rte_eth_devices[priv->dev_data->port_id];
1400
1401         /*
1402          * In case we have not DR support, the zero tables should be created
1403          * because DV expect to see them even if they cannot be created by
1404          * RDMA-CORE.
1405          */
1406         if (!flow_dv_tbl_resource_get(dev, 0, 0, 0, 0,
1407                 NULL, 0, 1, 0, &error) ||
1408             !flow_dv_tbl_resource_get(dev, 0, 1, 0, 0,
1409                 NULL, 0, 1, 0, &error) ||
1410             !flow_dv_tbl_resource_get(dev, 0, 0, 1, 0,
1411                 NULL, 0, 1, 0, &error)) {
1412                 err = ENOMEM;
1413                 goto error;
1414         }
1415         return err;
1416 error:
1417         mlx5_free_table_hash_list(priv);
1418 #endif /* HAVE_MLX5DV_DR */
1419 #endif
1420         return err;
1421 }
1422
1423 /**
1424  * Retrieve integer value from environment variable.
1425  *
1426  * @param[in] name
1427  *   Environment variable name.
1428  *
1429  * @return
1430  *   Integer value, 0 if the variable is not set.
1431  */
1432 int
1433 mlx5_getenv_int(const char *name)
1434 {
1435         const char *val = getenv(name);
1436
1437         if (val == NULL)
1438                 return 0;
1439         return atoi(val);
1440 }
1441
1442 /**
1443  * DPDK callback to add udp tunnel port
1444  *
1445  * @param[in] dev
1446  *   A pointer to eth_dev
1447  * @param[in] udp_tunnel
1448  *   A pointer to udp tunnel
1449  *
1450  * @return
1451  *   0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1452  */
1453 int
1454 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1455                          struct rte_eth_udp_tunnel *udp_tunnel)
1456 {
1457         MLX5_ASSERT(udp_tunnel != NULL);
1458         if (udp_tunnel->prot_type == RTE_ETH_TUNNEL_TYPE_VXLAN &&
1459             udp_tunnel->udp_port == 4789)
1460                 return 0;
1461         if (udp_tunnel->prot_type == RTE_ETH_TUNNEL_TYPE_VXLAN_GPE &&
1462             udp_tunnel->udp_port == 4790)
1463                 return 0;
1464         return -ENOTSUP;
1465 }
1466
1467 /**
1468  * Initialize process private data structure.
1469  *
1470  * @param dev
1471  *   Pointer to Ethernet device structure.
1472  *
1473  * @return
1474  *   0 on success, a negative errno value otherwise and rte_errno is set.
1475  */
1476 int
1477 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1478 {
1479         struct mlx5_priv *priv = dev->data->dev_private;
1480         struct mlx5_proc_priv *ppriv;
1481         size_t ppriv_size;
1482
1483         mlx5_proc_priv_uninit(dev);
1484         /*
1485          * UAR register table follows the process private structure. BlueFlame
1486          * registers for Tx queues are stored in the table.
1487          */
1488         ppriv_size = sizeof(struct mlx5_proc_priv) +
1489                      priv->txqs_n * sizeof(struct mlx5_uar_data);
1490         ppriv = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, ppriv_size,
1491                             RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1492         if (!ppriv) {
1493                 rte_errno = ENOMEM;
1494                 return -rte_errno;
1495         }
1496         ppriv->uar_table_sz = priv->txqs_n;
1497         dev->process_private = ppriv;
1498         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
1499                 priv->sh->pppriv = ppriv;
1500         return 0;
1501 }
1502
1503 /**
1504  * Un-initialize process private data structure.
1505  *
1506  * @param dev
1507  *   Pointer to Ethernet device structure.
1508  */
1509 void
1510 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1511 {
1512         if (!dev->process_private)
1513                 return;
1514         mlx5_free(dev->process_private);
1515         dev->process_private = NULL;
1516 }
1517
1518 /**
1519  * DPDK callback to close the device.
1520  *
1521  * Destroy all queues and objects, free memory.
1522  *
1523  * @param dev
1524  *   Pointer to Ethernet device structure.
1525  */
1526 int
1527 mlx5_dev_close(struct rte_eth_dev *dev)
1528 {
1529         struct mlx5_priv *priv = dev->data->dev_private;
1530         unsigned int i;
1531         int ret;
1532
1533         if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1534                 /* Check if process_private released. */
1535                 if (!dev->process_private)
1536                         return 0;
1537                 mlx5_tx_uar_uninit_secondary(dev);
1538                 mlx5_proc_priv_uninit(dev);
1539                 rte_eth_dev_release_port(dev);
1540                 return 0;
1541         }
1542         if (!priv->sh)
1543                 return 0;
1544         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1545                 dev->data->port_id,
1546                 ((priv->sh->cdev->ctx != NULL) ?
1547                 mlx5_os_get_ctx_device_name(priv->sh->cdev->ctx) : ""));
1548         /*
1549          * If default mreg copy action is removed at the stop stage,
1550          * the search will return none and nothing will be done anymore.
1551          */
1552         mlx5_flow_stop_default(dev);
1553         mlx5_traffic_disable(dev);
1554         /*
1555          * If all the flows are already flushed in the device stop stage,
1556          * then this will return directly without any action.
1557          */
1558         mlx5_flow_list_flush(dev, MLX5_FLOW_TYPE_GEN, true);
1559         mlx5_action_handle_flush(dev);
1560         mlx5_flow_meter_flush(dev, NULL);
1561         /* Prevent crashes when queues are still in use. */
1562         dev->rx_pkt_burst = rte_eth_pkt_burst_dummy;
1563         dev->tx_pkt_burst = rte_eth_pkt_burst_dummy;
1564         rte_wmb();
1565         /* Disable datapath on secondary process. */
1566         mlx5_mp_os_req_stop_rxtx(dev);
1567         /* Free the eCPRI flex parser resource. */
1568         mlx5_flex_parser_ecpri_release(dev);
1569         mlx5_flex_item_port_cleanup(dev);
1570         if (priv->rxq_privs != NULL) {
1571                 /* XXX race condition if mlx5_rx_burst() is still running. */
1572                 rte_delay_us_sleep(1000);
1573                 for (i = 0; (i != priv->rxqs_n); ++i)
1574                         mlx5_rxq_release(dev, i);
1575                 priv->rxqs_n = 0;
1576                 mlx5_free(priv->rxq_privs);
1577                 priv->rxq_privs = NULL;
1578         }
1579         if (priv->txqs != NULL) {
1580                 /* XXX race condition if mlx5_tx_burst() is still running. */
1581                 rte_delay_us_sleep(1000);
1582                 for (i = 0; (i != priv->txqs_n); ++i)
1583                         mlx5_txq_release(dev, i);
1584                 priv->txqs_n = 0;
1585                 priv->txqs = NULL;
1586         }
1587         mlx5_proc_priv_uninit(dev);
1588         if (priv->q_counters) {
1589                 mlx5_devx_cmd_destroy(priv->q_counters);
1590                 priv->q_counters = NULL;
1591         }
1592         if (priv->drop_queue.hrxq)
1593                 mlx5_drop_action_destroy(dev);
1594         if (priv->mreg_cp_tbl)
1595                 mlx5_hlist_destroy(priv->mreg_cp_tbl);
1596         mlx5_mprq_free_mp(dev);
1597         mlx5_os_free_shared_dr(priv);
1598         if (priv->rss_conf.rss_key != NULL)
1599                 mlx5_free(priv->rss_conf.rss_key);
1600         if (priv->reta_idx != NULL)
1601                 mlx5_free(priv->reta_idx);
1602         if (priv->config.vf)
1603                 mlx5_os_mac_addr_flush(dev);
1604         if (priv->nl_socket_route >= 0)
1605                 close(priv->nl_socket_route);
1606         if (priv->nl_socket_rdma >= 0)
1607                 close(priv->nl_socket_rdma);
1608         if (priv->vmwa_context)
1609                 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1610         ret = mlx5_hrxq_verify(dev);
1611         if (ret)
1612                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1613                         dev->data->port_id);
1614         ret = mlx5_ind_table_obj_verify(dev);
1615         if (ret)
1616                 DRV_LOG(WARNING, "port %u some indirection table still remain",
1617                         dev->data->port_id);
1618         ret = mlx5_rxq_obj_verify(dev);
1619         if (ret)
1620                 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1621                         dev->data->port_id);
1622         ret = mlx5_rxq_verify(dev);
1623         if (ret)
1624                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1625                         dev->data->port_id);
1626         ret = mlx5_txq_obj_verify(dev);
1627         if (ret)
1628                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1629                         dev->data->port_id);
1630         ret = mlx5_txq_verify(dev);
1631         if (ret)
1632                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1633                         dev->data->port_id);
1634         ret = mlx5_flow_verify(dev);
1635         if (ret)
1636                 DRV_LOG(WARNING, "port %u some flows still remain",
1637                         dev->data->port_id);
1638         if (priv->hrxqs)
1639                 mlx5_list_destroy(priv->hrxqs);
1640         /*
1641          * Free the shared context in last turn, because the cleanup
1642          * routines above may use some shared fields, like
1643          * mlx5_os_mac_addr_flush() uses ibdev_path for retrieving
1644          * ifindex if Netlink fails.
1645          */
1646         mlx5_free_shared_dev_ctx(priv->sh);
1647         if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1648                 unsigned int c = 0;
1649                 uint16_t port_id;
1650
1651                 MLX5_ETH_FOREACH_DEV(port_id, dev->device) {
1652                         struct mlx5_priv *opriv =
1653                                 rte_eth_devices[port_id].data->dev_private;
1654
1655                         if (!opriv ||
1656                             opriv->domain_id != priv->domain_id ||
1657                             &rte_eth_devices[port_id] == dev)
1658                                 continue;
1659                         ++c;
1660                         break;
1661                 }
1662                 if (!c)
1663                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1664         }
1665         memset(priv, 0, sizeof(*priv));
1666         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1667         /*
1668          * Reset mac_addrs to NULL such that it is not freed as part of
1669          * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1670          * it is freed when dev_private is freed.
1671          */
1672         dev->data->mac_addrs = NULL;
1673         return 0;
1674 }
1675
1676 const struct eth_dev_ops mlx5_dev_ops = {
1677         .dev_configure = mlx5_dev_configure,
1678         .dev_start = mlx5_dev_start,
1679         .dev_stop = mlx5_dev_stop,
1680         .dev_set_link_down = mlx5_set_link_down,
1681         .dev_set_link_up = mlx5_set_link_up,
1682         .dev_close = mlx5_dev_close,
1683         .promiscuous_enable = mlx5_promiscuous_enable,
1684         .promiscuous_disable = mlx5_promiscuous_disable,
1685         .allmulticast_enable = mlx5_allmulticast_enable,
1686         .allmulticast_disable = mlx5_allmulticast_disable,
1687         .link_update = mlx5_link_update,
1688         .stats_get = mlx5_stats_get,
1689         .stats_reset = mlx5_stats_reset,
1690         .xstats_get = mlx5_xstats_get,
1691         .xstats_reset = mlx5_xstats_reset,
1692         .xstats_get_names = mlx5_xstats_get_names,
1693         .fw_version_get = mlx5_fw_version_get,
1694         .dev_infos_get = mlx5_dev_infos_get,
1695         .representor_info_get = mlx5_representor_info_get,
1696         .read_clock = mlx5_txpp_read_clock,
1697         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1698         .vlan_filter_set = mlx5_vlan_filter_set,
1699         .rx_queue_setup = mlx5_rx_queue_setup,
1700         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1701         .tx_queue_setup = mlx5_tx_queue_setup,
1702         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1703         .rx_queue_release = mlx5_rx_queue_release,
1704         .tx_queue_release = mlx5_tx_queue_release,
1705         .rx_queue_start = mlx5_rx_queue_start,
1706         .rx_queue_stop = mlx5_rx_queue_stop,
1707         .tx_queue_start = mlx5_tx_queue_start,
1708         .tx_queue_stop = mlx5_tx_queue_stop,
1709         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1710         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1711         .mac_addr_remove = mlx5_mac_addr_remove,
1712         .mac_addr_add = mlx5_mac_addr_add,
1713         .mac_addr_set = mlx5_mac_addr_set,
1714         .set_mc_addr_list = mlx5_set_mc_addr_list,
1715         .mtu_set = mlx5_dev_set_mtu,
1716         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1717         .vlan_offload_set = mlx5_vlan_offload_set,
1718         .reta_update = mlx5_dev_rss_reta_update,
1719         .reta_query = mlx5_dev_rss_reta_query,
1720         .rss_hash_update = mlx5_rss_hash_update,
1721         .rss_hash_conf_get = mlx5_rss_hash_conf_get,
1722         .flow_ops_get = mlx5_flow_ops_get,
1723         .rxq_info_get = mlx5_rxq_info_get,
1724         .txq_info_get = mlx5_txq_info_get,
1725         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1726         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1727         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1728         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1729         .is_removed = mlx5_is_removed,
1730         .udp_tunnel_port_add  = mlx5_udp_tunnel_port_add,
1731         .get_module_info = mlx5_get_module_info,
1732         .get_module_eeprom = mlx5_get_module_eeprom,
1733         .hairpin_cap_get = mlx5_hairpin_cap_get,
1734         .mtr_ops_get = mlx5_flow_meter_ops_get,
1735         .hairpin_bind = mlx5_hairpin_bind,
1736         .hairpin_unbind = mlx5_hairpin_unbind,
1737         .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1738         .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1739         .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1740         .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1741         .get_monitor_addr = mlx5_get_monitor_addr,
1742 };
1743
1744 /* Available operations from secondary process. */
1745 const struct eth_dev_ops mlx5_dev_sec_ops = {
1746         .stats_get = mlx5_stats_get,
1747         .stats_reset = mlx5_stats_reset,
1748         .xstats_get = mlx5_xstats_get,
1749         .xstats_reset = mlx5_xstats_reset,
1750         .xstats_get_names = mlx5_xstats_get_names,
1751         .fw_version_get = mlx5_fw_version_get,
1752         .dev_infos_get = mlx5_dev_infos_get,
1753         .representor_info_get = mlx5_representor_info_get,
1754         .read_clock = mlx5_txpp_read_clock,
1755         .rx_queue_start = mlx5_rx_queue_start,
1756         .rx_queue_stop = mlx5_rx_queue_stop,
1757         .tx_queue_start = mlx5_tx_queue_start,
1758         .tx_queue_stop = mlx5_tx_queue_stop,
1759         .rxq_info_get = mlx5_rxq_info_get,
1760         .txq_info_get = mlx5_txq_info_get,
1761         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1762         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1763         .get_module_info = mlx5_get_module_info,
1764         .get_module_eeprom = mlx5_get_module_eeprom,
1765 };
1766
1767 /* Available operations in flow isolated mode. */
1768 const struct eth_dev_ops mlx5_dev_ops_isolate = {
1769         .dev_configure = mlx5_dev_configure,
1770         .dev_start = mlx5_dev_start,
1771         .dev_stop = mlx5_dev_stop,
1772         .dev_set_link_down = mlx5_set_link_down,
1773         .dev_set_link_up = mlx5_set_link_up,
1774         .dev_close = mlx5_dev_close,
1775         .promiscuous_enable = mlx5_promiscuous_enable,
1776         .promiscuous_disable = mlx5_promiscuous_disable,
1777         .allmulticast_enable = mlx5_allmulticast_enable,
1778         .allmulticast_disable = mlx5_allmulticast_disable,
1779         .link_update = mlx5_link_update,
1780         .stats_get = mlx5_stats_get,
1781         .stats_reset = mlx5_stats_reset,
1782         .xstats_get = mlx5_xstats_get,
1783         .xstats_reset = mlx5_xstats_reset,
1784         .xstats_get_names = mlx5_xstats_get_names,
1785         .fw_version_get = mlx5_fw_version_get,
1786         .dev_infos_get = mlx5_dev_infos_get,
1787         .representor_info_get = mlx5_representor_info_get,
1788         .read_clock = mlx5_txpp_read_clock,
1789         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1790         .vlan_filter_set = mlx5_vlan_filter_set,
1791         .rx_queue_setup = mlx5_rx_queue_setup,
1792         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1793         .tx_queue_setup = mlx5_tx_queue_setup,
1794         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1795         .rx_queue_release = mlx5_rx_queue_release,
1796         .tx_queue_release = mlx5_tx_queue_release,
1797         .rx_queue_start = mlx5_rx_queue_start,
1798         .rx_queue_stop = mlx5_rx_queue_stop,
1799         .tx_queue_start = mlx5_tx_queue_start,
1800         .tx_queue_stop = mlx5_tx_queue_stop,
1801         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1802         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1803         .mac_addr_remove = mlx5_mac_addr_remove,
1804         .mac_addr_add = mlx5_mac_addr_add,
1805         .mac_addr_set = mlx5_mac_addr_set,
1806         .set_mc_addr_list = mlx5_set_mc_addr_list,
1807         .mtu_set = mlx5_dev_set_mtu,
1808         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1809         .vlan_offload_set = mlx5_vlan_offload_set,
1810         .flow_ops_get = mlx5_flow_ops_get,
1811         .rxq_info_get = mlx5_rxq_info_get,
1812         .txq_info_get = mlx5_txq_info_get,
1813         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1814         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1815         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1816         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1817         .is_removed = mlx5_is_removed,
1818         .get_module_info = mlx5_get_module_info,
1819         .get_module_eeprom = mlx5_get_module_eeprom,
1820         .hairpin_cap_get = mlx5_hairpin_cap_get,
1821         .mtr_ops_get = mlx5_flow_meter_ops_get,
1822         .hairpin_bind = mlx5_hairpin_bind,
1823         .hairpin_unbind = mlx5_hairpin_unbind,
1824         .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1825         .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1826         .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1827         .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1828         .get_monitor_addr = mlx5_get_monitor_addr,
1829 };
1830
1831 /**
1832  * Verify and store value for device argument.
1833  *
1834  * @param[in] key
1835  *   Key argument to verify.
1836  * @param[in] val
1837  *   Value associated with key.
1838  * @param opaque
1839  *   User data.
1840  *
1841  * @return
1842  *   0 on success, a negative errno value otherwise and rte_errno is set.
1843  */
1844 static int
1845 mlx5_args_check(const char *key, const char *val, void *opaque)
1846 {
1847         struct mlx5_dev_config *config = opaque;
1848         unsigned long mod;
1849         signed long tmp;
1850
1851         /* No-op, port representors are processed in mlx5_dev_spawn(). */
1852         if (!strcmp(MLX5_DRIVER_KEY, key) || !strcmp(MLX5_REPRESENTOR, key) ||
1853             !strcmp(MLX5_SYS_MEM_EN, key) || !strcmp(MLX5_TX_DB_NC, key) ||
1854             !strcmp(MLX5_MR_MEMPOOL_REG_EN, key) ||
1855             !strcmp(MLX5_MR_EXT_MEMSEG_EN, key))
1856                 return 0;
1857         errno = 0;
1858         tmp = strtol(val, NULL, 0);
1859         if (errno) {
1860                 rte_errno = errno;
1861                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1862                 return -rte_errno;
1863         }
1864         if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
1865                 /* Negative values are acceptable for some keys only. */
1866                 rte_errno = EINVAL;
1867                 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
1868                 return -rte_errno;
1869         }
1870         mod = tmp >= 0 ? tmp : -tmp;
1871         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1872                 if (tmp > MLX5_CQE_RESP_FORMAT_L34H_STRIDX) {
1873                         DRV_LOG(ERR, "invalid CQE compression "
1874                                      "format parameter");
1875                         rte_errno = EINVAL;
1876                         return -rte_errno;
1877                 }
1878                 config->cqe_comp = !!tmp;
1879                 config->cqe_comp_fmt = tmp;
1880         } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1881                 config->hw_padding = !!tmp;
1882         } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1883                 config->mprq.enabled = !!tmp;
1884         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1885                 config->mprq.log_stride_num = tmp;
1886         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1887                 config->mprq.log_stride_size = tmp;
1888         } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1889                 config->mprq.max_memcpy_len = tmp;
1890         } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1891                 config->mprq.min_rxqs_num = tmp;
1892         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1893                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1894                                  " converted to txq_inline_max", key);
1895                 config->txq_inline_max = tmp;
1896         } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1897                 config->txq_inline_max = tmp;
1898         } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1899                 config->txq_inline_min = tmp;
1900         } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1901                 config->txq_inline_mpw = tmp;
1902         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1903                 config->txqs_inline = tmp;
1904         } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1905                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1906         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1907                 config->mps = !!tmp;
1908         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1909                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1910         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1911                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1912                                  " converted to txq_inline_mpw", key);
1913                 config->txq_inline_mpw = tmp;
1914         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1915                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1916         } else if (strcmp(MLX5_TX_PP, key) == 0) {
1917                 if (!mod) {
1918                         DRV_LOG(ERR, "Zero Tx packet pacing parameter");
1919                         rte_errno = EINVAL;
1920                         return -rte_errno;
1921                 }
1922                 config->tx_pp = tmp;
1923         } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
1924                 config->tx_skew = tmp;
1925         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1926                 config->rx_vec_en = !!tmp;
1927         } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1928                 config->l3_vxlan_en = !!tmp;
1929         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1930                 config->vf_nl_en = !!tmp;
1931         } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1932                 config->dv_esw_en = !!tmp;
1933         } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1934                 config->dv_flow_en = !!tmp;
1935         } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1936                 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1937                     tmp != MLX5_XMETA_MODE_META16 &&
1938                     tmp != MLX5_XMETA_MODE_META32 &&
1939                     tmp != MLX5_XMETA_MODE_MISS_INFO) {
1940                         DRV_LOG(ERR, "invalid extensive "
1941                                      "metadata parameter");
1942                         rte_errno = EINVAL;
1943                         return -rte_errno;
1944                 }
1945                 if (tmp != MLX5_XMETA_MODE_MISS_INFO)
1946                         config->dv_xmeta_en = tmp;
1947                 else
1948                         config->dv_miss_info = 1;
1949         } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
1950                 config->lacp_by_user = !!tmp;
1951         } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1952                 config->max_dump_files_num = tmp;
1953         } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1954                 config->lro.timeout = tmp;
1955         } else if (strcmp(RTE_DEVARGS_KEY_CLASS, key) == 0) {
1956                 DRV_LOG(DEBUG, "class argument is %s.", val);
1957         } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1958                 config->log_hp_size = tmp;
1959         } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1960                 if (tmp != MLX5_RCM_NONE &&
1961                     tmp != MLX5_RCM_LIGHT &&
1962                     tmp != MLX5_RCM_AGGR) {
1963                         DRV_LOG(ERR, "Unrecognized %s: \"%s\"", key, val);
1964                         rte_errno = EINVAL;
1965                         return -rte_errno;
1966                 }
1967                 config->reclaim_mode = tmp;
1968         } else if (strcmp(MLX5_DECAP_EN, key) == 0) {
1969                 config->decap_en = !!tmp;
1970         } else if (strcmp(MLX5_ALLOW_DUPLICATE_PATTERN, key) == 0) {
1971                 config->allow_duplicate_pattern = !!tmp;
1972         } else if (strcmp(MLX5_DELAY_DROP, key) == 0) {
1973                 config->std_delay_drop = !!(tmp & MLX5_DELAY_DROP_STANDARD);
1974                 config->hp_delay_drop = !!(tmp & MLX5_DELAY_DROP_HAIRPIN);
1975         } else {
1976                 DRV_LOG(WARNING,
1977                         "%s: unknown parameter, maybe it's for another class.",
1978                         key);
1979         }
1980         return 0;
1981 }
1982
1983 /**
1984  * Parse device parameters.
1985  *
1986  * @param config
1987  *   Pointer to device configuration structure.
1988  * @param devargs
1989  *   Device arguments structure.
1990  *
1991  * @return
1992  *   0 on success, a negative errno value otherwise and rte_errno is set.
1993  */
1994 int
1995 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1996 {
1997         struct rte_kvargs *kvlist;
1998         int ret = 0;
1999
2000         if (devargs == NULL)
2001                 return 0;
2002         /* Following UGLY cast is done to pass checkpatch. */
2003         kvlist = rte_kvargs_parse(devargs->args, NULL);
2004         if (kvlist == NULL) {
2005                 rte_errno = EINVAL;
2006                 return -rte_errno;
2007         }
2008         /* Process parameters. */
2009         ret = rte_kvargs_process(kvlist, NULL, mlx5_args_check, config);
2010         if (ret) {
2011                 rte_errno = EINVAL;
2012                 ret = -rte_errno;
2013         }
2014         rte_kvargs_free(kvlist);
2015         return ret;
2016 }
2017
2018 /**
2019  * Configures the minimal amount of data to inline into WQE
2020  * while sending packets.
2021  *
2022  * - the txq_inline_min has the maximal priority, if this
2023  *   key is specified in devargs
2024  * - if DevX is enabled the inline mode is queried from the
2025  *   device (HCA attributes and NIC vport context if needed).
2026  * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
2027  *   and none (0 bytes) for other NICs
2028  *
2029  * @param spawn
2030  *   Verbs device parameters (name, port, switch_info) to spawn.
2031  * @param config
2032  *   Device configuration parameters.
2033  */
2034 void
2035 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
2036                     struct mlx5_dev_config *config)
2037 {
2038         struct mlx5_hca_attr *hca_attr = &spawn->cdev->config.hca_attr;
2039
2040         if (config->txq_inline_min != MLX5_ARG_UNSET) {
2041                 /* Application defines size of inlined data explicitly. */
2042                 if (spawn->pci_dev != NULL) {
2043                         switch (spawn->pci_dev->id.device_id) {
2044                         case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2045                         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2046                                 if (config->txq_inline_min <
2047                                                (int)MLX5_INLINE_HSIZE_L2) {
2048                                         DRV_LOG(DEBUG,
2049                                                 "txq_inline_mix aligned to minimal ConnectX-4 required value %d",
2050                                                 (int)MLX5_INLINE_HSIZE_L2);
2051                                         config->txq_inline_min =
2052                                                         MLX5_INLINE_HSIZE_L2;
2053                                 }
2054                                 break;
2055                         }
2056                 }
2057                 goto exit;
2058         }
2059         if (hca_attr->eth_net_offloads) {
2060                 /* We have DevX enabled, inline mode queried successfully. */
2061                 switch (hca_attr->wqe_inline_mode) {
2062                 case MLX5_CAP_INLINE_MODE_L2:
2063                         /* outer L2 header must be inlined. */
2064                         config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2065                         goto exit;
2066                 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
2067                         /* No inline data are required by NIC. */
2068                         config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2069                         config->hw_vlan_insert =
2070                                 hca_attr->wqe_vlan_insert;
2071                         DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
2072                         goto exit;
2073                 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
2074                         /* inline mode is defined by NIC vport context. */
2075                         if (!hca_attr->eth_virt)
2076                                 break;
2077                         switch (hca_attr->vport_inline_mode) {
2078                         case MLX5_INLINE_MODE_NONE:
2079                                 config->txq_inline_min =
2080                                         MLX5_INLINE_HSIZE_NONE;
2081                                 goto exit;
2082                         case MLX5_INLINE_MODE_L2:
2083                                 config->txq_inline_min =
2084                                         MLX5_INLINE_HSIZE_L2;
2085                                 goto exit;
2086                         case MLX5_INLINE_MODE_IP:
2087                                 config->txq_inline_min =
2088                                         MLX5_INLINE_HSIZE_L3;
2089                                 goto exit;
2090                         case MLX5_INLINE_MODE_TCP_UDP:
2091                                 config->txq_inline_min =
2092                                         MLX5_INLINE_HSIZE_L4;
2093                                 goto exit;
2094                         case MLX5_INLINE_MODE_INNER_L2:
2095                                 config->txq_inline_min =
2096                                         MLX5_INLINE_HSIZE_INNER_L2;
2097                                 goto exit;
2098                         case MLX5_INLINE_MODE_INNER_IP:
2099                                 config->txq_inline_min =
2100                                         MLX5_INLINE_HSIZE_INNER_L3;
2101                                 goto exit;
2102                         case MLX5_INLINE_MODE_INNER_TCP_UDP:
2103                                 config->txq_inline_min =
2104                                         MLX5_INLINE_HSIZE_INNER_L4;
2105                                 goto exit;
2106                         }
2107                 }
2108         }
2109         if (spawn->pci_dev == NULL) {
2110                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2111                 goto exit;
2112         }
2113         /*
2114          * We get here if we are unable to deduce
2115          * inline data size with DevX. Try PCI ID
2116          * to determine old NICs.
2117          */
2118         switch (spawn->pci_dev->id.device_id) {
2119         case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2120         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2121         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
2122         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
2123                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2124                 config->hw_vlan_insert = 0;
2125                 break;
2126         case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
2127         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
2128         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
2129         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
2130                 /*
2131                  * These NICs support VLAN insertion from WQE and
2132                  * report the wqe_vlan_insert flag. But there is the bug
2133                  * and PFC control may be broken, so disable feature.
2134                  */
2135                 config->hw_vlan_insert = 0;
2136                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2137                 break;
2138         default:
2139                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2140                 break;
2141         }
2142 exit:
2143         DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
2144 }
2145
2146 /**
2147  * Configures the metadata mask fields in the shared context.
2148  *
2149  * @param [in] dev
2150  *   Pointer to Ethernet device.
2151  */
2152 void
2153 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
2154 {
2155         struct mlx5_priv *priv = dev->data->dev_private;
2156         struct mlx5_dev_ctx_shared *sh = priv->sh;
2157         uint32_t meta, mark, reg_c0;
2158
2159         reg_c0 = ~priv->vport_meta_mask;
2160         switch (priv->config.dv_xmeta_en) {
2161         case MLX5_XMETA_MODE_LEGACY:
2162                 meta = UINT32_MAX;
2163                 mark = MLX5_FLOW_MARK_MASK;
2164                 break;
2165         case MLX5_XMETA_MODE_META16:
2166                 meta = reg_c0 >> rte_bsf32(reg_c0);
2167                 mark = MLX5_FLOW_MARK_MASK;
2168                 break;
2169         case MLX5_XMETA_MODE_META32:
2170                 meta = UINT32_MAX;
2171                 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
2172                 break;
2173         default:
2174                 meta = 0;
2175                 mark = 0;
2176                 MLX5_ASSERT(false);
2177                 break;
2178         }
2179         if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
2180                 DRV_LOG(WARNING, "metadata MARK mask mismatch %08X:%08X",
2181                                  sh->dv_mark_mask, mark);
2182         else
2183                 sh->dv_mark_mask = mark;
2184         if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
2185                 DRV_LOG(WARNING, "metadata META mask mismatch %08X:%08X",
2186                                  sh->dv_meta_mask, meta);
2187         else
2188                 sh->dv_meta_mask = meta;
2189         if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
2190                 DRV_LOG(WARNING, "metadata reg_c0 mask mismatch %08X:%08X",
2191                                  sh->dv_meta_mask, reg_c0);
2192         else
2193                 sh->dv_regc0_mask = reg_c0;
2194         DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
2195         DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
2196         DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
2197         DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
2198 }
2199
2200 int
2201 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
2202 {
2203         static const char *const dynf_names[] = {
2204                 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
2205                 RTE_MBUF_DYNFLAG_METADATA_NAME,
2206                 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
2207         };
2208         unsigned int i;
2209
2210         if (n < RTE_DIM(dynf_names))
2211                 return -ENOMEM;
2212         for (i = 0; i < RTE_DIM(dynf_names); i++) {
2213                 if (names[i] == NULL)
2214                         return -EINVAL;
2215                 strcpy(names[i], dynf_names[i]);
2216         }
2217         return RTE_DIM(dynf_names);
2218 }
2219
2220 /**
2221  * Check sibling device configurations.
2222  *
2223  * Sibling devices sharing the Infiniband device context should have compatible
2224  * configurations. This regards representors and bonding device.
2225  *
2226  * @param sh
2227  *   Shared device context.
2228  * @param config
2229  *   Configuration of the device is going to be created.
2230  * @param dpdk_dev
2231  *   Backing DPDK device.
2232  *
2233  * @return
2234  *   0 on success, EINVAL otherwise
2235  */
2236 int
2237 mlx5_dev_check_sibling_config(struct mlx5_dev_ctx_shared *sh,
2238                               struct mlx5_dev_config *config,
2239                               struct rte_device *dpdk_dev)
2240 {
2241         struct mlx5_dev_config *sh_conf = NULL;
2242         uint16_t port_id;
2243
2244         MLX5_ASSERT(sh);
2245         /* Nothing to compare for the single/first device. */
2246         if (sh->refcnt == 1)
2247                 return 0;
2248         /* Find the device with shared context. */
2249         MLX5_ETH_FOREACH_DEV(port_id, dpdk_dev) {
2250                 struct mlx5_priv *opriv =
2251                         rte_eth_devices[port_id].data->dev_private;
2252
2253                 if (opriv && opriv->sh == sh) {
2254                         sh_conf = &opriv->config;
2255                         break;
2256                 }
2257         }
2258         if (!sh_conf)
2259                 return 0;
2260         if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
2261                 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
2262                              " for shared %s context", sh->ibdev_name);
2263                 rte_errno = EINVAL;
2264                 return rte_errno;
2265         }
2266         if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
2267                 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
2268                              " for shared %s context", sh->ibdev_name);
2269                 rte_errno = EINVAL;
2270                 return rte_errno;
2271         }
2272         return 0;
2273 }
2274
2275 /**
2276  * Look for the ethernet device belonging to mlx5 driver.
2277  *
2278  * @param[in] port_id
2279  *   port_id to start looking for device.
2280  * @param[in] odev
2281  *   Pointer to the hint device. When device is being probed
2282  *   the its siblings (master and preceding representors might
2283  *   not have assigned driver yet (because the mlx5_os_pci_probe()
2284  *   is not completed yet, for this case match on hint
2285  *   device may be used to detect sibling device.
2286  *
2287  * @return
2288  *   port_id of found device, RTE_MAX_ETHPORT if not found.
2289  */
2290 uint16_t
2291 mlx5_eth_find_next(uint16_t port_id, struct rte_device *odev)
2292 {
2293         while (port_id < RTE_MAX_ETHPORTS) {
2294                 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
2295
2296                 if (dev->state != RTE_ETH_DEV_UNUSED &&
2297                     dev->device &&
2298                     (dev->device == odev ||
2299                      (dev->device->driver &&
2300                      dev->device->driver->name &&
2301                      ((strcmp(dev->device->driver->name,
2302                               MLX5_PCI_DRIVER_NAME) == 0) ||
2303                       (strcmp(dev->device->driver->name,
2304                               MLX5_AUXILIARY_DRIVER_NAME) == 0)))))
2305                         break;
2306                 port_id++;
2307         }
2308         if (port_id >= RTE_MAX_ETHPORTS)
2309                 return RTE_MAX_ETHPORTS;
2310         return port_id;
2311 }
2312
2313 /**
2314  * Callback to remove a device.
2315  *
2316  * This function removes all Ethernet devices belong to a given device.
2317  *
2318  * @param[in] cdev
2319  *   Pointer to the generic device.
2320  *
2321  * @return
2322  *   0 on success, the function cannot fail.
2323  */
2324 int
2325 mlx5_net_remove(struct mlx5_common_device *cdev)
2326 {
2327         uint16_t port_id;
2328         int ret = 0;
2329
2330         RTE_ETH_FOREACH_DEV_OF(port_id, cdev->dev) {
2331                 /*
2332                  * mlx5_dev_close() is not registered to secondary process,
2333                  * call the close function explicitly for secondary process.
2334                  */
2335                 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
2336                         ret |= mlx5_dev_close(&rte_eth_devices[port_id]);
2337                 else
2338                         ret |= rte_eth_dev_close(port_id);
2339         }
2340         return ret == 0 ? 0 : -EIO;
2341 }
2342
2343 static const struct rte_pci_id mlx5_pci_id_map[] = {
2344         {
2345                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2346                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
2347         },
2348         {
2349                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2350                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
2351         },
2352         {
2353                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2354                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
2355         },
2356         {
2357                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2358                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
2359         },
2360         {
2361                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2362                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
2363         },
2364         {
2365                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2366                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
2367         },
2368         {
2369                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2370                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
2371         },
2372         {
2373                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2374                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
2375         },
2376         {
2377                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2378                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
2379         },
2380         {
2381                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2382                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
2383         },
2384         {
2385                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2386                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
2387         },
2388         {
2389                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2390                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
2391         },
2392         {
2393                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2394                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
2395         },
2396         {
2397                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2398                                 PCI_DEVICE_ID_MELLANOX_CONNECTXVF)
2399         },
2400         {
2401                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2402                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
2403         },
2404         {
2405                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2406                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
2407         },
2408         {
2409                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2410                                 PCI_DEVICE_ID_MELLANOX_CONNECTX7)
2411         },
2412         {
2413                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2414                                 PCI_DEVICE_ID_MELLANOX_CONNECTX7BF)
2415         },
2416         {
2417                 .vendor_id = 0
2418         }
2419 };
2420
2421 static struct mlx5_class_driver mlx5_net_driver = {
2422         .drv_class = MLX5_CLASS_ETH,
2423         .name = RTE_STR(MLX5_ETH_DRIVER_NAME),
2424         .id_table = mlx5_pci_id_map,
2425         .probe = mlx5_os_net_probe,
2426         .remove = mlx5_net_remove,
2427         .probe_again = 1,
2428         .intr_lsc = 1,
2429         .intr_rmv = 1,
2430 };
2431
2432 /* Initialize driver log type. */
2433 RTE_LOG_REGISTER_DEFAULT(mlx5_logtype, NOTICE)
2434
2435 /**
2436  * Driver initialization routine.
2437  */
2438 RTE_INIT(rte_mlx5_pmd_init)
2439 {
2440         pthread_mutex_init(&mlx5_dev_ctx_list_mutex, NULL);
2441         mlx5_common_init();
2442         /* Build the static tables for Verbs conversion. */
2443         mlx5_set_ptype_table();
2444         mlx5_set_cksum_table();
2445         mlx5_set_swp_types_table();
2446         if (mlx5_glue)
2447                 mlx5_class_driver_register(&mlx5_net_driver);
2448 }
2449
2450 RTE_PMD_EXPORT_NAME(MLX5_ETH_DRIVER_NAME, __COUNTER__);
2451 RTE_PMD_REGISTER_PCI_TABLE(MLX5_ETH_DRIVER_NAME, mlx5_pci_id_map);
2452 RTE_PMD_REGISTER_KMOD_DEP(MLX5_ETH_DRIVER_NAME, "* ib_uverbs & mlx5_core & mlx5_ib");