4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
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44 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
46 #pragma GCC diagnostic ignored "-Wpedantic"
48 #include <infiniband/verbs.h>
50 #pragma GCC diagnostic error "-Wpedantic"
53 #include <rte_malloc.h>
54 #include <rte_ethdev.h>
55 #include <rte_ethdev_pci.h>
57 #include <rte_common.h>
58 #include <rte_kvargs.h>
61 #include "mlx5_utils.h"
62 #include "mlx5_rxtx.h"
63 #include "mlx5_autoconf.h"
64 #include "mlx5_defs.h"
66 /* Device parameter to enable RX completion queue compression. */
67 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
69 /* Device parameter to configure inline send. */
70 #define MLX5_TXQ_INLINE "txq_inline"
73 * Device parameter to configure the number of TX queues threshold for
74 * enabling inline send.
76 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
78 /* Device parameter to enable multi-packet send WQEs. */
79 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
81 /* Device parameter to include 2 dsegs in the title WQEBB. */
82 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
84 /* Device parameter to limit the size of inlining packet. */
85 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
87 /* Device parameter to enable hardware TSO offload. */
88 #define MLX5_TSO "tso"
90 /* Device parameter to enable hardware Tx vector. */
91 #define MLX5_TX_VEC_EN "tx_vec_en"
93 /* Device parameter to enable hardware Rx vector. */
94 #define MLX5_RX_VEC_EN "rx_vec_en"
96 /* Default PMD specific parameter value. */
97 #define MLX5_ARG_UNSET (-1)
99 #ifndef HAVE_IBV_MLX5_MOD_MPW
100 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2)
101 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3)
110 int inline_max_packet_sz;
116 * Retrieve integer value from environment variable.
119 * Environment variable name.
122 * Integer value, 0 if the variable is not set.
125 mlx5_getenv_int(const char *name)
127 const char *val = getenv(name);
135 * Verbs callback to allocate a memory. This function should allocate the space
136 * according to the size provided residing inside a huge page.
137 * Please note that all allocation must respect the alignment from libmlx5
138 * (i.e. currently sysconf(_SC_PAGESIZE)).
141 * The size in bytes of the memory to allocate.
143 * A pointer to the callback data.
146 * a pointer to the allocate space.
149 mlx5_alloc_verbs_buf(size_t size, void *data)
151 struct priv *priv = data;
153 size_t alignment = sysconf(_SC_PAGESIZE);
155 assert(data != NULL);
156 assert(!mlx5_is_secondary());
157 ret = rte_malloc_socket(__func__, size, alignment,
158 priv->dev->device->numa_node);
159 DEBUG("Extern alloc size: %lu, align: %lu: %p", size, alignment, ret);
164 * Verbs callback to free a memory.
167 * A pointer to the memory to free.
169 * A pointer to the callback data.
172 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused)
174 assert(data != NULL);
175 assert(!mlx5_is_secondary());
176 DEBUG("Extern free request: %p", ptr);
181 * DPDK callback to close the device.
183 * Destroy all queues and objects, free memory.
186 * Pointer to Ethernet device structure.
189 mlx5_dev_close(struct rte_eth_dev *dev)
191 struct priv *priv = mlx5_get_priv(dev);
196 DEBUG("%p: closing device \"%s\"",
198 ((priv->ctx != NULL) ? priv->ctx->device->name : ""));
199 /* In case mlx5_dev_stop() has not been called. */
200 priv_dev_interrupt_handler_uninstall(priv, dev);
201 priv_dev_traffic_disable(priv, dev);
202 /* Prevent crashes when queues are still in use. */
203 dev->rx_pkt_burst = removed_rx_burst;
204 dev->tx_pkt_burst = removed_tx_burst;
205 if (priv->rxqs != NULL) {
206 /* XXX race condition if mlx5_rx_burst() is still running. */
208 for (i = 0; (i != priv->rxqs_n); ++i)
209 mlx5_priv_rxq_release(priv, i);
213 if (priv->txqs != NULL) {
214 /* XXX race condition if mlx5_tx_burst() is still running. */
216 for (i = 0; (i != priv->txqs_n); ++i)
217 mlx5_priv_txq_release(priv, i);
221 if (priv->pd != NULL) {
222 assert(priv->ctx != NULL);
223 claim_zero(ibv_dealloc_pd(priv->pd));
224 claim_zero(ibv_close_device(priv->ctx));
226 assert(priv->ctx == NULL);
227 if (priv->rss_conf.rss_key != NULL)
228 rte_free(priv->rss_conf.rss_key);
229 if (priv->reta_idx != NULL)
230 rte_free(priv->reta_idx);
231 priv_socket_uninit(priv);
232 ret = mlx5_priv_hrxq_ibv_verify(priv);
234 WARN("%p: some Hash Rx queue still remain", (void *)priv);
235 ret = mlx5_priv_ind_table_ibv_verify(priv);
237 WARN("%p: some Indirection table still remain", (void *)priv);
238 ret = mlx5_priv_rxq_ibv_verify(priv);
240 WARN("%p: some Verbs Rx queue still remain", (void *)priv);
241 ret = mlx5_priv_rxq_verify(priv);
243 WARN("%p: some Rx Queues still remain", (void *)priv);
244 ret = mlx5_priv_txq_ibv_verify(priv);
246 WARN("%p: some Verbs Tx queue still remain", (void *)priv);
247 ret = mlx5_priv_txq_verify(priv);
249 WARN("%p: some Tx Queues still remain", (void *)priv);
250 ret = priv_flow_verify(priv);
252 WARN("%p: some flows still remain", (void *)priv);
253 ret = priv_mr_verify(priv);
255 WARN("%p: some Memory Region still remain", (void *)priv);
257 memset(priv, 0, sizeof(*priv));
260 static const struct eth_dev_ops mlx5_dev_ops = {
261 .dev_configure = mlx5_dev_configure,
262 .dev_start = mlx5_dev_start,
263 .dev_stop = mlx5_dev_stop,
264 .dev_set_link_down = mlx5_set_link_down,
265 .dev_set_link_up = mlx5_set_link_up,
266 .dev_close = mlx5_dev_close,
267 .promiscuous_enable = mlx5_promiscuous_enable,
268 .promiscuous_disable = mlx5_promiscuous_disable,
269 .allmulticast_enable = mlx5_allmulticast_enable,
270 .allmulticast_disable = mlx5_allmulticast_disable,
271 .link_update = mlx5_link_update,
272 .stats_get = mlx5_stats_get,
273 .stats_reset = mlx5_stats_reset,
274 .xstats_get = mlx5_xstats_get,
275 .xstats_reset = mlx5_xstats_reset,
276 .xstats_get_names = mlx5_xstats_get_names,
277 .dev_infos_get = mlx5_dev_infos_get,
278 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
279 .vlan_filter_set = mlx5_vlan_filter_set,
280 .rx_queue_setup = mlx5_rx_queue_setup,
281 .tx_queue_setup = mlx5_tx_queue_setup,
282 .rx_queue_release = mlx5_rx_queue_release,
283 .tx_queue_release = mlx5_tx_queue_release,
284 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
285 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
286 .mac_addr_remove = mlx5_mac_addr_remove,
287 .mac_addr_add = mlx5_mac_addr_add,
288 .mac_addr_set = mlx5_mac_addr_set,
289 .mtu_set = mlx5_dev_set_mtu,
290 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
291 .vlan_offload_set = mlx5_vlan_offload_set,
292 .reta_update = mlx5_dev_rss_reta_update,
293 .reta_query = mlx5_dev_rss_reta_query,
294 .rss_hash_update = mlx5_rss_hash_update,
295 .rss_hash_conf_get = mlx5_rss_hash_conf_get,
296 .filter_ctrl = mlx5_dev_filter_ctrl,
297 .rx_descriptor_status = mlx5_rx_descriptor_status,
298 .tx_descriptor_status = mlx5_tx_descriptor_status,
299 .rx_queue_intr_enable = mlx5_rx_intr_enable,
300 .rx_queue_intr_disable = mlx5_rx_intr_disable,
304 static const struct eth_dev_ops mlx5_dev_sec_ops = {
305 .stats_get = mlx5_stats_get,
306 .stats_reset = mlx5_stats_reset,
307 .xstats_get = mlx5_xstats_get,
308 .xstats_reset = mlx5_xstats_reset,
309 .xstats_get_names = mlx5_xstats_get_names,
310 .dev_infos_get = mlx5_dev_infos_get,
311 .rx_descriptor_status = mlx5_rx_descriptor_status,
312 .tx_descriptor_status = mlx5_tx_descriptor_status,
316 struct rte_pci_addr pci_addr; /* associated PCI address */
317 uint32_t ports; /* physical ports bitfield. */
321 * Get device index in mlx5_dev[] from PCI bus address.
323 * @param[in] pci_addr
324 * PCI bus address to look for.
327 * mlx5_dev[] index on success, -1 on failure.
330 mlx5_dev_idx(struct rte_pci_addr *pci_addr)
335 assert(pci_addr != NULL);
336 for (i = 0; (i != RTE_DIM(mlx5_dev)); ++i) {
337 if ((mlx5_dev[i].pci_addr.domain == pci_addr->domain) &&
338 (mlx5_dev[i].pci_addr.bus == pci_addr->bus) &&
339 (mlx5_dev[i].pci_addr.devid == pci_addr->devid) &&
340 (mlx5_dev[i].pci_addr.function == pci_addr->function))
342 if ((mlx5_dev[i].ports == 0) && (ret == -1))
349 * Verify and store value for device argument.
352 * Key argument to verify.
354 * Value associated with key.
359 * 0 on success, negative errno value on failure.
362 mlx5_args_check(const char *key, const char *val, void *opaque)
364 struct mlx5_args *args = opaque;
368 tmp = strtoul(val, NULL, 0);
370 WARN("%s: \"%s\" is not a valid integer", key, val);
373 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
374 args->cqe_comp = !!tmp;
375 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
376 args->txq_inline = tmp;
377 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
378 args->txqs_inline = tmp;
379 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
381 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
382 args->mpw_hdr_dseg = !!tmp;
383 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
384 args->inline_max_packet_sz = tmp;
385 } else if (strcmp(MLX5_TSO, key) == 0) {
387 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
388 args->tx_vec_en = !!tmp;
389 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
390 args->rx_vec_en = !!tmp;
392 WARN("%s: unknown parameter", key);
399 * Parse device parameters.
402 * Pointer to private structure.
404 * Device arguments structure.
407 * 0 on success, errno value on failure.
410 mlx5_args(struct mlx5_args *args, struct rte_devargs *devargs)
412 const char **params = (const char *[]){
413 MLX5_RXQ_CQE_COMP_EN,
415 MLX5_TXQS_MIN_INLINE,
417 MLX5_TXQ_MPW_HDR_DSEG_EN,
418 MLX5_TXQ_MAX_INLINE_LEN,
424 struct rte_kvargs *kvlist;
430 /* Following UGLY cast is done to pass checkpatch. */
431 kvlist = rte_kvargs_parse(devargs->args, params);
434 /* Process parameters. */
435 for (i = 0; (params[i] != NULL); ++i) {
436 if (rte_kvargs_count(kvlist, params[i])) {
437 ret = rte_kvargs_process(kvlist, params[i],
438 mlx5_args_check, args);
440 rte_kvargs_free(kvlist);
445 rte_kvargs_free(kvlist);
449 static struct rte_pci_driver mlx5_driver;
452 * Assign parameters from args into priv, only non default
453 * values are considered.
456 * Pointer to private structure.
458 * Pointer to args values.
461 mlx5_args_assign(struct priv *priv, struct mlx5_args *args)
463 if (args->cqe_comp != MLX5_ARG_UNSET)
464 priv->cqe_comp = args->cqe_comp;
465 if (args->txq_inline != MLX5_ARG_UNSET)
466 priv->txq_inline = args->txq_inline;
467 if (args->txqs_inline != MLX5_ARG_UNSET)
468 priv->txqs_inline = args->txqs_inline;
469 if (args->mps != MLX5_ARG_UNSET)
470 priv->mps = args->mps ? priv->mps : 0;
471 if (args->mpw_hdr_dseg != MLX5_ARG_UNSET)
472 priv->mpw_hdr_dseg = args->mpw_hdr_dseg;
473 if (args->inline_max_packet_sz != MLX5_ARG_UNSET)
474 priv->inline_max_packet_sz = args->inline_max_packet_sz;
475 if (args->tso != MLX5_ARG_UNSET)
476 priv->tso = args->tso;
477 if (args->tx_vec_en != MLX5_ARG_UNSET)
478 priv->tx_vec_en = args->tx_vec_en;
479 if (args->rx_vec_en != MLX5_ARG_UNSET)
480 priv->rx_vec_en = args->rx_vec_en;
484 * DPDK callback to register a PCI device.
486 * This function creates an Ethernet device for each port of a given
490 * PCI driver structure (mlx5_driver).
492 * PCI device information.
495 * 0 on success, negative errno value on failure.
498 mlx5_pci_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
500 struct ibv_device **list;
501 struct ibv_device *ibv_dev;
503 struct ibv_context *attr_ctx = NULL;
504 struct ibv_device_attr_ex device_attr;
507 unsigned int tunnel_en = 0;
510 struct mlx5dv_context attrs_out;
513 assert(pci_drv == &mlx5_driver);
514 /* Get mlx5_dev[] index. */
515 idx = mlx5_dev_idx(&pci_dev->addr);
517 ERROR("this driver cannot support any more adapters");
520 DEBUG("using driver device index %d", idx);
522 /* Save PCI address. */
523 mlx5_dev[idx].pci_addr = pci_dev->addr;
524 list = ibv_get_device_list(&i);
528 ERROR("cannot list devices, is ib_uverbs loaded?");
533 * For each listed device, check related sysfs entry against
534 * the provided PCI ID.
537 struct rte_pci_addr pci_addr;
540 DEBUG("checking device \"%s\"", list[i]->name);
541 if (mlx5_ibv_device_to_pci_addr(list[i], &pci_addr))
543 if ((pci_dev->addr.domain != pci_addr.domain) ||
544 (pci_dev->addr.bus != pci_addr.bus) ||
545 (pci_dev->addr.devid != pci_addr.devid) ||
546 (pci_dev->addr.function != pci_addr.function))
548 sriov = ((pci_dev->id.device_id ==
549 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF) ||
550 (pci_dev->id.device_id ==
551 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF) ||
552 (pci_dev->id.device_id ==
553 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF) ||
554 (pci_dev->id.device_id ==
555 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF));
556 switch (pci_dev->id.device_id) {
557 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
560 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
561 case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
562 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
563 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
564 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
570 INFO("PCI information matches, using device \"%s\""
573 sriov ? "true" : "false");
574 attr_ctx = ibv_open_device(list[i]);
578 if (attr_ctx == NULL) {
579 ibv_free_device_list(list);
582 ERROR("cannot access device, is mlx5_ib loaded?");
585 ERROR("cannot use device, are drivers up to date?");
593 DEBUG("device opened");
595 * Multi-packet send is supported by ConnectX-4 Lx PF as well
596 * as all ConnectX-5 devices.
598 mlx5dv_query_device(attr_ctx, &attrs_out);
599 if (attrs_out.flags & (MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW |
600 MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED)) {
601 INFO("Enhanced MPW is detected\n");
602 mps = MLX5_MPW_ENHANCED;
603 } else if (attrs_out.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
604 INFO("MPW is detected\n");
607 INFO("MPW is disabled\n");
608 mps = MLX5_MPW_DISABLED;
610 if (ibv_query_device_ex(attr_ctx, NULL, &device_attr))
612 INFO("%u port(s) detected", device_attr.orig_attr.phys_port_cnt);
614 for (i = 0; i < device_attr.orig_attr.phys_port_cnt; i++) {
615 uint32_t port = i + 1; /* ports are indexed from one */
616 uint32_t test = (1 << i);
617 struct ibv_context *ctx = NULL;
618 struct ibv_port_attr port_attr;
619 struct ibv_pd *pd = NULL;
620 struct priv *priv = NULL;
621 struct rte_eth_dev *eth_dev;
622 struct ibv_device_attr_ex device_attr_ex;
623 struct ether_addr mac;
624 uint16_t num_vfs = 0;
625 struct mlx5_args args = {
626 .cqe_comp = MLX5_ARG_UNSET,
627 .txq_inline = MLX5_ARG_UNSET,
628 .txqs_inline = MLX5_ARG_UNSET,
629 .mps = MLX5_ARG_UNSET,
630 .mpw_hdr_dseg = MLX5_ARG_UNSET,
631 .inline_max_packet_sz = MLX5_ARG_UNSET,
632 .tso = MLX5_ARG_UNSET,
633 .tx_vec_en = MLX5_ARG_UNSET,
634 .rx_vec_en = MLX5_ARG_UNSET,
637 mlx5_dev[idx].ports |= test;
639 if (mlx5_is_secondary()) {
640 /* from rte_ethdev.c */
641 char name[RTE_ETH_NAME_MAX_LEN];
643 snprintf(name, sizeof(name), "%s port %u",
644 ibv_get_device_name(ibv_dev), port);
645 eth_dev = rte_eth_dev_attach_secondary(name);
646 if (eth_dev == NULL) {
647 ERROR("can not attach rte ethdev");
651 eth_dev->device = &pci_dev->device;
652 eth_dev->dev_ops = &mlx5_dev_sec_ops;
653 priv = eth_dev->data->dev_private;
654 /* Receive command fd from primary process */
655 err = priv_socket_connect(priv);
660 /* Remap UAR for Tx queues. */
661 err = priv_tx_uar_remap(priv, err);
666 priv_dev_select_rx_function(priv, eth_dev);
667 priv_dev_select_tx_function(priv, eth_dev);
671 DEBUG("using port %u (%08" PRIx32 ")", port, test);
673 ctx = ibv_open_device(ibv_dev);
679 /* Check port status. */
680 err = ibv_query_port(ctx, port, &port_attr);
682 ERROR("port query failed: %s", strerror(err));
686 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
687 ERROR("port %d is not configured in Ethernet mode",
693 if (port_attr.state != IBV_PORT_ACTIVE)
694 DEBUG("port %d is not active: \"%s\" (%d)",
695 port, ibv_port_state_str(port_attr.state),
698 /* Allocate protection domain. */
699 pd = ibv_alloc_pd(ctx);
701 ERROR("PD allocation failure");
706 mlx5_dev[idx].ports |= test;
708 /* from rte_ethdev.c */
709 priv = rte_zmalloc("ethdev private structure",
711 RTE_CACHE_LINE_SIZE);
713 ERROR("priv allocation failure");
719 strncpy(priv->ibdev_path, priv->ctx->device->ibdev_path,
720 sizeof(priv->ibdev_path));
721 priv->device_attr = device_attr;
724 priv->mtu = ETHER_MTU;
725 priv->mps = mps; /* Enable MPW by default if supported. */
726 priv->cqe_comp = 1; /* Enable compression by default. */
727 priv->tunnel_en = tunnel_en;
728 /* Enable vector by default if supported. */
731 err = mlx5_args(&args, pci_dev->device.devargs);
733 ERROR("failed to process device arguments: %s",
737 mlx5_args_assign(priv, &args);
738 if (ibv_query_device_ex(ctx, NULL, &device_attr_ex)) {
739 ERROR("ibv_query_device_ex() failed");
744 !!(device_attr_ex.device_cap_flags_ex &
745 IBV_DEVICE_RAW_IP_CSUM);
746 DEBUG("checksum offloading is %ssupported",
747 (priv->hw_csum ? "" : "not "));
749 #ifdef HAVE_IBV_DEVICE_VXLAN_SUPPORT
750 priv->hw_csum_l2tun = !!(exp_device_attr.exp_device_cap_flags &
751 IBV_DEVICE_VXLAN_SUPPORT);
753 DEBUG("L2 tunnel checksum offloads are %ssupported",
754 (priv->hw_csum_l2tun ? "" : "not "));
756 priv->ind_table_max_size =
757 device_attr_ex.rss_caps.max_rwq_indirection_table_size;
758 /* Remove this check once DPDK supports larger/variable
759 * indirection tables. */
760 if (priv->ind_table_max_size >
761 (unsigned int)ETH_RSS_RETA_SIZE_512)
762 priv->ind_table_max_size = ETH_RSS_RETA_SIZE_512;
763 DEBUG("maximum RX indirection table size is %u",
764 priv->ind_table_max_size);
765 priv->hw_vlan_strip = !!(device_attr_ex.raw_packet_caps &
766 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
767 DEBUG("VLAN stripping is %ssupported",
768 (priv->hw_vlan_strip ? "" : "not "));
771 !!(device_attr_ex.orig_attr.device_cap_flags &
772 IBV_WQ_FLAGS_SCATTER_FCS);
773 DEBUG("FCS stripping configuration is %ssupported",
774 (priv->hw_fcs_strip ? "" : "not "));
776 #ifdef HAVE_IBV_WQ_FLAG_RX_END_PADDING
777 priv->hw_padding = !!device_attr_ex.rx_pad_end_addr_align;
779 DEBUG("hardware RX end alignment padding is %ssupported",
780 (priv->hw_padding ? "" : "not "));
782 priv_get_num_vfs(priv, &num_vfs);
783 priv->sriov = (num_vfs || sriov);
784 priv->tso = ((priv->tso) &&
785 (device_attr_ex.tso_caps.max_tso > 0) &&
786 (device_attr_ex.tso_caps.supported_qpts &
787 (1 << IBV_QPT_RAW_PACKET)));
789 priv->max_tso_payload_sz =
790 device_attr_ex.tso_caps.max_tso;
791 if (priv->mps && !mps) {
792 ERROR("multi-packet send not supported on this device"
793 " (" MLX5_TXQ_MPW_EN ")");
796 } else if (priv->mps && priv->tso) {
797 WARN("multi-packet send not supported in conjunction "
798 "with TSO. MPS disabled");
802 priv->mps == MLX5_MPW_ENHANCED ? "Enhanced " : "",
803 priv->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled");
804 /* Set default values for Enhanced MPW, a.k.a MPWv2. */
805 if (priv->mps == MLX5_MPW_ENHANCED) {
806 if (args.txqs_inline == MLX5_ARG_UNSET)
807 priv->txqs_inline = MLX5_EMPW_MIN_TXQS;
808 if (args.inline_max_packet_sz == MLX5_ARG_UNSET)
809 priv->inline_max_packet_sz =
810 MLX5_EMPW_MAX_INLINE_LEN;
811 if (args.txq_inline == MLX5_ARG_UNSET)
812 priv->txq_inline = MLX5_WQE_SIZE_MAX -
815 /* Configure the first MAC address by default. */
816 if (priv_get_mac(priv, &mac.addr_bytes)) {
817 ERROR("cannot get MAC address, is mlx5_en loaded?"
818 " (errno: %s)", strerror(errno));
822 INFO("port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x",
824 mac.addr_bytes[0], mac.addr_bytes[1],
825 mac.addr_bytes[2], mac.addr_bytes[3],
826 mac.addr_bytes[4], mac.addr_bytes[5]);
829 char ifname[IF_NAMESIZE];
831 if (priv_get_ifname(priv, &ifname) == 0)
832 DEBUG("port %u ifname is \"%s\"",
835 DEBUG("port %u ifname is unknown", priv->port);
838 /* Get actual MTU if possible. */
839 priv_get_mtu(priv, &priv->mtu);
840 DEBUG("port %u MTU is %u", priv->port, priv->mtu);
842 /* from rte_ethdev.c */
844 char name[RTE_ETH_NAME_MAX_LEN];
846 snprintf(name, sizeof(name), "%s port %u",
847 ibv_get_device_name(ibv_dev), port);
848 eth_dev = rte_eth_dev_allocate(name);
850 if (eth_dev == NULL) {
851 ERROR("can not allocate rte ethdev");
855 eth_dev->data->dev_private = priv;
856 eth_dev->data->mac_addrs = priv->mac;
857 eth_dev->device = &pci_dev->device;
858 rte_eth_copy_pci_info(eth_dev, pci_dev);
859 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
860 eth_dev->device->driver = &mlx5_driver.driver;
862 eth_dev->dev_ops = &mlx5_dev_ops;
863 /* Register MAC address. */
864 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
865 TAILQ_INIT(&priv->flows);
866 TAILQ_INIT(&priv->ctrl_flows);
868 /* Hint libmlx5 to use PMD allocator for data plane resources */
869 struct mlx5dv_ctx_allocators alctr = {
870 .alloc = &mlx5_alloc_verbs_buf,
871 .free = &mlx5_free_verbs_buf,
874 mlx5dv_set_context_attr(ctx, MLX5DV_CTX_ATTR_BUF_ALLOCATORS,
875 (void *)((uintptr_t)&alctr));
877 /* Bring Ethernet device up. */
878 DEBUG("forcing Ethernet interface up");
879 priv_set_flags(priv, ~IFF_UP, IFF_UP);
880 mlx5_link_update(priv->dev, 1);
887 claim_zero(ibv_dealloc_pd(pd));
889 claim_zero(ibv_close_device(ctx));
894 * XXX if something went wrong in the loop above, there is a resource
895 * leak (ctx, pd, priv, dpdk ethdev) but we can do nothing about it as
896 * long as the dpdk does not provide a way to deallocate a ethdev and a
897 * way to enumerate the registered ethdevs to free the previous ones.
900 /* no port found, complain */
901 if (!mlx5_dev[idx].ports) {
908 claim_zero(ibv_close_device(attr_ctx));
910 ibv_free_device_list(list);
915 static const struct rte_pci_id mlx5_pci_id_map[] = {
917 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
918 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
921 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
922 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
925 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
926 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
929 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
930 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
933 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
934 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
937 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
938 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
941 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
942 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
945 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
946 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
953 static struct rte_pci_driver mlx5_driver = {
955 .name = MLX5_DRIVER_NAME
957 .id_table = mlx5_pci_id_map,
958 .probe = mlx5_pci_probe,
959 .drv_flags = RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV,
963 * Driver initialization routine.
965 RTE_INIT(rte_mlx5_pmd_init);
967 rte_mlx5_pmd_init(void)
969 /* Build the static table for ptype conversion. */
970 mlx5_set_ptype_table();
972 * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use
973 * huge pages. Calling ibv_fork_init() during init allows
974 * applications to use fork() safely for purposes other than
975 * using this PMD, which is not supported in forked processes.
977 setenv("RDMAV_HUGEPAGES_SAFE", "1", 1);
978 /* Don't map UAR to WC if BlueFlame is not used.*/
979 setenv("MLX5_SHUT_UP_BF", "1", 1);
981 rte_pci_register(&mlx5_driver);
984 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
985 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
986 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");