1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
13 #include <rte_malloc.h>
14 #include <ethdev_driver.h>
16 #include <rte_bus_pci.h>
17 #include <rte_common.h>
18 #include <rte_kvargs.h>
19 #include <rte_rwlock.h>
20 #include <rte_spinlock.h>
21 #include <rte_string_fns.h>
22 #include <rte_eal_paging.h>
23 #include <rte_alarm.h>
24 #include <rte_cycles.h>
26 #include <mlx5_glue.h>
27 #include <mlx5_devx_cmds.h>
28 #include <mlx5_common.h>
29 #include <mlx5_common_os.h>
30 #include <mlx5_common_mp.h>
31 #include <mlx5_malloc.h>
33 #include "mlx5_defs.h"
35 #include "mlx5_utils.h"
36 #include "mlx5_rxtx.h"
39 #include "mlx5_autoconf.h"
40 #include "mlx5_flow.h"
41 #include "mlx5_flow_os.h"
42 #include "rte_pmd_mlx5.h"
44 #define MLX5_ETH_DRIVER_NAME mlx5_eth
46 /* Driver type key for new device global syntax. */
47 #define MLX5_DRIVER_KEY "driver"
49 /* Device parameter to enable RX completion queue compression. */
50 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
52 /* Device parameter to enable padding Rx packet to cacheline size. */
53 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
55 /* Device parameter to enable Multi-Packet Rx queue. */
56 #define MLX5_RX_MPRQ_EN "mprq_en"
58 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
59 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
61 /* Device parameter to configure log 2 of the stride size for MPRQ. */
62 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
64 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
65 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
67 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
68 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
70 /* Device parameter to configure inline send. Deprecated, ignored.*/
71 #define MLX5_TXQ_INLINE "txq_inline"
73 /* Device parameter to limit packet size to inline with ordinary SEND. */
74 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
76 /* Device parameter to configure minimal data size to inline. */
77 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
79 /* Device parameter to limit packet size to inline with Enhanced MPW. */
80 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
83 * Device parameter to configure the number of TX queues threshold for
84 * enabling inline send.
86 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
89 * Device parameter to configure the number of TX queues threshold for
90 * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
92 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
94 /* Device parameter to enable multi-packet send WQEs. */
95 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
98 * Device parameter to force doorbell register mapping
99 * to non-cahed region eliminating the extra write memory barrier.
101 #define MLX5_TX_DB_NC "tx_db_nc"
104 * Device parameter to include 2 dsegs in the title WQEBB.
105 * Deprecated, ignored.
107 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
110 * Device parameter to limit the size of inlining packet.
111 * Deprecated, ignored.
113 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
116 * Device parameter to enable Tx scheduling on timestamps
117 * and specify the packet pacing granularity in nanoseconds.
119 #define MLX5_TX_PP "tx_pp"
122 * Device parameter to specify skew in nanoseconds on Tx datapath,
123 * it represents the time between SQ start WQE processing and
124 * appearing actual packet data on the wire.
126 #define MLX5_TX_SKEW "tx_skew"
129 * Device parameter to enable hardware Tx vector.
130 * Deprecated, ignored (no vectorized Tx routines anymore).
132 #define MLX5_TX_VEC_EN "tx_vec_en"
134 /* Device parameter to enable hardware Rx vector. */
135 #define MLX5_RX_VEC_EN "rx_vec_en"
137 /* Allow L3 VXLAN flow creation. */
138 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
140 /* Activate DV E-Switch flow steering. */
141 #define MLX5_DV_ESW_EN "dv_esw_en"
143 /* Activate DV flow steering. */
144 #define MLX5_DV_FLOW_EN "dv_flow_en"
146 /* Enable extensive flow metadata support. */
147 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
149 /* Device parameter to let the user manage the lacp traffic of bonded device */
150 #define MLX5_LACP_BY_USER "lacp_by_user"
152 /* Activate Netlink support in VF mode. */
153 #define MLX5_VF_NL_EN "vf_nl_en"
155 /* Enable extending memsegs when creating a MR. */
156 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
158 /* Select port representors to instantiate. */
159 #define MLX5_REPRESENTOR "representor"
161 /* Device parameter to configure the maximum number of dump files per queue. */
162 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
164 /* Configure timeout of LRO session (in microseconds). */
165 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
168 * Device parameter to configure the total data buffer size for a single
169 * hairpin queue (logarithm value).
171 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
173 /* Flow memory reclaim mode. */
174 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
176 /* The default memory allocator used in PMD. */
177 #define MLX5_SYS_MEM_EN "sys_mem_en"
178 /* Decap will be used or not. */
179 #define MLX5_DECAP_EN "decap_en"
181 /* Device parameter to configure allow or prevent duplicate rules pattern. */
182 #define MLX5_ALLOW_DUPLICATE_PATTERN "allow_duplicate_pattern"
184 /* Device parameter to configure implicit registration of mempool memory. */
185 #define MLX5_MR_MEMPOOL_REG_EN "mr_mempool_reg_en"
187 /* Device parameter to configure the delay drop when creating Rxqs. */
188 #define MLX5_DELAY_DROP "delay_drop"
190 /* Shared memory between primary and secondary processes. */
191 struct mlx5_shared_data *mlx5_shared_data;
193 /** Driver-specific log messages type. */
196 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
197 LIST_HEAD_INITIALIZER();
198 static pthread_mutex_t mlx5_dev_ctx_list_mutex;
199 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
200 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
201 [MLX5_IPOOL_DECAP_ENCAP] = {
202 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
208 .malloc = mlx5_malloc,
210 .type = "mlx5_encap_decap_ipool",
212 [MLX5_IPOOL_PUSH_VLAN] = {
213 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
219 .malloc = mlx5_malloc,
221 .type = "mlx5_push_vlan_ipool",
224 .size = sizeof(struct mlx5_flow_dv_tag_resource),
230 .per_core_cache = (1 << 16),
231 .malloc = mlx5_malloc,
233 .type = "mlx5_tag_ipool",
235 [MLX5_IPOOL_PORT_ID] = {
236 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
242 .malloc = mlx5_malloc,
244 .type = "mlx5_port_id_ipool",
246 [MLX5_IPOOL_JUMP] = {
247 .size = sizeof(struct mlx5_flow_tbl_data_entry),
253 .malloc = mlx5_malloc,
255 .type = "mlx5_jump_ipool",
257 [MLX5_IPOOL_SAMPLE] = {
258 .size = sizeof(struct mlx5_flow_dv_sample_resource),
264 .malloc = mlx5_malloc,
266 .type = "mlx5_sample_ipool",
268 [MLX5_IPOOL_DEST_ARRAY] = {
269 .size = sizeof(struct mlx5_flow_dv_dest_array_resource),
275 .malloc = mlx5_malloc,
277 .type = "mlx5_dest_array_ipool",
279 [MLX5_IPOOL_TUNNEL_ID] = {
280 .size = sizeof(struct mlx5_flow_tunnel),
281 .trunk_size = MLX5_MAX_TUNNELS,
284 .type = "mlx5_tunnel_offload",
286 [MLX5_IPOOL_TNL_TBL_ID] = {
289 .type = "mlx5_flow_tnl_tbl_ipool",
294 * The ipool index should grow continually from small to big,
295 * for meter idx, so not set grow_trunk to avoid meter index
296 * not jump continually.
298 .size = sizeof(struct mlx5_legacy_flow_meter),
302 .malloc = mlx5_malloc,
304 .type = "mlx5_meter_ipool",
307 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
313 .malloc = mlx5_malloc,
315 .type = "mlx5_mcp_ipool",
317 [MLX5_IPOOL_HRXQ] = {
318 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
324 .malloc = mlx5_malloc,
326 .type = "mlx5_hrxq_ipool",
328 [MLX5_IPOOL_MLX5_FLOW] = {
330 * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
331 * It set in run time according to PCI function configuration.
339 .per_core_cache = 1 << 19,
340 .malloc = mlx5_malloc,
342 .type = "mlx5_flow_handle_ipool",
344 [MLX5_IPOOL_RTE_FLOW] = {
345 .size = sizeof(struct rte_flow),
349 .malloc = mlx5_malloc,
351 .type = "rte_flow_ipool",
353 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID] = {
356 .type = "mlx5_flow_rss_id_ipool",
358 [MLX5_IPOOL_RSS_SHARED_ACTIONS] = {
359 .size = sizeof(struct mlx5_shared_action_rss),
365 .malloc = mlx5_malloc,
367 .type = "mlx5_shared_action_rss",
369 [MLX5_IPOOL_MTR_POLICY] = {
371 * The ipool index should grow continually from small to big,
372 * for policy idx, so not set grow_trunk to avoid policy index
373 * not jump continually.
375 .size = sizeof(struct mlx5_flow_meter_sub_policy),
379 .malloc = mlx5_malloc,
381 .type = "mlx5_meter_policy_ipool",
385 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
386 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
388 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 1024
391 * Decide whether representor ID is a HPF(host PF) port on BF2.
394 * Pointer to Ethernet device structure.
397 * Non-zero if HPF, otherwise 0.
400 mlx5_is_hpf(struct rte_eth_dev *dev)
402 struct mlx5_priv *priv = dev->data->dev_private;
403 uint16_t repr = MLX5_REPRESENTOR_REPR(priv->representor_id);
404 int type = MLX5_REPRESENTOR_TYPE(priv->representor_id);
406 return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_VF &&
407 MLX5_REPRESENTOR_REPR(-1) == repr;
411 * Decide whether representor ID is a SF port representor.
414 * Pointer to Ethernet device structure.
417 * Non-zero if HPF, otherwise 0.
420 mlx5_is_sf_repr(struct rte_eth_dev *dev)
422 struct mlx5_priv *priv = dev->data->dev_private;
423 int type = MLX5_REPRESENTOR_TYPE(priv->representor_id);
425 return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_SF;
429 * Initialize the ASO aging management structure.
432 * Pointer to mlx5_dev_ctx_shared object to free
435 * 0 on success, a negative errno value otherwise and rte_errno is set.
438 mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh)
444 sh->aso_age_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->aso_age_mng),
445 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
446 if (!sh->aso_age_mng) {
447 DRV_LOG(ERR, "aso_age_mng allocation was failed.");
451 err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_FLOW_HIT);
453 mlx5_free(sh->aso_age_mng);
456 rte_rwlock_init(&sh->aso_age_mng->resize_rwl);
457 rte_spinlock_init(&sh->aso_age_mng->free_sl);
458 LIST_INIT(&sh->aso_age_mng->free);
463 * Close and release all the resources of the ASO aging management structure.
466 * Pointer to mlx5_dev_ctx_shared object to free.
469 mlx5_flow_aso_age_mng_close(struct mlx5_dev_ctx_shared *sh)
473 mlx5_aso_flow_hit_queue_poll_stop(sh);
474 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_FLOW_HIT);
475 if (sh->aso_age_mng->pools) {
476 struct mlx5_aso_age_pool *pool;
478 for (i = 0; i < sh->aso_age_mng->next; ++i) {
479 pool = sh->aso_age_mng->pools[i];
480 claim_zero(mlx5_devx_cmd_destroy
481 (pool->flow_hit_aso_obj));
482 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j)
483 if (pool->actions[j].dr_action)
485 (mlx5_flow_os_destroy_flow_action
486 (pool->actions[j].dr_action));
489 mlx5_free(sh->aso_age_mng->pools);
491 mlx5_free(sh->aso_age_mng);
495 * Initialize the shared aging list information per port.
498 * Pointer to mlx5_dev_ctx_shared object.
501 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
504 struct mlx5_age_info *age_info;
506 for (i = 0; i < sh->max_port; i++) {
507 age_info = &sh->port[i].age_info;
509 TAILQ_INIT(&age_info->aged_counters);
510 LIST_INIT(&age_info->aged_aso);
511 rte_spinlock_init(&age_info->aged_sl);
512 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
517 * DV flow counter mode detect and config.
520 * Pointer to rte_eth_dev structure.
524 mlx5_flow_counter_mode_config(struct rte_eth_dev *dev __rte_unused)
526 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
527 struct mlx5_priv *priv = dev->data->dev_private;
528 struct mlx5_dev_ctx_shared *sh = priv->sh;
529 struct mlx5_hca_attr *hca_attr = &sh->cdev->config.hca_attr;
532 #ifndef HAVE_IBV_DEVX_ASYNC
536 if (!sh->cdev->config.devx || !priv->config.dv_flow_en ||
537 !hca_attr->flow_counters_dump ||
538 !(hca_attr->flow_counter_bulk_alloc_bitmap & 0x4) ||
539 (mlx5_flow_dv_discover_counter_offset_support(dev) == -ENOTSUP))
543 DRV_LOG(INFO, "Use fall-back DV counter management. Flow "
544 "counter dump:%d, bulk_alloc_bitmap:0x%hhx.",
545 hca_attr->flow_counters_dump,
546 hca_attr->flow_counter_bulk_alloc_bitmap);
547 /* Initialize fallback mode only on the port initializes sh. */
549 sh->cmng.counter_fallback = fallback;
550 else if (fallback != sh->cmng.counter_fallback)
551 DRV_LOG(WARNING, "Port %d in sh has different fallback mode "
552 "with others:%d.", PORT_ID(priv), fallback);
557 * Initialize the counters management structure.
560 * Pointer to mlx5_dev_ctx_shared object to free
563 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
567 memset(&sh->cmng, 0, sizeof(sh->cmng));
568 TAILQ_INIT(&sh->cmng.flow_counters);
569 sh->cmng.min_id = MLX5_CNT_BATCH_OFFSET;
570 sh->cmng.max_id = -1;
571 sh->cmng.last_pool_idx = POOL_IDX_INVALID;
572 rte_spinlock_init(&sh->cmng.pool_update_sl);
573 for (i = 0; i < MLX5_COUNTER_TYPE_MAX; i++) {
574 TAILQ_INIT(&sh->cmng.counters[i]);
575 rte_spinlock_init(&sh->cmng.csl[i]);
580 * Destroy all the resources allocated for a counter memory management.
583 * Pointer to the memory management structure.
586 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
588 uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
590 LIST_REMOVE(mng, next);
591 mlx5_os_wrapped_mkey_destroy(&mng->wm);
596 * Close and release all the resources of the counters management.
599 * Pointer to mlx5_dev_ctx_shared object to free.
602 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
604 struct mlx5_counter_stats_mem_mng *mng;
610 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
611 if (rte_errno != EINPROGRESS)
616 if (sh->cmng.pools) {
617 struct mlx5_flow_counter_pool *pool;
618 uint16_t n_valid = sh->cmng.n_valid;
619 bool fallback = sh->cmng.counter_fallback;
621 for (i = 0; i < n_valid; ++i) {
622 pool = sh->cmng.pools[i];
623 if (!fallback && pool->min_dcs)
624 claim_zero(mlx5_devx_cmd_destroy
626 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
627 struct mlx5_flow_counter *cnt =
628 MLX5_POOL_GET_CNT(pool, j);
632 (mlx5_flow_os_destroy_flow_action
634 if (fallback && MLX5_POOL_GET_CNT
635 (pool, j)->dcs_when_free)
636 claim_zero(mlx5_devx_cmd_destroy
637 (cnt->dcs_when_free));
641 mlx5_free(sh->cmng.pools);
643 mng = LIST_FIRST(&sh->cmng.mem_mngs);
645 mlx5_flow_destroy_counter_stat_mem_mng(mng);
646 mng = LIST_FIRST(&sh->cmng.mem_mngs);
648 memset(&sh->cmng, 0, sizeof(sh->cmng));
652 * Initialize the aso flow meters management structure.
655 * Pointer to mlx5_dev_ctx_shared object to free
658 mlx5_aso_flow_mtrs_mng_init(struct mlx5_dev_ctx_shared *sh)
661 sh->mtrmng = mlx5_malloc(MLX5_MEM_ZERO,
663 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
666 "meter management allocation was failed.");
670 if (sh->meter_aso_en) {
671 rte_spinlock_init(&sh->mtrmng->pools_mng.mtrsl);
672 rte_rwlock_init(&sh->mtrmng->pools_mng.resize_mtrwl);
673 LIST_INIT(&sh->mtrmng->pools_mng.meters);
675 sh->mtrmng->def_policy_id = MLX5_INVALID_POLICY_ID;
681 * Close and release all the resources of
682 * the ASO flow meter management structure.
685 * Pointer to mlx5_dev_ctx_shared object to free.
688 mlx5_aso_flow_mtrs_mng_close(struct mlx5_dev_ctx_shared *sh)
690 struct mlx5_aso_mtr_pool *mtr_pool;
691 struct mlx5_flow_mtr_mng *mtrmng = sh->mtrmng;
693 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
694 struct mlx5_aso_mtr *aso_mtr;
696 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
698 if (sh->meter_aso_en) {
699 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_POLICER);
700 idx = mtrmng->pools_mng.n_valid;
702 mtr_pool = mtrmng->pools_mng.pools[idx];
703 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
704 for (i = 0; i < MLX5_ASO_MTRS_PER_POOL; i++) {
705 aso_mtr = &mtr_pool->mtrs[i];
706 if (aso_mtr->fm.meter_action)
708 (mlx5_glue->destroy_flow_action
709 (aso_mtr->fm.meter_action));
711 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
712 claim_zero(mlx5_devx_cmd_destroy
713 (mtr_pool->devx_obj));
714 mtrmng->pools_mng.n_valid--;
717 mlx5_free(sh->mtrmng->pools_mng.pools);
719 mlx5_free(sh->mtrmng);
723 /* Send FLOW_AGED event if needed. */
725 mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh)
727 struct mlx5_age_info *age_info;
730 for (i = 0; i < sh->max_port; i++) {
731 age_info = &sh->port[i].age_info;
732 if (!MLX5_AGE_GET(age_info, MLX5_AGE_EVENT_NEW))
734 MLX5_AGE_UNSET(age_info, MLX5_AGE_EVENT_NEW);
735 if (MLX5_AGE_GET(age_info, MLX5_AGE_TRIGGER)) {
736 MLX5_AGE_UNSET(age_info, MLX5_AGE_TRIGGER);
737 rte_eth_dev_callback_process
738 (&rte_eth_devices[sh->port[i].devx_ih_port_id],
739 RTE_ETH_EVENT_FLOW_AGED, NULL);
745 * Initialize the ASO connection tracking structure.
748 * Pointer to mlx5_dev_ctx_shared object.
751 * 0 on success, a negative errno value otherwise and rte_errno is set.
754 mlx5_flow_aso_ct_mng_init(struct mlx5_dev_ctx_shared *sh)
760 sh->ct_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->ct_mng),
761 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
763 DRV_LOG(ERR, "ASO CT management allocation failed.");
767 err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_CONNECTION_TRACKING);
769 mlx5_free(sh->ct_mng);
770 /* rte_errno should be extracted from the failure. */
774 rte_spinlock_init(&sh->ct_mng->ct_sl);
775 rte_rwlock_init(&sh->ct_mng->resize_rwl);
776 LIST_INIT(&sh->ct_mng->free_cts);
781 * Close and release all the resources of the
782 * ASO connection tracking management structure.
785 * Pointer to mlx5_dev_ctx_shared object to free.
788 mlx5_flow_aso_ct_mng_close(struct mlx5_dev_ctx_shared *sh)
790 struct mlx5_aso_ct_pools_mng *mng = sh->ct_mng;
791 struct mlx5_aso_ct_pool *ct_pool;
792 struct mlx5_aso_ct_action *ct;
798 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_CONNECTION_TRACKING);
802 ct_pool = mng->pools[idx];
803 for (i = 0; i < MLX5_ASO_CT_ACTIONS_PER_POOL; i++) {
804 ct = &ct_pool->actions[i];
805 val = __atomic_fetch_sub(&ct->refcnt, 1,
807 MLX5_ASSERT(val == 1);
810 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
811 if (ct->dr_action_orig)
812 claim_zero(mlx5_glue->destroy_flow_action
813 (ct->dr_action_orig));
814 if (ct->dr_action_rply)
815 claim_zero(mlx5_glue->destroy_flow_action
816 (ct->dr_action_rply));
819 claim_zero(mlx5_devx_cmd_destroy(ct_pool->devx_obj));
821 DRV_LOG(DEBUG, "%u ASO CT objects are being used in the pool %u",
825 /* in case of failure. */
828 mlx5_free(mng->pools);
830 /* Management structure must be cleared to 0s during allocation. */
835 * Initialize the flow resources' indexed mempool.
838 * Pointer to mlx5_dev_ctx_shared object.
840 * Pointer to user dev config.
843 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
844 const struct mlx5_dev_config *config)
847 struct mlx5_indexed_pool_config cfg;
849 for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
850 cfg = mlx5_ipool_cfg[i];
855 * Set MLX5_IPOOL_MLX5_FLOW ipool size
856 * according to PCI function flow configuration.
858 case MLX5_IPOOL_MLX5_FLOW:
859 cfg.size = config->dv_flow_en ?
860 sizeof(struct mlx5_flow_handle) :
861 MLX5_FLOW_HANDLE_VERBS_SIZE;
864 if (config->reclaim_mode) {
865 cfg.release_mem_en = 1;
866 cfg.per_core_cache = 0;
868 cfg.release_mem_en = 0;
870 sh->ipool[i] = mlx5_ipool_create(&cfg);
876 * Release the flow resources' indexed mempool.
879 * Pointer to mlx5_dev_ctx_shared object.
882 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
886 for (i = 0; i < MLX5_IPOOL_MAX; ++i)
887 mlx5_ipool_destroy(sh->ipool[i]);
888 for (i = 0; i < MLX5_MAX_MODIFY_NUM; ++i)
889 if (sh->mdh_ipools[i])
890 mlx5_ipool_destroy(sh->mdh_ipools[i]);
894 * Check if dynamic flex parser for eCPRI already exists.
897 * Pointer to Ethernet device structure.
900 * true on exists, false on not.
903 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
905 struct mlx5_priv *priv = dev->data->dev_private;
906 struct mlx5_ecpri_parser_profile *prf = &priv->sh->ecpri_parser;
912 * Allocation of a flex parser for eCPRI. Once created, this parser related
913 * resources will be held until the device is closed.
916 * Pointer to Ethernet device structure.
919 * 0 on success, a negative errno value otherwise and rte_errno is set.
922 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
924 struct mlx5_priv *priv = dev->data->dev_private;
925 struct mlx5_ecpri_parser_profile *prf = &priv->sh->ecpri_parser;
926 struct mlx5_devx_graph_node_attr node = {
927 .modify_field_select = 0,
932 if (!priv->sh->cdev->config.hca_attr.parse_graph_flex_node) {
933 DRV_LOG(ERR, "Dynamic flex parser is not supported "
934 "for device %s.", priv->dev_data->name);
937 node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED;
938 /* 8 bytes now: 4B common header + 4B message body header. */
939 node.header_length_base_value = 0x8;
940 /* After MAC layer: Ether / VLAN. */
941 node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC;
942 /* Type of compared condition should be 0xAEFE in the L2 layer. */
943 node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI;
944 /* Sample #0: type in common header. */
945 node.sample[0].flow_match_sample_en = 1;
947 node.sample[0].flow_match_sample_offset_mode = 0x0;
948 /* Only the 2nd byte will be used. */
949 node.sample[0].flow_match_sample_field_base_offset = 0x0;
950 /* Sample #1: message payload. */
951 node.sample[1].flow_match_sample_en = 1;
953 node.sample[1].flow_match_sample_offset_mode = 0x0;
955 * Only the first two bytes will be used right now, and its offset will
956 * start after the common header that with the length of a DW(u32).
958 node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);
959 prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->cdev->ctx, &node);
961 DRV_LOG(ERR, "Failed to create flex parser node object.");
962 return (rte_errno == 0) ? -ENODEV : -rte_errno;
965 ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num);
967 DRV_LOG(ERR, "Failed to query sample IDs.");
968 return (rte_errno == 0) ? -ENODEV : -rte_errno;
970 prf->offset[0] = 0x0;
971 prf->offset[1] = sizeof(uint32_t);
972 prf->ids[0] = ids[0];
973 prf->ids[1] = ids[1];
978 * Destroy the flex parser node, including the parser itself, input / output
979 * arcs and DW samples. Resources could be reused then.
982 * Pointer to Ethernet device structure.
985 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
987 struct mlx5_priv *priv = dev->data->dev_private;
988 struct mlx5_ecpri_parser_profile *prf = &priv->sh->ecpri_parser;
991 mlx5_devx_cmd_destroy(prf->obj);
996 mlx5_get_supported_sw_parsing_offloads(const struct mlx5_hca_attr *attr)
998 uint32_t sw_parsing_offloads = 0;
1001 sw_parsing_offloads |= MLX5_SW_PARSING_CAP;
1003 sw_parsing_offloads |= MLX5_SW_PARSING_CSUM_CAP;
1006 sw_parsing_offloads |= MLX5_SW_PARSING_TSO_CAP;
1008 return sw_parsing_offloads;
1012 mlx5_get_supported_tunneling_offloads(const struct mlx5_hca_attr *attr)
1014 uint32_t tn_offloads = 0;
1016 if (attr->tunnel_stateless_vxlan)
1017 tn_offloads |= MLX5_TUNNELED_OFFLOADS_VXLAN_CAP;
1018 if (attr->tunnel_stateless_gre)
1019 tn_offloads |= MLX5_TUNNELED_OFFLOADS_GRE_CAP;
1020 if (attr->tunnel_stateless_geneve_rx)
1021 tn_offloads |= MLX5_TUNNELED_OFFLOADS_GENEVE_CAP;
1025 /* Fill all fields of UAR structure. */
1027 mlx5_rxtx_uars_prepare(struct mlx5_dev_ctx_shared *sh)
1031 ret = mlx5_devx_uar_prepare(sh->cdev, &sh->tx_uar);
1033 DRV_LOG(ERR, "Failed to prepare Tx DevX UAR.");
1036 MLX5_ASSERT(sh->tx_uar.obj);
1037 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->tx_uar.obj));
1038 ret = mlx5_devx_uar_prepare(sh->cdev, &sh->rx_uar);
1040 DRV_LOG(ERR, "Failed to prepare Rx DevX UAR.");
1041 mlx5_devx_uar_release(&sh->tx_uar);
1044 MLX5_ASSERT(sh->rx_uar.obj);
1045 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->rx_uar.obj));
1050 mlx5_rxtx_uars_release(struct mlx5_dev_ctx_shared *sh)
1052 mlx5_devx_uar_release(&sh->rx_uar);
1053 mlx5_devx_uar_release(&sh->tx_uar);
1057 * rte_mempool_walk() callback to unregister Rx mempools.
1058 * It used when implicit mempool registration is disabled.
1061 * The mempool being walked.
1063 * Pointer to the device shared context.
1066 mlx5_dev_ctx_shared_rx_mempool_unregister_cb(struct rte_mempool *mp, void *arg)
1068 struct mlx5_dev_ctx_shared *sh = arg;
1070 mlx5_dev_mempool_unregister(sh->cdev, mp);
1074 * Callback used when implicit mempool registration is disabled
1075 * in order to track Rx mempool destruction.
1078 * Mempool life cycle event.
1080 * An Rx mempool registered explicitly when the port is started.
1082 * Pointer to a device shared context.
1085 mlx5_dev_ctx_shared_rx_mempool_event_cb(enum rte_mempool_event event,
1086 struct rte_mempool *mp, void *arg)
1088 struct mlx5_dev_ctx_shared *sh = arg;
1090 if (event == RTE_MEMPOOL_EVENT_DESTROY)
1091 mlx5_dev_mempool_unregister(sh->cdev, mp);
1095 mlx5_dev_ctx_shared_mempool_subscribe(struct rte_eth_dev *dev)
1097 struct mlx5_priv *priv = dev->data->dev_private;
1098 struct mlx5_dev_ctx_shared *sh = priv->sh;
1101 /* Check if we only need to track Rx mempool destruction. */
1102 if (!sh->cdev->config.mr_mempool_reg_en) {
1103 ret = rte_mempool_event_callback_register
1104 (mlx5_dev_ctx_shared_rx_mempool_event_cb, sh);
1105 return ret == 0 || rte_errno == EEXIST ? 0 : ret;
1107 return mlx5_dev_mempool_subscribe(sh->cdev);
1111 * Set up multiple TISs with different affinities according to
1112 * number of bonding ports
1115 * Pointer of shared context.
1118 * Zero on success, -1 otherwise.
1121 mlx5_setup_tis(struct mlx5_dev_ctx_shared *sh)
1124 struct mlx5_devx_lag_context lag_ctx = { 0 };
1125 struct mlx5_devx_tis_attr tis_attr = { 0 };
1127 tis_attr.transport_domain = sh->td->id;
1128 if (sh->bond.n_port) {
1129 if (!mlx5_devx_cmd_query_lag(sh->cdev->ctx, &lag_ctx)) {
1130 sh->lag.tx_remap_affinity[0] =
1131 lag_ctx.tx_remap_affinity_1;
1132 sh->lag.tx_remap_affinity[1] =
1133 lag_ctx.tx_remap_affinity_2;
1134 sh->lag.affinity_mode = lag_ctx.port_select_mode;
1136 DRV_LOG(ERR, "Failed to query lag affinity.");
1139 if (sh->lag.affinity_mode == MLX5_LAG_MODE_TIS) {
1140 for (i = 0; i < sh->bond.n_port; i++) {
1141 tis_attr.lag_tx_port_affinity =
1142 MLX5_IFC_LAG_MAP_TIS_AFFINITY(i,
1144 sh->tis[i] = mlx5_devx_cmd_create_tis(sh->cdev->ctx,
1147 DRV_LOG(ERR, "Failed to TIS %d/%d for bonding device"
1148 " %s.", i, sh->bond.n_port,
1153 DRV_LOG(DEBUG, "LAG number of ports : %d, affinity_1 & 2 : pf%d & %d.\n",
1154 sh->bond.n_port, lag_ctx.tx_remap_affinity_1,
1155 lag_ctx.tx_remap_affinity_2);
1158 if (sh->lag.affinity_mode == MLX5_LAG_MODE_HASH)
1159 DRV_LOG(INFO, "Device %s enabled HW hash based LAG.",
1162 tis_attr.lag_tx_port_affinity = 0;
1163 sh->tis[0] = mlx5_devx_cmd_create_tis(sh->cdev->ctx, &tis_attr);
1165 DRV_LOG(ERR, "Failed to TIS 0 for bonding device"
1166 " %s.", sh->ibdev_name);
1173 * Configure realtime timestamp format.
1176 * Pointer to mlx5_dev_ctx_shared object.
1178 * Device configuration parameters.
1180 * Pointer to DevX HCA capabilities structure.
1183 mlx5_rt_timestamp_config(struct mlx5_dev_ctx_shared *sh,
1184 struct mlx5_dev_config *config,
1185 struct mlx5_hca_attr *hca_attr)
1187 uint32_t dw_cnt = MLX5_ST_SZ_DW(register_mtutc);
1188 uint32_t reg[dw_cnt];
1191 if (hca_attr->access_register_user)
1192 ret = mlx5_devx_cmd_register_read(sh->cdev->ctx,
1193 MLX5_REGISTER_ID_MTUTC, 0,
1198 /* MTUTC register is read successfully. */
1199 ts_mode = MLX5_GET(register_mtutc, reg, time_stamp_mode);
1200 if (ts_mode == MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME)
1201 config->rt_timestamp = 1;
1203 /* Kernel does not support register reading. */
1204 if (hca_attr->dev_freq_khz == (NS_PER_S / MS_PER_S))
1205 config->rt_timestamp = 1;
1210 * Allocate shared device context. If there is multiport device the
1211 * master and representors will share this context, if there is single
1212 * port dedicated device, the context will be used by only given
1213 * port due to unification.
1215 * Routine first searches the context for the specified device name,
1216 * if found the shared context assumed and reference counter is incremented.
1217 * If no context found the new one is created and initialized with specified
1218 * device context and parameters.
1221 * Pointer to the device attributes (name, port, etc).
1223 * Pointer to device configuration structure.
1226 * Pointer to mlx5_dev_ctx_shared object on success,
1227 * otherwise NULL and rte_errno is set.
1229 struct mlx5_dev_ctx_shared *
1230 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
1231 const struct mlx5_dev_config *config)
1233 struct mlx5_dev_ctx_shared *sh;
1238 /* Secondary process should not create the shared context. */
1239 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1240 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1241 /* Search for IB context by device name. */
1242 LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
1243 if (!strcmp(sh->ibdev_name, spawn->phys_dev_name)) {
1248 /* No device found, we have to create new shared context. */
1249 MLX5_ASSERT(spawn->max_port);
1250 sh = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
1251 sizeof(struct mlx5_dev_ctx_shared) +
1252 spawn->max_port * sizeof(struct mlx5_dev_shared_port),
1253 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
1255 DRV_LOG(ERR, "Shared context allocation failure.");
1259 pthread_mutex_init(&sh->txpp.mutex, NULL);
1260 sh->numa_node = spawn->cdev->dev->numa_node;
1261 sh->cdev = spawn->cdev;
1262 sh->esw_mode = !!(spawn->info.master || spawn->info.representor);
1263 if (spawn->bond_info)
1264 sh->bond = *spawn->bond_info;
1265 err = mlx5_os_get_dev_attr(sh->cdev, &sh->device_attr);
1267 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
1271 sh->max_port = spawn->max_port;
1272 sh->reclaim_mode = config->reclaim_mode;
1273 strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->cdev->ctx),
1274 sizeof(sh->ibdev_name) - 1);
1275 strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->cdev->ctx),
1276 sizeof(sh->ibdev_path) - 1);
1278 * Setting port_id to max unallowed value means there is no interrupt
1279 * subhandler installed for the given port index i.
1281 for (i = 0; i < sh->max_port; i++) {
1282 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
1283 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
1285 if (sh->cdev->config.devx) {
1286 sh->td = mlx5_devx_cmd_create_td(sh->cdev->ctx);
1288 DRV_LOG(ERR, "TD allocation failure");
1292 if (mlx5_setup_tis(sh)) {
1293 DRV_LOG(ERR, "TIS allocation failure");
1297 err = mlx5_rxtx_uars_prepare(sh);
1302 /* Initialize UAR access locks for 32bit implementations. */
1303 rte_spinlock_init(&sh->uar_lock_cq);
1304 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
1305 rte_spinlock_init(&sh->uar_lock[i]);
1308 mlx5_os_dev_shared_handler_install(sh);
1309 if (LIST_EMPTY(&mlx5_dev_ctx_list)) {
1310 err = mlx5_flow_os_init_workspace_once();
1314 mlx5_flow_aging_init(sh);
1315 mlx5_flow_counters_mng_init(sh);
1316 mlx5_flow_ipool_create(sh, config);
1317 /* Add context to the global device list. */
1318 LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
1319 rte_spinlock_init(&sh->geneve_tlv_opt_sl);
1321 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1325 pthread_mutex_destroy(&sh->txpp.mutex);
1326 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1328 mlx5_rxtx_uars_release(sh);
1332 claim_zero(mlx5_devx_cmd_destroy(sh->tis[i]));
1333 } while (++i < (uint32_t)sh->bond.n_port);
1335 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1342 * Free shared IB device context. Decrement counter and if zero free
1343 * all allocated resources and close handles.
1346 * Pointer to mlx5_dev_ctx_shared object to free
1349 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
1354 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1355 #ifdef RTE_LIBRTE_MLX5_DEBUG
1356 /* Check the object presence in the list. */
1357 struct mlx5_dev_ctx_shared *lctx;
1359 LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
1364 DRV_LOG(ERR, "Freeing non-existing shared IB context");
1369 MLX5_ASSERT(sh->refcnt);
1370 /* Secondary process should not free the shared context. */
1371 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1374 /* Stop watching for mempool events and unregister all mempools. */
1375 if (!sh->cdev->config.mr_mempool_reg_en) {
1376 ret = rte_mempool_event_callback_unregister
1377 (mlx5_dev_ctx_shared_rx_mempool_event_cb, sh);
1380 (mlx5_dev_ctx_shared_rx_mempool_unregister_cb, sh);
1382 /* Remove context from the global device list. */
1383 LIST_REMOVE(sh, next);
1384 /* Release resources on the last device removal. */
1385 if (LIST_EMPTY(&mlx5_dev_ctx_list)) {
1386 mlx5_os_net_cleanup();
1387 mlx5_flow_os_release_workspace();
1389 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1390 if (sh->flex_parsers_dv) {
1391 mlx5_list_destroy(sh->flex_parsers_dv);
1392 sh->flex_parsers_dv = NULL;
1395 * Ensure there is no async event handler installed.
1396 * Only primary process handles async device events.
1398 mlx5_flow_counters_mng_close(sh);
1400 mlx5_flow_aso_ct_mng_close(sh);
1401 if (sh->aso_age_mng) {
1402 mlx5_flow_aso_age_mng_close(sh);
1403 sh->aso_age_mng = NULL;
1406 mlx5_aso_flow_mtrs_mng_close(sh);
1407 mlx5_flow_ipool_destroy(sh);
1408 mlx5_os_dev_shared_handler_uninstall(sh);
1409 mlx5_rxtx_uars_release(sh);
1412 claim_zero(mlx5_devx_cmd_destroy(sh->tis[i]));
1413 } while (++i < sh->bond.n_port);
1415 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1416 MLX5_ASSERT(sh->geneve_tlv_option_resource == NULL);
1417 pthread_mutex_destroy(&sh->txpp.mutex);
1421 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1425 * Destroy table hash list.
1428 * Pointer to the private device data structure.
1431 mlx5_free_table_hash_list(struct mlx5_priv *priv)
1433 struct mlx5_dev_ctx_shared *sh = priv->sh;
1437 mlx5_hlist_destroy(sh->flow_tbls);
1438 sh->flow_tbls = NULL;
1442 * Initialize flow table hash list and create the root tables entry
1446 * Pointer to the private device data structure.
1449 * Zero on success, positive error code otherwise.
1452 mlx5_alloc_table_hash_list(struct mlx5_priv *priv __rte_unused)
1455 /* Tables are only used in DV and DR modes. */
1456 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
1457 struct mlx5_dev_ctx_shared *sh = priv->sh;
1458 char s[MLX5_NAME_SIZE];
1461 snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1462 sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE,
1464 flow_dv_tbl_create_cb,
1465 flow_dv_tbl_match_cb,
1466 flow_dv_tbl_remove_cb,
1467 flow_dv_tbl_clone_cb,
1468 flow_dv_tbl_clone_free_cb);
1469 if (!sh->flow_tbls) {
1470 DRV_LOG(ERR, "flow tables with hash creation failed.");
1474 #ifndef HAVE_MLX5DV_DR
1475 struct rte_flow_error error;
1476 struct rte_eth_dev *dev = &rte_eth_devices[priv->dev_data->port_id];
1479 * In case we have not DR support, the zero tables should be created
1480 * because DV expect to see them even if they cannot be created by
1483 if (!flow_dv_tbl_resource_get(dev, 0, 0, 0, 0,
1484 NULL, 0, 1, 0, &error) ||
1485 !flow_dv_tbl_resource_get(dev, 0, 1, 0, 0,
1486 NULL, 0, 1, 0, &error) ||
1487 !flow_dv_tbl_resource_get(dev, 0, 0, 1, 0,
1488 NULL, 0, 1, 0, &error)) {
1494 mlx5_free_table_hash_list(priv);
1495 #endif /* HAVE_MLX5DV_DR */
1501 * Retrieve integer value from environment variable.
1504 * Environment variable name.
1507 * Integer value, 0 if the variable is not set.
1510 mlx5_getenv_int(const char *name)
1512 const char *val = getenv(name);
1520 * DPDK callback to add udp tunnel port
1523 * A pointer to eth_dev
1524 * @param[in] udp_tunnel
1525 * A pointer to udp tunnel
1528 * 0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1531 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1532 struct rte_eth_udp_tunnel *udp_tunnel)
1534 MLX5_ASSERT(udp_tunnel != NULL);
1535 if (udp_tunnel->prot_type == RTE_ETH_TUNNEL_TYPE_VXLAN &&
1536 udp_tunnel->udp_port == 4789)
1538 if (udp_tunnel->prot_type == RTE_ETH_TUNNEL_TYPE_VXLAN_GPE &&
1539 udp_tunnel->udp_port == 4790)
1545 * Initialize process private data structure.
1548 * Pointer to Ethernet device structure.
1551 * 0 on success, a negative errno value otherwise and rte_errno is set.
1554 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1556 struct mlx5_priv *priv = dev->data->dev_private;
1557 struct mlx5_proc_priv *ppriv;
1560 mlx5_proc_priv_uninit(dev);
1562 * UAR register table follows the process private structure. BlueFlame
1563 * registers for Tx queues are stored in the table.
1565 ppriv_size = sizeof(struct mlx5_proc_priv) +
1566 priv->txqs_n * sizeof(struct mlx5_uar_data);
1567 ppriv = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, ppriv_size,
1568 RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1573 ppriv->uar_table_sz = priv->txqs_n;
1574 dev->process_private = ppriv;
1575 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
1576 priv->sh->pppriv = ppriv;
1581 * Un-initialize process private data structure.
1584 * Pointer to Ethernet device structure.
1587 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1589 if (!dev->process_private)
1591 mlx5_free(dev->process_private);
1592 dev->process_private = NULL;
1596 * DPDK callback to close the device.
1598 * Destroy all queues and objects, free memory.
1601 * Pointer to Ethernet device structure.
1604 mlx5_dev_close(struct rte_eth_dev *dev)
1606 struct mlx5_priv *priv = dev->data->dev_private;
1610 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1611 /* Check if process_private released. */
1612 if (!dev->process_private)
1614 mlx5_tx_uar_uninit_secondary(dev);
1615 mlx5_proc_priv_uninit(dev);
1616 rte_eth_dev_release_port(dev);
1621 DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1623 ((priv->sh->cdev->ctx != NULL) ?
1624 mlx5_os_get_ctx_device_name(priv->sh->cdev->ctx) : ""));
1626 * If default mreg copy action is removed at the stop stage,
1627 * the search will return none and nothing will be done anymore.
1629 mlx5_flow_stop_default(dev);
1630 mlx5_traffic_disable(dev);
1632 * If all the flows are already flushed in the device stop stage,
1633 * then this will return directly without any action.
1635 mlx5_flow_list_flush(dev, MLX5_FLOW_TYPE_GEN, true);
1636 mlx5_action_handle_flush(dev);
1637 mlx5_flow_meter_flush(dev, NULL);
1638 /* Prevent crashes when queues are still in use. */
1639 dev->rx_pkt_burst = rte_eth_pkt_burst_dummy;
1640 dev->tx_pkt_burst = rte_eth_pkt_burst_dummy;
1642 /* Disable datapath on secondary process. */
1643 mlx5_mp_os_req_stop_rxtx(dev);
1644 /* Free the eCPRI flex parser resource. */
1645 mlx5_flex_parser_ecpri_release(dev);
1646 mlx5_flex_item_port_cleanup(dev);
1647 if (priv->rxq_privs != NULL) {
1648 /* XXX race condition if mlx5_rx_burst() is still running. */
1649 rte_delay_us_sleep(1000);
1650 for (i = 0; (i != priv->rxqs_n); ++i)
1651 mlx5_rxq_release(dev, i);
1653 mlx5_free(priv->rxq_privs);
1654 priv->rxq_privs = NULL;
1656 if (priv->txqs != NULL) {
1657 /* XXX race condition if mlx5_tx_burst() is still running. */
1658 rte_delay_us_sleep(1000);
1659 for (i = 0; (i != priv->txqs_n); ++i)
1660 mlx5_txq_release(dev, i);
1664 mlx5_proc_priv_uninit(dev);
1665 if (priv->q_counters) {
1666 mlx5_devx_cmd_destroy(priv->q_counters);
1667 priv->q_counters = NULL;
1669 if (priv->drop_queue.hrxq)
1670 mlx5_drop_action_destroy(dev);
1671 if (priv->mreg_cp_tbl)
1672 mlx5_hlist_destroy(priv->mreg_cp_tbl);
1673 mlx5_mprq_free_mp(dev);
1674 mlx5_os_free_shared_dr(priv);
1675 if (priv->rss_conf.rss_key != NULL)
1676 mlx5_free(priv->rss_conf.rss_key);
1677 if (priv->reta_idx != NULL)
1678 mlx5_free(priv->reta_idx);
1679 if (priv->config.vf)
1680 mlx5_os_mac_addr_flush(dev);
1681 if (priv->nl_socket_route >= 0)
1682 close(priv->nl_socket_route);
1683 if (priv->nl_socket_rdma >= 0)
1684 close(priv->nl_socket_rdma);
1685 if (priv->vmwa_context)
1686 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1687 ret = mlx5_hrxq_verify(dev);
1689 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1690 dev->data->port_id);
1691 ret = mlx5_ind_table_obj_verify(dev);
1693 DRV_LOG(WARNING, "port %u some indirection table still remain",
1694 dev->data->port_id);
1695 ret = mlx5_rxq_obj_verify(dev);
1697 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1698 dev->data->port_id);
1699 ret = mlx5_rxq_verify(dev);
1701 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1702 dev->data->port_id);
1703 ret = mlx5_txq_obj_verify(dev);
1705 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1706 dev->data->port_id);
1707 ret = mlx5_txq_verify(dev);
1709 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1710 dev->data->port_id);
1711 ret = mlx5_flow_verify(dev);
1713 DRV_LOG(WARNING, "port %u some flows still remain",
1714 dev->data->port_id);
1716 mlx5_list_destroy(priv->hrxqs);
1718 * Free the shared context in last turn, because the cleanup
1719 * routines above may use some shared fields, like
1720 * mlx5_os_mac_addr_flush() uses ibdev_path for retrieving
1721 * ifindex if Netlink fails.
1723 mlx5_free_shared_dev_ctx(priv->sh);
1724 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1728 MLX5_ETH_FOREACH_DEV(port_id, dev->device) {
1729 struct mlx5_priv *opriv =
1730 rte_eth_devices[port_id].data->dev_private;
1733 opriv->domain_id != priv->domain_id ||
1734 &rte_eth_devices[port_id] == dev)
1740 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1742 memset(priv, 0, sizeof(*priv));
1743 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1745 * Reset mac_addrs to NULL such that it is not freed as part of
1746 * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1747 * it is freed when dev_private is freed.
1749 dev->data->mac_addrs = NULL;
1753 const struct eth_dev_ops mlx5_dev_ops = {
1754 .dev_configure = mlx5_dev_configure,
1755 .dev_start = mlx5_dev_start,
1756 .dev_stop = mlx5_dev_stop,
1757 .dev_set_link_down = mlx5_set_link_down,
1758 .dev_set_link_up = mlx5_set_link_up,
1759 .dev_close = mlx5_dev_close,
1760 .promiscuous_enable = mlx5_promiscuous_enable,
1761 .promiscuous_disable = mlx5_promiscuous_disable,
1762 .allmulticast_enable = mlx5_allmulticast_enable,
1763 .allmulticast_disable = mlx5_allmulticast_disable,
1764 .link_update = mlx5_link_update,
1765 .stats_get = mlx5_stats_get,
1766 .stats_reset = mlx5_stats_reset,
1767 .xstats_get = mlx5_xstats_get,
1768 .xstats_reset = mlx5_xstats_reset,
1769 .xstats_get_names = mlx5_xstats_get_names,
1770 .fw_version_get = mlx5_fw_version_get,
1771 .dev_infos_get = mlx5_dev_infos_get,
1772 .representor_info_get = mlx5_representor_info_get,
1773 .read_clock = mlx5_txpp_read_clock,
1774 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1775 .vlan_filter_set = mlx5_vlan_filter_set,
1776 .rx_queue_setup = mlx5_rx_queue_setup,
1777 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1778 .tx_queue_setup = mlx5_tx_queue_setup,
1779 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1780 .rx_queue_release = mlx5_rx_queue_release,
1781 .tx_queue_release = mlx5_tx_queue_release,
1782 .rx_queue_start = mlx5_rx_queue_start,
1783 .rx_queue_stop = mlx5_rx_queue_stop,
1784 .tx_queue_start = mlx5_tx_queue_start,
1785 .tx_queue_stop = mlx5_tx_queue_stop,
1786 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1787 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1788 .mac_addr_remove = mlx5_mac_addr_remove,
1789 .mac_addr_add = mlx5_mac_addr_add,
1790 .mac_addr_set = mlx5_mac_addr_set,
1791 .set_mc_addr_list = mlx5_set_mc_addr_list,
1792 .mtu_set = mlx5_dev_set_mtu,
1793 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1794 .vlan_offload_set = mlx5_vlan_offload_set,
1795 .reta_update = mlx5_dev_rss_reta_update,
1796 .reta_query = mlx5_dev_rss_reta_query,
1797 .rss_hash_update = mlx5_rss_hash_update,
1798 .rss_hash_conf_get = mlx5_rss_hash_conf_get,
1799 .flow_ops_get = mlx5_flow_ops_get,
1800 .rxq_info_get = mlx5_rxq_info_get,
1801 .txq_info_get = mlx5_txq_info_get,
1802 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1803 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1804 .rx_queue_intr_enable = mlx5_rx_intr_enable,
1805 .rx_queue_intr_disable = mlx5_rx_intr_disable,
1806 .is_removed = mlx5_is_removed,
1807 .udp_tunnel_port_add = mlx5_udp_tunnel_port_add,
1808 .get_module_info = mlx5_get_module_info,
1809 .get_module_eeprom = mlx5_get_module_eeprom,
1810 .hairpin_cap_get = mlx5_hairpin_cap_get,
1811 .mtr_ops_get = mlx5_flow_meter_ops_get,
1812 .hairpin_bind = mlx5_hairpin_bind,
1813 .hairpin_unbind = mlx5_hairpin_unbind,
1814 .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1815 .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1816 .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1817 .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1818 .get_monitor_addr = mlx5_get_monitor_addr,
1821 /* Available operations from secondary process. */
1822 const struct eth_dev_ops mlx5_dev_sec_ops = {
1823 .stats_get = mlx5_stats_get,
1824 .stats_reset = mlx5_stats_reset,
1825 .xstats_get = mlx5_xstats_get,
1826 .xstats_reset = mlx5_xstats_reset,
1827 .xstats_get_names = mlx5_xstats_get_names,
1828 .fw_version_get = mlx5_fw_version_get,
1829 .dev_infos_get = mlx5_dev_infos_get,
1830 .representor_info_get = mlx5_representor_info_get,
1831 .read_clock = mlx5_txpp_read_clock,
1832 .rx_queue_start = mlx5_rx_queue_start,
1833 .rx_queue_stop = mlx5_rx_queue_stop,
1834 .tx_queue_start = mlx5_tx_queue_start,
1835 .tx_queue_stop = mlx5_tx_queue_stop,
1836 .rxq_info_get = mlx5_rxq_info_get,
1837 .txq_info_get = mlx5_txq_info_get,
1838 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1839 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1840 .get_module_info = mlx5_get_module_info,
1841 .get_module_eeprom = mlx5_get_module_eeprom,
1844 /* Available operations in flow isolated mode. */
1845 const struct eth_dev_ops mlx5_dev_ops_isolate = {
1846 .dev_configure = mlx5_dev_configure,
1847 .dev_start = mlx5_dev_start,
1848 .dev_stop = mlx5_dev_stop,
1849 .dev_set_link_down = mlx5_set_link_down,
1850 .dev_set_link_up = mlx5_set_link_up,
1851 .dev_close = mlx5_dev_close,
1852 .promiscuous_enable = mlx5_promiscuous_enable,
1853 .promiscuous_disable = mlx5_promiscuous_disable,
1854 .allmulticast_enable = mlx5_allmulticast_enable,
1855 .allmulticast_disable = mlx5_allmulticast_disable,
1856 .link_update = mlx5_link_update,
1857 .stats_get = mlx5_stats_get,
1858 .stats_reset = mlx5_stats_reset,
1859 .xstats_get = mlx5_xstats_get,
1860 .xstats_reset = mlx5_xstats_reset,
1861 .xstats_get_names = mlx5_xstats_get_names,
1862 .fw_version_get = mlx5_fw_version_get,
1863 .dev_infos_get = mlx5_dev_infos_get,
1864 .representor_info_get = mlx5_representor_info_get,
1865 .read_clock = mlx5_txpp_read_clock,
1866 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1867 .vlan_filter_set = mlx5_vlan_filter_set,
1868 .rx_queue_setup = mlx5_rx_queue_setup,
1869 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1870 .tx_queue_setup = mlx5_tx_queue_setup,
1871 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1872 .rx_queue_release = mlx5_rx_queue_release,
1873 .tx_queue_release = mlx5_tx_queue_release,
1874 .rx_queue_start = mlx5_rx_queue_start,
1875 .rx_queue_stop = mlx5_rx_queue_stop,
1876 .tx_queue_start = mlx5_tx_queue_start,
1877 .tx_queue_stop = mlx5_tx_queue_stop,
1878 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1879 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1880 .mac_addr_remove = mlx5_mac_addr_remove,
1881 .mac_addr_add = mlx5_mac_addr_add,
1882 .mac_addr_set = mlx5_mac_addr_set,
1883 .set_mc_addr_list = mlx5_set_mc_addr_list,
1884 .mtu_set = mlx5_dev_set_mtu,
1885 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1886 .vlan_offload_set = mlx5_vlan_offload_set,
1887 .flow_ops_get = mlx5_flow_ops_get,
1888 .rxq_info_get = mlx5_rxq_info_get,
1889 .txq_info_get = mlx5_txq_info_get,
1890 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1891 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1892 .rx_queue_intr_enable = mlx5_rx_intr_enable,
1893 .rx_queue_intr_disable = mlx5_rx_intr_disable,
1894 .is_removed = mlx5_is_removed,
1895 .get_module_info = mlx5_get_module_info,
1896 .get_module_eeprom = mlx5_get_module_eeprom,
1897 .hairpin_cap_get = mlx5_hairpin_cap_get,
1898 .mtr_ops_get = mlx5_flow_meter_ops_get,
1899 .hairpin_bind = mlx5_hairpin_bind,
1900 .hairpin_unbind = mlx5_hairpin_unbind,
1901 .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1902 .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1903 .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1904 .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1905 .get_monitor_addr = mlx5_get_monitor_addr,
1909 * Verify and store value for device argument.
1912 * Key argument to verify.
1914 * Value associated with key.
1919 * 0 on success, a negative errno value otherwise and rte_errno is set.
1922 mlx5_args_check(const char *key, const char *val, void *opaque)
1924 struct mlx5_dev_config *config = opaque;
1928 /* No-op, port representors are processed in mlx5_dev_spawn(). */
1929 if (!strcmp(MLX5_DRIVER_KEY, key) || !strcmp(MLX5_REPRESENTOR, key) ||
1930 !strcmp(MLX5_SYS_MEM_EN, key) || !strcmp(MLX5_TX_DB_NC, key) ||
1931 !strcmp(MLX5_MR_MEMPOOL_REG_EN, key) ||
1932 !strcmp(MLX5_MR_EXT_MEMSEG_EN, key))
1935 tmp = strtol(val, NULL, 0);
1938 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1941 if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
1942 /* Negative values are acceptable for some keys only. */
1944 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
1947 mod = tmp >= 0 ? tmp : -tmp;
1948 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1949 if (tmp > MLX5_CQE_RESP_FORMAT_L34H_STRIDX) {
1950 DRV_LOG(ERR, "invalid CQE compression "
1951 "format parameter");
1955 config->cqe_comp = !!tmp;
1956 config->cqe_comp_fmt = tmp;
1957 } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1958 config->hw_padding = !!tmp;
1959 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1960 config->mprq.enabled = !!tmp;
1961 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1962 config->mprq.log_stride_num = tmp;
1963 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1964 config->mprq.log_stride_size = tmp;
1965 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1966 config->mprq.max_memcpy_len = tmp;
1967 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1968 config->mprq.min_rxqs_num = tmp;
1969 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1970 DRV_LOG(WARNING, "%s: deprecated parameter,"
1971 " converted to txq_inline_max", key);
1972 config->txq_inline_max = tmp;
1973 } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1974 config->txq_inline_max = tmp;
1975 } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1976 config->txq_inline_min = tmp;
1977 } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1978 config->txq_inline_mpw = tmp;
1979 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1980 config->txqs_inline = tmp;
1981 } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1982 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1983 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1984 config->mps = !!tmp;
1985 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1986 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1987 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1988 DRV_LOG(WARNING, "%s: deprecated parameter,"
1989 " converted to txq_inline_mpw", key);
1990 config->txq_inline_mpw = tmp;
1991 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1992 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1993 } else if (strcmp(MLX5_TX_PP, key) == 0) {
1995 DRV_LOG(ERR, "Zero Tx packet pacing parameter");
1999 config->tx_pp = tmp;
2000 } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
2001 config->tx_skew = tmp;
2002 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
2003 config->rx_vec_en = !!tmp;
2004 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
2005 config->l3_vxlan_en = !!tmp;
2006 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
2007 config->vf_nl_en = !!tmp;
2008 } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
2009 config->dv_esw_en = !!tmp;
2010 } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
2011 config->dv_flow_en = !!tmp;
2012 } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
2013 if (tmp != MLX5_XMETA_MODE_LEGACY &&
2014 tmp != MLX5_XMETA_MODE_META16 &&
2015 tmp != MLX5_XMETA_MODE_META32 &&
2016 tmp != MLX5_XMETA_MODE_MISS_INFO) {
2017 DRV_LOG(ERR, "invalid extensive "
2018 "metadata parameter");
2022 if (tmp != MLX5_XMETA_MODE_MISS_INFO)
2023 config->dv_xmeta_en = tmp;
2025 config->dv_miss_info = 1;
2026 } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
2027 config->lacp_by_user = !!tmp;
2028 } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
2029 config->max_dump_files_num = tmp;
2030 } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
2031 config->lro.timeout = tmp;
2032 } else if (strcmp(RTE_DEVARGS_KEY_CLASS, key) == 0) {
2033 DRV_LOG(DEBUG, "class argument is %s.", val);
2034 } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
2035 config->log_hp_size = tmp;
2036 } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
2037 if (tmp != MLX5_RCM_NONE &&
2038 tmp != MLX5_RCM_LIGHT &&
2039 tmp != MLX5_RCM_AGGR) {
2040 DRV_LOG(ERR, "Unrecognized %s: \"%s\"", key, val);
2044 config->reclaim_mode = tmp;
2045 } else if (strcmp(MLX5_DECAP_EN, key) == 0) {
2046 config->decap_en = !!tmp;
2047 } else if (strcmp(MLX5_ALLOW_DUPLICATE_PATTERN, key) == 0) {
2048 config->allow_duplicate_pattern = !!tmp;
2049 } else if (strcmp(MLX5_DELAY_DROP, key) == 0) {
2050 config->std_delay_drop = !!(tmp & MLX5_DELAY_DROP_STANDARD);
2051 config->hp_delay_drop = !!(tmp & MLX5_DELAY_DROP_HAIRPIN);
2054 "%s: unknown parameter, maybe it's for another class.",
2061 * Parse device parameters.
2064 * Pointer to device configuration structure.
2066 * Device arguments structure.
2069 * 0 on success, a negative errno value otherwise and rte_errno is set.
2072 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
2074 struct rte_kvargs *kvlist;
2077 if (devargs == NULL)
2079 /* Following UGLY cast is done to pass checkpatch. */
2080 kvlist = rte_kvargs_parse(devargs->args, NULL);
2081 if (kvlist == NULL) {
2085 /* Process parameters. */
2086 ret = rte_kvargs_process(kvlist, NULL, mlx5_args_check, config);
2091 rte_kvargs_free(kvlist);
2096 * Configures the minimal amount of data to inline into WQE
2097 * while sending packets.
2099 * - the txq_inline_min has the maximal priority, if this
2100 * key is specified in devargs
2101 * - if DevX is enabled the inline mode is queried from the
2102 * device (HCA attributes and NIC vport context if needed).
2103 * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
2104 * and none (0 bytes) for other NICs
2107 * Verbs device parameters (name, port, switch_info) to spawn.
2109 * Device configuration parameters.
2112 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
2113 struct mlx5_dev_config *config)
2115 struct mlx5_hca_attr *hca_attr = &spawn->cdev->config.hca_attr;
2117 if (config->txq_inline_min != MLX5_ARG_UNSET) {
2118 /* Application defines size of inlined data explicitly. */
2119 if (spawn->pci_dev != NULL) {
2120 switch (spawn->pci_dev->id.device_id) {
2121 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2122 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2123 if (config->txq_inline_min <
2124 (int)MLX5_INLINE_HSIZE_L2) {
2126 "txq_inline_mix aligned to minimal ConnectX-4 required value %d",
2127 (int)MLX5_INLINE_HSIZE_L2);
2128 config->txq_inline_min =
2129 MLX5_INLINE_HSIZE_L2;
2136 if (hca_attr->eth_net_offloads) {
2137 /* We have DevX enabled, inline mode queried successfully. */
2138 switch (hca_attr->wqe_inline_mode) {
2139 case MLX5_CAP_INLINE_MODE_L2:
2140 /* outer L2 header must be inlined. */
2141 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2143 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
2144 /* No inline data are required by NIC. */
2145 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2146 config->hw_vlan_insert =
2147 hca_attr->wqe_vlan_insert;
2148 DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
2150 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
2151 /* inline mode is defined by NIC vport context. */
2152 if (!hca_attr->eth_virt)
2154 switch (hca_attr->vport_inline_mode) {
2155 case MLX5_INLINE_MODE_NONE:
2156 config->txq_inline_min =
2157 MLX5_INLINE_HSIZE_NONE;
2159 case MLX5_INLINE_MODE_L2:
2160 config->txq_inline_min =
2161 MLX5_INLINE_HSIZE_L2;
2163 case MLX5_INLINE_MODE_IP:
2164 config->txq_inline_min =
2165 MLX5_INLINE_HSIZE_L3;
2167 case MLX5_INLINE_MODE_TCP_UDP:
2168 config->txq_inline_min =
2169 MLX5_INLINE_HSIZE_L4;
2171 case MLX5_INLINE_MODE_INNER_L2:
2172 config->txq_inline_min =
2173 MLX5_INLINE_HSIZE_INNER_L2;
2175 case MLX5_INLINE_MODE_INNER_IP:
2176 config->txq_inline_min =
2177 MLX5_INLINE_HSIZE_INNER_L3;
2179 case MLX5_INLINE_MODE_INNER_TCP_UDP:
2180 config->txq_inline_min =
2181 MLX5_INLINE_HSIZE_INNER_L4;
2186 if (spawn->pci_dev == NULL) {
2187 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2191 * We get here if we are unable to deduce
2192 * inline data size with DevX. Try PCI ID
2193 * to determine old NICs.
2195 switch (spawn->pci_dev->id.device_id) {
2196 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2197 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2198 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
2199 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
2200 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2201 config->hw_vlan_insert = 0;
2203 case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
2204 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
2205 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
2206 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
2208 * These NICs support VLAN insertion from WQE and
2209 * report the wqe_vlan_insert flag. But there is the bug
2210 * and PFC control may be broken, so disable feature.
2212 config->hw_vlan_insert = 0;
2213 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2216 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2220 DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
2224 * Configures the metadata mask fields in the shared context.
2227 * Pointer to Ethernet device.
2230 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
2232 struct mlx5_priv *priv = dev->data->dev_private;
2233 struct mlx5_dev_ctx_shared *sh = priv->sh;
2234 uint32_t meta, mark, reg_c0;
2236 reg_c0 = ~priv->vport_meta_mask;
2237 switch (priv->config.dv_xmeta_en) {
2238 case MLX5_XMETA_MODE_LEGACY:
2240 mark = MLX5_FLOW_MARK_MASK;
2242 case MLX5_XMETA_MODE_META16:
2243 meta = reg_c0 >> rte_bsf32(reg_c0);
2244 mark = MLX5_FLOW_MARK_MASK;
2246 case MLX5_XMETA_MODE_META32:
2248 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
2256 if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
2257 DRV_LOG(WARNING, "metadata MARK mask mismatch %08X:%08X",
2258 sh->dv_mark_mask, mark);
2260 sh->dv_mark_mask = mark;
2261 if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
2262 DRV_LOG(WARNING, "metadata META mask mismatch %08X:%08X",
2263 sh->dv_meta_mask, meta);
2265 sh->dv_meta_mask = meta;
2266 if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
2267 DRV_LOG(WARNING, "metadata reg_c0 mask mismatch %08X:%08X",
2268 sh->dv_meta_mask, reg_c0);
2270 sh->dv_regc0_mask = reg_c0;
2271 DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
2272 DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
2273 DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
2274 DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
2278 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
2280 static const char *const dynf_names[] = {
2281 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
2282 RTE_MBUF_DYNFLAG_METADATA_NAME,
2283 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
2287 if (n < RTE_DIM(dynf_names))
2289 for (i = 0; i < RTE_DIM(dynf_names); i++) {
2290 if (names[i] == NULL)
2292 strcpy(names[i], dynf_names[i]);
2294 return RTE_DIM(dynf_names);
2298 * Check sibling device configurations.
2300 * Sibling devices sharing the Infiniband device context should have compatible
2301 * configurations. This regards representors and bonding device.
2304 * Shared device context.
2306 * Configuration of the device is going to be created.
2308 * Backing DPDK device.
2311 * 0 on success, EINVAL otherwise
2314 mlx5_dev_check_sibling_config(struct mlx5_dev_ctx_shared *sh,
2315 struct mlx5_dev_config *config,
2316 struct rte_device *dpdk_dev)
2318 struct mlx5_dev_config *sh_conf = NULL;
2322 /* Nothing to compare for the single/first device. */
2323 if (sh->refcnt == 1)
2325 /* Find the device with shared context. */
2326 MLX5_ETH_FOREACH_DEV(port_id, dpdk_dev) {
2327 struct mlx5_priv *opriv =
2328 rte_eth_devices[port_id].data->dev_private;
2330 if (opriv && opriv->sh == sh) {
2331 sh_conf = &opriv->config;
2337 if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
2338 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
2339 " for shared %s context", sh->ibdev_name);
2343 if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
2344 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
2345 " for shared %s context", sh->ibdev_name);
2353 * Look for the ethernet device belonging to mlx5 driver.
2355 * @param[in] port_id
2356 * port_id to start looking for device.
2358 * Pointer to the hint device. When device is being probed
2359 * the its siblings (master and preceding representors might
2360 * not have assigned driver yet (because the mlx5_os_pci_probe()
2361 * is not completed yet, for this case match on hint
2362 * device may be used to detect sibling device.
2365 * port_id of found device, RTE_MAX_ETHPORT if not found.
2368 mlx5_eth_find_next(uint16_t port_id, struct rte_device *odev)
2370 while (port_id < RTE_MAX_ETHPORTS) {
2371 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
2373 if (dev->state != RTE_ETH_DEV_UNUSED &&
2375 (dev->device == odev ||
2376 (dev->device->driver &&
2377 dev->device->driver->name &&
2378 ((strcmp(dev->device->driver->name,
2379 MLX5_PCI_DRIVER_NAME) == 0) ||
2380 (strcmp(dev->device->driver->name,
2381 MLX5_AUXILIARY_DRIVER_NAME) == 0)))))
2385 if (port_id >= RTE_MAX_ETHPORTS)
2386 return RTE_MAX_ETHPORTS;
2391 * Callback to remove a device.
2393 * This function removes all Ethernet devices belong to a given device.
2396 * Pointer to the generic device.
2399 * 0 on success, the function cannot fail.
2402 mlx5_net_remove(struct mlx5_common_device *cdev)
2407 RTE_ETH_FOREACH_DEV_OF(port_id, cdev->dev) {
2409 * mlx5_dev_close() is not registered to secondary process,
2410 * call the close function explicitly for secondary process.
2412 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
2413 ret |= mlx5_dev_close(&rte_eth_devices[port_id]);
2415 ret |= rte_eth_dev_close(port_id);
2417 return ret == 0 ? 0 : -EIO;
2420 static const struct rte_pci_id mlx5_pci_id_map[] = {
2422 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2423 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
2426 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2427 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
2430 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2431 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
2434 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2435 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
2438 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2439 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
2442 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2443 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
2446 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2447 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
2450 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2451 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
2454 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2455 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
2458 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2459 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
2462 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2463 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
2466 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2467 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
2470 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2471 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
2474 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2475 PCI_DEVICE_ID_MELLANOX_CONNECTXVF)
2478 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2479 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
2482 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2483 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
2486 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2487 PCI_DEVICE_ID_MELLANOX_CONNECTX7)
2490 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2491 PCI_DEVICE_ID_MELLANOX_CONNECTX7BF)
2498 static struct mlx5_class_driver mlx5_net_driver = {
2499 .drv_class = MLX5_CLASS_ETH,
2500 .name = RTE_STR(MLX5_ETH_DRIVER_NAME),
2501 .id_table = mlx5_pci_id_map,
2502 .probe = mlx5_os_net_probe,
2503 .remove = mlx5_net_remove,
2509 /* Initialize driver log type. */
2510 RTE_LOG_REGISTER_DEFAULT(mlx5_logtype, NOTICE)
2513 * Driver initialization routine.
2515 RTE_INIT(rte_mlx5_pmd_init)
2517 pthread_mutex_init(&mlx5_dev_ctx_list_mutex, NULL);
2519 /* Build the static tables for Verbs conversion. */
2520 mlx5_set_ptype_table();
2521 mlx5_set_cksum_table();
2522 mlx5_set_swp_types_table();
2524 mlx5_class_driver_register(&mlx5_net_driver);
2527 RTE_PMD_EXPORT_NAME(MLX5_ETH_DRIVER_NAME, __COUNTER__);
2528 RTE_PMD_REGISTER_PCI_TABLE(MLX5_ETH_DRIVER_NAME, mlx5_pci_id_map);
2529 RTE_PMD_REGISTER_KMOD_DEP(MLX5_ETH_DRIVER_NAME, "* ib_uverbs & mlx5_core & mlx5_ib");