1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
13 #include <rte_malloc.h>
14 #include <rte_ethdev_driver.h>
15 #include <rte_ethdev_pci.h>
17 #include <rte_bus_pci.h>
18 #include <rte_common.h>
19 #include <rte_kvargs.h>
20 #include <rte_rwlock.h>
21 #include <rte_spinlock.h>
22 #include <rte_string_fns.h>
23 #include <rte_alarm.h>
25 #include <mlx5_glue.h>
26 #include <mlx5_devx_cmds.h>
27 #include <mlx5_common.h>
28 #include <mlx5_common_os.h>
29 #include <mlx5_common_mp.h>
30 #include <mlx5_common_pci.h>
31 #include <mlx5_malloc.h>
33 #include "mlx5_defs.h"
35 #include "mlx5_utils.h"
36 #include "mlx5_rxtx.h"
37 #include "mlx5_autoconf.h"
39 #include "mlx5_flow.h"
40 #include "rte_pmd_mlx5.h"
42 /* Device parameter to enable RX completion queue compression. */
43 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
45 /* Device parameter to enable RX completion entry padding to 128B. */
46 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
48 /* Device parameter to enable padding Rx packet to cacheline size. */
49 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
51 /* Device parameter to enable Multi-Packet Rx queue. */
52 #define MLX5_RX_MPRQ_EN "mprq_en"
54 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
55 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
57 /* Device parameter to configure log 2 of the stride size for MPRQ. */
58 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
60 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
61 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
63 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
64 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
66 /* Device parameter to configure inline send. Deprecated, ignored.*/
67 #define MLX5_TXQ_INLINE "txq_inline"
69 /* Device parameter to limit packet size to inline with ordinary SEND. */
70 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
72 /* Device parameter to configure minimal data size to inline. */
73 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
75 /* Device parameter to limit packet size to inline with Enhanced MPW. */
76 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
79 * Device parameter to configure the number of TX queues threshold for
80 * enabling inline send.
82 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
85 * Device parameter to configure the number of TX queues threshold for
86 * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
88 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
90 /* Device parameter to enable multi-packet send WQEs. */
91 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
94 * Device parameter to force doorbell register mapping
95 * to non-cahed region eliminating the extra write memory barrier.
97 #define MLX5_TX_DB_NC "tx_db_nc"
100 * Device parameter to include 2 dsegs in the title WQEBB.
101 * Deprecated, ignored.
103 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
106 * Device parameter to limit the size of inlining packet.
107 * Deprecated, ignored.
109 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
112 * Device parameter to enable Tx scheduling on timestamps
113 * and specify the packet pacing granularity in nanoseconds.
115 #define MLX5_TX_PP "tx_pp"
118 * Device parameter to specify skew in nanoseconds on Tx datapath,
119 * it represents the time between SQ start WQE processing and
120 * appearing actual packet data on the wire.
122 #define MLX5_TX_SKEW "tx_skew"
125 * Device parameter to enable hardware Tx vector.
126 * Deprecated, ignored (no vectorized Tx routines anymore).
128 #define MLX5_TX_VEC_EN "tx_vec_en"
130 /* Device parameter to enable hardware Rx vector. */
131 #define MLX5_RX_VEC_EN "rx_vec_en"
133 /* Allow L3 VXLAN flow creation. */
134 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
136 /* Activate DV E-Switch flow steering. */
137 #define MLX5_DV_ESW_EN "dv_esw_en"
139 /* Activate DV flow steering. */
140 #define MLX5_DV_FLOW_EN "dv_flow_en"
142 /* Enable extensive flow metadata support. */
143 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
145 /* Device parameter to let the user manage the lacp traffic of bonded device */
146 #define MLX5_LACP_BY_USER "lacp_by_user"
148 /* Activate Netlink support in VF mode. */
149 #define MLX5_VF_NL_EN "vf_nl_en"
151 /* Enable extending memsegs when creating a MR. */
152 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
154 /* Select port representors to instantiate. */
155 #define MLX5_REPRESENTOR "representor"
157 /* Device parameter to configure the maximum number of dump files per queue. */
158 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
160 /* Configure timeout of LRO session (in microseconds). */
161 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
164 * Device parameter to configure the total data buffer size for a single
165 * hairpin queue (logarithm value).
167 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
169 /* Flow memory reclaim mode. */
170 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
172 /* The default memory allocator used in PMD. */
173 #define MLX5_SYS_MEM_EN "sys_mem_en"
174 /* Decap will be used or not. */
175 #define MLX5_DECAP_EN "decap_en"
177 /* Shared memory between primary and secondary processes. */
178 struct mlx5_shared_data *mlx5_shared_data;
180 /** Driver-specific log messages type. */
183 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
184 LIST_HEAD_INITIALIZER();
185 static pthread_mutex_t mlx5_dev_ctx_list_mutex = PTHREAD_MUTEX_INITIALIZER;
187 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
188 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
190 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
196 .malloc = mlx5_malloc,
198 .type = "mlx5_encap_decap_ipool",
201 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
207 .malloc = mlx5_malloc,
209 .type = "mlx5_push_vlan_ipool",
212 .size = sizeof(struct mlx5_flow_dv_tag_resource),
218 .malloc = mlx5_malloc,
220 .type = "mlx5_tag_ipool",
223 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
229 .malloc = mlx5_malloc,
231 .type = "mlx5_port_id_ipool",
234 .size = sizeof(struct mlx5_flow_tbl_data_entry),
240 .malloc = mlx5_malloc,
242 .type = "mlx5_jump_ipool",
245 .size = sizeof(struct mlx5_flow_dv_sample_resource),
251 .malloc = mlx5_malloc,
253 .type = "mlx5_sample_ipool",
256 .size = sizeof(struct mlx5_flow_dv_dest_array_resource),
262 .malloc = mlx5_malloc,
264 .type = "mlx5_dest_array_ipool",
268 .size = sizeof(struct mlx5_flow_meter),
274 .malloc = mlx5_malloc,
276 .type = "mlx5_meter_ipool",
279 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
285 .malloc = mlx5_malloc,
287 .type = "mlx5_mcp_ipool",
290 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
296 .malloc = mlx5_malloc,
298 .type = "mlx5_hrxq_ipool",
302 * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
303 * It set in run time according to PCI function configuration.
311 .malloc = mlx5_malloc,
313 .type = "mlx5_flow_handle_ipool",
316 .size = sizeof(struct rte_flow),
320 .malloc = mlx5_malloc,
322 .type = "rte_flow_ipool",
327 .type = "mlx5_flow_rss_id_ipool",
332 .type = "mlx5_flow_tnl_flow_ipool",
337 .type = "mlx5_flow_tnl_tbl_ipool",
342 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
343 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
345 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
348 * Initialize the shared aging list information per port.
351 * Pointer to mlx5_dev_ctx_shared object.
354 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
357 struct mlx5_age_info *age_info;
359 for (i = 0; i < sh->max_port; i++) {
360 age_info = &sh->port[i].age_info;
362 TAILQ_INIT(&age_info->aged_counters);
363 rte_spinlock_init(&age_info->aged_sl);
364 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
369 * Initialize the counters management structure.
372 * Pointer to mlx5_dev_ctx_shared object to free
375 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
379 memset(&sh->cmng, 0, sizeof(sh->cmng));
380 TAILQ_INIT(&sh->cmng.flow_counters);
381 sh->cmng.min_id = MLX5_CNT_BATCH_OFFSET;
382 sh->cmng.max_id = -1;
383 sh->cmng.last_pool_idx = POOL_IDX_INVALID;
384 rte_spinlock_init(&sh->cmng.pool_update_sl);
385 for (i = 0; i < MLX5_COUNTER_TYPE_MAX; i++) {
386 TAILQ_INIT(&sh->cmng.counters[i]);
387 rte_spinlock_init(&sh->cmng.csl[i]);
392 * Destroy all the resources allocated for a counter memory management.
395 * Pointer to the memory management structure.
398 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
400 uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
402 LIST_REMOVE(mng, next);
403 claim_zero(mlx5_devx_cmd_destroy(mng->dm));
404 claim_zero(mlx5_glue->devx_umem_dereg(mng->umem));
409 * Close and release all the resources of the counters management.
412 * Pointer to mlx5_dev_ctx_shared object to free.
415 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
417 struct mlx5_counter_stats_mem_mng *mng;
423 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
424 if (rte_errno != EINPROGRESS)
429 if (sh->cmng.pools) {
430 struct mlx5_flow_counter_pool *pool;
431 uint16_t n_valid = sh->cmng.n_valid;
432 bool fallback = sh->cmng.counter_fallback;
434 for (i = 0; i < n_valid; ++i) {
435 pool = sh->cmng.pools[i];
436 if (!fallback && pool->min_dcs)
437 claim_zero(mlx5_devx_cmd_destroy
439 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
440 struct mlx5_flow_counter *cnt =
441 MLX5_POOL_GET_CNT(pool, j);
445 (mlx5_glue->destroy_flow_action
447 if (fallback && MLX5_POOL_GET_CNT
448 (pool, j)->dcs_when_free)
449 claim_zero(mlx5_devx_cmd_destroy
450 (cnt->dcs_when_free));
454 mlx5_free(sh->cmng.pools);
456 mng = LIST_FIRST(&sh->cmng.mem_mngs);
458 mlx5_flow_destroy_counter_stat_mem_mng(mng);
459 mng = LIST_FIRST(&sh->cmng.mem_mngs);
461 memset(&sh->cmng, 0, sizeof(sh->cmng));
465 * Initialize the flow resources' indexed mempool.
468 * Pointer to mlx5_dev_ctx_shared object.
470 * Pointer to user dev config.
473 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
474 const struct mlx5_dev_config *config)
477 struct mlx5_indexed_pool_config cfg;
479 for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
480 cfg = mlx5_ipool_cfg[i];
485 * Set MLX5_IPOOL_MLX5_FLOW ipool size
486 * according to PCI function flow configuration.
488 case MLX5_IPOOL_MLX5_FLOW:
489 cfg.size = config->dv_flow_en ?
490 sizeof(struct mlx5_flow_handle) :
491 MLX5_FLOW_HANDLE_VERBS_SIZE;
494 if (config->reclaim_mode)
495 cfg.release_mem_en = 1;
496 sh->ipool[i] = mlx5_ipool_create(&cfg);
501 * Release the flow resources' indexed mempool.
504 * Pointer to mlx5_dev_ctx_shared object.
507 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
511 for (i = 0; i < MLX5_IPOOL_MAX; ++i)
512 mlx5_ipool_destroy(sh->ipool[i]);
516 * Check if dynamic flex parser for eCPRI already exists.
519 * Pointer to Ethernet device structure.
522 * true on exists, false on not.
525 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
527 struct mlx5_priv *priv = dev->data->dev_private;
528 struct mlx5_flex_parser_profiles *prf =
529 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
535 * Allocation of a flex parser for eCPRI. Once created, this parser related
536 * resources will be held until the device is closed.
539 * Pointer to Ethernet device structure.
542 * 0 on success, a negative errno value otherwise and rte_errno is set.
545 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
547 struct mlx5_priv *priv = dev->data->dev_private;
548 struct mlx5_flex_parser_profiles *prf =
549 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
550 struct mlx5_devx_graph_node_attr node = {
551 .modify_field_select = 0,
556 if (!priv->config.hca_attr.parse_graph_flex_node) {
557 DRV_LOG(ERR, "Dynamic flex parser is not supported "
558 "for device %s.", priv->dev_data->name);
561 node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED;
562 /* 8 bytes now: 4B common header + 4B message body header. */
563 node.header_length_base_value = 0x8;
564 /* After MAC layer: Ether / VLAN. */
565 node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC;
566 /* Type of compared condition should be 0xAEFE in the L2 layer. */
567 node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI;
568 /* Sample #0: type in common header. */
569 node.sample[0].flow_match_sample_en = 1;
571 node.sample[0].flow_match_sample_offset_mode = 0x0;
572 /* Only the 2nd byte will be used. */
573 node.sample[0].flow_match_sample_field_base_offset = 0x0;
574 /* Sample #1: message payload. */
575 node.sample[1].flow_match_sample_en = 1;
577 node.sample[1].flow_match_sample_offset_mode = 0x0;
579 * Only the first two bytes will be used right now, and its offset will
580 * start after the common header that with the length of a DW(u32).
582 node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);
583 prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->ctx, &node);
585 DRV_LOG(ERR, "Failed to create flex parser node object.");
586 return (rte_errno == 0) ? -ENODEV : -rte_errno;
589 ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num);
591 DRV_LOG(ERR, "Failed to query sample IDs.");
592 return (rte_errno == 0) ? -ENODEV : -rte_errno;
594 prf->offset[0] = 0x0;
595 prf->offset[1] = sizeof(uint32_t);
596 prf->ids[0] = ids[0];
597 prf->ids[1] = ids[1];
602 * Destroy the flex parser node, including the parser itself, input / output
603 * arcs and DW samples. Resources could be reused then.
606 * Pointer to Ethernet device structure.
609 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
611 struct mlx5_priv *priv = dev->data->dev_private;
612 struct mlx5_flex_parser_profiles *prf =
613 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
616 mlx5_devx_cmd_destroy(prf->obj);
621 * Allocate Rx and Tx UARs in robust fashion.
622 * This routine handles the following UAR allocation issues:
624 * - tries to allocate the UAR with the most appropriate memory
625 * mapping type from the ones supported by the host
627 * - tries to allocate the UAR with non-NULL base address
628 * OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as
629 * UAR base address if UAR was not the first object in the UAR page.
630 * It caused the PMD failure and we should try to get another UAR
631 * till we get the first one with non-NULL base address returned.
634 mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh,
635 const struct mlx5_dev_config *config)
637 uint32_t uar_mapping, retry;
641 for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
642 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
643 /* Control the mapping type according to the settings. */
644 uar_mapping = (config->dbnc == MLX5_TXDB_NCACHED) ?
645 MLX5DV_UAR_ALLOC_TYPE_NC :
646 MLX5DV_UAR_ALLOC_TYPE_BF;
648 RTE_SET_USED(config);
650 * It seems we have no way to control the memory mapping type
651 * for the UAR, the default "Write-Combining" type is supposed.
652 * The UAR initialization on queue creation queries the
653 * actual mapping type done by Verbs/kernel and setups the
654 * PMD datapath accordingly.
658 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->ctx, uar_mapping);
659 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
661 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
662 if (config->dbnc == MLX5_TXDB_CACHED ||
663 config->dbnc == MLX5_TXDB_HEURISTIC)
664 DRV_LOG(WARNING, "Devarg tx_db_nc setting "
665 "is not supported by DevX");
667 * In some environments like virtual machine
668 * the Write Combining mapped might be not supported
669 * and UAR allocation fails. We try "Non-Cached"
670 * mapping for the case. The tx_burst routines take
671 * the UAR mapping type into account on UAR setup
674 DRV_LOG(WARNING, "Failed to allocate Tx DevX UAR (BF)");
675 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
676 sh->tx_uar = mlx5_glue->devx_alloc_uar
677 (sh->ctx, uar_mapping);
678 } else if (!sh->tx_uar &&
679 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_NC) {
680 if (config->dbnc == MLX5_TXDB_NCACHED)
681 DRV_LOG(WARNING, "Devarg tx_db_nc settings "
682 "is not supported by DevX");
684 * If Verbs/kernel does not support "Non-Cached"
685 * try the "Write-Combining".
687 DRV_LOG(WARNING, "Failed to allocate Tx DevX UAR (NC)");
688 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_BF;
689 sh->tx_uar = mlx5_glue->devx_alloc_uar
690 (sh->ctx, uar_mapping);
694 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (BF/NC)");
698 base_addr = mlx5_os_get_devx_uar_base_addr(sh->tx_uar);
702 * The UARs are allocated by rdma_core within the
703 * IB device context, on context closure all UARs
704 * will be freed, should be no memory/object leakage.
706 DRV_LOG(WARNING, "Retrying to allocate Tx DevX UAR");
709 /* Check whether we finally succeeded with valid UAR allocation. */
711 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (NULL base)");
715 for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
717 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
718 (sh->ctx, uar_mapping);
719 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
720 if (!sh->devx_rx_uar &&
721 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
723 * Rx UAR is used to control interrupts only,
724 * should be no datapath noticeable impact,
725 * can try "Non-Cached" mapping safely.
727 DRV_LOG(WARNING, "Failed to allocate Rx DevX UAR (BF)");
728 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
729 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
730 (sh->ctx, uar_mapping);
733 if (!sh->devx_rx_uar) {
734 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (BF/NC)");
738 base_addr = mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar);
742 * The UARs are allocated by rdma_core within the
743 * IB device context, on context closure all UARs
744 * will be freed, should be no memory/object leakage.
746 DRV_LOG(WARNING, "Retrying to allocate Rx DevX UAR");
747 sh->devx_rx_uar = NULL;
749 /* Check whether we finally succeeded with valid UAR allocation. */
750 if (!sh->devx_rx_uar) {
751 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (NULL base)");
759 * Allocate shared device context. If there is multiport device the
760 * master and representors will share this context, if there is single
761 * port dedicated device, the context will be used by only given
762 * port due to unification.
764 * Routine first searches the context for the specified device name,
765 * if found the shared context assumed and reference counter is incremented.
766 * If no context found the new one is created and initialized with specified
767 * device context and parameters.
770 * Pointer to the device attributes (name, port, etc).
772 * Pointer to device configuration structure.
775 * Pointer to mlx5_dev_ctx_shared object on success,
776 * otherwise NULL and rte_errno is set.
778 struct mlx5_dev_ctx_shared *
779 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
780 const struct mlx5_dev_config *config)
782 struct mlx5_dev_ctx_shared *sh;
785 struct mlx5_devx_tis_attr tis_attr = { 0 };
788 /* Secondary process should not create the shared context. */
789 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
790 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
791 /* Search for IB context by device name. */
792 LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
793 if (!strcmp(sh->ibdev_name,
794 mlx5_os_get_dev_device_name(spawn->phys_dev))) {
799 /* No device found, we have to create new shared context. */
800 MLX5_ASSERT(spawn->max_port);
801 sh = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
802 sizeof(struct mlx5_dev_ctx_shared) +
804 sizeof(struct mlx5_dev_shared_port),
805 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
807 DRV_LOG(ERR, "shared context allocation failure");
811 err = mlx5_os_open_device(spawn, config, sh);
814 err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
816 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
820 sh->max_port = spawn->max_port;
821 strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
822 sizeof(sh->ibdev_name) - 1);
823 strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
824 sizeof(sh->ibdev_path) - 1);
826 * Setting port_id to max unallowed value means
827 * there is no interrupt subhandler installed for
828 * the given port index i.
830 for (i = 0; i < sh->max_port; i++) {
831 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
832 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
834 sh->pd = mlx5_glue->alloc_pd(sh->ctx);
835 if (sh->pd == NULL) {
836 DRV_LOG(ERR, "PD allocation failure");
841 /* Query the EQN for this core. */
842 err = mlx5_glue->devx_query_eqn(sh->ctx, 0, &sh->eqn);
845 DRV_LOG(ERR, "Failed to query event queue number %d.",
849 err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
851 DRV_LOG(ERR, "Fail to extract pdn from PD");
854 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
856 DRV_LOG(ERR, "TD allocation failure");
860 tis_attr.transport_domain = sh->td->id;
861 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
863 DRV_LOG(ERR, "TIS allocation failure");
867 err = mlx5_alloc_rxtx_uars(sh, config);
870 MLX5_ASSERT(sh->tx_uar);
871 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->tx_uar));
873 MLX5_ASSERT(sh->devx_rx_uar);
874 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar));
877 /* Initialize UAR access locks for 32bit implementations. */
878 rte_spinlock_init(&sh->uar_lock_cq);
879 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
880 rte_spinlock_init(&sh->uar_lock[i]);
883 * Once the device is added to the list of memory event
884 * callback, its global MR cache table cannot be expanded
885 * on the fly because of deadlock. If it overflows, lookup
886 * should be done by searching MR list linearly, which is slow.
888 * At this point the device is not added to the memory
889 * event list yet, context is just being created.
891 err = mlx5_mr_btree_init(&sh->share_cache.cache,
892 MLX5_MR_BTREE_CACHE_N * 2,
893 spawn->pci_dev->device.numa_node);
898 mlx5_os_set_reg_mr_cb(&sh->share_cache.reg_mr_cb,
899 &sh->share_cache.dereg_mr_cb);
900 mlx5_os_dev_shared_handler_install(sh);
901 sh->cnt_id_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_DWORD);
902 if (!sh->cnt_id_tbl) {
906 mlx5_flow_aging_init(sh);
907 mlx5_flow_counters_mng_init(sh);
908 mlx5_flow_ipool_create(sh, config);
909 /* Add device to memory callback list. */
910 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
911 LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
913 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
914 /* Add context to the global device list. */
915 LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
917 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
920 pthread_mutex_destroy(&sh->txpp.mutex);
921 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
924 mlx5_l3t_destroy(sh->cnt_id_tbl);
926 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
928 claim_zero(mlx5_devx_cmd_destroy(sh->td));
930 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
932 mlx5_glue->devx_free_uar(sh->tx_uar);
934 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
936 claim_zero(mlx5_glue->close_device(sh->ctx));
938 MLX5_ASSERT(err > 0);
944 * Free shared IB device context. Decrement counter and if zero free
945 * all allocated resources and close handles.
948 * Pointer to mlx5_dev_ctx_shared object to free
951 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
953 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
954 #ifdef RTE_LIBRTE_MLX5_DEBUG
955 /* Check the object presence in the list. */
956 struct mlx5_dev_ctx_shared *lctx;
958 LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
963 DRV_LOG(ERR, "Freeing non-existing shared IB context");
968 MLX5_ASSERT(sh->refcnt);
969 /* Secondary process should not free the shared context. */
970 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
973 /* Remove from memory callback device list. */
974 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
975 LIST_REMOVE(sh, mem_event_cb);
976 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
977 /* Release created Memory Regions. */
978 mlx5_mr_release_cache(&sh->share_cache);
979 /* Remove context from the global device list. */
980 LIST_REMOVE(sh, next);
981 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
983 * Ensure there is no async event handler installed.
984 * Only primary process handles async device events.
986 mlx5_flow_counters_mng_close(sh);
987 mlx5_flow_ipool_destroy(sh);
988 mlx5_os_dev_shared_handler_uninstall(sh);
989 if (sh->cnt_id_tbl) {
990 mlx5_l3t_destroy(sh->cnt_id_tbl);
991 sh->cnt_id_tbl = NULL;
994 mlx5_glue->devx_free_uar(sh->tx_uar);
998 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
1000 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1002 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1003 if (sh->devx_rx_uar)
1004 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1006 claim_zero(mlx5_glue->close_device(sh->ctx));
1007 pthread_mutex_destroy(&sh->txpp.mutex);
1011 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1015 * Destroy table hash list and all the root entries per domain.
1018 * Pointer to the private device data structure.
1021 mlx5_free_table_hash_list(struct mlx5_priv *priv)
1023 struct mlx5_dev_ctx_shared *sh = priv->sh;
1024 struct mlx5_flow_tbl_data_entry *tbl_data;
1025 union mlx5_flow_tbl_key table_key = {
1033 struct mlx5_hlist_entry *pos;
1037 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64, NULL);
1039 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
1041 MLX5_ASSERT(tbl_data);
1042 mlx5_hlist_remove(sh->flow_tbls, pos);
1043 mlx5_free(tbl_data);
1045 table_key.direction = 1;
1046 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64, NULL);
1048 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
1050 MLX5_ASSERT(tbl_data);
1051 mlx5_hlist_remove(sh->flow_tbls, pos);
1052 mlx5_free(tbl_data);
1054 table_key.direction = 0;
1055 table_key.domain = 1;
1056 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64, NULL);
1058 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
1060 MLX5_ASSERT(tbl_data);
1061 mlx5_hlist_remove(sh->flow_tbls, pos);
1062 mlx5_free(tbl_data);
1064 mlx5_hlist_destroy(sh->flow_tbls);
1068 * Initialize flow table hash list and create the root tables entry
1072 * Pointer to the private device data structure.
1075 * Zero on success, positive error code otherwise.
1078 mlx5_alloc_table_hash_list(struct mlx5_priv *priv)
1080 struct mlx5_dev_ctx_shared *sh = priv->sh;
1081 char s[MLX5_HLIST_NAMESIZE];
1085 snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1086 sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE,
1087 0, 0, NULL, NULL, NULL);
1088 if (!sh->flow_tbls) {
1089 DRV_LOG(ERR, "flow tables with hash creation failed.");
1093 #ifndef HAVE_MLX5DV_DR
1095 * In case we have not DR support, the zero tables should be created
1096 * because DV expect to see them even if they cannot be created by
1099 union mlx5_flow_tbl_key table_key = {
1107 struct mlx5_flow_tbl_data_entry *tbl_data = mlx5_malloc(MLX5_MEM_ZERO,
1108 sizeof(*tbl_data), 0,
1115 tbl_data->entry.key = table_key.v64;
1116 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1119 __atomic_store_n(&tbl_data->tbl.refcnt, 1, __ATOMIC_RELAXED);
1120 table_key.direction = 1;
1121 tbl_data = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tbl_data), 0,
1127 tbl_data->entry.key = table_key.v64;
1128 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1131 __atomic_store_n(&tbl_data->tbl.refcnt, 1, __ATOMIC_RELAXED);
1132 table_key.direction = 0;
1133 table_key.domain = 1;
1134 tbl_data = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tbl_data), 0,
1140 tbl_data->entry.key = table_key.v64;
1141 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1144 __atomic_store_n(&tbl_data->tbl.refcnt, 1, __ATOMIC_RELAXED);
1147 mlx5_free_table_hash_list(priv);
1148 #endif /* HAVE_MLX5DV_DR */
1153 * Retrieve integer value from environment variable.
1156 * Environment variable name.
1159 * Integer value, 0 if the variable is not set.
1162 mlx5_getenv_int(const char *name)
1164 const char *val = getenv(name);
1172 * DPDK callback to add udp tunnel port
1175 * A pointer to eth_dev
1176 * @param[in] udp_tunnel
1177 * A pointer to udp tunnel
1180 * 0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1183 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1184 struct rte_eth_udp_tunnel *udp_tunnel)
1186 MLX5_ASSERT(udp_tunnel != NULL);
1187 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1188 udp_tunnel->udp_port == 4789)
1190 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1191 udp_tunnel->udp_port == 4790)
1197 * Initialize process private data structure.
1200 * Pointer to Ethernet device structure.
1203 * 0 on success, a negative errno value otherwise and rte_errno is set.
1206 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1208 struct mlx5_priv *priv = dev->data->dev_private;
1209 struct mlx5_proc_priv *ppriv;
1213 * UAR register table follows the process private structure. BlueFlame
1214 * registers for Tx queues are stored in the table.
1217 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1218 ppriv = mlx5_malloc(MLX5_MEM_RTE, ppriv_size, RTE_CACHE_LINE_SIZE,
1219 dev->device->numa_node);
1224 ppriv->uar_table_sz = ppriv_size;
1225 dev->process_private = ppriv;
1230 * Un-initialize process private data structure.
1233 * Pointer to Ethernet device structure.
1236 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1238 if (!dev->process_private)
1240 mlx5_free(dev->process_private);
1241 dev->process_private = NULL;
1245 * DPDK callback to close the device.
1247 * Destroy all queues and objects, free memory.
1250 * Pointer to Ethernet device structure.
1253 mlx5_dev_close(struct rte_eth_dev *dev)
1255 struct mlx5_priv *priv = dev->data->dev_private;
1259 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1260 /* Check if process_private released. */
1261 if (!dev->process_private)
1263 mlx5_tx_uar_uninit_secondary(dev);
1264 mlx5_proc_priv_uninit(dev);
1265 rte_eth_dev_release_port(dev);
1270 DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1272 ((priv->sh->ctx != NULL) ?
1273 mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
1275 * If default mreg copy action is removed at the stop stage,
1276 * the search will return none and nothing will be done anymore.
1278 mlx5_flow_stop_default(dev);
1279 mlx5_traffic_disable(dev);
1281 * If all the flows are already flushed in the device stop stage,
1282 * then this will return directly without any action.
1284 mlx5_flow_list_flush(dev, &priv->flows, true);
1285 mlx5_shared_action_flush(dev);
1286 mlx5_flow_meter_flush(dev, NULL);
1287 /* Prevent crashes when queues are still in use. */
1288 dev->rx_pkt_burst = removed_rx_burst;
1289 dev->tx_pkt_burst = removed_tx_burst;
1291 /* Disable datapath on secondary process. */
1292 mlx5_mp_os_req_stop_rxtx(dev);
1293 /* Free the eCPRI flex parser resource. */
1294 mlx5_flex_parser_ecpri_release(dev);
1295 if (priv->rxqs != NULL) {
1296 /* XXX race condition if mlx5_rx_burst() is still running. */
1298 for (i = 0; (i != priv->rxqs_n); ++i)
1299 mlx5_rxq_release(dev, i);
1303 if (priv->txqs != NULL) {
1304 /* XXX race condition if mlx5_tx_burst() is still running. */
1306 for (i = 0; (i != priv->txqs_n); ++i)
1307 mlx5_txq_release(dev, i);
1311 mlx5_proc_priv_uninit(dev);
1312 if (priv->drop_queue.hrxq)
1313 mlx5_drop_action_destroy(dev);
1314 if (priv->mreg_cp_tbl)
1315 mlx5_hlist_destroy(priv->mreg_cp_tbl);
1316 mlx5_mprq_free_mp(dev);
1317 mlx5_os_free_shared_dr(priv);
1318 if (priv->rss_conf.rss_key != NULL)
1319 mlx5_free(priv->rss_conf.rss_key);
1320 if (priv->reta_idx != NULL)
1321 mlx5_free(priv->reta_idx);
1322 if (priv->config.vf)
1323 mlx5_os_mac_addr_flush(dev);
1324 if (priv->nl_socket_route >= 0)
1325 close(priv->nl_socket_route);
1326 if (priv->nl_socket_rdma >= 0)
1327 close(priv->nl_socket_rdma);
1328 if (priv->vmwa_context)
1329 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1330 ret = mlx5_hrxq_verify(dev);
1332 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1333 dev->data->port_id);
1334 ret = mlx5_ind_table_obj_verify(dev);
1336 DRV_LOG(WARNING, "port %u some indirection table still remain",
1337 dev->data->port_id);
1338 ret = mlx5_rxq_obj_verify(dev);
1340 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1341 dev->data->port_id);
1342 ret = mlx5_rxq_verify(dev);
1344 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1345 dev->data->port_id);
1346 ret = mlx5_txq_obj_verify(dev);
1348 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1349 dev->data->port_id);
1350 ret = mlx5_txq_verify(dev);
1352 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1353 dev->data->port_id);
1354 ret = mlx5_flow_verify(dev);
1356 DRV_LOG(WARNING, "port %u some flows still remain",
1357 dev->data->port_id);
1359 * Free the shared context in last turn, because the cleanup
1360 * routines above may use some shared fields, like
1361 * mlx5_os_mac_addr_flush() uses ibdev_path for retrieveing
1362 * ifindex if Netlink fails.
1364 mlx5_free_shared_dev_ctx(priv->sh);
1365 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1369 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1370 struct mlx5_priv *opriv =
1371 rte_eth_devices[port_id].data->dev_private;
1374 opriv->domain_id != priv->domain_id ||
1375 &rte_eth_devices[port_id] == dev)
1381 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1383 memset(priv, 0, sizeof(*priv));
1384 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1386 * Reset mac_addrs to NULL such that it is not freed as part of
1387 * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1388 * it is freed when dev_private is freed.
1390 dev->data->mac_addrs = NULL;
1395 * Verify and store value for device argument.
1398 * Key argument to verify.
1400 * Value associated with key.
1405 * 0 on success, a negative errno value otherwise and rte_errno is set.
1408 mlx5_args_check(const char *key, const char *val, void *opaque)
1410 struct mlx5_dev_config *config = opaque;
1414 /* No-op, port representors are processed in mlx5_dev_spawn(). */
1415 if (!strcmp(MLX5_REPRESENTOR, key))
1418 tmp = strtol(val, NULL, 0);
1421 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1424 if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
1425 /* Negative values are acceptable for some keys only. */
1427 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
1430 mod = tmp >= 0 ? tmp : -tmp;
1431 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1432 config->cqe_comp = !!tmp;
1433 } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
1434 config->cqe_pad = !!tmp;
1435 } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1436 config->hw_padding = !!tmp;
1437 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1438 config->mprq.enabled = !!tmp;
1439 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1440 config->mprq.stride_num_n = tmp;
1441 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1442 config->mprq.stride_size_n = tmp;
1443 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1444 config->mprq.max_memcpy_len = tmp;
1445 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1446 config->mprq.min_rxqs_num = tmp;
1447 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1448 DRV_LOG(WARNING, "%s: deprecated parameter,"
1449 " converted to txq_inline_max", key);
1450 config->txq_inline_max = tmp;
1451 } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1452 config->txq_inline_max = tmp;
1453 } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1454 config->txq_inline_min = tmp;
1455 } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1456 config->txq_inline_mpw = tmp;
1457 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1458 config->txqs_inline = tmp;
1459 } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1460 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1461 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1462 config->mps = !!tmp;
1463 } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1464 if (tmp != MLX5_TXDB_CACHED &&
1465 tmp != MLX5_TXDB_NCACHED &&
1466 tmp != MLX5_TXDB_HEURISTIC) {
1467 DRV_LOG(ERR, "invalid Tx doorbell "
1468 "mapping parameter");
1473 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1474 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1475 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1476 DRV_LOG(WARNING, "%s: deprecated parameter,"
1477 " converted to txq_inline_mpw", key);
1478 config->txq_inline_mpw = tmp;
1479 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1480 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1481 } else if (strcmp(MLX5_TX_PP, key) == 0) {
1483 DRV_LOG(ERR, "Zero Tx packet pacing parameter");
1487 config->tx_pp = tmp;
1488 } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
1489 config->tx_skew = tmp;
1490 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1491 config->rx_vec_en = !!tmp;
1492 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1493 config->l3_vxlan_en = !!tmp;
1494 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1495 config->vf_nl_en = !!tmp;
1496 } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1497 config->dv_esw_en = !!tmp;
1498 } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1499 config->dv_flow_en = !!tmp;
1500 } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1501 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1502 tmp != MLX5_XMETA_MODE_META16 &&
1503 tmp != MLX5_XMETA_MODE_META32 &&
1504 tmp != MLX5_XMETA_MODE_MISS_INFO) {
1505 DRV_LOG(ERR, "invalid extensive "
1506 "metadata parameter");
1510 if (tmp != MLX5_XMETA_MODE_MISS_INFO)
1511 config->dv_xmeta_en = tmp;
1513 config->dv_miss_info = 1;
1514 } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
1515 config->lacp_by_user = !!tmp;
1516 } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1517 config->mr_ext_memseg_en = !!tmp;
1518 } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1519 config->max_dump_files_num = tmp;
1520 } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1521 config->lro.timeout = tmp;
1522 } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1523 DRV_LOG(DEBUG, "class argument is %s.", val);
1524 } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1525 config->log_hp_size = tmp;
1526 } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1527 if (tmp != MLX5_RCM_NONE &&
1528 tmp != MLX5_RCM_LIGHT &&
1529 tmp != MLX5_RCM_AGGR) {
1530 DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1534 config->reclaim_mode = tmp;
1535 } else if (strcmp(MLX5_SYS_MEM_EN, key) == 0) {
1536 config->sys_mem_en = !!tmp;
1537 } else if (strcmp(MLX5_DECAP_EN, key) == 0) {
1538 config->decap_en = !!tmp;
1540 DRV_LOG(WARNING, "%s: unknown parameter", key);
1548 * Parse device parameters.
1551 * Pointer to device configuration structure.
1553 * Device arguments structure.
1556 * 0 on success, a negative errno value otherwise and rte_errno is set.
1559 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1561 const char **params = (const char *[]){
1562 MLX5_RXQ_CQE_COMP_EN,
1563 MLX5_RXQ_CQE_PAD_EN,
1564 MLX5_RXQ_PKT_PAD_EN,
1566 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1567 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1568 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1571 MLX5_TXQ_INLINE_MIN,
1572 MLX5_TXQ_INLINE_MAX,
1573 MLX5_TXQ_INLINE_MPW,
1574 MLX5_TXQS_MIN_INLINE,
1577 MLX5_TXQ_MPW_HDR_DSEG_EN,
1578 MLX5_TXQ_MAX_INLINE_LEN,
1590 MLX5_MR_EXT_MEMSEG_EN,
1592 MLX5_MAX_DUMP_FILES_NUM,
1593 MLX5_LRO_TIMEOUT_USEC,
1594 MLX5_CLASS_ARG_NAME,
1601 struct rte_kvargs *kvlist;
1605 if (devargs == NULL)
1607 /* Following UGLY cast is done to pass checkpatch. */
1608 kvlist = rte_kvargs_parse(devargs->args, params);
1609 if (kvlist == NULL) {
1613 /* Process parameters. */
1614 for (i = 0; (params[i] != NULL); ++i) {
1615 if (rte_kvargs_count(kvlist, params[i])) {
1616 ret = rte_kvargs_process(kvlist, params[i],
1617 mlx5_args_check, config);
1620 rte_kvargs_free(kvlist);
1625 rte_kvargs_free(kvlist);
1630 * Configures the minimal amount of data to inline into WQE
1631 * while sending packets.
1633 * - the txq_inline_min has the maximal priority, if this
1634 * key is specified in devargs
1635 * - if DevX is enabled the inline mode is queried from the
1636 * device (HCA attributes and NIC vport context if needed).
1637 * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1638 * and none (0 bytes) for other NICs
1641 * Verbs device parameters (name, port, switch_info) to spawn.
1643 * Device configuration parameters.
1646 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1647 struct mlx5_dev_config *config)
1649 if (config->txq_inline_min != MLX5_ARG_UNSET) {
1650 /* Application defines size of inlined data explicitly. */
1651 switch (spawn->pci_dev->id.device_id) {
1652 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1653 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1654 if (config->txq_inline_min <
1655 (int)MLX5_INLINE_HSIZE_L2) {
1657 "txq_inline_mix aligned to minimal"
1658 " ConnectX-4 required value %d",
1659 (int)MLX5_INLINE_HSIZE_L2);
1660 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1666 if (config->hca_attr.eth_net_offloads) {
1667 /* We have DevX enabled, inline mode queried successfully. */
1668 switch (config->hca_attr.wqe_inline_mode) {
1669 case MLX5_CAP_INLINE_MODE_L2:
1670 /* outer L2 header must be inlined. */
1671 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1673 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1674 /* No inline data are required by NIC. */
1675 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1676 config->hw_vlan_insert =
1677 config->hca_attr.wqe_vlan_insert;
1678 DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1680 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1681 /* inline mode is defined by NIC vport context. */
1682 if (!config->hca_attr.eth_virt)
1684 switch (config->hca_attr.vport_inline_mode) {
1685 case MLX5_INLINE_MODE_NONE:
1686 config->txq_inline_min =
1687 MLX5_INLINE_HSIZE_NONE;
1689 case MLX5_INLINE_MODE_L2:
1690 config->txq_inline_min =
1691 MLX5_INLINE_HSIZE_L2;
1693 case MLX5_INLINE_MODE_IP:
1694 config->txq_inline_min =
1695 MLX5_INLINE_HSIZE_L3;
1697 case MLX5_INLINE_MODE_TCP_UDP:
1698 config->txq_inline_min =
1699 MLX5_INLINE_HSIZE_L4;
1701 case MLX5_INLINE_MODE_INNER_L2:
1702 config->txq_inline_min =
1703 MLX5_INLINE_HSIZE_INNER_L2;
1705 case MLX5_INLINE_MODE_INNER_IP:
1706 config->txq_inline_min =
1707 MLX5_INLINE_HSIZE_INNER_L3;
1709 case MLX5_INLINE_MODE_INNER_TCP_UDP:
1710 config->txq_inline_min =
1711 MLX5_INLINE_HSIZE_INNER_L4;
1717 * We get here if we are unable to deduce
1718 * inline data size with DevX. Try PCI ID
1719 * to determine old NICs.
1721 switch (spawn->pci_dev->id.device_id) {
1722 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1723 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1724 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
1725 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1726 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1727 config->hw_vlan_insert = 0;
1729 case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
1730 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1731 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
1732 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1734 * These NICs support VLAN insertion from WQE and
1735 * report the wqe_vlan_insert flag. But there is the bug
1736 * and PFC control may be broken, so disable feature.
1738 config->hw_vlan_insert = 0;
1739 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1742 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1746 DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
1750 * Configures the metadata mask fields in the shared context.
1753 * Pointer to Ethernet device.
1756 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
1758 struct mlx5_priv *priv = dev->data->dev_private;
1759 struct mlx5_dev_ctx_shared *sh = priv->sh;
1760 uint32_t meta, mark, reg_c0;
1762 reg_c0 = ~priv->vport_meta_mask;
1763 switch (priv->config.dv_xmeta_en) {
1764 case MLX5_XMETA_MODE_LEGACY:
1766 mark = MLX5_FLOW_MARK_MASK;
1768 case MLX5_XMETA_MODE_META16:
1769 meta = reg_c0 >> rte_bsf32(reg_c0);
1770 mark = MLX5_FLOW_MARK_MASK;
1772 case MLX5_XMETA_MODE_META32:
1774 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
1782 if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
1783 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
1784 sh->dv_mark_mask, mark);
1786 sh->dv_mark_mask = mark;
1787 if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
1788 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
1789 sh->dv_meta_mask, meta);
1791 sh->dv_meta_mask = meta;
1792 if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
1793 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
1794 sh->dv_meta_mask, reg_c0);
1796 sh->dv_regc0_mask = reg_c0;
1797 DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
1798 DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
1799 DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
1800 DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
1804 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
1806 static const char *const dynf_names[] = {
1807 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
1808 RTE_MBUF_DYNFLAG_METADATA_NAME,
1809 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
1813 if (n < RTE_DIM(dynf_names))
1815 for (i = 0; i < RTE_DIM(dynf_names); i++) {
1816 if (names[i] == NULL)
1818 strcpy(names[i], dynf_names[i]);
1820 return RTE_DIM(dynf_names);
1824 * Comparison callback to sort device data.
1826 * This is meant to be used with qsort().
1829 * Pointer to pointer to first data object.
1831 * Pointer to pointer to second data object.
1834 * 0 if both objects are equal, less than 0 if the first argument is less
1835 * than the second, greater than 0 otherwise.
1838 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
1839 struct mlx5_dev_config *config)
1841 struct mlx5_dev_ctx_shared *sh = priv->sh;
1842 struct mlx5_dev_config *sh_conf = NULL;
1846 /* Nothing to compare for the single/first device. */
1847 if (sh->refcnt == 1)
1849 /* Find the device with shared context. */
1850 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1851 struct mlx5_priv *opriv =
1852 rte_eth_devices[port_id].data->dev_private;
1854 if (opriv && opriv != priv && opriv->sh == sh) {
1855 sh_conf = &opriv->config;
1861 if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
1862 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
1863 " for shared %s context", sh->ibdev_name);
1867 if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
1868 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
1869 " for shared %s context", sh->ibdev_name);
1877 * Look for the ethernet device belonging to mlx5 driver.
1879 * @param[in] port_id
1880 * port_id to start looking for device.
1881 * @param[in] pci_dev
1882 * Pointer to the hint PCI device. When device is being probed
1883 * the its siblings (master and preceding representors might
1884 * not have assigned driver yet (because the mlx5_os_pci_probe()
1885 * is not completed yet, for this case match on hint PCI
1886 * device may be used to detect sibling device.
1889 * port_id of found device, RTE_MAX_ETHPORT if not found.
1892 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
1894 while (port_id < RTE_MAX_ETHPORTS) {
1895 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
1897 if (dev->state != RTE_ETH_DEV_UNUSED &&
1899 (dev->device == &pci_dev->device ||
1900 (dev->device->driver &&
1901 dev->device->driver->name &&
1902 !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
1906 if (port_id >= RTE_MAX_ETHPORTS)
1907 return RTE_MAX_ETHPORTS;
1912 * DPDK callback to remove a PCI device.
1914 * This function removes all Ethernet devices belong to a given PCI device.
1916 * @param[in] pci_dev
1917 * Pointer to the PCI device.
1920 * 0 on success, the function cannot fail.
1923 mlx5_pci_remove(struct rte_pci_device *pci_dev)
1928 RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
1930 * mlx5_dev_close() is not registered to secondary process,
1931 * call the close function explicitly for secondary process.
1933 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
1934 ret |= mlx5_dev_close(&rte_eth_devices[port_id]);
1936 ret |= rte_eth_dev_close(port_id);
1938 return ret == 0 ? 0 : -EIO;
1941 static const struct rte_pci_id mlx5_pci_id_map[] = {
1943 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1944 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
1947 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1948 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
1951 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1952 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
1955 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1956 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
1959 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1960 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
1963 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1964 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
1967 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1968 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
1971 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1972 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
1975 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1976 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
1979 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1980 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
1983 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1984 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
1987 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1988 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
1991 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1992 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
1995 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1996 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF)
1999 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2000 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
2003 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2004 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
2007 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2008 PCI_DEVICE_ID_MELLANOX_CONNECTX7)
2011 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2012 PCI_DEVICE_ID_MELLANOX_CONNECTX7BF)
2019 static struct mlx5_pci_driver mlx5_driver = {
2020 .driver_class = MLX5_CLASS_NET,
2023 .name = MLX5_DRIVER_NAME,
2025 .id_table = mlx5_pci_id_map,
2026 .probe = mlx5_os_pci_probe,
2027 .remove = mlx5_pci_remove,
2028 .dma_map = mlx5_dma_map,
2029 .dma_unmap = mlx5_dma_unmap,
2030 .drv_flags = PCI_DRV_FLAGS,
2034 /* Initialize driver log type. */
2035 RTE_LOG_REGISTER(mlx5_logtype, pmd.net.mlx5, NOTICE)
2038 * Driver initialization routine.
2040 RTE_INIT(rte_mlx5_pmd_init)
2043 /* Build the static tables for Verbs conversion. */
2044 mlx5_set_ptype_table();
2045 mlx5_set_cksum_table();
2046 mlx5_set_swp_types_table();
2048 mlx5_pci_driver_register(&mlx5_driver);
2051 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
2052 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
2053 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");