4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
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8 * modification, are permitted provided that the following conditions
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44 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
46 #pragma GCC diagnostic ignored "-Wpedantic"
48 #include <infiniband/verbs.h>
50 #pragma GCC diagnostic error "-Wpedantic"
53 #include <rte_malloc.h>
54 #include <rte_ethdev.h>
55 #include <rte_ethdev_pci.h>
57 #include <rte_bus_pci.h>
58 #include <rte_common.h>
59 #include <rte_kvargs.h>
62 #include "mlx5_utils.h"
63 #include "mlx5_rxtx.h"
64 #include "mlx5_autoconf.h"
65 #include "mlx5_defs.h"
67 /* Device parameter to enable RX completion queue compression. */
68 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
70 /* Device parameter to configure inline send. */
71 #define MLX5_TXQ_INLINE "txq_inline"
74 * Device parameter to configure the number of TX queues threshold for
75 * enabling inline send.
77 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
79 /* Device parameter to enable multi-packet send WQEs. */
80 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
82 /* Device parameter to include 2 dsegs in the title WQEBB. */
83 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
85 /* Device parameter to limit the size of inlining packet. */
86 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
88 /* Device parameter to enable hardware TSO offload. */
89 #define MLX5_TSO "tso"
91 /* Device parameter to enable hardware Tx vector. */
92 #define MLX5_TX_VEC_EN "tx_vec_en"
94 /* Device parameter to enable hardware Rx vector. */
95 #define MLX5_RX_VEC_EN "rx_vec_en"
97 /* Default PMD specific parameter value. */
98 #define MLX5_ARG_UNSET (-1)
100 #ifndef HAVE_IBV_MLX5_MOD_MPW
101 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2)
102 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3)
105 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP
106 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4)
115 int inline_max_packet_sz;
121 * Retrieve integer value from environment variable.
124 * Environment variable name.
127 * Integer value, 0 if the variable is not set.
130 mlx5_getenv_int(const char *name)
132 const char *val = getenv(name);
140 * Verbs callback to allocate a memory. This function should allocate the space
141 * according to the size provided residing inside a huge page.
142 * Please note that all allocation must respect the alignment from libmlx5
143 * (i.e. currently sysconf(_SC_PAGESIZE)).
146 * The size in bytes of the memory to allocate.
148 * A pointer to the callback data.
151 * a pointer to the allocate space.
154 mlx5_alloc_verbs_buf(size_t size, void *data)
156 struct priv *priv = data;
158 size_t alignment = sysconf(_SC_PAGESIZE);
160 assert(data != NULL);
161 ret = rte_malloc_socket(__func__, size, alignment,
162 priv->dev->device->numa_node);
163 DEBUG("Extern alloc size: %lu, align: %lu: %p", size, alignment, ret);
168 * Verbs callback to free a memory.
171 * A pointer to the memory to free.
173 * A pointer to the callback data.
176 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused)
178 assert(data != NULL);
179 DEBUG("Extern free request: %p", ptr);
184 * DPDK callback to close the device.
186 * Destroy all queues and objects, free memory.
189 * Pointer to Ethernet device structure.
192 mlx5_dev_close(struct rte_eth_dev *dev)
194 struct priv *priv = dev->data->dev_private;
199 DEBUG("%p: closing device \"%s\"",
201 ((priv->ctx != NULL) ? priv->ctx->device->name : ""));
202 /* In case mlx5_dev_stop() has not been called. */
203 priv_dev_interrupt_handler_uninstall(priv, dev);
204 priv_dev_traffic_disable(priv, dev);
205 /* Prevent crashes when queues are still in use. */
206 dev->rx_pkt_burst = removed_rx_burst;
207 dev->tx_pkt_burst = removed_tx_burst;
208 if (priv->rxqs != NULL) {
209 /* XXX race condition if mlx5_rx_burst() is still running. */
211 for (i = 0; (i != priv->rxqs_n); ++i)
212 mlx5_priv_rxq_release(priv, i);
216 if (priv->txqs != NULL) {
217 /* XXX race condition if mlx5_tx_burst() is still running. */
219 for (i = 0; (i != priv->txqs_n); ++i)
220 mlx5_priv_txq_release(priv, i);
224 if (priv->pd != NULL) {
225 assert(priv->ctx != NULL);
226 claim_zero(ibv_dealloc_pd(priv->pd));
227 claim_zero(ibv_close_device(priv->ctx));
229 assert(priv->ctx == NULL);
230 if (priv->rss_conf.rss_key != NULL)
231 rte_free(priv->rss_conf.rss_key);
232 if (priv->reta_idx != NULL)
233 rte_free(priv->reta_idx);
234 priv_socket_uninit(priv);
235 ret = mlx5_priv_hrxq_ibv_verify(priv);
237 WARN("%p: some Hash Rx queue still remain", (void *)priv);
238 ret = mlx5_priv_ind_table_ibv_verify(priv);
240 WARN("%p: some Indirection table still remain", (void *)priv);
241 ret = mlx5_priv_rxq_ibv_verify(priv);
243 WARN("%p: some Verbs Rx queue still remain", (void *)priv);
244 ret = mlx5_priv_rxq_verify(priv);
246 WARN("%p: some Rx Queues still remain", (void *)priv);
247 ret = mlx5_priv_txq_ibv_verify(priv);
249 WARN("%p: some Verbs Tx queue still remain", (void *)priv);
250 ret = mlx5_priv_txq_verify(priv);
252 WARN("%p: some Tx Queues still remain", (void *)priv);
253 ret = priv_flow_verify(priv);
255 WARN("%p: some flows still remain", (void *)priv);
256 ret = priv_mr_verify(priv);
258 WARN("%p: some Memory Region still remain", (void *)priv);
260 memset(priv, 0, sizeof(*priv));
263 const struct eth_dev_ops mlx5_dev_ops = {
264 .dev_configure = mlx5_dev_configure,
265 .dev_start = mlx5_dev_start,
266 .dev_stop = mlx5_dev_stop,
267 .dev_set_link_down = mlx5_set_link_down,
268 .dev_set_link_up = mlx5_set_link_up,
269 .dev_close = mlx5_dev_close,
270 .promiscuous_enable = mlx5_promiscuous_enable,
271 .promiscuous_disable = mlx5_promiscuous_disable,
272 .allmulticast_enable = mlx5_allmulticast_enable,
273 .allmulticast_disable = mlx5_allmulticast_disable,
274 .link_update = mlx5_link_update,
275 .stats_get = mlx5_stats_get,
276 .stats_reset = mlx5_stats_reset,
277 .xstats_get = mlx5_xstats_get,
278 .xstats_reset = mlx5_xstats_reset,
279 .xstats_get_names = mlx5_xstats_get_names,
280 .dev_infos_get = mlx5_dev_infos_get,
281 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
282 .vlan_filter_set = mlx5_vlan_filter_set,
283 .rx_queue_setup = mlx5_rx_queue_setup,
284 .tx_queue_setup = mlx5_tx_queue_setup,
285 .rx_queue_release = mlx5_rx_queue_release,
286 .tx_queue_release = mlx5_tx_queue_release,
287 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
288 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
289 .mac_addr_remove = mlx5_mac_addr_remove,
290 .mac_addr_add = mlx5_mac_addr_add,
291 .mac_addr_set = mlx5_mac_addr_set,
292 .mtu_set = mlx5_dev_set_mtu,
293 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
294 .vlan_offload_set = mlx5_vlan_offload_set,
295 .reta_update = mlx5_dev_rss_reta_update,
296 .reta_query = mlx5_dev_rss_reta_query,
297 .rss_hash_update = mlx5_rss_hash_update,
298 .rss_hash_conf_get = mlx5_rss_hash_conf_get,
299 .filter_ctrl = mlx5_dev_filter_ctrl,
300 .rx_descriptor_status = mlx5_rx_descriptor_status,
301 .tx_descriptor_status = mlx5_tx_descriptor_status,
302 .rx_queue_intr_enable = mlx5_rx_intr_enable,
303 .rx_queue_intr_disable = mlx5_rx_intr_disable,
306 static const struct eth_dev_ops mlx5_dev_sec_ops = {
307 .stats_get = mlx5_stats_get,
308 .stats_reset = mlx5_stats_reset,
309 .xstats_get = mlx5_xstats_get,
310 .xstats_reset = mlx5_xstats_reset,
311 .xstats_get_names = mlx5_xstats_get_names,
312 .dev_infos_get = mlx5_dev_infos_get,
313 .rx_descriptor_status = mlx5_rx_descriptor_status,
314 .tx_descriptor_status = mlx5_tx_descriptor_status,
317 /* Available operators in flow isolated mode. */
318 const struct eth_dev_ops mlx5_dev_ops_isolate = {
319 .dev_configure = mlx5_dev_configure,
320 .dev_start = mlx5_dev_start,
321 .dev_stop = mlx5_dev_stop,
322 .dev_set_link_down = mlx5_set_link_down,
323 .dev_set_link_up = mlx5_set_link_up,
324 .dev_close = mlx5_dev_close,
325 .link_update = mlx5_link_update,
326 .stats_get = mlx5_stats_get,
327 .stats_reset = mlx5_stats_reset,
328 .xstats_get = mlx5_xstats_get,
329 .xstats_reset = mlx5_xstats_reset,
330 .xstats_get_names = mlx5_xstats_get_names,
331 .dev_infos_get = mlx5_dev_infos_get,
332 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
333 .vlan_filter_set = mlx5_vlan_filter_set,
334 .rx_queue_setup = mlx5_rx_queue_setup,
335 .tx_queue_setup = mlx5_tx_queue_setup,
336 .rx_queue_release = mlx5_rx_queue_release,
337 .tx_queue_release = mlx5_tx_queue_release,
338 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
339 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
340 .mac_addr_remove = mlx5_mac_addr_remove,
341 .mac_addr_add = mlx5_mac_addr_add,
342 .mac_addr_set = mlx5_mac_addr_set,
343 .mtu_set = mlx5_dev_set_mtu,
344 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
345 .vlan_offload_set = mlx5_vlan_offload_set,
346 .filter_ctrl = mlx5_dev_filter_ctrl,
347 .rx_descriptor_status = mlx5_rx_descriptor_status,
348 .tx_descriptor_status = mlx5_tx_descriptor_status,
349 .rx_queue_intr_enable = mlx5_rx_intr_enable,
350 .rx_queue_intr_disable = mlx5_rx_intr_disable,
354 struct rte_pci_addr pci_addr; /* associated PCI address */
355 uint32_t ports; /* physical ports bitfield. */
359 * Get device index in mlx5_dev[] from PCI bus address.
361 * @param[in] pci_addr
362 * PCI bus address to look for.
365 * mlx5_dev[] index on success, -1 on failure.
368 mlx5_dev_idx(struct rte_pci_addr *pci_addr)
373 assert(pci_addr != NULL);
374 for (i = 0; (i != RTE_DIM(mlx5_dev)); ++i) {
375 if ((mlx5_dev[i].pci_addr.domain == pci_addr->domain) &&
376 (mlx5_dev[i].pci_addr.bus == pci_addr->bus) &&
377 (mlx5_dev[i].pci_addr.devid == pci_addr->devid) &&
378 (mlx5_dev[i].pci_addr.function == pci_addr->function))
380 if ((mlx5_dev[i].ports == 0) && (ret == -1))
387 * Verify and store value for device argument.
390 * Key argument to verify.
392 * Value associated with key.
397 * 0 on success, negative errno value on failure.
400 mlx5_args_check(const char *key, const char *val, void *opaque)
402 struct mlx5_args *args = opaque;
406 tmp = strtoul(val, NULL, 0);
408 WARN("%s: \"%s\" is not a valid integer", key, val);
411 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
412 args->cqe_comp = !!tmp;
413 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
414 args->txq_inline = tmp;
415 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
416 args->txqs_inline = tmp;
417 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
419 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
420 args->mpw_hdr_dseg = !!tmp;
421 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
422 args->inline_max_packet_sz = tmp;
423 } else if (strcmp(MLX5_TSO, key) == 0) {
425 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
426 args->tx_vec_en = !!tmp;
427 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
428 args->rx_vec_en = !!tmp;
430 WARN("%s: unknown parameter", key);
437 * Parse device parameters.
440 * Pointer to private structure.
442 * Device arguments structure.
445 * 0 on success, errno value on failure.
448 mlx5_args(struct mlx5_args *args, struct rte_devargs *devargs)
450 const char **params = (const char *[]){
451 MLX5_RXQ_CQE_COMP_EN,
453 MLX5_TXQS_MIN_INLINE,
455 MLX5_TXQ_MPW_HDR_DSEG_EN,
456 MLX5_TXQ_MAX_INLINE_LEN,
462 struct rte_kvargs *kvlist;
468 /* Following UGLY cast is done to pass checkpatch. */
469 kvlist = rte_kvargs_parse(devargs->args, params);
472 /* Process parameters. */
473 for (i = 0; (params[i] != NULL); ++i) {
474 if (rte_kvargs_count(kvlist, params[i])) {
475 ret = rte_kvargs_process(kvlist, params[i],
476 mlx5_args_check, args);
478 rte_kvargs_free(kvlist);
483 rte_kvargs_free(kvlist);
487 static struct rte_pci_driver mlx5_driver;
490 * Assign parameters from args into priv, only non default
491 * values are considered.
494 * Pointer to private structure.
496 * Pointer to args values.
499 mlx5_args_assign(struct priv *priv, struct mlx5_args *args)
501 if (args->cqe_comp != MLX5_ARG_UNSET)
502 priv->cqe_comp = args->cqe_comp;
503 if (args->txq_inline != MLX5_ARG_UNSET)
504 priv->txq_inline = args->txq_inline;
505 if (args->txqs_inline != MLX5_ARG_UNSET)
506 priv->txqs_inline = args->txqs_inline;
507 if (args->mps != MLX5_ARG_UNSET)
508 priv->mps = args->mps ? priv->mps : 0;
509 if (args->mpw_hdr_dseg != MLX5_ARG_UNSET)
510 priv->mpw_hdr_dseg = args->mpw_hdr_dseg;
511 if (args->inline_max_packet_sz != MLX5_ARG_UNSET)
512 priv->inline_max_packet_sz = args->inline_max_packet_sz;
513 if (args->tso != MLX5_ARG_UNSET)
514 priv->tso = args->tso;
515 if (args->tx_vec_en != MLX5_ARG_UNSET)
516 priv->tx_vec_en = args->tx_vec_en;
517 if (args->rx_vec_en != MLX5_ARG_UNSET)
518 priv->rx_vec_en = args->rx_vec_en;
522 * DPDK callback to register a PCI device.
524 * This function creates an Ethernet device for each port of a given
528 * PCI driver structure (mlx5_driver).
530 * PCI device information.
533 * 0 on success, negative errno value on failure.
536 mlx5_pci_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
538 struct ibv_device **list;
539 struct ibv_device *ibv_dev;
541 struct ibv_context *attr_ctx = NULL;
542 struct ibv_device_attr_ex device_attr;
545 unsigned int cqe_comp;
546 unsigned int tunnel_en = 0;
549 struct mlx5dv_context attrs_out;
550 #ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT
551 struct ibv_counter_set_description cs_desc;
555 assert(pci_drv == &mlx5_driver);
556 /* Get mlx5_dev[] index. */
557 idx = mlx5_dev_idx(&pci_dev->addr);
559 ERROR("this driver cannot support any more adapters");
562 DEBUG("using driver device index %d", idx);
564 /* Save PCI address. */
565 mlx5_dev[idx].pci_addr = pci_dev->addr;
566 list = ibv_get_device_list(&i);
570 ERROR("cannot list devices, is ib_uverbs loaded?");
575 * For each listed device, check related sysfs entry against
576 * the provided PCI ID.
579 struct rte_pci_addr pci_addr;
582 DEBUG("checking device \"%s\"", list[i]->name);
583 if (mlx5_ibv_device_to_pci_addr(list[i], &pci_addr))
585 if ((pci_dev->addr.domain != pci_addr.domain) ||
586 (pci_dev->addr.bus != pci_addr.bus) ||
587 (pci_dev->addr.devid != pci_addr.devid) ||
588 (pci_dev->addr.function != pci_addr.function))
590 sriov = ((pci_dev->id.device_id ==
591 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF) ||
592 (pci_dev->id.device_id ==
593 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF) ||
594 (pci_dev->id.device_id ==
595 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF) ||
596 (pci_dev->id.device_id ==
597 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF));
598 switch (pci_dev->id.device_id) {
599 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
602 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
603 case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
604 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
605 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
606 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
612 INFO("PCI information matches, using device \"%s\""
615 sriov ? "true" : "false");
616 attr_ctx = ibv_open_device(list[i]);
620 if (attr_ctx == NULL) {
621 ibv_free_device_list(list);
624 ERROR("cannot access device, is mlx5_ib loaded?");
627 ERROR("cannot use device, are drivers up to date?");
635 DEBUG("device opened");
637 * Multi-packet send is supported by ConnectX-4 Lx PF as well
638 * as all ConnectX-5 devices.
640 mlx5dv_query_device(attr_ctx, &attrs_out);
641 if (attrs_out.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
642 if (attrs_out.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) {
643 DEBUG("Enhanced MPW is supported");
644 mps = MLX5_MPW_ENHANCED;
646 DEBUG("MPW is supported");
650 DEBUG("MPW isn't supported");
651 mps = MLX5_MPW_DISABLED;
653 if (RTE_CACHE_LINE_SIZE == 128 &&
654 !(attrs_out.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP))
658 if (ibv_query_device_ex(attr_ctx, NULL, &device_attr))
660 INFO("%u port(s) detected", device_attr.orig_attr.phys_port_cnt);
662 for (i = 0; i < device_attr.orig_attr.phys_port_cnt; i++) {
663 uint32_t port = i + 1; /* ports are indexed from one */
664 uint32_t test = (1 << i);
665 struct ibv_context *ctx = NULL;
666 struct ibv_port_attr port_attr;
667 struct ibv_pd *pd = NULL;
668 struct priv *priv = NULL;
669 struct rte_eth_dev *eth_dev;
670 struct ibv_device_attr_ex device_attr_ex;
671 struct ether_addr mac;
672 uint16_t num_vfs = 0;
673 struct ibv_device_attr_ex device_attr;
674 struct mlx5_args args = {
675 .cqe_comp = MLX5_ARG_UNSET,
676 .txq_inline = MLX5_ARG_UNSET,
677 .txqs_inline = MLX5_ARG_UNSET,
678 .mps = MLX5_ARG_UNSET,
679 .mpw_hdr_dseg = MLX5_ARG_UNSET,
680 .inline_max_packet_sz = MLX5_ARG_UNSET,
681 .tso = MLX5_ARG_UNSET,
682 .tx_vec_en = MLX5_ARG_UNSET,
683 .rx_vec_en = MLX5_ARG_UNSET,
686 mlx5_dev[idx].ports |= test;
688 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
689 /* from rte_ethdev.c */
690 char name[RTE_ETH_NAME_MAX_LEN];
692 snprintf(name, sizeof(name), "%s port %u",
693 ibv_get_device_name(ibv_dev), port);
694 eth_dev = rte_eth_dev_attach_secondary(name);
695 if (eth_dev == NULL) {
696 ERROR("can not attach rte ethdev");
700 eth_dev->device = &pci_dev->device;
701 eth_dev->dev_ops = &mlx5_dev_sec_ops;
702 priv = eth_dev->data->dev_private;
703 /* Receive command fd from primary process */
704 err = priv_socket_connect(priv);
709 /* Remap UAR for Tx queues. */
710 err = priv_tx_uar_remap(priv, err);
715 priv_dev_select_rx_function(priv, eth_dev);
716 priv_dev_select_tx_function(priv, eth_dev);
720 DEBUG("using port %u (%08" PRIx32 ")", port, test);
722 ctx = ibv_open_device(ibv_dev);
728 ibv_query_device_ex(ctx, NULL, &device_attr);
729 /* Check port status. */
730 err = ibv_query_port(ctx, port, &port_attr);
732 ERROR("port query failed: %s", strerror(err));
736 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
737 ERROR("port %d is not configured in Ethernet mode",
743 if (port_attr.state != IBV_PORT_ACTIVE)
744 DEBUG("port %d is not active: \"%s\" (%d)",
745 port, ibv_port_state_str(port_attr.state),
748 /* Allocate protection domain. */
749 pd = ibv_alloc_pd(ctx);
751 ERROR("PD allocation failure");
756 mlx5_dev[idx].ports |= test;
758 /* from rte_ethdev.c */
759 priv = rte_zmalloc("ethdev private structure",
761 RTE_CACHE_LINE_SIZE);
763 ERROR("priv allocation failure");
769 strncpy(priv->ibdev_path, priv->ctx->device->ibdev_path,
770 sizeof(priv->ibdev_path));
771 priv->device_attr = device_attr;
774 priv->mtu = ETHER_MTU;
775 priv->mps = mps; /* Enable MPW by default if supported. */
776 priv->cqe_comp = cqe_comp;
777 priv->tunnel_en = tunnel_en;
778 /* Enable vector by default if supported. */
781 err = mlx5_args(&args, pci_dev->device.devargs);
783 ERROR("failed to process device arguments: %s",
787 mlx5_args_assign(priv, &args);
788 if (ibv_query_device_ex(ctx, NULL, &device_attr_ex)) {
789 ERROR("ibv_query_device_ex() failed");
794 !!(device_attr_ex.device_cap_flags_ex &
795 IBV_DEVICE_RAW_IP_CSUM);
796 DEBUG("checksum offloading is %ssupported",
797 (priv->hw_csum ? "" : "not "));
799 #ifdef HAVE_IBV_DEVICE_VXLAN_SUPPORT
800 priv->hw_csum_l2tun = !!(exp_device_attr.exp_device_cap_flags &
801 IBV_DEVICE_VXLAN_SUPPORT);
803 DEBUG("Rx L2 tunnel checksum offloads are %ssupported",
804 (priv->hw_csum_l2tun ? "" : "not "));
806 #ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT
807 priv->counter_set_supported = !!(device_attr.max_counter_sets);
808 ibv_describe_counter_set(ctx, 0, &cs_desc);
809 DEBUG("counter type = %d, num of cs = %ld, attributes = %d",
810 cs_desc.counter_type, cs_desc.num_of_cs,
813 priv->ind_table_max_size =
814 device_attr_ex.rss_caps.max_rwq_indirection_table_size;
815 /* Remove this check once DPDK supports larger/variable
816 * indirection tables. */
817 if (priv->ind_table_max_size >
818 (unsigned int)ETH_RSS_RETA_SIZE_512)
819 priv->ind_table_max_size = ETH_RSS_RETA_SIZE_512;
820 DEBUG("maximum RX indirection table size is %u",
821 priv->ind_table_max_size);
822 priv->hw_vlan_strip = !!(device_attr_ex.raw_packet_caps &
823 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
824 DEBUG("VLAN stripping is %ssupported",
825 (priv->hw_vlan_strip ? "" : "not "));
828 !!(device_attr_ex.orig_attr.device_cap_flags &
829 IBV_WQ_FLAGS_SCATTER_FCS);
830 DEBUG("FCS stripping configuration is %ssupported",
831 (priv->hw_fcs_strip ? "" : "not "));
833 #ifdef HAVE_IBV_WQ_FLAG_RX_END_PADDING
834 priv->hw_padding = !!device_attr_ex.rx_pad_end_addr_align;
836 DEBUG("hardware RX end alignment padding is %ssupported",
837 (priv->hw_padding ? "" : "not "));
839 priv_get_num_vfs(priv, &num_vfs);
840 priv->sriov = (num_vfs || sriov);
841 priv->tso = ((priv->tso) &&
842 (device_attr_ex.tso_caps.max_tso > 0) &&
843 (device_attr_ex.tso_caps.supported_qpts &
844 (1 << IBV_QPT_RAW_PACKET)));
846 priv->max_tso_payload_sz =
847 device_attr_ex.tso_caps.max_tso;
848 if (priv->mps && !mps) {
849 ERROR("multi-packet send not supported on this device"
850 " (" MLX5_TXQ_MPW_EN ")");
853 } else if (priv->mps && priv->tso) {
854 WARN("multi-packet send not supported in conjunction "
855 "with TSO. MPS disabled");
859 priv->mps == MLX5_MPW_ENHANCED ? "Enhanced " : "",
860 priv->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled");
861 /* Set default values for Enhanced MPW, a.k.a MPWv2. */
862 if (priv->mps == MLX5_MPW_ENHANCED) {
863 if (args.txqs_inline == MLX5_ARG_UNSET)
864 priv->txqs_inline = MLX5_EMPW_MIN_TXQS;
865 if (args.inline_max_packet_sz == MLX5_ARG_UNSET)
866 priv->inline_max_packet_sz =
867 MLX5_EMPW_MAX_INLINE_LEN;
868 if (args.txq_inline == MLX5_ARG_UNSET)
869 priv->txq_inline = MLX5_WQE_SIZE_MAX -
872 if (priv->cqe_comp && !cqe_comp) {
873 WARN("Rx CQE compression isn't supported");
876 /* Configure the first MAC address by default. */
877 if (priv_get_mac(priv, &mac.addr_bytes)) {
878 ERROR("cannot get MAC address, is mlx5_en loaded?"
879 " (errno: %s)", strerror(errno));
883 INFO("port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x",
885 mac.addr_bytes[0], mac.addr_bytes[1],
886 mac.addr_bytes[2], mac.addr_bytes[3],
887 mac.addr_bytes[4], mac.addr_bytes[5]);
890 char ifname[IF_NAMESIZE];
892 if (priv_get_ifname(priv, &ifname) == 0)
893 DEBUG("port %u ifname is \"%s\"",
896 DEBUG("port %u ifname is unknown", priv->port);
899 /* Get actual MTU if possible. */
900 priv_get_mtu(priv, &priv->mtu);
901 DEBUG("port %u MTU is %u", priv->port, priv->mtu);
903 /* from rte_ethdev.c */
905 char name[RTE_ETH_NAME_MAX_LEN];
907 snprintf(name, sizeof(name), "%s port %u",
908 ibv_get_device_name(ibv_dev), port);
909 eth_dev = rte_eth_dev_allocate(name);
911 if (eth_dev == NULL) {
912 ERROR("can not allocate rte ethdev");
916 eth_dev->data->dev_private = priv;
917 eth_dev->data->mac_addrs = priv->mac;
918 eth_dev->device = &pci_dev->device;
919 rte_eth_copy_pci_info(eth_dev, pci_dev);
920 eth_dev->device->driver = &mlx5_driver.driver;
922 eth_dev->dev_ops = &mlx5_dev_ops;
923 /* Register MAC address. */
924 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
925 TAILQ_INIT(&priv->flows);
926 TAILQ_INIT(&priv->ctrl_flows);
928 /* Hint libmlx5 to use PMD allocator for data plane resources */
929 struct mlx5dv_ctx_allocators alctr = {
930 .alloc = &mlx5_alloc_verbs_buf,
931 .free = &mlx5_free_verbs_buf,
934 mlx5dv_set_context_attr(ctx, MLX5DV_CTX_ATTR_BUF_ALLOCATORS,
935 (void *)((uintptr_t)&alctr));
937 /* Bring Ethernet device up. */
938 DEBUG("forcing Ethernet interface up");
939 priv_set_flags(priv, ~IFF_UP, IFF_UP);
940 mlx5_link_update(priv->dev, 1);
947 claim_zero(ibv_dealloc_pd(pd));
949 claim_zero(ibv_close_device(ctx));
954 * XXX if something went wrong in the loop above, there is a resource
955 * leak (ctx, pd, priv, dpdk ethdev) but we can do nothing about it as
956 * long as the dpdk does not provide a way to deallocate a ethdev and a
957 * way to enumerate the registered ethdevs to free the previous ones.
960 /* no port found, complain */
961 if (!mlx5_dev[idx].ports) {
968 claim_zero(ibv_close_device(attr_ctx));
970 ibv_free_device_list(list);
975 static const struct rte_pci_id mlx5_pci_id_map[] = {
977 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
978 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
981 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
982 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
985 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
986 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
989 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
990 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
993 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
994 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
997 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
998 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
1001 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1002 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
1005 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1006 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
1013 static struct rte_pci_driver mlx5_driver = {
1015 .name = MLX5_DRIVER_NAME
1017 .id_table = mlx5_pci_id_map,
1018 .probe = mlx5_pci_probe,
1019 .drv_flags = RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV,
1023 * Driver initialization routine.
1025 RTE_INIT(rte_mlx5_pmd_init);
1027 rte_mlx5_pmd_init(void)
1029 /* Build the static table for ptype conversion. */
1030 mlx5_set_ptype_table();
1032 * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use
1033 * huge pages. Calling ibv_fork_init() during init allows
1034 * applications to use fork() safely for purposes other than
1035 * using this PMD, which is not supported in forked processes.
1037 setenv("RDMAV_HUGEPAGES_SAFE", "1", 1);
1038 /* Match the size of Rx completion entry to the size of a cacheline. */
1039 if (RTE_CACHE_LINE_SIZE == 128)
1040 setenv("MLX5_CQE_SIZE", "128", 0);
1042 rte_pci_register(&mlx5_driver);
1045 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
1046 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
1047 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");