drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <stdint.h>
  10 #include <stdlib.h>
  11 #include <errno.h>
  12
  13 #include <rte_malloc.h>
  14 #include <ethdev_driver.h>
  15 #include <rte_pci.h>
  16 #include <rte_bus_pci.h>
  17 #include <rte_common.h>
  18 #include <rte_kvargs.h>
  19 #include <rte_rwlock.h>
  20 #include <rte_spinlock.h>
  21 #include <rte_string_fns.h>
  22 #include <rte_alarm.h>
  23 #include <rte_cycles.h>
  24
  25 #include <mlx5_glue.h>
  26 #include <mlx5_devx_cmds.h>
  27 #include <mlx5_common.h>
  28 #include <mlx5_common_os.h>
  29 #include <mlx5_common_mp.h>
  30 #include <mlx5_malloc.h>
  31
  32 #include "mlx5_defs.h"
  33 #include "mlx5.h"
  34 #include "mlx5_utils.h"
  35 #include "mlx5_rxtx.h"
  36 #include "mlx5_rx.h"
  37 #include "mlx5_tx.h"
  38 #include "mlx5_autoconf.h"
  39 #include "mlx5_flow.h"
  40 #include "mlx5_flow_os.h"
  41 #include "rte_pmd_mlx5.h"
  42
  43 #define MLX5_ETH_DRIVER_NAME mlx5_eth
  44
  45 /* Driver type key for new device global syntax. */
  46 #define MLX5_DRIVER_KEY "driver"
  47
  48 /* Device parameter to enable RX completion queue compression. */
  49 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  50
  51 /* Device parameter to enable padding Rx packet to cacheline size. */
  52 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
  53
  54 /* Device parameter to enable Multi-Packet Rx queue. */
  55 #define MLX5_RX_MPRQ_EN "mprq_en"
  56
  57 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
  58 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
  59
  60 /* Device parameter to configure log 2 of the stride size for MPRQ. */
  61 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
  62
  63 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
  64 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
  65
  66 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
  67 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
  68
  69 /* Device parameter to configure inline send. Deprecated, ignored.*/
  70 #define MLX5_TXQ_INLINE "txq_inline"
  71
  72 /* Device parameter to limit packet size to inline with ordinary SEND. */
  73 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
  74
  75 /* Device parameter to configure minimal data size to inline. */
  76 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
  77
  78 /* Device parameter to limit packet size to inline with Enhanced MPW. */
  79 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
  80
  81 /*
  82  * Device parameter to configure the number of TX queues threshold for
  83  * enabling inline send.
  84  */
  85 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  86
  87 /*
  88  * Device parameter to configure the number of TX queues threshold for
  89  * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
  90  */
  91 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
  92
  93 /* Device parameter to enable multi-packet send WQEs. */
  94 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
  95
  96 /*
  97  * Device parameter to force doorbell register mapping
  98  * to non-cahed region eliminating the extra write memory barrier.
  99  */
 100 #define MLX5_TX_DB_NC "tx_db_nc"
 101
 102 /*
 103  * Device parameter to include 2 dsegs in the title WQEBB.
 104  * Deprecated, ignored.
 105  */
 106 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
 107
 108 /*
 109  * Device parameter to limit the size of inlining packet.
 110  * Deprecated, ignored.
 111  */
 112 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
 113
 114 /*
 115  * Device parameter to enable Tx scheduling on timestamps
 116  * and specify the packet pacing granularity in nanoseconds.
 117  */
 118 #define MLX5_TX_PP "tx_pp"
 119
 120 /*
 121  * Device parameter to specify skew in nanoseconds on Tx datapath,
 122  * it represents the time between SQ start WQE processing and
 123  * appearing actual packet data on the wire.
 124  */
 125 #define MLX5_TX_SKEW "tx_skew"
 126
 127 /*
 128  * Device parameter to enable hardware Tx vector.
 129  * Deprecated, ignored (no vectorized Tx routines anymore).
 130  */
 131 #define MLX5_TX_VEC_EN "tx_vec_en"
 132
 133 /* Device parameter to enable hardware Rx vector. */
 134 #define MLX5_RX_VEC_EN "rx_vec_en"
 135
 136 /* Allow L3 VXLAN flow creation. */
 137 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
 138
 139 /* Activate DV E-Switch flow steering. */
 140 #define MLX5_DV_ESW_EN "dv_esw_en"
 141
 142 /* Activate DV flow steering. */
 143 #define MLX5_DV_FLOW_EN "dv_flow_en"
 144
 145 /* Enable extensive flow metadata support. */
 146 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
 147
 148 /* Device parameter to let the user manage the lacp traffic of bonded device */
 149 #define MLX5_LACP_BY_USER "lacp_by_user"
 150
 151 /* Activate Netlink support in VF mode. */
 152 #define MLX5_VF_NL_EN "vf_nl_en"
 153
 154 /* Enable extending memsegs when creating a MR. */
 155 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
 156
 157 /* Select port representors to instantiate. */
 158 #define MLX5_REPRESENTOR "representor"
 159
 160 /* Device parameter to configure the maximum number of dump files per queue. */
 161 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
 162
 163 /* Configure timeout of LRO session (in microseconds). */
 164 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
 165
 166 /*
 167  * Device parameter to configure the total data buffer size for a single
 168  * hairpin queue (logarithm value).
 169  */
 170 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
 171
 172 /* Flow memory reclaim mode. */
 173 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
 174
 175 /* The default memory allocator used in PMD. */
 176 #define MLX5_SYS_MEM_EN "sys_mem_en"
 177 /* Decap will be used or not. */
 178 #define MLX5_DECAP_EN "decap_en"
 179
 180 /* Device parameter to configure allow or prevent duplicate rules pattern. */
 181 #define MLX5_ALLOW_DUPLICATE_PATTERN "allow_duplicate_pattern"
 182
 183 /* Device parameter to configure implicit registration of mempool memory. */
 184 #define MLX5_MR_MEMPOOL_REG_EN "mr_mempool_reg_en"
 185
 186 /* Shared memory between primary and secondary processes. */
 187 struct mlx5_shared_data *mlx5_shared_data;
 188
 189 /** Driver-specific log messages type. */
 190 int mlx5_logtype;
 191
 192 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
 193                                                 LIST_HEAD_INITIALIZER();
 194 static pthread_mutex_t mlx5_dev_ctx_list_mutex;
 195 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
 196 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
 197         [MLX5_IPOOL_DECAP_ENCAP] = {
 198                 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
 199                 .trunk_size = 64,
 200                 .grow_trunk = 3,
 201                 .grow_shift = 2,
 202                 .need_lock = 1,
 203                 .release_mem_en = 1,
 204                 .malloc = mlx5_malloc,
 205                 .free = mlx5_free,
 206                 .type = "mlx5_encap_decap_ipool",
 207         },
 208         [MLX5_IPOOL_PUSH_VLAN] = {
 209                 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
 210                 .trunk_size = 64,
 211                 .grow_trunk = 3,
 212                 .grow_shift = 2,
 213                 .need_lock = 1,
 214                 .release_mem_en = 1,
 215                 .malloc = mlx5_malloc,
 216                 .free = mlx5_free,
 217                 .type = "mlx5_push_vlan_ipool",
 218         },
 219         [MLX5_IPOOL_TAG] = {
 220                 .size = sizeof(struct mlx5_flow_dv_tag_resource),
 221                 .trunk_size = 64,
 222                 .grow_trunk = 3,
 223                 .grow_shift = 2,
 224                 .need_lock = 1,
 225                 .release_mem_en = 0,
 226                 .per_core_cache = (1 << 16),
 227                 .malloc = mlx5_malloc,
 228                 .free = mlx5_free,
 229                 .type = "mlx5_tag_ipool",
 230         },
 231         [MLX5_IPOOL_PORT_ID] = {
 232                 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
 233                 .trunk_size = 64,
 234                 .grow_trunk = 3,
 235                 .grow_shift = 2,
 236                 .need_lock = 1,
 237                 .release_mem_en = 1,
 238                 .malloc = mlx5_malloc,
 239                 .free = mlx5_free,
 240                 .type = "mlx5_port_id_ipool",
 241         },
 242         [MLX5_IPOOL_JUMP] = {
 243                 .size = sizeof(struct mlx5_flow_tbl_data_entry),
 244                 .trunk_size = 64,
 245                 .grow_trunk = 3,
 246                 .grow_shift = 2,
 247                 .need_lock = 1,
 248                 .release_mem_en = 1,
 249                 .malloc = mlx5_malloc,
 250                 .free = mlx5_free,
 251                 .type = "mlx5_jump_ipool",
 252         },
 253         [MLX5_IPOOL_SAMPLE] = {
 254                 .size = sizeof(struct mlx5_flow_dv_sample_resource),
 255                 .trunk_size = 64,
 256                 .grow_trunk = 3,
 257                 .grow_shift = 2,
 258                 .need_lock = 1,
 259                 .release_mem_en = 1,
 260                 .malloc = mlx5_malloc,
 261                 .free = mlx5_free,
 262                 .type = "mlx5_sample_ipool",
 263         },
 264         [MLX5_IPOOL_DEST_ARRAY] = {
 265                 .size = sizeof(struct mlx5_flow_dv_dest_array_resource),
 266                 .trunk_size = 64,
 267                 .grow_trunk = 3,
 268                 .grow_shift = 2,
 269                 .need_lock = 1,
 270                 .release_mem_en = 1,
 271                 .malloc = mlx5_malloc,
 272                 .free = mlx5_free,
 273                 .type = "mlx5_dest_array_ipool",
 274         },
 275         [MLX5_IPOOL_TUNNEL_ID] = {
 276                 .size = sizeof(struct mlx5_flow_tunnel),
 277                 .trunk_size = MLX5_MAX_TUNNELS,
 278                 .need_lock = 1,
 279                 .release_mem_en = 1,
 280                 .type = "mlx5_tunnel_offload",
 281         },
 282         [MLX5_IPOOL_TNL_TBL_ID] = {
 283                 .size = 0,
 284                 .need_lock = 1,
 285                 .type = "mlx5_flow_tnl_tbl_ipool",
 286         },
 287 #endif
 288         [MLX5_IPOOL_MTR] = {
 289                 /**
 290                  * The ipool index should grow continually from small to big,
 291                  * for meter idx, so not set grow_trunk to avoid meter index
 292                  * not jump continually.
 293                  */
 294                 .size = sizeof(struct mlx5_legacy_flow_meter),
 295                 .trunk_size = 64,
 296                 .need_lock = 1,
 297                 .release_mem_en = 1,
 298                 .malloc = mlx5_malloc,
 299                 .free = mlx5_free,
 300                 .type = "mlx5_meter_ipool",
 301         },
 302         [MLX5_IPOOL_MCP] = {
 303                 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
 304                 .trunk_size = 64,
 305                 .grow_trunk = 3,
 306                 .grow_shift = 2,
 307                 .need_lock = 1,
 308                 .release_mem_en = 1,
 309                 .malloc = mlx5_malloc,
 310                 .free = mlx5_free,
 311                 .type = "mlx5_mcp_ipool",
 312         },
 313         [MLX5_IPOOL_HRXQ] = {
 314                 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
 315                 .trunk_size = 64,
 316                 .grow_trunk = 3,
 317                 .grow_shift = 2,
 318                 .need_lock = 1,
 319                 .release_mem_en = 1,
 320                 .malloc = mlx5_malloc,
 321                 .free = mlx5_free,
 322                 .type = "mlx5_hrxq_ipool",
 323         },
 324         [MLX5_IPOOL_MLX5_FLOW] = {
 325                 /*
 326                  * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
 327                  * It set in run time according to PCI function configuration.
 328                  */
 329                 .size = 0,
 330                 .trunk_size = 64,
 331                 .grow_trunk = 3,
 332                 .grow_shift = 2,
 333                 .need_lock = 1,
 334                 .release_mem_en = 0,
 335                 .per_core_cache = 1 << 19,
 336                 .malloc = mlx5_malloc,
 337                 .free = mlx5_free,
 338                 .type = "mlx5_flow_handle_ipool",
 339         },
 340         [MLX5_IPOOL_RTE_FLOW] = {
 341                 .size = sizeof(struct rte_flow),
 342                 .trunk_size = 4096,
 343                 .need_lock = 1,
 344                 .release_mem_en = 1,
 345                 .malloc = mlx5_malloc,
 346                 .free = mlx5_free,
 347                 .type = "rte_flow_ipool",
 348         },
 349         [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID] = {
 350                 .size = 0,
 351                 .need_lock = 1,
 352                 .type = "mlx5_flow_rss_id_ipool",
 353         },
 354         [MLX5_IPOOL_RSS_SHARED_ACTIONS] = {
 355                 .size = sizeof(struct mlx5_shared_action_rss),
 356                 .trunk_size = 64,
 357                 .grow_trunk = 3,
 358                 .grow_shift = 2,
 359                 .need_lock = 1,
 360                 .release_mem_en = 1,
 361                 .malloc = mlx5_malloc,
 362                 .free = mlx5_free,
 363                 .type = "mlx5_shared_action_rss",
 364         },
 365         [MLX5_IPOOL_MTR_POLICY] = {
 366                 /**
 367                  * The ipool index should grow continually from small to big,
 368                  * for policy idx, so not set grow_trunk to avoid policy index
 369                  * not jump continually.
 370                  */
 371                 .size = sizeof(struct mlx5_flow_meter_sub_policy),
 372                 .trunk_size = 64,
 373                 .need_lock = 1,
 374                 .release_mem_en = 1,
 375                 .malloc = mlx5_malloc,
 376                 .free = mlx5_free,
 377                 .type = "mlx5_meter_policy_ipool",
 378         },
 379 };
 380
 381
 382 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
 383 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
 384
 385 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 1024
 386
 387 /**
 388  * Decide whether representor ID is a HPF(host PF) port on BF2.
 389  *
 390  * @param dev
 391  *   Pointer to Ethernet device structure.
 392  *
 393  * @return
 394  *   Non-zero if HPF, otherwise 0.
 395  */
 396 bool
 397 mlx5_is_hpf(struct rte_eth_dev *dev)
 398 {
 399         struct mlx5_priv *priv = dev->data->dev_private;
 400         uint16_t repr = MLX5_REPRESENTOR_REPR(priv->representor_id);
 401         int type = MLX5_REPRESENTOR_TYPE(priv->representor_id);
 402
 403         return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_VF &&
 404                MLX5_REPRESENTOR_REPR(-1) == repr;
 405 }
 406
 407 /**
 408  * Decide whether representor ID is a SF port representor.
 409  *
 410  * @param dev
 411  *   Pointer to Ethernet device structure.
 412  *
 413  * @return
 414  *   Non-zero if HPF, otherwise 0.
 415  */
 416 bool
 417 mlx5_is_sf_repr(struct rte_eth_dev *dev)
 418 {
 419         struct mlx5_priv *priv = dev->data->dev_private;
 420         int type = MLX5_REPRESENTOR_TYPE(priv->representor_id);
 421
 422         return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_SF;
 423 }
 424
 425 /**
 426  * Initialize the ASO aging management structure.
 427  *
 428  * @param[in] sh
 429  *   Pointer to mlx5_dev_ctx_shared object to free
 430  *
 431  * @return
 432  *   0 on success, a negative errno value otherwise and rte_errno is set.
 433  */
 434 int
 435 mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh)
 436 {
 437         int err;
 438
 439         if (sh->aso_age_mng)
 440                 return 0;
 441         sh->aso_age_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->aso_age_mng),
 442                                       RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 443         if (!sh->aso_age_mng) {
 444                 DRV_LOG(ERR, "aso_age_mng allocation was failed.");
 445                 rte_errno = ENOMEM;
 446                 return -ENOMEM;
 447         }
 448         err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_FLOW_HIT);
 449         if (err) {
 450                 mlx5_free(sh->aso_age_mng);
 451                 return -1;
 452         }
 453         rte_rwlock_init(&sh->aso_age_mng->resize_rwl);
 454         rte_spinlock_init(&sh->aso_age_mng->free_sl);
 455         LIST_INIT(&sh->aso_age_mng->free);
 456         return 0;
 457 }
 458
 459 /**
 460  * Close and release all the resources of the ASO aging management structure.
 461  *
 462  * @param[in] sh
 463  *   Pointer to mlx5_dev_ctx_shared object to free.
 464  */
 465 static void
 466 mlx5_flow_aso_age_mng_close(struct mlx5_dev_ctx_shared *sh)
 467 {
 468         int i, j;
 469
 470         mlx5_aso_flow_hit_queue_poll_stop(sh);
 471         mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_FLOW_HIT);
 472         if (sh->aso_age_mng->pools) {
 473                 struct mlx5_aso_age_pool *pool;
 474
 475                 for (i = 0; i < sh->aso_age_mng->next; ++i) {
 476                         pool = sh->aso_age_mng->pools[i];
 477                         claim_zero(mlx5_devx_cmd_destroy
 478                                                 (pool->flow_hit_aso_obj));
 479                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j)
 480                                 if (pool->actions[j].dr_action)
 481                                         claim_zero
 482                                             (mlx5_flow_os_destroy_flow_action
 483                                               (pool->actions[j].dr_action));
 484                         mlx5_free(pool);
 485                 }
 486                 mlx5_free(sh->aso_age_mng->pools);
 487         }
 488         mlx5_free(sh->aso_age_mng);
 489 }
 490
 491 /**
 492  * Initialize the shared aging list information per port.
 493  *
 494  * @param[in] sh
 495  *   Pointer to mlx5_dev_ctx_shared object.
 496  */
 497 static void
 498 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
 499 {
 500         uint32_t i;
 501         struct mlx5_age_info *age_info;
 502
 503         for (i = 0; i < sh->max_port; i++) {
 504                 age_info = &sh->port[i].age_info;
 505                 age_info->flags = 0;
 506                 TAILQ_INIT(&age_info->aged_counters);
 507                 LIST_INIT(&age_info->aged_aso);
 508                 rte_spinlock_init(&age_info->aged_sl);
 509                 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
 510         }
 511 }
 512
 513 /**
 514  * Initialize the counters management structure.
 515  *
 516  * @param[in] sh
 517  *   Pointer to mlx5_dev_ctx_shared object to free
 518  */
 519 static void
 520 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
 521 {
 522         struct mlx5_hca_attr *attr = &sh->cdev->config.hca_attr;
 523         int i;
 524
 525         memset(&sh->cmng, 0, sizeof(sh->cmng));
 526         TAILQ_INIT(&sh->cmng.flow_counters);
 527         sh->cmng.min_id = MLX5_CNT_BATCH_OFFSET;
 528         sh->cmng.max_id = -1;
 529         sh->cmng.last_pool_idx = POOL_IDX_INVALID;
 530         rte_spinlock_init(&sh->cmng.pool_update_sl);
 531         for (i = 0; i < MLX5_COUNTER_TYPE_MAX; i++) {
 532                 TAILQ_INIT(&sh->cmng.counters[i]);
 533                 rte_spinlock_init(&sh->cmng.csl[i]);
 534         }
 535         if (sh->devx && !haswell_broadwell_cpu) {
 536                 sh->cmng.relaxed_ordering_write = attr->relaxed_ordering_write;
 537                 sh->cmng.relaxed_ordering_read = attr->relaxed_ordering_read;
 538         }
 539 }
 540
 541 /**
 542  * Destroy all the resources allocated for a counter memory management.
 543  *
 544  * @param[in] mng
 545  *   Pointer to the memory management structure.
 546  */
 547 static void
 548 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
 549 {
 550         uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
 551
 552         LIST_REMOVE(mng, next);
 553         claim_zero(mlx5_devx_cmd_destroy(mng->dm));
 554         claim_zero(mlx5_os_umem_dereg(mng->umem));
 555         mlx5_free(mem);
 556 }
 557
 558 /**
 559  * Close and release all the resources of the counters management.
 560  *
 561  * @param[in] sh
 562  *   Pointer to mlx5_dev_ctx_shared object to free.
 563  */
 564 static void
 565 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
 566 {
 567         struct mlx5_counter_stats_mem_mng *mng;
 568         int i, j;
 569         int retries = 1024;
 570
 571         rte_errno = 0;
 572         while (--retries) {
 573                 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
 574                 if (rte_errno != EINPROGRESS)
 575                         break;
 576                 rte_pause();
 577         }
 578
 579         if (sh->cmng.pools) {
 580                 struct mlx5_flow_counter_pool *pool;
 581                 uint16_t n_valid = sh->cmng.n_valid;
 582                 bool fallback = sh->cmng.counter_fallback;
 583
 584                 for (i = 0; i < n_valid; ++i) {
 585                         pool = sh->cmng.pools[i];
 586                         if (!fallback && pool->min_dcs)
 587                                 claim_zero(mlx5_devx_cmd_destroy
 588                                                                (pool->min_dcs));
 589                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
 590                                 struct mlx5_flow_counter *cnt =
 591                                                 MLX5_POOL_GET_CNT(pool, j);
 592
 593                                 if (cnt->action)
 594                                         claim_zero
 595                                          (mlx5_flow_os_destroy_flow_action
 596                                           (cnt->action));
 597                                 if (fallback && MLX5_POOL_GET_CNT
 598                                     (pool, j)->dcs_when_free)
 599                                         claim_zero(mlx5_devx_cmd_destroy
 600                                                    (cnt->dcs_when_free));
 601                         }
 602                         mlx5_free(pool);
 603                 }
 604                 mlx5_free(sh->cmng.pools);
 605         }
 606         mng = LIST_FIRST(&sh->cmng.mem_mngs);
 607         while (mng) {
 608                 mlx5_flow_destroy_counter_stat_mem_mng(mng);
 609                 mng = LIST_FIRST(&sh->cmng.mem_mngs);
 610         }
 611         memset(&sh->cmng, 0, sizeof(sh->cmng));
 612 }
 613
 614 /**
 615  * Initialize the aso flow meters management structure.
 616  *
 617  * @param[in] sh
 618  *   Pointer to mlx5_dev_ctx_shared object to free
 619  */
 620 int
 621 mlx5_aso_flow_mtrs_mng_init(struct mlx5_dev_ctx_shared *sh)
 622 {
 623         if (!sh->mtrmng) {
 624                 sh->mtrmng = mlx5_malloc(MLX5_MEM_ZERO,
 625                         sizeof(*sh->mtrmng),
 626                         RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 627                 if (!sh->mtrmng) {
 628                         DRV_LOG(ERR,
 629                         "meter management allocation was failed.");
 630                         rte_errno = ENOMEM;
 631                         return -ENOMEM;
 632                 }
 633                 if (sh->meter_aso_en) {
 634                         rte_spinlock_init(&sh->mtrmng->pools_mng.mtrsl);
 635                         rte_rwlock_init(&sh->mtrmng->pools_mng.resize_mtrwl);
 636                         LIST_INIT(&sh->mtrmng->pools_mng.meters);
 637                 }
 638                 sh->mtrmng->def_policy_id = MLX5_INVALID_POLICY_ID;
 639         }
 640         return 0;
 641 }
 642
 643 /**
 644  * Close and release all the resources of
 645  * the ASO flow meter management structure.
 646  *
 647  * @param[in] sh
 648  *   Pointer to mlx5_dev_ctx_shared object to free.
 649  */
 650 static void
 651 mlx5_aso_flow_mtrs_mng_close(struct mlx5_dev_ctx_shared *sh)
 652 {
 653         struct mlx5_aso_mtr_pool *mtr_pool;
 654         struct mlx5_flow_mtr_mng *mtrmng = sh->mtrmng;
 655         uint32_t idx;
 656 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
 657         struct mlx5_aso_mtr *aso_mtr;
 658         int i;
 659 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
 660
 661         if (sh->meter_aso_en) {
 662                 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_POLICER);
 663                 idx = mtrmng->pools_mng.n_valid;
 664                 while (idx--) {
 665                         mtr_pool = mtrmng->pools_mng.pools[idx];
 666 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
 667                         for (i = 0; i < MLX5_ASO_MTRS_PER_POOL; i++) {
 668                                 aso_mtr = &mtr_pool->mtrs[i];
 669                                 if (aso_mtr->fm.meter_action)
 670                                         claim_zero
 671                                         (mlx5_glue->destroy_flow_action
 672                                         (aso_mtr->fm.meter_action));
 673                         }
 674 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
 675                         claim_zero(mlx5_devx_cmd_destroy
 676                                                 (mtr_pool->devx_obj));
 677                         mtrmng->pools_mng.n_valid--;
 678                         mlx5_free(mtr_pool);
 679                 }
 680                 mlx5_free(sh->mtrmng->pools_mng.pools);
 681         }
 682         mlx5_free(sh->mtrmng);
 683         sh->mtrmng = NULL;
 684 }
 685
 686 /* Send FLOW_AGED event if needed. */
 687 void
 688 mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh)
 689 {
 690         struct mlx5_age_info *age_info;
 691         uint32_t i;
 692
 693         for (i = 0; i < sh->max_port; i++) {
 694                 age_info = &sh->port[i].age_info;
 695                 if (!MLX5_AGE_GET(age_info, MLX5_AGE_EVENT_NEW))
 696                         continue;
 697                 MLX5_AGE_UNSET(age_info, MLX5_AGE_EVENT_NEW);
 698                 if (MLX5_AGE_GET(age_info, MLX5_AGE_TRIGGER)) {
 699                         MLX5_AGE_UNSET(age_info, MLX5_AGE_TRIGGER);
 700                         rte_eth_dev_callback_process
 701                                 (&rte_eth_devices[sh->port[i].devx_ih_port_id],
 702                                 RTE_ETH_EVENT_FLOW_AGED, NULL);
 703                 }
 704         }
 705 }
 706
 707 /*
 708  * Initialize the ASO connection tracking structure.
 709  *
 710  * @param[in] sh
 711  *   Pointer to mlx5_dev_ctx_shared object.
 712  *
 713  * @return
 714  *   0 on success, a negative errno value otherwise and rte_errno is set.
 715  */
 716 int
 717 mlx5_flow_aso_ct_mng_init(struct mlx5_dev_ctx_shared *sh)
 718 {
 719         int err;
 720
 721         if (sh->ct_mng)
 722                 return 0;
 723         sh->ct_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->ct_mng),
 724                                  RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 725         if (!sh->ct_mng) {
 726                 DRV_LOG(ERR, "ASO CT management allocation failed.");
 727                 rte_errno = ENOMEM;
 728                 return -rte_errno;
 729         }
 730         err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_CONNECTION_TRACKING);
 731         if (err) {
 732                 mlx5_free(sh->ct_mng);
 733                 /* rte_errno should be extracted from the failure. */
 734                 rte_errno = EINVAL;
 735                 return -rte_errno;
 736         }
 737         rte_spinlock_init(&sh->ct_mng->ct_sl);
 738         rte_rwlock_init(&sh->ct_mng->resize_rwl);
 739         LIST_INIT(&sh->ct_mng->free_cts);
 740         return 0;
 741 }
 742
 743 /*
 744  * Close and release all the resources of the
 745  * ASO connection tracking management structure.
 746  *
 747  * @param[in] sh
 748  *   Pointer to mlx5_dev_ctx_shared object to free.
 749  */
 750 static void
 751 mlx5_flow_aso_ct_mng_close(struct mlx5_dev_ctx_shared *sh)
 752 {
 753         struct mlx5_aso_ct_pools_mng *mng = sh->ct_mng;
 754         struct mlx5_aso_ct_pool *ct_pool;
 755         struct mlx5_aso_ct_action *ct;
 756         uint32_t idx;
 757         uint32_t val;
 758         uint32_t cnt;
 759         int i;
 760
 761         mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_CONNECTION_TRACKING);
 762         idx = mng->next;
 763         while (idx--) {
 764                 cnt = 0;
 765                 ct_pool = mng->pools[idx];
 766                 for (i = 0; i < MLX5_ASO_CT_ACTIONS_PER_POOL; i++) {
 767                         ct = &ct_pool->actions[i];
 768                         val = __atomic_fetch_sub(&ct->refcnt, 1,
 769                                                  __ATOMIC_RELAXED);
 770                         MLX5_ASSERT(val == 1);
 771                         if (val > 1)
 772                                 cnt++;
 773 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
 774                         if (ct->dr_action_orig)
 775                                 claim_zero(mlx5_glue->destroy_flow_action
 776                                                         (ct->dr_action_orig));
 777                         if (ct->dr_action_rply)
 778                                 claim_zero(mlx5_glue->destroy_flow_action
 779                                                         (ct->dr_action_rply));
 780 #endif
 781                 }
 782                 claim_zero(mlx5_devx_cmd_destroy(ct_pool->devx_obj));
 783                 if (cnt) {
 784                         DRV_LOG(DEBUG, "%u ASO CT objects are being used in the pool %u",
 785                                 cnt, i);
 786                 }
 787                 mlx5_free(ct_pool);
 788                 /* in case of failure. */
 789                 mng->next--;
 790         }
 791         mlx5_free(mng->pools);
 792         mlx5_free(mng);
 793         /* Management structure must be cleared to 0s during allocation. */
 794         sh->ct_mng = NULL;
 795 }
 796
 797 /**
 798  * Initialize the flow resources' indexed mempool.
 799  *
 800  * @param[in] sh
 801  *   Pointer to mlx5_dev_ctx_shared object.
 802  * @param[in] config
 803  *   Pointer to user dev config.
 804  */
 805 static void
 806 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
 807                        const struct mlx5_dev_config *config)
 808 {
 809         uint8_t i;
 810         struct mlx5_indexed_pool_config cfg;
 811
 812         for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
 813                 cfg = mlx5_ipool_cfg[i];
 814                 switch (i) {
 815                 default:
 816                         break;
 817                 /*
 818                  * Set MLX5_IPOOL_MLX5_FLOW ipool size
 819                  * according to PCI function flow configuration.
 820                  */
 821                 case MLX5_IPOOL_MLX5_FLOW:
 822                         cfg.size = config->dv_flow_en ?
 823                                 sizeof(struct mlx5_flow_handle) :
 824                                 MLX5_FLOW_HANDLE_VERBS_SIZE;
 825                         break;
 826                 }
 827                 if (config->reclaim_mode) {
 828                         cfg.release_mem_en = 1;
 829                         cfg.per_core_cache = 0;
 830                 } else {
 831                         cfg.release_mem_en = 0;
 832                 }
 833                 sh->ipool[i] = mlx5_ipool_create(&cfg);
 834         }
 835 }
 836
 837
 838 /**
 839  * Release the flow resources' indexed mempool.
 840  *
 841  * @param[in] sh
 842  *   Pointer to mlx5_dev_ctx_shared object.
 843  */
 844 static void
 845 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
 846 {
 847         uint8_t i;
 848
 849         for (i = 0; i < MLX5_IPOOL_MAX; ++i)
 850                 mlx5_ipool_destroy(sh->ipool[i]);
 851         for (i = 0; i < MLX5_MAX_MODIFY_NUM; ++i)
 852                 if (sh->mdh_ipools[i])
 853                         mlx5_ipool_destroy(sh->mdh_ipools[i]);
 854 }
 855
 856 /*
 857  * Check if dynamic flex parser for eCPRI already exists.
 858  *
 859  * @param dev
 860  *   Pointer to Ethernet device structure.
 861  *
 862  * @return
 863  *   true on exists, false on not.
 864  */
 865 bool
 866 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
 867 {
 868         struct mlx5_priv *priv = dev->data->dev_private;
 869         struct mlx5_ecpri_parser_profile *prf = &priv->sh->ecpri_parser;
 870
 871         return !!prf->obj;
 872 }
 873
 874 /*
 875  * Allocation of a flex parser for eCPRI. Once created, this parser related
 876  * resources will be held until the device is closed.
 877  *
 878  * @param dev
 879  *   Pointer to Ethernet device structure.
 880  *
 881  * @return
 882  *   0 on success, a negative errno value otherwise and rte_errno is set.
 883  */
 884 int
 885 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
 886 {
 887         struct mlx5_priv *priv = dev->data->dev_private;
 888         struct mlx5_ecpri_parser_profile *prf = &priv->sh->ecpri_parser;
 889         struct mlx5_devx_graph_node_attr node = {
 890                 .modify_field_select = 0,
 891         };
 892         uint32_t ids[8];
 893         int ret;
 894
 895         if (!priv->config.hca_attr.parse_graph_flex_node) {
 896                 DRV_LOG(ERR, "Dynamic flex parser is not supported "
 897                         "for device %s.", priv->dev_data->name);
 898                 return -ENOTSUP;
 899         }
 900         node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED;
 901         /* 8 bytes now: 4B common header + 4B message body header. */
 902         node.header_length_base_value = 0x8;
 903         /* After MAC layer: Ether / VLAN. */
 904         node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC;
 905         /* Type of compared condition should be 0xAEFE in the L2 layer. */
 906         node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI;
 907         /* Sample #0: type in common header. */
 908         node.sample[0].flow_match_sample_en = 1;
 909         /* Fixed offset. */
 910         node.sample[0].flow_match_sample_offset_mode = 0x0;
 911         /* Only the 2nd byte will be used. */
 912         node.sample[0].flow_match_sample_field_base_offset = 0x0;
 913         /* Sample #1: message payload. */
 914         node.sample[1].flow_match_sample_en = 1;
 915         /* Fixed offset. */
 916         node.sample[1].flow_match_sample_offset_mode = 0x0;
 917         /*
 918          * Only the first two bytes will be used right now, and its offset will
 919          * start after the common header that with the length of a DW(u32).
 920          */
 921         node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);
 922         prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->cdev->ctx, &node);
 923         if (!prf->obj) {
 924                 DRV_LOG(ERR, "Failed to create flex parser node object.");
 925                 return (rte_errno == 0) ? -ENODEV : -rte_errno;
 926         }
 927         prf->num = 2;
 928         ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num);
 929         if (ret) {
 930                 DRV_LOG(ERR, "Failed to query sample IDs.");
 931                 return (rte_errno == 0) ? -ENODEV : -rte_errno;
 932         }
 933         prf->offset[0] = 0x0;
 934         prf->offset[1] = sizeof(uint32_t);
 935         prf->ids[0] = ids[0];
 936         prf->ids[1] = ids[1];
 937         return 0;
 938 }
 939
 940 /*
 941  * Destroy the flex parser node, including the parser itself, input / output
 942  * arcs and DW samples. Resources could be reused then.
 943  *
 944  * @param dev
 945  *   Pointer to Ethernet device structure.
 946  */
 947 static void
 948 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
 949 {
 950         struct mlx5_priv *priv = dev->data->dev_private;
 951         struct mlx5_ecpri_parser_profile *prf = &priv->sh->ecpri_parser;
 952
 953         if (prf->obj)
 954                 mlx5_devx_cmd_destroy(prf->obj);
 955         prf->obj = NULL;
 956 }
 957
 958 uint32_t
 959 mlx5_get_supported_sw_parsing_offloads(const struct mlx5_hca_attr *attr)
 960 {
 961         uint32_t sw_parsing_offloads = 0;
 962
 963         if (attr->swp) {
 964                 sw_parsing_offloads |= MLX5_SW_PARSING_CAP;
 965                 if (attr->swp_csum)
 966                         sw_parsing_offloads |= MLX5_SW_PARSING_CSUM_CAP;
 967
 968                 if (attr->swp_lso)
 969                         sw_parsing_offloads |= MLX5_SW_PARSING_TSO_CAP;
 970         }
 971         return sw_parsing_offloads;
 972 }
 973
 974 uint32_t
 975 mlx5_get_supported_tunneling_offloads(const struct mlx5_hca_attr *attr)
 976 {
 977         uint32_t tn_offloads = 0;
 978
 979         if (attr->tunnel_stateless_vxlan)
 980                 tn_offloads |= MLX5_TUNNELED_OFFLOADS_VXLAN_CAP;
 981         if (attr->tunnel_stateless_gre)
 982                 tn_offloads |= MLX5_TUNNELED_OFFLOADS_GRE_CAP;
 983         if (attr->tunnel_stateless_geneve_rx)
 984                 tn_offloads |= MLX5_TUNNELED_OFFLOADS_GENEVE_CAP;
 985         return tn_offloads;
 986 }
 987
 988 /*
 989  * Allocate Rx and Tx UARs in robust fashion.
 990  * This routine handles the following UAR allocation issues:
 991  *
 992  *  - tries to allocate the UAR with the most appropriate memory
 993  *    mapping type from the ones supported by the host
 994  *
 995  *  - tries to allocate the UAR with non-NULL base address
 996  *    OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as
 997  *    UAR base address if UAR was not the first object in the UAR page.
 998  *    It caused the PMD failure and we should try to get another UAR
 999  *    till we get the first one with non-NULL base address returned.
1000  */
1001 static int
1002 mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh,
1003                      const struct mlx5_common_dev_config *config)
1004 {
1005         uint32_t uar_mapping, retry;
1006         int err = 0;
1007         void *base_addr;
1008
1009         for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
1010 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
1011                 /* Control the mapping type according to the settings. */
1012                 uar_mapping = (config->dbnc == MLX5_TXDB_NCACHED) ?
1013                               MLX5DV_UAR_ALLOC_TYPE_NC :
1014                               MLX5DV_UAR_ALLOC_TYPE_BF;
1015 #else
1016                 RTE_SET_USED(config);
1017                 /*
1018                  * It seems we have no way to control the memory mapping type
1019                  * for the UAR, the default "Write-Combining" type is supposed.
1020                  * The UAR initialization on queue creation queries the
1021                  * actual mapping type done by Verbs/kernel and setups the
1022                  * PMD datapath accordingly.
1023                  */
1024                 uar_mapping = 0;
1025 #endif
1026                 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->cdev->ctx,
1027                                                        uar_mapping);
1028 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
1029                 if (!sh->tx_uar &&
1030                     uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
1031                         if (config->dbnc == MLX5_TXDB_CACHED ||
1032                             config->dbnc == MLX5_TXDB_HEURISTIC)
1033                                 DRV_LOG(WARNING, "Devarg tx_db_nc setting "
1034                                                  "is not supported by DevX");
1035                         /*
1036                          * In some environments like virtual machine
1037                          * the Write Combining mapped might be not supported
1038                          * and UAR allocation fails. We try "Non-Cached"
1039                          * mapping for the case. The tx_burst routines take
1040                          * the UAR mapping type into account on UAR setup
1041                          * on queue creation.
1042                          */
1043                         DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (BF)");
1044                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
1045                         sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->cdev->ctx,
1046                                                                uar_mapping);
1047                 } else if (!sh->tx_uar &&
1048                            uar_mapping == MLX5DV_UAR_ALLOC_TYPE_NC) {
1049                         if (config->dbnc == MLX5_TXDB_NCACHED)
1050                                 DRV_LOG(WARNING, "Devarg tx_db_nc settings "
1051                                                  "is not supported by DevX");
1052                         /*
1053                          * If Verbs/kernel does not support "Non-Cached"
1054                          * try the "Write-Combining".
1055                          */
1056                         DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (NC)");
1057                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_BF;
1058                         sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->cdev->ctx,
1059                                                                uar_mapping);
1060                 }
1061 #endif
1062                 if (!sh->tx_uar) {
1063                         DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (BF/NC)");
1064                         err = ENOMEM;
1065                         goto exit;
1066                 }
1067                 base_addr = mlx5_os_get_devx_uar_base_addr(sh->tx_uar);
1068                 if (base_addr)
1069                         break;
1070                 /*
1071                  * The UARs are allocated by rdma_core within the
1072                  * IB device context, on context closure all UARs
1073                  * will be freed, should be no memory/object leakage.
1074                  */
1075                 DRV_LOG(DEBUG, "Retrying to allocate Tx DevX UAR");
1076                 sh->tx_uar = NULL;
1077         }
1078         /* Check whether we finally succeeded with valid UAR allocation. */
1079         if (!sh->tx_uar) {
1080                 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (NULL base)");
1081                 err = ENOMEM;
1082                 goto exit;
1083         }
1084         for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
1085                 uar_mapping = 0;
1086                 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar(sh->cdev->ctx,
1087                                                             uar_mapping);
1088 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
1089                 if (!sh->devx_rx_uar &&
1090                     uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
1091                         /*
1092                          * Rx UAR is used to control interrupts only,
1093                          * should be no datapath noticeable impact,
1094                          * can try "Non-Cached" mapping safely.
1095                          */
1096                         DRV_LOG(DEBUG, "Failed to allocate Rx DevX UAR (BF)");
1097                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
1098                         sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
1099                                                    (sh->cdev->ctx, uar_mapping);
1100                 }
1101 #endif
1102                 if (!sh->devx_rx_uar) {
1103                         DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (BF/NC)");
1104                         err = ENOMEM;
1105                         goto exit;
1106                 }
1107                 base_addr = mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar);
1108                 if (base_addr)
1109                         break;
1110                 /*
1111                  * The UARs are allocated by rdma_core within the
1112                  * IB device context, on context closure all UARs
1113                  * will be freed, should be no memory/object leakage.
1114                  */
1115                 DRV_LOG(DEBUG, "Retrying to allocate Rx DevX UAR");
1116                 sh->devx_rx_uar = NULL;
1117         }
1118         /* Check whether we finally succeeded with valid UAR allocation. */
1119         if (!sh->devx_rx_uar) {
1120                 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (NULL base)");
1121                 err = ENOMEM;
1122         }
1123 exit:
1124         return err;
1125 }
1126
1127 /**
1128  * rte_mempool_walk() callback to unregister Rx mempools.
1129  * It used when implicit mempool registration is disabled.
1130  *
1131  * @param mp
1132  *   The mempool being walked.
1133  * @param arg
1134  *   Pointer to the device shared context.
1135  */
1136 static void
1137 mlx5_dev_ctx_shared_rx_mempool_unregister_cb(struct rte_mempool *mp, void *arg)
1138 {
1139         struct mlx5_dev_ctx_shared *sh = arg;
1140
1141         mlx5_dev_mempool_unregister(sh->cdev, mp);
1142 }
1143
1144 /**
1145  * Callback used when implicit mempool registration is disabled
1146  * in order to track Rx mempool destruction.
1147  *
1148  * @param event
1149  *   Mempool life cycle event.
1150  * @param mp
1151  *   An Rx mempool registered explicitly when the port is started.
1152  * @param arg
1153  *   Pointer to a device shared context.
1154  */
1155 static void
1156 mlx5_dev_ctx_shared_rx_mempool_event_cb(enum rte_mempool_event event,
1157                                         struct rte_mempool *mp, void *arg)
1158 {
1159         struct mlx5_dev_ctx_shared *sh = arg;
1160
1161         if (event == RTE_MEMPOOL_EVENT_DESTROY)
1162                 mlx5_dev_mempool_unregister(sh->cdev, mp);
1163 }
1164
1165 int
1166 mlx5_dev_ctx_shared_mempool_subscribe(struct rte_eth_dev *dev)
1167 {
1168         struct mlx5_priv *priv = dev->data->dev_private;
1169         struct mlx5_dev_ctx_shared *sh = priv->sh;
1170         int ret;
1171
1172         /* Check if we only need to track Rx mempool destruction. */
1173         if (!sh->cdev->config.mr_mempool_reg_en) {
1174                 ret = rte_mempool_event_callback_register
1175                                 (mlx5_dev_ctx_shared_rx_mempool_event_cb, sh);
1176                 return ret == 0 || rte_errno == EEXIST ? 0 : ret;
1177         }
1178         return mlx5_dev_mempool_subscribe(sh->cdev);
1179 }
1180
1181 /**
1182  * Set up multiple TISs with different affinities according to
1183  * number of bonding ports
1184  *
1185  * @param priv
1186  * Pointer of shared context.
1187  *
1188  * @return
1189  * Zero on success, -1 otherwise.
1190  */
1191 static int
1192 mlx5_setup_tis(struct mlx5_dev_ctx_shared *sh)
1193 {
1194         int i;
1195         struct mlx5_devx_lag_context lag_ctx = { 0 };
1196         struct mlx5_devx_tis_attr tis_attr = { 0 };
1197
1198         tis_attr.transport_domain = sh->td->id;
1199         if (sh->bond.n_port) {
1200                 if (!mlx5_devx_cmd_query_lag(sh->cdev->ctx, &lag_ctx)) {
1201                         sh->lag.tx_remap_affinity[0] =
1202                                 lag_ctx.tx_remap_affinity_1;
1203                         sh->lag.tx_remap_affinity[1] =
1204                                 lag_ctx.tx_remap_affinity_2;
1205                         sh->lag.affinity_mode = lag_ctx.port_select_mode;
1206                 } else {
1207                         DRV_LOG(ERR, "Failed to query lag affinity.");
1208                         return -1;
1209                 }
1210                 if (sh->lag.affinity_mode == MLX5_LAG_MODE_TIS) {
1211                         for (i = 0; i < sh->bond.n_port; i++) {
1212                                 tis_attr.lag_tx_port_affinity =
1213                                         MLX5_IFC_LAG_MAP_TIS_AFFINITY(i,
1214                                                         sh->bond.n_port);
1215                                 sh->tis[i] = mlx5_devx_cmd_create_tis(sh->cdev->ctx,
1216                                                 &tis_attr);
1217                                 if (!sh->tis[i]) {
1218                                         DRV_LOG(ERR, "Failed to TIS %d/%d for bonding device"
1219                                                 " %s.", i, sh->bond.n_port,
1220                                                 sh->ibdev_name);
1221                                         return -1;
1222                                 }
1223                         }
1224                         DRV_LOG(DEBUG, "LAG number of ports : %d, affinity_1 & 2 : pf%d & %d.\n",
1225                                 sh->bond.n_port, lag_ctx.tx_remap_affinity_1,
1226                                 lag_ctx.tx_remap_affinity_2);
1227                         return 0;
1228                 }
1229                 if (sh->lag.affinity_mode == MLX5_LAG_MODE_HASH)
1230                         DRV_LOG(INFO, "Device %s enabled HW hash based LAG.",
1231                                         sh->ibdev_name);
1232         }
1233         tis_attr.lag_tx_port_affinity = 0;
1234         sh->tis[0] = mlx5_devx_cmd_create_tis(sh->cdev->ctx, &tis_attr);
1235         if (!sh->tis[0]) {
1236                 DRV_LOG(ERR, "Failed to TIS 0 for bonding device"
1237                         " %s.", sh->ibdev_name);
1238                 return -1;
1239         }
1240         return 0;
1241 }
1242
1243 /**
1244  * Allocate shared device context. If there is multiport device the
1245  * master and representors will share this context, if there is single
1246  * port dedicated device, the context will be used by only given
1247  * port due to unification.
1248  *
1249  * Routine first searches the context for the specified device name,
1250  * if found the shared context assumed and reference counter is incremented.
1251  * If no context found the new one is created and initialized with specified
1252  * device context and parameters.
1253  *
1254  * @param[in] spawn
1255  *   Pointer to the device attributes (name, port, etc).
1256  * @param[in] config
1257  *   Pointer to device configuration structure.
1258  *
1259  * @return
1260  *   Pointer to mlx5_dev_ctx_shared object on success,
1261  *   otherwise NULL and rte_errno is set.
1262  */
1263 struct mlx5_dev_ctx_shared *
1264 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
1265                           const struct mlx5_dev_config *config)
1266 {
1267         struct mlx5_dev_ctx_shared *sh;
1268         int err = 0;
1269         uint32_t i;
1270
1271         MLX5_ASSERT(spawn);
1272         /* Secondary process should not create the shared context. */
1273         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1274         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1275         /* Search for IB context by device name. */
1276         LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
1277                 if (!strcmp(sh->ibdev_name, spawn->phys_dev_name)) {
1278                         sh->refcnt++;
1279                         goto exit;
1280                 }
1281         }
1282         /* No device found, we have to create new shared context. */
1283         MLX5_ASSERT(spawn->max_port);
1284         sh = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
1285                          sizeof(struct mlx5_dev_ctx_shared) +
1286                          spawn->max_port *
1287                          sizeof(struct mlx5_dev_shared_port),
1288                          RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
1289         if (!sh) {
1290                 DRV_LOG(ERR, "shared context allocation failure");
1291                 rte_errno  = ENOMEM;
1292                 goto exit;
1293         }
1294         pthread_mutex_init(&sh->txpp.mutex, NULL);
1295         sh->numa_node = spawn->cdev->dev->numa_node;
1296         sh->cdev = spawn->cdev;
1297         sh->devx = sh->cdev->config.devx;
1298         if (spawn->bond_info)
1299                 sh->bond = *spawn->bond_info;
1300         err = mlx5_os_get_dev_attr(sh->cdev, &sh->device_attr);
1301         if (err) {
1302                 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
1303                 goto error;
1304         }
1305         sh->refcnt = 1;
1306         sh->max_port = spawn->max_port;
1307         sh->reclaim_mode = config->reclaim_mode;
1308         strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->cdev->ctx),
1309                 sizeof(sh->ibdev_name) - 1);
1310         strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->cdev->ctx),
1311                 sizeof(sh->ibdev_path) - 1);
1312         /*
1313          * Setting port_id to max unallowed value means
1314          * there is no interrupt subhandler installed for
1315          * the given port index i.
1316          */
1317         for (i = 0; i < sh->max_port; i++) {
1318                 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
1319                 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
1320         }
1321         if (sh->devx) {
1322                 sh->td = mlx5_devx_cmd_create_td(sh->cdev->ctx);
1323                 if (!sh->td) {
1324                         DRV_LOG(ERR, "TD allocation failure");
1325                         err = ENOMEM;
1326                         goto error;
1327                 }
1328                 if (mlx5_setup_tis(sh)) {
1329                         DRV_LOG(ERR, "TIS allocation failure");
1330                         err = ENOMEM;
1331                         goto error;
1332                 }
1333                 err = mlx5_alloc_rxtx_uars(sh, &sh->cdev->config);
1334                 if (err)
1335                         goto error;
1336                 MLX5_ASSERT(sh->tx_uar);
1337                 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->tx_uar));
1338
1339                 MLX5_ASSERT(sh->devx_rx_uar);
1340                 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar));
1341         }
1342 #ifndef RTE_ARCH_64
1343         /* Initialize UAR access locks for 32bit implementations. */
1344         rte_spinlock_init(&sh->uar_lock_cq);
1345         for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
1346                 rte_spinlock_init(&sh->uar_lock[i]);
1347 #endif
1348         mlx5_os_dev_shared_handler_install(sh);
1349         if (LIST_EMPTY(&mlx5_dev_ctx_list)) {
1350                 err = mlx5_flow_os_init_workspace_once();
1351                 if (err)
1352                         goto error;
1353         }
1354         mlx5_flow_aging_init(sh);
1355         mlx5_flow_counters_mng_init(sh);
1356         mlx5_flow_ipool_create(sh, config);
1357         /* Add context to the global device list. */
1358         LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
1359         rte_spinlock_init(&sh->geneve_tlv_opt_sl);
1360 exit:
1361         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1362         return sh;
1363 error:
1364         pthread_mutex_destroy(&sh->txpp.mutex);
1365         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1366         MLX5_ASSERT(sh);
1367         if (sh->td)
1368                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1369         i = 0;
1370         do {
1371                 if (sh->tis[i])
1372                         claim_zero(mlx5_devx_cmd_destroy(sh->tis[i]));
1373         } while (++i < (uint32_t)sh->bond.n_port);
1374         if (sh->devx_rx_uar)
1375                 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1376         if (sh->tx_uar)
1377                 mlx5_glue->devx_free_uar(sh->tx_uar);
1378         mlx5_free(sh);
1379         MLX5_ASSERT(err > 0);
1380         rte_errno = err;
1381         return NULL;
1382 }
1383
1384 /**
1385  * Free shared IB device context. Decrement counter and if zero free
1386  * all allocated resources and close handles.
1387  *
1388  * @param[in] sh
1389  *   Pointer to mlx5_dev_ctx_shared object to free
1390  */
1391 void
1392 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
1393 {
1394         int ret;
1395         int i = 0;
1396
1397         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1398 #ifdef RTE_LIBRTE_MLX5_DEBUG
1399         /* Check the object presence in the list. */
1400         struct mlx5_dev_ctx_shared *lctx;
1401
1402         LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
1403                 if (lctx == sh)
1404                         break;
1405         MLX5_ASSERT(lctx);
1406         if (lctx != sh) {
1407                 DRV_LOG(ERR, "Freeing non-existing shared IB context");
1408                 goto exit;
1409         }
1410 #endif
1411         MLX5_ASSERT(sh);
1412         MLX5_ASSERT(sh->refcnt);
1413         /* Secondary process should not free the shared context. */
1414         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1415         if (--sh->refcnt)
1416                 goto exit;
1417         /* Stop watching for mempool events and unregister all mempools. */
1418         if (!sh->cdev->config.mr_mempool_reg_en) {
1419                 ret = rte_mempool_event_callback_unregister
1420                                 (mlx5_dev_ctx_shared_rx_mempool_event_cb, sh);
1421                 if (ret == 0)
1422                         rte_mempool_walk
1423                              (mlx5_dev_ctx_shared_rx_mempool_unregister_cb, sh);
1424         }
1425         /* Remove context from the global device list. */
1426         LIST_REMOVE(sh, next);
1427         /* Release resources on the last device removal. */
1428         if (LIST_EMPTY(&mlx5_dev_ctx_list)) {
1429                 mlx5_os_net_cleanup();
1430                 mlx5_flow_os_release_workspace();
1431         }
1432         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1433         /*
1434          *  Ensure there is no async event handler installed.
1435          *  Only primary process handles async device events.
1436          **/
1437         mlx5_flow_counters_mng_close(sh);
1438         if (sh->aso_age_mng) {
1439                 mlx5_flow_aso_age_mng_close(sh);
1440                 sh->aso_age_mng = NULL;
1441         }
1442         if (sh->mtrmng)
1443                 mlx5_aso_flow_mtrs_mng_close(sh);
1444         mlx5_flow_ipool_destroy(sh);
1445         mlx5_os_dev_shared_handler_uninstall(sh);
1446         if (sh->tx_uar) {
1447                 mlx5_glue->devx_free_uar(sh->tx_uar);
1448                 sh->tx_uar = NULL;
1449         }
1450         do {
1451                 if (sh->tis[i])
1452                         claim_zero(mlx5_devx_cmd_destroy(sh->tis[i]));
1453         } while (++i < sh->bond.n_port);
1454         if (sh->td)
1455                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1456         if (sh->devx_rx_uar)
1457                 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1458         MLX5_ASSERT(sh->geneve_tlv_option_resource == NULL);
1459         pthread_mutex_destroy(&sh->txpp.mutex);
1460         mlx5_free(sh);
1461         return;
1462 exit:
1463         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1464 }
1465
1466 /**
1467  * Destroy table hash list.
1468  *
1469  * @param[in] priv
1470  *   Pointer to the private device data structure.
1471  */
1472 void
1473 mlx5_free_table_hash_list(struct mlx5_priv *priv)
1474 {
1475         struct mlx5_dev_ctx_shared *sh = priv->sh;
1476
1477         if (!sh->flow_tbls)
1478                 return;
1479         mlx5_hlist_destroy(sh->flow_tbls);
1480         sh->flow_tbls = NULL;
1481 }
1482
1483 /**
1484  * Initialize flow table hash list and create the root tables entry
1485  * for each domain.
1486  *
1487  * @param[in] priv
1488  *   Pointer to the private device data structure.
1489  *
1490  * @return
1491  *   Zero on success, positive error code otherwise.
1492  */
1493 int
1494 mlx5_alloc_table_hash_list(struct mlx5_priv *priv __rte_unused)
1495 {
1496         int err = 0;
1497         /* Tables are only used in DV and DR modes. */
1498 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
1499         struct mlx5_dev_ctx_shared *sh = priv->sh;
1500         char s[MLX5_NAME_SIZE];
1501
1502         MLX5_ASSERT(sh);
1503         snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1504         sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE,
1505                                           false, true, sh,
1506                                           flow_dv_tbl_create_cb,
1507                                           flow_dv_tbl_match_cb,
1508                                           flow_dv_tbl_remove_cb,
1509                                           flow_dv_tbl_clone_cb,
1510                                           flow_dv_tbl_clone_free_cb);
1511         if (!sh->flow_tbls) {
1512                 DRV_LOG(ERR, "flow tables with hash creation failed.");
1513                 err = ENOMEM;
1514                 return err;
1515         }
1516 #ifndef HAVE_MLX5DV_DR
1517         struct rte_flow_error error;
1518         struct rte_eth_dev *dev = &rte_eth_devices[priv->dev_data->port_id];
1519
1520         /*
1521          * In case we have not DR support, the zero tables should be created
1522          * because DV expect to see them even if they cannot be created by
1523          * RDMA-CORE.
1524          */
1525         if (!flow_dv_tbl_resource_get(dev, 0, 0, 0, 0,
1526                 NULL, 0, 1, 0, &error) ||
1527             !flow_dv_tbl_resource_get(dev, 0, 1, 0, 0,
1528                 NULL, 0, 1, 0, &error) ||
1529             !flow_dv_tbl_resource_get(dev, 0, 0, 1, 0,
1530                 NULL, 0, 1, 0, &error)) {
1531                 err = ENOMEM;
1532                 goto error;
1533         }
1534         return err;
1535 error:
1536         mlx5_free_table_hash_list(priv);
1537 #endif /* HAVE_MLX5DV_DR */
1538 #endif
1539         return err;
1540 }
1541
1542 /**
1543  * Retrieve integer value from environment variable.
1544  *
1545  * @param[in] name
1546  *   Environment variable name.
1547  *
1548  * @return
1549  *   Integer value, 0 if the variable is not set.
1550  */
1551 int
1552 mlx5_getenv_int(const char *name)
1553 {
1554         const char *val = getenv(name);
1555
1556         if (val == NULL)
1557                 return 0;
1558         return atoi(val);
1559 }
1560
1561 /**
1562  * DPDK callback to add udp tunnel port
1563  *
1564  * @param[in] dev
1565  *   A pointer to eth_dev
1566  * @param[in] udp_tunnel
1567  *   A pointer to udp tunnel
1568  *
1569  * @return
1570  *   0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1571  */
1572 int
1573 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1574                          struct rte_eth_udp_tunnel *udp_tunnel)
1575 {
1576         MLX5_ASSERT(udp_tunnel != NULL);
1577         if (udp_tunnel->prot_type == RTE_ETH_TUNNEL_TYPE_VXLAN &&
1578             udp_tunnel->udp_port == 4789)
1579                 return 0;
1580         if (udp_tunnel->prot_type == RTE_ETH_TUNNEL_TYPE_VXLAN_GPE &&
1581             udp_tunnel->udp_port == 4790)
1582                 return 0;
1583         return -ENOTSUP;
1584 }
1585
1586 /**
1587  * Initialize process private data structure.
1588  *
1589  * @param dev
1590  *   Pointer to Ethernet device structure.
1591  *
1592  * @return
1593  *   0 on success, a negative errno value otherwise and rte_errno is set.
1594  */
1595 int
1596 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1597 {
1598         struct mlx5_priv *priv = dev->data->dev_private;
1599         struct mlx5_proc_priv *ppriv;
1600         size_t ppriv_size;
1601
1602         mlx5_proc_priv_uninit(dev);
1603         /*
1604          * UAR register table follows the process private structure. BlueFlame
1605          * registers for Tx queues are stored in the table.
1606          */
1607         ppriv_size =
1608                 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1609         ppriv = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, ppriv_size,
1610                             RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1611         if (!ppriv) {
1612                 rte_errno = ENOMEM;
1613                 return -rte_errno;
1614         }
1615         ppriv->uar_table_sz = priv->txqs_n;
1616         dev->process_private = ppriv;
1617         return 0;
1618 }
1619
1620 /**
1621  * Un-initialize process private data structure.
1622  *
1623  * @param dev
1624  *   Pointer to Ethernet device structure.
1625  */
1626 void
1627 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1628 {
1629         if (!dev->process_private)
1630                 return;
1631         mlx5_free(dev->process_private);
1632         dev->process_private = NULL;
1633 }
1634
1635 /**
1636  * DPDK callback to close the device.
1637  *
1638  * Destroy all queues and objects, free memory.
1639  *
1640  * @param dev
1641  *   Pointer to Ethernet device structure.
1642  */
1643 int
1644 mlx5_dev_close(struct rte_eth_dev *dev)
1645 {
1646         struct mlx5_priv *priv = dev->data->dev_private;
1647         unsigned int i;
1648         int ret;
1649
1650         if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1651                 /* Check if process_private released. */
1652                 if (!dev->process_private)
1653                         return 0;
1654                 mlx5_tx_uar_uninit_secondary(dev);
1655                 mlx5_proc_priv_uninit(dev);
1656                 rte_eth_dev_release_port(dev);
1657                 return 0;
1658         }
1659         if (!priv->sh)
1660                 return 0;
1661         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1662                 dev->data->port_id,
1663                 ((priv->sh->cdev->ctx != NULL) ?
1664                 mlx5_os_get_ctx_device_name(priv->sh->cdev->ctx) : ""));
1665         /*
1666          * If default mreg copy action is removed at the stop stage,
1667          * the search will return none and nothing will be done anymore.
1668          */
1669         mlx5_flow_stop_default(dev);
1670         mlx5_traffic_disable(dev);
1671         /*
1672          * If all the flows are already flushed in the device stop stage,
1673          * then this will return directly without any action.
1674          */
1675         mlx5_flow_list_flush(dev, MLX5_FLOW_TYPE_GEN, true);
1676         mlx5_action_handle_flush(dev);
1677         mlx5_flow_meter_flush(dev, NULL);
1678         /* Prevent crashes when queues are still in use. */
1679         dev->rx_pkt_burst = removed_rx_burst;
1680         dev->tx_pkt_burst = removed_tx_burst;
1681         rte_wmb();
1682         /* Disable datapath on secondary process. */
1683         mlx5_mp_os_req_stop_rxtx(dev);
1684         /* Free the eCPRI flex parser resource. */
1685         mlx5_flex_parser_ecpri_release(dev);
1686         if (priv->rxqs != NULL) {
1687                 /* XXX race condition if mlx5_rx_burst() is still running. */
1688                 rte_delay_us_sleep(1000);
1689                 for (i = 0; (i != priv->rxqs_n); ++i)
1690                         mlx5_rxq_release(dev, i);
1691                 priv->rxqs_n = 0;
1692                 priv->rxqs = NULL;
1693         }
1694         if (priv->representor) {
1695                 /* Each representor has a dedicated interrupts handler */
1696                 mlx5_free(dev->intr_handle);
1697                 dev->intr_handle = NULL;
1698         }
1699         if (priv->txqs != NULL) {
1700                 /* XXX race condition if mlx5_tx_burst() is still running. */
1701                 rte_delay_us_sleep(1000);
1702                 for (i = 0; (i != priv->txqs_n); ++i)
1703                         mlx5_txq_release(dev, i);
1704                 priv->txqs_n = 0;
1705                 priv->txqs = NULL;
1706         }
1707         mlx5_proc_priv_uninit(dev);
1708         if (priv->q_counters) {
1709                 mlx5_devx_cmd_destroy(priv->q_counters);
1710                 priv->q_counters = NULL;
1711         }
1712         if (priv->drop_queue.hrxq)
1713                 mlx5_drop_action_destroy(dev);
1714         if (priv->mreg_cp_tbl)
1715                 mlx5_hlist_destroy(priv->mreg_cp_tbl);
1716         mlx5_mprq_free_mp(dev);
1717         if (priv->sh->ct_mng)
1718                 mlx5_flow_aso_ct_mng_close(priv->sh);
1719         mlx5_os_free_shared_dr(priv);
1720         if (priv->rss_conf.rss_key != NULL)
1721                 mlx5_free(priv->rss_conf.rss_key);
1722         if (priv->reta_idx != NULL)
1723                 mlx5_free(priv->reta_idx);
1724         if (priv->config.vf)
1725                 mlx5_os_mac_addr_flush(dev);
1726         if (priv->nl_socket_route >= 0)
1727                 close(priv->nl_socket_route);
1728         if (priv->nl_socket_rdma >= 0)
1729                 close(priv->nl_socket_rdma);
1730         if (priv->vmwa_context)
1731                 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1732         ret = mlx5_hrxq_verify(dev);
1733         if (ret)
1734                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1735                         dev->data->port_id);
1736         ret = mlx5_ind_table_obj_verify(dev);
1737         if (ret)
1738                 DRV_LOG(WARNING, "port %u some indirection table still remain",
1739                         dev->data->port_id);
1740         ret = mlx5_rxq_obj_verify(dev);
1741         if (ret)
1742                 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1743                         dev->data->port_id);
1744         ret = mlx5_rxq_verify(dev);
1745         if (ret)
1746                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1747                         dev->data->port_id);
1748         ret = mlx5_txq_obj_verify(dev);
1749         if (ret)
1750                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1751                         dev->data->port_id);
1752         ret = mlx5_txq_verify(dev);
1753         if (ret)
1754                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1755                         dev->data->port_id);
1756         ret = mlx5_flow_verify(dev);
1757         if (ret)
1758                 DRV_LOG(WARNING, "port %u some flows still remain",
1759                         dev->data->port_id);
1760         if (priv->hrxqs)
1761                 mlx5_list_destroy(priv->hrxqs);
1762         /*
1763          * Free the shared context in last turn, because the cleanup
1764          * routines above may use some shared fields, like
1765          * mlx5_os_mac_addr_flush() uses ibdev_path for retrieveing
1766          * ifindex if Netlink fails.
1767          */
1768         mlx5_free_shared_dev_ctx(priv->sh);
1769         if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1770                 unsigned int c = 0;
1771                 uint16_t port_id;
1772
1773                 MLX5_ETH_FOREACH_DEV(port_id, dev->device) {
1774                         struct mlx5_priv *opriv =
1775                                 rte_eth_devices[port_id].data->dev_private;
1776
1777                         if (!opriv ||
1778                             opriv->domain_id != priv->domain_id ||
1779                             &rte_eth_devices[port_id] == dev)
1780                                 continue;
1781                         ++c;
1782                         break;
1783                 }
1784                 if (!c)
1785                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1786         }
1787         memset(priv, 0, sizeof(*priv));
1788         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1789         /*
1790          * Reset mac_addrs to NULL such that it is not freed as part of
1791          * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1792          * it is freed when dev_private is freed.
1793          */
1794         dev->data->mac_addrs = NULL;
1795         return 0;
1796 }
1797
1798 const struct eth_dev_ops mlx5_dev_ops = {
1799         .dev_configure = mlx5_dev_configure,
1800         .dev_start = mlx5_dev_start,
1801         .dev_stop = mlx5_dev_stop,
1802         .dev_set_link_down = mlx5_set_link_down,
1803         .dev_set_link_up = mlx5_set_link_up,
1804         .dev_close = mlx5_dev_close,
1805         .promiscuous_enable = mlx5_promiscuous_enable,
1806         .promiscuous_disable = mlx5_promiscuous_disable,
1807         .allmulticast_enable = mlx5_allmulticast_enable,
1808         .allmulticast_disable = mlx5_allmulticast_disable,
1809         .link_update = mlx5_link_update,
1810         .stats_get = mlx5_stats_get,
1811         .stats_reset = mlx5_stats_reset,
1812         .xstats_get = mlx5_xstats_get,
1813         .xstats_reset = mlx5_xstats_reset,
1814         .xstats_get_names = mlx5_xstats_get_names,
1815         .fw_version_get = mlx5_fw_version_get,
1816         .dev_infos_get = mlx5_dev_infos_get,
1817         .representor_info_get = mlx5_representor_info_get,
1818         .read_clock = mlx5_txpp_read_clock,
1819         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1820         .vlan_filter_set = mlx5_vlan_filter_set,
1821         .rx_queue_setup = mlx5_rx_queue_setup,
1822         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1823         .tx_queue_setup = mlx5_tx_queue_setup,
1824         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1825         .rx_queue_release = mlx5_rx_queue_release,
1826         .tx_queue_release = mlx5_tx_queue_release,
1827         .rx_queue_start = mlx5_rx_queue_start,
1828         .rx_queue_stop = mlx5_rx_queue_stop,
1829         .tx_queue_start = mlx5_tx_queue_start,
1830         .tx_queue_stop = mlx5_tx_queue_stop,
1831         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1832         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1833         .mac_addr_remove = mlx5_mac_addr_remove,
1834         .mac_addr_add = mlx5_mac_addr_add,
1835         .mac_addr_set = mlx5_mac_addr_set,
1836         .set_mc_addr_list = mlx5_set_mc_addr_list,
1837         .mtu_set = mlx5_dev_set_mtu,
1838         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1839         .vlan_offload_set = mlx5_vlan_offload_set,
1840         .reta_update = mlx5_dev_rss_reta_update,
1841         .reta_query = mlx5_dev_rss_reta_query,
1842         .rss_hash_update = mlx5_rss_hash_update,
1843         .rss_hash_conf_get = mlx5_rss_hash_conf_get,
1844         .flow_ops_get = mlx5_flow_ops_get,
1845         .rxq_info_get = mlx5_rxq_info_get,
1846         .txq_info_get = mlx5_txq_info_get,
1847         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1848         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1849         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1850         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1851         .is_removed = mlx5_is_removed,
1852         .udp_tunnel_port_add  = mlx5_udp_tunnel_port_add,
1853         .get_module_info = mlx5_get_module_info,
1854         .get_module_eeprom = mlx5_get_module_eeprom,
1855         .hairpin_cap_get = mlx5_hairpin_cap_get,
1856         .mtr_ops_get = mlx5_flow_meter_ops_get,
1857         .hairpin_bind = mlx5_hairpin_bind,
1858         .hairpin_unbind = mlx5_hairpin_unbind,
1859         .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1860         .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1861         .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1862         .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1863         .get_monitor_addr = mlx5_get_monitor_addr,
1864 };
1865
1866 /* Available operations from secondary process. */
1867 const struct eth_dev_ops mlx5_dev_sec_ops = {
1868         .stats_get = mlx5_stats_get,
1869         .stats_reset = mlx5_stats_reset,
1870         .xstats_get = mlx5_xstats_get,
1871         .xstats_reset = mlx5_xstats_reset,
1872         .xstats_get_names = mlx5_xstats_get_names,
1873         .fw_version_get = mlx5_fw_version_get,
1874         .dev_infos_get = mlx5_dev_infos_get,
1875         .representor_info_get = mlx5_representor_info_get,
1876         .read_clock = mlx5_txpp_read_clock,
1877         .rx_queue_start = mlx5_rx_queue_start,
1878         .rx_queue_stop = mlx5_rx_queue_stop,
1879         .tx_queue_start = mlx5_tx_queue_start,
1880         .tx_queue_stop = mlx5_tx_queue_stop,
1881         .rxq_info_get = mlx5_rxq_info_get,
1882         .txq_info_get = mlx5_txq_info_get,
1883         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1884         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1885         .get_module_info = mlx5_get_module_info,
1886         .get_module_eeprom = mlx5_get_module_eeprom,
1887 };
1888
1889 /* Available operations in flow isolated mode. */
1890 const struct eth_dev_ops mlx5_dev_ops_isolate = {
1891         .dev_configure = mlx5_dev_configure,
1892         .dev_start = mlx5_dev_start,
1893         .dev_stop = mlx5_dev_stop,
1894         .dev_set_link_down = mlx5_set_link_down,
1895         .dev_set_link_up = mlx5_set_link_up,
1896         .dev_close = mlx5_dev_close,
1897         .promiscuous_enable = mlx5_promiscuous_enable,
1898         .promiscuous_disable = mlx5_promiscuous_disable,
1899         .allmulticast_enable = mlx5_allmulticast_enable,
1900         .allmulticast_disable = mlx5_allmulticast_disable,
1901         .link_update = mlx5_link_update,
1902         .stats_get = mlx5_stats_get,
1903         .stats_reset = mlx5_stats_reset,
1904         .xstats_get = mlx5_xstats_get,
1905         .xstats_reset = mlx5_xstats_reset,
1906         .xstats_get_names = mlx5_xstats_get_names,
1907         .fw_version_get = mlx5_fw_version_get,
1908         .dev_infos_get = mlx5_dev_infos_get,
1909         .representor_info_get = mlx5_representor_info_get,
1910         .read_clock = mlx5_txpp_read_clock,
1911         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1912         .vlan_filter_set = mlx5_vlan_filter_set,
1913         .rx_queue_setup = mlx5_rx_queue_setup,
1914         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1915         .tx_queue_setup = mlx5_tx_queue_setup,
1916         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1917         .rx_queue_release = mlx5_rx_queue_release,
1918         .tx_queue_release = mlx5_tx_queue_release,
1919         .rx_queue_start = mlx5_rx_queue_start,
1920         .rx_queue_stop = mlx5_rx_queue_stop,
1921         .tx_queue_start = mlx5_tx_queue_start,
1922         .tx_queue_stop = mlx5_tx_queue_stop,
1923         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1924         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1925         .mac_addr_remove = mlx5_mac_addr_remove,
1926         .mac_addr_add = mlx5_mac_addr_add,
1927         .mac_addr_set = mlx5_mac_addr_set,
1928         .set_mc_addr_list = mlx5_set_mc_addr_list,
1929         .mtu_set = mlx5_dev_set_mtu,
1930         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1931         .vlan_offload_set = mlx5_vlan_offload_set,
1932         .flow_ops_get = mlx5_flow_ops_get,
1933         .rxq_info_get = mlx5_rxq_info_get,
1934         .txq_info_get = mlx5_txq_info_get,
1935         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1936         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1937         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1938         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1939         .is_removed = mlx5_is_removed,
1940         .get_module_info = mlx5_get_module_info,
1941         .get_module_eeprom = mlx5_get_module_eeprom,
1942         .hairpin_cap_get = mlx5_hairpin_cap_get,
1943         .mtr_ops_get = mlx5_flow_meter_ops_get,
1944         .hairpin_bind = mlx5_hairpin_bind,
1945         .hairpin_unbind = mlx5_hairpin_unbind,
1946         .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1947         .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1948         .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1949         .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1950         .get_monitor_addr = mlx5_get_monitor_addr,
1951 };
1952
1953 /**
1954  * Verify and store value for device argument.
1955  *
1956  * @param[in] key
1957  *   Key argument to verify.
1958  * @param[in] val
1959  *   Value associated with key.
1960  * @param opaque
1961  *   User data.
1962  *
1963  * @return
1964  *   0 on success, a negative errno value otherwise and rte_errno is set.
1965  */
1966 static int
1967 mlx5_args_check(const char *key, const char *val, void *opaque)
1968 {
1969         struct mlx5_dev_config *config = opaque;
1970         unsigned long mod;
1971         signed long tmp;
1972
1973         /* No-op, port representors are processed in mlx5_dev_spawn(). */
1974         if (!strcmp(MLX5_DRIVER_KEY, key) || !strcmp(MLX5_REPRESENTOR, key) ||
1975             !strcmp(MLX5_SYS_MEM_EN, key) || !strcmp(MLX5_TX_DB_NC, key) ||
1976             !strcmp(MLX5_MR_MEMPOOL_REG_EN, key) ||
1977             !strcmp(MLX5_MR_EXT_MEMSEG_EN, key))
1978                 return 0;
1979         errno = 0;
1980         tmp = strtol(val, NULL, 0);
1981         if (errno) {
1982                 rte_errno = errno;
1983                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1984                 return -rte_errno;
1985         }
1986         if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
1987                 /* Negative values are acceptable for some keys only. */
1988                 rte_errno = EINVAL;
1989                 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
1990                 return -rte_errno;
1991         }
1992         mod = tmp >= 0 ? tmp : -tmp;
1993         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1994                 if (tmp > MLX5_CQE_RESP_FORMAT_L34H_STRIDX) {
1995                         DRV_LOG(ERR, "invalid CQE compression "
1996                                      "format parameter");
1997                         rte_errno = EINVAL;
1998                         return -rte_errno;
1999                 }
2000                 config->cqe_comp = !!tmp;
2001                 config->cqe_comp_fmt = tmp;
2002         } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
2003                 config->hw_padding = !!tmp;
2004         } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
2005                 config->mprq.enabled = !!tmp;
2006         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
2007                 config->mprq.stride_num_n = tmp;
2008         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
2009                 config->mprq.stride_size_n = tmp;
2010         } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
2011                 config->mprq.max_memcpy_len = tmp;
2012         } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
2013                 config->mprq.min_rxqs_num = tmp;
2014         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
2015                 DRV_LOG(WARNING, "%s: deprecated parameter,"
2016                                  " converted to txq_inline_max", key);
2017                 config->txq_inline_max = tmp;
2018         } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
2019                 config->txq_inline_max = tmp;
2020         } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
2021                 config->txq_inline_min = tmp;
2022         } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
2023                 config->txq_inline_mpw = tmp;
2024         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
2025                 config->txqs_inline = tmp;
2026         } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
2027                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
2028         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
2029                 config->mps = !!tmp;
2030         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
2031                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
2032         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
2033                 DRV_LOG(WARNING, "%s: deprecated parameter,"
2034                                  " converted to txq_inline_mpw", key);
2035                 config->txq_inline_mpw = tmp;
2036         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
2037                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
2038         } else if (strcmp(MLX5_TX_PP, key) == 0) {
2039                 if (!mod) {
2040                         DRV_LOG(ERR, "Zero Tx packet pacing parameter");
2041                         rte_errno = EINVAL;
2042                         return -rte_errno;
2043                 }
2044                 config->tx_pp = tmp;
2045         } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
2046                 config->tx_skew = tmp;
2047         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
2048                 config->rx_vec_en = !!tmp;
2049         } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
2050                 config->l3_vxlan_en = !!tmp;
2051         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
2052                 config->vf_nl_en = !!tmp;
2053         } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
2054                 config->dv_esw_en = !!tmp;
2055         } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
2056                 config->dv_flow_en = !!tmp;
2057         } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
2058                 if (tmp != MLX5_XMETA_MODE_LEGACY &&
2059                     tmp != MLX5_XMETA_MODE_META16 &&
2060                     tmp != MLX5_XMETA_MODE_META32 &&
2061                     tmp != MLX5_XMETA_MODE_MISS_INFO) {
2062                         DRV_LOG(ERR, "invalid extensive "
2063                                      "metadata parameter");
2064                         rte_errno = EINVAL;
2065                         return -rte_errno;
2066                 }
2067                 if (tmp != MLX5_XMETA_MODE_MISS_INFO)
2068                         config->dv_xmeta_en = tmp;
2069                 else
2070                         config->dv_miss_info = 1;
2071         } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
2072                 config->lacp_by_user = !!tmp;
2073         } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
2074                 config->max_dump_files_num = tmp;
2075         } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
2076                 config->lro.timeout = tmp;
2077         } else if (strcmp(RTE_DEVARGS_KEY_CLASS, key) == 0) {
2078                 DRV_LOG(DEBUG, "class argument is %s.", val);
2079         } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
2080                 config->log_hp_size = tmp;
2081         } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
2082                 if (tmp != MLX5_RCM_NONE &&
2083                     tmp != MLX5_RCM_LIGHT &&
2084                     tmp != MLX5_RCM_AGGR) {
2085                         DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
2086                         rte_errno = EINVAL;
2087                         return -rte_errno;
2088                 }
2089                 config->reclaim_mode = tmp;
2090         } else if (strcmp(MLX5_DECAP_EN, key) == 0) {
2091                 config->decap_en = !!tmp;
2092         } else if (strcmp(MLX5_ALLOW_DUPLICATE_PATTERN, key) == 0) {
2093                 config->allow_duplicate_pattern = !!tmp;
2094         } else {
2095                 DRV_LOG(WARNING, "%s: unknown parameter", key);
2096                 rte_errno = EINVAL;
2097                 return -rte_errno;
2098         }
2099         return 0;
2100 }
2101
2102 /**
2103  * Parse device parameters.
2104  *
2105  * @param config
2106  *   Pointer to device configuration structure.
2107  * @param devargs
2108  *   Device arguments structure.
2109  *
2110  * @return
2111  *   0 on success, a negative errno value otherwise and rte_errno is set.
2112  */
2113 int
2114 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
2115 {
2116         const char **params = (const char *[]){
2117                 MLX5_DRIVER_KEY,
2118                 MLX5_RXQ_CQE_COMP_EN,
2119                 MLX5_RXQ_PKT_PAD_EN,
2120                 MLX5_RX_MPRQ_EN,
2121                 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
2122                 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
2123                 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
2124                 MLX5_RXQS_MIN_MPRQ,
2125                 MLX5_TXQ_INLINE,
2126                 MLX5_TXQ_INLINE_MIN,
2127                 MLX5_TXQ_INLINE_MAX,
2128                 MLX5_TXQ_INLINE_MPW,
2129                 MLX5_TXQS_MIN_INLINE,
2130                 MLX5_TXQS_MAX_VEC,
2131                 MLX5_TXQ_MPW_EN,
2132                 MLX5_TXQ_MPW_HDR_DSEG_EN,
2133                 MLX5_TXQ_MAX_INLINE_LEN,
2134                 MLX5_TX_DB_NC,
2135                 MLX5_TX_PP,
2136                 MLX5_TX_SKEW,
2137                 MLX5_TX_VEC_EN,
2138                 MLX5_RX_VEC_EN,
2139                 MLX5_L3_VXLAN_EN,
2140                 MLX5_VF_NL_EN,
2141                 MLX5_DV_ESW_EN,
2142                 MLX5_DV_FLOW_EN,
2143                 MLX5_DV_XMETA_EN,
2144                 MLX5_LACP_BY_USER,
2145                 MLX5_MR_EXT_MEMSEG_EN,
2146                 MLX5_REPRESENTOR,
2147                 MLX5_MAX_DUMP_FILES_NUM,
2148                 MLX5_LRO_TIMEOUT_USEC,
2149                 RTE_DEVARGS_KEY_CLASS,
2150                 MLX5_HP_BUF_SIZE,
2151                 MLX5_RECLAIM_MEM,
2152                 MLX5_SYS_MEM_EN,
2153                 MLX5_DECAP_EN,
2154                 MLX5_ALLOW_DUPLICATE_PATTERN,
2155                 MLX5_MR_MEMPOOL_REG_EN,
2156                 NULL,
2157         };
2158         struct rte_kvargs *kvlist;
2159         int ret = 0;
2160         int i;
2161
2162         if (devargs == NULL)
2163                 return 0;
2164         /* Following UGLY cast is done to pass checkpatch. */
2165         kvlist = rte_kvargs_parse(devargs->args, params);
2166         if (kvlist == NULL) {
2167                 rte_errno = EINVAL;
2168                 return -rte_errno;
2169         }
2170         /* Process parameters. */
2171         for (i = 0; (params[i] != NULL); ++i) {
2172                 if (rte_kvargs_count(kvlist, params[i])) {
2173                         ret = rte_kvargs_process(kvlist, params[i],
2174                                                  mlx5_args_check, config);
2175                         if (ret) {
2176                                 rte_errno = EINVAL;
2177                                 rte_kvargs_free(kvlist);
2178                                 return -rte_errno;
2179                         }
2180                 }
2181         }
2182         rte_kvargs_free(kvlist);
2183         return 0;
2184 }
2185
2186 /**
2187  * Configures the minimal amount of data to inline into WQE
2188  * while sending packets.
2189  *
2190  * - the txq_inline_min has the maximal priority, if this
2191  *   key is specified in devargs
2192  * - if DevX is enabled the inline mode is queried from the
2193  *   device (HCA attributes and NIC vport context if needed).
2194  * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
2195  *   and none (0 bytes) for other NICs
2196  *
2197  * @param spawn
2198  *   Verbs device parameters (name, port, switch_info) to spawn.
2199  * @param config
2200  *   Device configuration parameters.
2201  */
2202 void
2203 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
2204                     struct mlx5_dev_config *config)
2205 {
2206         if (config->txq_inline_min != MLX5_ARG_UNSET) {
2207                 /* Application defines size of inlined data explicitly. */
2208                 if (spawn->pci_dev != NULL) {
2209                         switch (spawn->pci_dev->id.device_id) {
2210                         case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2211                         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2212                                 if (config->txq_inline_min <
2213                                                (int)MLX5_INLINE_HSIZE_L2) {
2214                                         DRV_LOG(DEBUG,
2215                                                 "txq_inline_mix aligned to minimal ConnectX-4 required value %d",
2216                                                 (int)MLX5_INLINE_HSIZE_L2);
2217                                         config->txq_inline_min =
2218                                                         MLX5_INLINE_HSIZE_L2;
2219                                 }
2220                                 break;
2221                         }
2222                 }
2223                 goto exit;
2224         }
2225         if (config->hca_attr.eth_net_offloads) {
2226                 /* We have DevX enabled, inline mode queried successfully. */
2227                 switch (config->hca_attr.wqe_inline_mode) {
2228                 case MLX5_CAP_INLINE_MODE_L2:
2229                         /* outer L2 header must be inlined. */
2230                         config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2231                         goto exit;
2232                 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
2233                         /* No inline data are required by NIC. */
2234                         config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2235                         config->hw_vlan_insert =
2236                                 config->hca_attr.wqe_vlan_insert;
2237                         DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
2238                         goto exit;
2239                 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
2240                         /* inline mode is defined by NIC vport context. */
2241                         if (!config->hca_attr.eth_virt)
2242                                 break;
2243                         switch (config->hca_attr.vport_inline_mode) {
2244                         case MLX5_INLINE_MODE_NONE:
2245                                 config->txq_inline_min =
2246                                         MLX5_INLINE_HSIZE_NONE;
2247                                 goto exit;
2248                         case MLX5_INLINE_MODE_L2:
2249                                 config->txq_inline_min =
2250                                         MLX5_INLINE_HSIZE_L2;
2251                                 goto exit;
2252                         case MLX5_INLINE_MODE_IP:
2253                                 config->txq_inline_min =
2254                                         MLX5_INLINE_HSIZE_L3;
2255                                 goto exit;
2256                         case MLX5_INLINE_MODE_TCP_UDP:
2257                                 config->txq_inline_min =
2258                                         MLX5_INLINE_HSIZE_L4;
2259                                 goto exit;
2260                         case MLX5_INLINE_MODE_INNER_L2:
2261                                 config->txq_inline_min =
2262                                         MLX5_INLINE_HSIZE_INNER_L2;
2263                                 goto exit;
2264                         case MLX5_INLINE_MODE_INNER_IP:
2265                                 config->txq_inline_min =
2266                                         MLX5_INLINE_HSIZE_INNER_L3;
2267                                 goto exit;
2268                         case MLX5_INLINE_MODE_INNER_TCP_UDP:
2269                                 config->txq_inline_min =
2270                                         MLX5_INLINE_HSIZE_INNER_L4;
2271                                 goto exit;
2272                         }
2273                 }
2274         }
2275         if (spawn->pci_dev == NULL) {
2276                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2277                 goto exit;
2278         }
2279         /*
2280          * We get here if we are unable to deduce
2281          * inline data size with DevX. Try PCI ID
2282          * to determine old NICs.
2283          */
2284         switch (spawn->pci_dev->id.device_id) {
2285         case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2286         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2287         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
2288         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
2289                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2290                 config->hw_vlan_insert = 0;
2291                 break;
2292         case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
2293         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
2294         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
2295         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
2296                 /*
2297                  * These NICs support VLAN insertion from WQE and
2298                  * report the wqe_vlan_insert flag. But there is the bug
2299                  * and PFC control may be broken, so disable feature.
2300                  */
2301                 config->hw_vlan_insert = 0;
2302                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2303                 break;
2304         default:
2305                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2306                 break;
2307         }
2308 exit:
2309         DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
2310 }
2311
2312 /**
2313  * Configures the metadata mask fields in the shared context.
2314  *
2315  * @param [in] dev
2316  *   Pointer to Ethernet device.
2317  */
2318 void
2319 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
2320 {
2321         struct mlx5_priv *priv = dev->data->dev_private;
2322         struct mlx5_dev_ctx_shared *sh = priv->sh;
2323         uint32_t meta, mark, reg_c0;
2324
2325         reg_c0 = ~priv->vport_meta_mask;
2326         switch (priv->config.dv_xmeta_en) {
2327         case MLX5_XMETA_MODE_LEGACY:
2328                 meta = UINT32_MAX;
2329                 mark = MLX5_FLOW_MARK_MASK;
2330                 break;
2331         case MLX5_XMETA_MODE_META16:
2332                 meta = reg_c0 >> rte_bsf32(reg_c0);
2333                 mark = MLX5_FLOW_MARK_MASK;
2334                 break;
2335         case MLX5_XMETA_MODE_META32:
2336                 meta = UINT32_MAX;
2337                 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
2338                 break;
2339         default:
2340                 meta = 0;
2341                 mark = 0;
2342                 MLX5_ASSERT(false);
2343                 break;
2344         }
2345         if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
2346                 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
2347                                  sh->dv_mark_mask, mark);
2348         else
2349                 sh->dv_mark_mask = mark;
2350         if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
2351                 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
2352                                  sh->dv_meta_mask, meta);
2353         else
2354                 sh->dv_meta_mask = meta;
2355         if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
2356                 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
2357                                  sh->dv_meta_mask, reg_c0);
2358         else
2359                 sh->dv_regc0_mask = reg_c0;
2360         DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
2361         DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
2362         DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
2363         DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
2364 }
2365
2366 int
2367 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
2368 {
2369         static const char *const dynf_names[] = {
2370                 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
2371                 RTE_MBUF_DYNFLAG_METADATA_NAME,
2372                 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
2373         };
2374         unsigned int i;
2375
2376         if (n < RTE_DIM(dynf_names))
2377                 return -ENOMEM;
2378         for (i = 0; i < RTE_DIM(dynf_names); i++) {
2379                 if (names[i] == NULL)
2380                         return -EINVAL;
2381                 strcpy(names[i], dynf_names[i]);
2382         }
2383         return RTE_DIM(dynf_names);
2384 }
2385
2386 /**
2387  * Comparison callback to sort device data.
2388  *
2389  * This is meant to be used with qsort().
2390  *
2391  * @param a[in]
2392  *   Pointer to pointer to first data object.
2393  * @param b[in]
2394  *   Pointer to pointer to second data object.
2395  *
2396  * @return
2397  *   0 if both objects are equal, less than 0 if the first argument is less
2398  *   than the second, greater than 0 otherwise.
2399  */
2400 int
2401 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
2402                               struct mlx5_dev_config *config,
2403                               struct rte_device *dpdk_dev)
2404 {
2405         struct mlx5_dev_ctx_shared *sh = priv->sh;
2406         struct mlx5_dev_config *sh_conf = NULL;
2407         uint16_t port_id;
2408
2409         MLX5_ASSERT(sh);
2410         /* Nothing to compare for the single/first device. */
2411         if (sh->refcnt == 1)
2412                 return 0;
2413         /* Find the device with shared context. */
2414         MLX5_ETH_FOREACH_DEV(port_id, dpdk_dev) {
2415                 struct mlx5_priv *opriv =
2416                         rte_eth_devices[port_id].data->dev_private;
2417
2418                 if (opriv && opriv != priv && opriv->sh == sh) {
2419                         sh_conf = &opriv->config;
2420                         break;
2421                 }
2422         }
2423         if (!sh_conf)
2424                 return 0;
2425         if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
2426                 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
2427                              " for shared %s context", sh->ibdev_name);
2428                 rte_errno = EINVAL;
2429                 return rte_errno;
2430         }
2431         if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
2432                 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
2433                              " for shared %s context", sh->ibdev_name);
2434                 rte_errno = EINVAL;
2435                 return rte_errno;
2436         }
2437         return 0;
2438 }
2439
2440 /**
2441  * Look for the ethernet device belonging to mlx5 driver.
2442  *
2443  * @param[in] port_id
2444  *   port_id to start looking for device.
2445  * @param[in] odev
2446  *   Pointer to the hint device. When device is being probed
2447  *   the its siblings (master and preceding representors might
2448  *   not have assigned driver yet (because the mlx5_os_pci_probe()
2449  *   is not completed yet, for this case match on hint
2450  *   device may be used to detect sibling device.
2451  *
2452  * @return
2453  *   port_id of found device, RTE_MAX_ETHPORT if not found.
2454  */
2455 uint16_t
2456 mlx5_eth_find_next(uint16_t port_id, struct rte_device *odev)
2457 {
2458         while (port_id < RTE_MAX_ETHPORTS) {
2459                 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
2460
2461                 if (dev->state != RTE_ETH_DEV_UNUSED &&
2462                     dev->device &&
2463                     (dev->device == odev ||
2464                      (dev->device->driver &&
2465                      dev->device->driver->name &&
2466                      ((strcmp(dev->device->driver->name,
2467                               MLX5_PCI_DRIVER_NAME) == 0) ||
2468                       (strcmp(dev->device->driver->name,
2469                               MLX5_AUXILIARY_DRIVER_NAME) == 0)))))
2470                         break;
2471                 port_id++;
2472         }
2473         if (port_id >= RTE_MAX_ETHPORTS)
2474                 return RTE_MAX_ETHPORTS;
2475         return port_id;
2476 }
2477
2478 /**
2479  * Callback to remove a device.
2480  *
2481  * This function removes all Ethernet devices belong to a given device.
2482  *
2483  * @param[in] cdev
2484  *   Pointer to the generic device.
2485  *
2486  * @return
2487  *   0 on success, the function cannot fail.
2488  */
2489 int
2490 mlx5_net_remove(struct mlx5_common_device *cdev)
2491 {
2492         uint16_t port_id;
2493         int ret = 0;
2494
2495         RTE_ETH_FOREACH_DEV_OF(port_id, cdev->dev) {
2496                 /*
2497                  * mlx5_dev_close() is not registered to secondary process,
2498                  * call the close function explicitly for secondary process.
2499                  */
2500                 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
2501                         ret |= mlx5_dev_close(&rte_eth_devices[port_id]);
2502                 else
2503                         ret |= rte_eth_dev_close(port_id);
2504         }
2505         return ret == 0 ? 0 : -EIO;
2506 }
2507
2508 static const struct rte_pci_id mlx5_pci_id_map[] = {
2509         {
2510                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2511                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
2512         },
2513         {
2514                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2515                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
2516         },
2517         {
2518                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2519                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
2520         },
2521         {
2522                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2523                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
2524         },
2525         {
2526                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2527                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
2528         },
2529         {
2530                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2531                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
2532         },
2533         {
2534                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2535                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
2536         },
2537         {
2538                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2539                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
2540         },
2541         {
2542                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2543                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
2544         },
2545         {
2546                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2547                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
2548         },
2549         {
2550                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2551                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
2552         },
2553         {
2554                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2555                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
2556         },
2557         {
2558                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2559                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
2560         },
2561         {
2562                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2563                                 PCI_DEVICE_ID_MELLANOX_CONNECTXVF)
2564         },
2565         {
2566                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2567                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
2568         },
2569         {
2570                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2571                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
2572         },
2573         {
2574                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2575                                 PCI_DEVICE_ID_MELLANOX_CONNECTX7)
2576         },
2577         {
2578                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2579                                 PCI_DEVICE_ID_MELLANOX_CONNECTX7BF)
2580         },
2581         {
2582                 .vendor_id = 0
2583         }
2584 };
2585
2586 static struct mlx5_class_driver mlx5_net_driver = {
2587         .drv_class = MLX5_CLASS_ETH,
2588         .name = RTE_STR(MLX5_ETH_DRIVER_NAME),
2589         .id_table = mlx5_pci_id_map,
2590         .probe = mlx5_os_net_probe,
2591         .remove = mlx5_net_remove,
2592         .probe_again = 1,
2593         .intr_lsc = 1,
2594         .intr_rmv = 1,
2595 };
2596
2597 /* Initialize driver log type. */
2598 RTE_LOG_REGISTER_DEFAULT(mlx5_logtype, NOTICE)
2599
2600 /**
2601  * Driver initialization routine.
2602  */
2603 RTE_INIT(rte_mlx5_pmd_init)
2604 {
2605         pthread_mutex_init(&mlx5_dev_ctx_list_mutex, NULL);
2606         mlx5_common_init();
2607         /* Build the static tables for Verbs conversion. */
2608         mlx5_set_ptype_table();
2609         mlx5_set_cksum_table();
2610         mlx5_set_swp_types_table();
2611         if (mlx5_glue)
2612                 mlx5_class_driver_register(&mlx5_net_driver);
2613 }
2614
2615 RTE_PMD_EXPORT_NAME(MLX5_ETH_DRIVER_NAME, __COUNTER__);
2616 RTE_PMD_REGISTER_PCI_TABLE(MLX5_ETH_DRIVER_NAME, mlx5_pci_id_map);
2617 RTE_PMD_REGISTER_KMOD_DEP(MLX5_ETH_DRIVER_NAME, "* ib_uverbs & mlx5_core & mlx5_ib");