1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
13 #include <rte_malloc.h>
14 #include <ethdev_driver.h>
15 #include <ethdev_pci.h>
17 #include <rte_bus_pci.h>
18 #include <rte_common.h>
19 #include <rte_kvargs.h>
20 #include <rte_rwlock.h>
21 #include <rte_spinlock.h>
22 #include <rte_string_fns.h>
23 #include <rte_alarm.h>
24 #include <rte_cycles.h>
26 #include <mlx5_glue.h>
27 #include <mlx5_devx_cmds.h>
28 #include <mlx5_common.h>
29 #include <mlx5_common_os.h>
30 #include <mlx5_common_mp.h>
31 #include <mlx5_common_pci.h>
32 #include <mlx5_malloc.h>
34 #include "mlx5_defs.h"
36 #include "mlx5_utils.h"
37 #include "mlx5_rxtx.h"
40 #include "mlx5_autoconf.h"
42 #include "mlx5_flow.h"
43 #include "mlx5_flow_os.h"
44 #include "rte_pmd_mlx5.h"
46 /* Device parameter to enable RX completion queue compression. */
47 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
49 /* Device parameter to enable padding Rx packet to cacheline size. */
50 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
52 /* Device parameter to enable Multi-Packet Rx queue. */
53 #define MLX5_RX_MPRQ_EN "mprq_en"
55 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
56 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
58 /* Device parameter to configure log 2 of the stride size for MPRQ. */
59 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
61 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
62 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
64 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
65 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
67 /* Device parameter to configure inline send. Deprecated, ignored.*/
68 #define MLX5_TXQ_INLINE "txq_inline"
70 /* Device parameter to limit packet size to inline with ordinary SEND. */
71 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
73 /* Device parameter to configure minimal data size to inline. */
74 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
76 /* Device parameter to limit packet size to inline with Enhanced MPW. */
77 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
80 * Device parameter to configure the number of TX queues threshold for
81 * enabling inline send.
83 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
86 * Device parameter to configure the number of TX queues threshold for
87 * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
89 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
91 /* Device parameter to enable multi-packet send WQEs. */
92 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
95 * Device parameter to force doorbell register mapping
96 * to non-cahed region eliminating the extra write memory barrier.
98 #define MLX5_TX_DB_NC "tx_db_nc"
101 * Device parameter to include 2 dsegs in the title WQEBB.
102 * Deprecated, ignored.
104 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
107 * Device parameter to limit the size of inlining packet.
108 * Deprecated, ignored.
110 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
113 * Device parameter to enable Tx scheduling on timestamps
114 * and specify the packet pacing granularity in nanoseconds.
116 #define MLX5_TX_PP "tx_pp"
119 * Device parameter to specify skew in nanoseconds on Tx datapath,
120 * it represents the time between SQ start WQE processing and
121 * appearing actual packet data on the wire.
123 #define MLX5_TX_SKEW "tx_skew"
126 * Device parameter to enable hardware Tx vector.
127 * Deprecated, ignored (no vectorized Tx routines anymore).
129 #define MLX5_TX_VEC_EN "tx_vec_en"
131 /* Device parameter to enable hardware Rx vector. */
132 #define MLX5_RX_VEC_EN "rx_vec_en"
134 /* Allow L3 VXLAN flow creation. */
135 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
137 /* Activate DV E-Switch flow steering. */
138 #define MLX5_DV_ESW_EN "dv_esw_en"
140 /* Activate DV flow steering. */
141 #define MLX5_DV_FLOW_EN "dv_flow_en"
143 /* Enable extensive flow metadata support. */
144 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
146 /* Device parameter to let the user manage the lacp traffic of bonded device */
147 #define MLX5_LACP_BY_USER "lacp_by_user"
149 /* Activate Netlink support in VF mode. */
150 #define MLX5_VF_NL_EN "vf_nl_en"
152 /* Enable extending memsegs when creating a MR. */
153 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
155 /* Select port representors to instantiate. */
156 #define MLX5_REPRESENTOR "representor"
158 /* Device parameter to configure the maximum number of dump files per queue. */
159 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
161 /* Configure timeout of LRO session (in microseconds). */
162 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
165 * Device parameter to configure the total data buffer size for a single
166 * hairpin queue (logarithm value).
168 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
170 /* Flow memory reclaim mode. */
171 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
173 /* The default memory allocator used in PMD. */
174 #define MLX5_SYS_MEM_EN "sys_mem_en"
175 /* Decap will be used or not. */
176 #define MLX5_DECAP_EN "decap_en"
178 /* Device parameter to configure allow or prevent duplicate rules pattern. */
179 #define MLX5_ALLOW_DUPLICATE_PATTERN "allow_duplicate_pattern"
181 /* Shared memory between primary and secondary processes. */
182 struct mlx5_shared_data *mlx5_shared_data;
184 /** Driver-specific log messages type. */
187 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
188 LIST_HEAD_INITIALIZER();
189 static pthread_mutex_t mlx5_dev_ctx_list_mutex;
190 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
191 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
192 [MLX5_IPOOL_DECAP_ENCAP] = {
193 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
199 .malloc = mlx5_malloc,
201 .type = "mlx5_encap_decap_ipool",
203 [MLX5_IPOOL_PUSH_VLAN] = {
204 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
210 .malloc = mlx5_malloc,
212 .type = "mlx5_push_vlan_ipool",
215 .size = sizeof(struct mlx5_flow_dv_tag_resource),
221 .per_core_cache = (1 << 16),
222 .malloc = mlx5_malloc,
224 .type = "mlx5_tag_ipool",
226 [MLX5_IPOOL_PORT_ID] = {
227 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
233 .malloc = mlx5_malloc,
235 .type = "mlx5_port_id_ipool",
237 [MLX5_IPOOL_JUMP] = {
238 .size = sizeof(struct mlx5_flow_tbl_data_entry),
244 .malloc = mlx5_malloc,
246 .type = "mlx5_jump_ipool",
248 [MLX5_IPOOL_SAMPLE] = {
249 .size = sizeof(struct mlx5_flow_dv_sample_resource),
255 .malloc = mlx5_malloc,
257 .type = "mlx5_sample_ipool",
259 [MLX5_IPOOL_DEST_ARRAY] = {
260 .size = sizeof(struct mlx5_flow_dv_dest_array_resource),
266 .malloc = mlx5_malloc,
268 .type = "mlx5_dest_array_ipool",
270 [MLX5_IPOOL_TUNNEL_ID] = {
271 .size = sizeof(struct mlx5_flow_tunnel),
272 .trunk_size = MLX5_MAX_TUNNELS,
275 .type = "mlx5_tunnel_offload",
277 [MLX5_IPOOL_TNL_TBL_ID] = {
280 .type = "mlx5_flow_tnl_tbl_ipool",
285 * The ipool index should grow continually from small to big,
286 * for meter idx, so not set grow_trunk to avoid meter index
287 * not jump continually.
289 .size = sizeof(struct mlx5_legacy_flow_meter),
293 .malloc = mlx5_malloc,
295 .type = "mlx5_meter_ipool",
298 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
304 .malloc = mlx5_malloc,
306 .type = "mlx5_mcp_ipool",
308 [MLX5_IPOOL_HRXQ] = {
309 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
315 .malloc = mlx5_malloc,
317 .type = "mlx5_hrxq_ipool",
319 [MLX5_IPOOL_MLX5_FLOW] = {
321 * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
322 * It set in run time according to PCI function configuration.
330 .per_core_cache = 1 << 19,
331 .malloc = mlx5_malloc,
333 .type = "mlx5_flow_handle_ipool",
335 [MLX5_IPOOL_RTE_FLOW] = {
336 .size = sizeof(struct rte_flow),
340 .malloc = mlx5_malloc,
342 .type = "rte_flow_ipool",
344 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID] = {
347 .type = "mlx5_flow_rss_id_ipool",
349 [MLX5_IPOOL_RSS_SHARED_ACTIONS] = {
350 .size = sizeof(struct mlx5_shared_action_rss),
356 .malloc = mlx5_malloc,
358 .type = "mlx5_shared_action_rss",
360 [MLX5_IPOOL_MTR_POLICY] = {
362 * The ipool index should grow continually from small to big,
363 * for policy idx, so not set grow_trunk to avoid policy index
364 * not jump continually.
366 .size = sizeof(struct mlx5_flow_meter_sub_policy),
370 .malloc = mlx5_malloc,
372 .type = "mlx5_meter_policy_ipool",
377 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
378 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
380 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 1024
383 * Decide whether representor ID is a HPF(host PF) port on BF2.
386 * Pointer to Ethernet device structure.
389 * Non-zero if HPF, otherwise 0.
392 mlx5_is_hpf(struct rte_eth_dev *dev)
394 struct mlx5_priv *priv = dev->data->dev_private;
395 uint16_t repr = MLX5_REPRESENTOR_REPR(priv->representor_id);
396 int type = MLX5_REPRESENTOR_TYPE(priv->representor_id);
398 return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_VF &&
399 MLX5_REPRESENTOR_REPR(-1) == repr;
403 * Initialize the ASO aging management structure.
406 * Pointer to mlx5_dev_ctx_shared object to free
409 * 0 on success, a negative errno value otherwise and rte_errno is set.
412 mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh)
418 sh->aso_age_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->aso_age_mng),
419 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
420 if (!sh->aso_age_mng) {
421 DRV_LOG(ERR, "aso_age_mng allocation was failed.");
425 err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_FLOW_HIT);
427 mlx5_free(sh->aso_age_mng);
430 rte_spinlock_init(&sh->aso_age_mng->resize_sl);
431 rte_spinlock_init(&sh->aso_age_mng->free_sl);
432 LIST_INIT(&sh->aso_age_mng->free);
437 * Close and release all the resources of the ASO aging management structure.
440 * Pointer to mlx5_dev_ctx_shared object to free.
443 mlx5_flow_aso_age_mng_close(struct mlx5_dev_ctx_shared *sh)
447 mlx5_aso_flow_hit_queue_poll_stop(sh);
448 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_FLOW_HIT);
449 if (sh->aso_age_mng->pools) {
450 struct mlx5_aso_age_pool *pool;
452 for (i = 0; i < sh->aso_age_mng->next; ++i) {
453 pool = sh->aso_age_mng->pools[i];
454 claim_zero(mlx5_devx_cmd_destroy
455 (pool->flow_hit_aso_obj));
456 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j)
457 if (pool->actions[j].dr_action)
459 (mlx5_flow_os_destroy_flow_action
460 (pool->actions[j].dr_action));
463 mlx5_free(sh->aso_age_mng->pools);
465 mlx5_free(sh->aso_age_mng);
469 * Initialize the shared aging list information per port.
472 * Pointer to mlx5_dev_ctx_shared object.
475 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
478 struct mlx5_age_info *age_info;
480 for (i = 0; i < sh->max_port; i++) {
481 age_info = &sh->port[i].age_info;
483 TAILQ_INIT(&age_info->aged_counters);
484 LIST_INIT(&age_info->aged_aso);
485 rte_spinlock_init(&age_info->aged_sl);
486 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
491 * Initialize the counters management structure.
494 * Pointer to mlx5_dev_ctx_shared object to free
497 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
501 memset(&sh->cmng, 0, sizeof(sh->cmng));
502 TAILQ_INIT(&sh->cmng.flow_counters);
503 sh->cmng.min_id = MLX5_CNT_BATCH_OFFSET;
504 sh->cmng.max_id = -1;
505 sh->cmng.last_pool_idx = POOL_IDX_INVALID;
506 rte_spinlock_init(&sh->cmng.pool_update_sl);
507 for (i = 0; i < MLX5_COUNTER_TYPE_MAX; i++) {
508 TAILQ_INIT(&sh->cmng.counters[i]);
509 rte_spinlock_init(&sh->cmng.csl[i]);
514 * Destroy all the resources allocated for a counter memory management.
517 * Pointer to the memory management structure.
520 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
522 uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
524 LIST_REMOVE(mng, next);
525 claim_zero(mlx5_devx_cmd_destroy(mng->dm));
526 claim_zero(mlx5_os_umem_dereg(mng->umem));
531 * Close and release all the resources of the counters management.
534 * Pointer to mlx5_dev_ctx_shared object to free.
537 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
539 struct mlx5_counter_stats_mem_mng *mng;
545 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
546 if (rte_errno != EINPROGRESS)
551 if (sh->cmng.pools) {
552 struct mlx5_flow_counter_pool *pool;
553 uint16_t n_valid = sh->cmng.n_valid;
554 bool fallback = sh->cmng.counter_fallback;
556 for (i = 0; i < n_valid; ++i) {
557 pool = sh->cmng.pools[i];
558 if (!fallback && pool->min_dcs)
559 claim_zero(mlx5_devx_cmd_destroy
561 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
562 struct mlx5_flow_counter *cnt =
563 MLX5_POOL_GET_CNT(pool, j);
567 (mlx5_flow_os_destroy_flow_action
569 if (fallback && MLX5_POOL_GET_CNT
570 (pool, j)->dcs_when_free)
571 claim_zero(mlx5_devx_cmd_destroy
572 (cnt->dcs_when_free));
576 mlx5_free(sh->cmng.pools);
578 mng = LIST_FIRST(&sh->cmng.mem_mngs);
580 mlx5_flow_destroy_counter_stat_mem_mng(mng);
581 mng = LIST_FIRST(&sh->cmng.mem_mngs);
583 memset(&sh->cmng, 0, sizeof(sh->cmng));
587 * Initialize the aso flow meters management structure.
590 * Pointer to mlx5_dev_ctx_shared object to free
593 mlx5_aso_flow_mtrs_mng_init(struct mlx5_dev_ctx_shared *sh)
596 sh->mtrmng = mlx5_malloc(MLX5_MEM_ZERO,
598 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
601 "meter management allocation was failed.");
605 if (sh->meter_aso_en) {
606 rte_spinlock_init(&sh->mtrmng->pools_mng.mtrsl);
607 LIST_INIT(&sh->mtrmng->pools_mng.meters);
609 sh->mtrmng->def_policy_id = MLX5_INVALID_POLICY_ID;
615 * Close and release all the resources of
616 * the ASO flow meter management structure.
619 * Pointer to mlx5_dev_ctx_shared object to free.
622 mlx5_aso_flow_mtrs_mng_close(struct mlx5_dev_ctx_shared *sh)
624 struct mlx5_aso_mtr_pool *mtr_pool;
625 struct mlx5_flow_mtr_mng *mtrmng = sh->mtrmng;
627 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
628 struct mlx5_aso_mtr *aso_mtr;
630 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
632 if (sh->meter_aso_en) {
633 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_POLICER);
634 idx = mtrmng->pools_mng.n_valid;
636 mtr_pool = mtrmng->pools_mng.pools[idx];
637 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
638 for (i = 0; i < MLX5_ASO_MTRS_PER_POOL; i++) {
639 aso_mtr = &mtr_pool->mtrs[i];
640 if (aso_mtr->fm.meter_action)
642 (mlx5_glue->destroy_flow_action
643 (aso_mtr->fm.meter_action));
645 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
646 claim_zero(mlx5_devx_cmd_destroy
647 (mtr_pool->devx_obj));
648 mtrmng->pools_mng.n_valid--;
651 mlx5_free(sh->mtrmng->pools_mng.pools);
653 mlx5_free(sh->mtrmng);
657 /* Send FLOW_AGED event if needed. */
659 mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh)
661 struct mlx5_age_info *age_info;
664 for (i = 0; i < sh->max_port; i++) {
665 age_info = &sh->port[i].age_info;
666 if (!MLX5_AGE_GET(age_info, MLX5_AGE_EVENT_NEW))
668 MLX5_AGE_UNSET(age_info, MLX5_AGE_EVENT_NEW);
669 if (MLX5_AGE_GET(age_info, MLX5_AGE_TRIGGER)) {
670 MLX5_AGE_UNSET(age_info, MLX5_AGE_TRIGGER);
671 rte_eth_dev_callback_process
672 (&rte_eth_devices[sh->port[i].devx_ih_port_id],
673 RTE_ETH_EVENT_FLOW_AGED, NULL);
679 * Initialize the ASO connection tracking structure.
682 * Pointer to mlx5_dev_ctx_shared object.
685 * 0 on success, a negative errno value otherwise and rte_errno is set.
688 mlx5_flow_aso_ct_mng_init(struct mlx5_dev_ctx_shared *sh)
694 sh->ct_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->ct_mng),
695 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
697 DRV_LOG(ERR, "ASO CT management allocation failed.");
701 err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_CONNECTION_TRACKING);
703 mlx5_free(sh->ct_mng);
704 /* rte_errno should be extracted from the failure. */
708 rte_spinlock_init(&sh->ct_mng->ct_sl);
709 rte_rwlock_init(&sh->ct_mng->resize_rwl);
710 LIST_INIT(&sh->ct_mng->free_cts);
715 * Close and release all the resources of the
716 * ASO connection tracking management structure.
719 * Pointer to mlx5_dev_ctx_shared object to free.
722 mlx5_flow_aso_ct_mng_close(struct mlx5_dev_ctx_shared *sh)
724 struct mlx5_aso_ct_pools_mng *mng = sh->ct_mng;
725 struct mlx5_aso_ct_pool *ct_pool;
726 struct mlx5_aso_ct_action *ct;
732 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_CONNECTION_TRACKING);
736 ct_pool = mng->pools[idx];
737 for (i = 0; i < MLX5_ASO_CT_ACTIONS_PER_POOL; i++) {
738 ct = &ct_pool->actions[i];
739 val = __atomic_fetch_sub(&ct->refcnt, 1,
741 MLX5_ASSERT(val == 1);
744 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
745 if (ct->dr_action_orig)
746 claim_zero(mlx5_glue->destroy_flow_action
747 (ct->dr_action_orig));
748 if (ct->dr_action_rply)
749 claim_zero(mlx5_glue->destroy_flow_action
750 (ct->dr_action_rply));
753 claim_zero(mlx5_devx_cmd_destroy(ct_pool->devx_obj));
755 DRV_LOG(DEBUG, "%u ASO CT objects are being used in the pool %u",
759 /* in case of failure. */
762 mlx5_free(mng->pools);
764 /* Management structure must be cleared to 0s during allocation. */
769 * Initialize the flow resources' indexed mempool.
772 * Pointer to mlx5_dev_ctx_shared object.
774 * Pointer to user dev config.
777 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
778 const struct mlx5_dev_config *config)
781 struct mlx5_indexed_pool_config cfg;
783 for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
784 cfg = mlx5_ipool_cfg[i];
789 * Set MLX5_IPOOL_MLX5_FLOW ipool size
790 * according to PCI function flow configuration.
792 case MLX5_IPOOL_MLX5_FLOW:
793 cfg.size = config->dv_flow_en ?
794 sizeof(struct mlx5_flow_handle) :
795 MLX5_FLOW_HANDLE_VERBS_SIZE;
798 if (config->reclaim_mode) {
799 cfg.release_mem_en = 1;
800 cfg.per_core_cache = 0;
802 cfg.release_mem_en = 0;
804 sh->ipool[i] = mlx5_ipool_create(&cfg);
810 * Release the flow resources' indexed mempool.
813 * Pointer to mlx5_dev_ctx_shared object.
816 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
820 for (i = 0; i < MLX5_IPOOL_MAX; ++i)
821 mlx5_ipool_destroy(sh->ipool[i]);
822 for (i = 0; i < MLX5_MAX_MODIFY_NUM; ++i)
823 if (sh->mdh_ipools[i])
824 mlx5_ipool_destroy(sh->mdh_ipools[i]);
828 * Check if dynamic flex parser for eCPRI already exists.
831 * Pointer to Ethernet device structure.
834 * true on exists, false on not.
837 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
839 struct mlx5_priv *priv = dev->data->dev_private;
840 struct mlx5_flex_parser_profiles *prf =
841 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
847 * Allocation of a flex parser for eCPRI. Once created, this parser related
848 * resources will be held until the device is closed.
851 * Pointer to Ethernet device structure.
854 * 0 on success, a negative errno value otherwise and rte_errno is set.
857 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
859 struct mlx5_priv *priv = dev->data->dev_private;
860 struct mlx5_flex_parser_profiles *prf =
861 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
862 struct mlx5_devx_graph_node_attr node = {
863 .modify_field_select = 0,
868 if (!priv->config.hca_attr.parse_graph_flex_node) {
869 DRV_LOG(ERR, "Dynamic flex parser is not supported "
870 "for device %s.", priv->dev_data->name);
873 node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED;
874 /* 8 bytes now: 4B common header + 4B message body header. */
875 node.header_length_base_value = 0x8;
876 /* After MAC layer: Ether / VLAN. */
877 node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC;
878 /* Type of compared condition should be 0xAEFE in the L2 layer. */
879 node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI;
880 /* Sample #0: type in common header. */
881 node.sample[0].flow_match_sample_en = 1;
883 node.sample[0].flow_match_sample_offset_mode = 0x0;
884 /* Only the 2nd byte will be used. */
885 node.sample[0].flow_match_sample_field_base_offset = 0x0;
886 /* Sample #1: message payload. */
887 node.sample[1].flow_match_sample_en = 1;
889 node.sample[1].flow_match_sample_offset_mode = 0x0;
891 * Only the first two bytes will be used right now, and its offset will
892 * start after the common header that with the length of a DW(u32).
894 node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);
895 prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->ctx, &node);
897 DRV_LOG(ERR, "Failed to create flex parser node object.");
898 return (rte_errno == 0) ? -ENODEV : -rte_errno;
901 ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num);
903 DRV_LOG(ERR, "Failed to query sample IDs.");
904 return (rte_errno == 0) ? -ENODEV : -rte_errno;
906 prf->offset[0] = 0x0;
907 prf->offset[1] = sizeof(uint32_t);
908 prf->ids[0] = ids[0];
909 prf->ids[1] = ids[1];
914 * Destroy the flex parser node, including the parser itself, input / output
915 * arcs and DW samples. Resources could be reused then.
918 * Pointer to Ethernet device structure.
921 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
923 struct mlx5_priv *priv = dev->data->dev_private;
924 struct mlx5_flex_parser_profiles *prf =
925 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
928 mlx5_devx_cmd_destroy(prf->obj);
933 * Allocate Rx and Tx UARs in robust fashion.
934 * This routine handles the following UAR allocation issues:
936 * - tries to allocate the UAR with the most appropriate memory
937 * mapping type from the ones supported by the host
939 * - tries to allocate the UAR with non-NULL base address
940 * OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as
941 * UAR base address if UAR was not the first object in the UAR page.
942 * It caused the PMD failure and we should try to get another UAR
943 * till we get the first one with non-NULL base address returned.
946 mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh,
947 const struct mlx5_dev_config *config)
949 uint32_t uar_mapping, retry;
953 for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
954 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
955 /* Control the mapping type according to the settings. */
956 uar_mapping = (config->dbnc == MLX5_TXDB_NCACHED) ?
957 MLX5DV_UAR_ALLOC_TYPE_NC :
958 MLX5DV_UAR_ALLOC_TYPE_BF;
960 RTE_SET_USED(config);
962 * It seems we have no way to control the memory mapping type
963 * for the UAR, the default "Write-Combining" type is supposed.
964 * The UAR initialization on queue creation queries the
965 * actual mapping type done by Verbs/kernel and setups the
966 * PMD datapath accordingly.
970 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->ctx, uar_mapping);
971 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
973 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
974 if (config->dbnc == MLX5_TXDB_CACHED ||
975 config->dbnc == MLX5_TXDB_HEURISTIC)
976 DRV_LOG(WARNING, "Devarg tx_db_nc setting "
977 "is not supported by DevX");
979 * In some environments like virtual machine
980 * the Write Combining mapped might be not supported
981 * and UAR allocation fails. We try "Non-Cached"
982 * mapping for the case. The tx_burst routines take
983 * the UAR mapping type into account on UAR setup
986 DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (BF)");
987 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
988 sh->tx_uar = mlx5_glue->devx_alloc_uar
989 (sh->ctx, uar_mapping);
990 } else if (!sh->tx_uar &&
991 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_NC) {
992 if (config->dbnc == MLX5_TXDB_NCACHED)
993 DRV_LOG(WARNING, "Devarg tx_db_nc settings "
994 "is not supported by DevX");
996 * If Verbs/kernel does not support "Non-Cached"
997 * try the "Write-Combining".
999 DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (NC)");
1000 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_BF;
1001 sh->tx_uar = mlx5_glue->devx_alloc_uar
1002 (sh->ctx, uar_mapping);
1006 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (BF/NC)");
1010 base_addr = mlx5_os_get_devx_uar_base_addr(sh->tx_uar);
1014 * The UARs are allocated by rdma_core within the
1015 * IB device context, on context closure all UARs
1016 * will be freed, should be no memory/object leakage.
1018 DRV_LOG(DEBUG, "Retrying to allocate Tx DevX UAR");
1021 /* Check whether we finally succeeded with valid UAR allocation. */
1023 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (NULL base)");
1027 for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
1029 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
1030 (sh->ctx, uar_mapping);
1031 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
1032 if (!sh->devx_rx_uar &&
1033 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
1035 * Rx UAR is used to control interrupts only,
1036 * should be no datapath noticeable impact,
1037 * can try "Non-Cached" mapping safely.
1039 DRV_LOG(DEBUG, "Failed to allocate Rx DevX UAR (BF)");
1040 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
1041 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
1042 (sh->ctx, uar_mapping);
1045 if (!sh->devx_rx_uar) {
1046 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (BF/NC)");
1050 base_addr = mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar);
1054 * The UARs are allocated by rdma_core within the
1055 * IB device context, on context closure all UARs
1056 * will be freed, should be no memory/object leakage.
1058 DRV_LOG(DEBUG, "Retrying to allocate Rx DevX UAR");
1059 sh->devx_rx_uar = NULL;
1061 /* Check whether we finally succeeded with valid UAR allocation. */
1062 if (!sh->devx_rx_uar) {
1063 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (NULL base)");
1071 * Allocate shared device context. If there is multiport device the
1072 * master and representors will share this context, if there is single
1073 * port dedicated device, the context will be used by only given
1074 * port due to unification.
1076 * Routine first searches the context for the specified device name,
1077 * if found the shared context assumed and reference counter is incremented.
1078 * If no context found the new one is created and initialized with specified
1079 * device context and parameters.
1082 * Pointer to the device attributes (name, port, etc).
1084 * Pointer to device configuration structure.
1087 * Pointer to mlx5_dev_ctx_shared object on success,
1088 * otherwise NULL and rte_errno is set.
1090 struct mlx5_dev_ctx_shared *
1091 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
1092 const struct mlx5_dev_config *config)
1094 struct mlx5_dev_ctx_shared *sh;
1097 struct mlx5_devx_tis_attr tis_attr = { 0 };
1100 /* Secondary process should not create the shared context. */
1101 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1102 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1103 /* Search for IB context by device name. */
1104 LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
1105 if (!strcmp(sh->ibdev_name,
1106 mlx5_os_get_dev_device_name(spawn->phys_dev))) {
1111 /* No device found, we have to create new shared context. */
1112 MLX5_ASSERT(spawn->max_port);
1113 sh = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
1114 sizeof(struct mlx5_dev_ctx_shared) +
1116 sizeof(struct mlx5_dev_shared_port),
1117 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
1119 DRV_LOG(ERR, "shared context allocation failure");
1123 if (spawn->bond_info)
1124 sh->bond = *spawn->bond_info;
1125 err = mlx5_os_open_device(spawn, config, sh);
1128 err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
1130 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
1134 sh->max_port = spawn->max_port;
1135 sh->reclaim_mode = config->reclaim_mode;
1136 strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
1137 sizeof(sh->ibdev_name) - 1);
1138 strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
1139 sizeof(sh->ibdev_path) - 1);
1141 * Setting port_id to max unallowed value means
1142 * there is no interrupt subhandler installed for
1143 * the given port index i.
1145 for (i = 0; i < sh->max_port; i++) {
1146 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
1147 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
1149 sh->pd = mlx5_os_alloc_pd(sh->ctx);
1150 if (sh->pd == NULL) {
1151 DRV_LOG(ERR, "PD allocation failure");
1156 err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
1158 DRV_LOG(ERR, "Fail to extract pdn from PD");
1161 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
1163 DRV_LOG(ERR, "TD allocation failure");
1167 tis_attr.transport_domain = sh->td->id;
1168 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
1170 DRV_LOG(ERR, "TIS allocation failure");
1174 err = mlx5_alloc_rxtx_uars(sh, config);
1177 MLX5_ASSERT(sh->tx_uar);
1178 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->tx_uar));
1180 MLX5_ASSERT(sh->devx_rx_uar);
1181 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar));
1184 /* Initialize UAR access locks for 32bit implementations. */
1185 rte_spinlock_init(&sh->uar_lock_cq);
1186 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
1187 rte_spinlock_init(&sh->uar_lock[i]);
1190 * Once the device is added to the list of memory event
1191 * callback, its global MR cache table cannot be expanded
1192 * on the fly because of deadlock. If it overflows, lookup
1193 * should be done by searching MR list linearly, which is slow.
1195 * At this point the device is not added to the memory
1196 * event list yet, context is just being created.
1198 err = mlx5_mr_btree_init(&sh->share_cache.cache,
1199 MLX5_MR_BTREE_CACHE_N * 2,
1200 spawn->pci_dev->device.numa_node);
1205 mlx5_os_set_reg_mr_cb(&sh->share_cache.reg_mr_cb,
1206 &sh->share_cache.dereg_mr_cb);
1207 mlx5_os_dev_shared_handler_install(sh);
1208 sh->cnt_id_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_DWORD);
1209 if (!sh->cnt_id_tbl) {
1213 if (LIST_EMPTY(&mlx5_dev_ctx_list)) {
1214 err = mlx5_flow_os_init_workspace_once();
1218 mlx5_flow_aging_init(sh);
1219 mlx5_flow_counters_mng_init(sh);
1220 mlx5_flow_ipool_create(sh, config);
1221 /* Add device to memory callback list. */
1222 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1223 LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
1225 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1226 /* Add context to the global device list. */
1227 LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
1228 rte_spinlock_init(&sh->geneve_tlv_opt_sl);
1230 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1233 pthread_mutex_destroy(&sh->txpp.mutex);
1234 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1237 mlx5_l3t_destroy(sh->cnt_id_tbl);
1239 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1241 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1242 if (sh->devx_rx_uar)
1243 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1245 mlx5_glue->devx_free_uar(sh->tx_uar);
1247 claim_zero(mlx5_os_dealloc_pd(sh->pd));
1249 claim_zero(mlx5_glue->close_device(sh->ctx));
1251 MLX5_ASSERT(err > 0);
1257 * Free shared IB device context. Decrement counter and if zero free
1258 * all allocated resources and close handles.
1261 * Pointer to mlx5_dev_ctx_shared object to free
1264 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
1266 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1267 #ifdef RTE_LIBRTE_MLX5_DEBUG
1268 /* Check the object presence in the list. */
1269 struct mlx5_dev_ctx_shared *lctx;
1271 LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
1276 DRV_LOG(ERR, "Freeing non-existing shared IB context");
1281 MLX5_ASSERT(sh->refcnt);
1282 /* Secondary process should not free the shared context. */
1283 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1286 /* Remove from memory callback device list. */
1287 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1288 LIST_REMOVE(sh, mem_event_cb);
1289 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1290 /* Release created Memory Regions. */
1291 mlx5_mr_release_cache(&sh->share_cache);
1292 /* Remove context from the global device list. */
1293 LIST_REMOVE(sh, next);
1294 /* Release flow workspaces objects on the last device. */
1295 if (LIST_EMPTY(&mlx5_dev_ctx_list))
1296 mlx5_flow_os_release_workspace();
1297 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1299 * Ensure there is no async event handler installed.
1300 * Only primary process handles async device events.
1302 mlx5_flow_counters_mng_close(sh);
1303 if (sh->aso_age_mng) {
1304 mlx5_flow_aso_age_mng_close(sh);
1305 sh->aso_age_mng = NULL;
1308 mlx5_aso_flow_mtrs_mng_close(sh);
1309 mlx5_flow_ipool_destroy(sh);
1310 mlx5_os_dev_shared_handler_uninstall(sh);
1311 if (sh->cnt_id_tbl) {
1312 mlx5_l3t_destroy(sh->cnt_id_tbl);
1313 sh->cnt_id_tbl = NULL;
1316 mlx5_glue->devx_free_uar(sh->tx_uar);
1320 claim_zero(mlx5_os_dealloc_pd(sh->pd));
1322 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1324 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1325 if (sh->devx_rx_uar)
1326 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1328 claim_zero(mlx5_glue->close_device(sh->ctx));
1329 MLX5_ASSERT(sh->geneve_tlv_option_resource == NULL);
1330 pthread_mutex_destroy(&sh->txpp.mutex);
1334 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1338 * Destroy table hash list.
1341 * Pointer to the private device data structure.
1344 mlx5_free_table_hash_list(struct mlx5_priv *priv)
1346 struct mlx5_dev_ctx_shared *sh = priv->sh;
1350 mlx5_hlist_destroy(sh->flow_tbls);
1354 * Initialize flow table hash list and create the root tables entry
1358 * Pointer to the private device data structure.
1361 * Zero on success, positive error code otherwise.
1364 mlx5_alloc_table_hash_list(struct mlx5_priv *priv __rte_unused)
1367 /* Tables are only used in DV and DR modes. */
1368 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
1369 struct mlx5_dev_ctx_shared *sh = priv->sh;
1370 char s[MLX5_NAME_SIZE];
1373 snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1374 sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE,
1376 flow_dv_tbl_create_cb,
1377 flow_dv_tbl_match_cb,
1378 flow_dv_tbl_remove_cb,
1379 flow_dv_tbl_clone_cb,
1380 flow_dv_tbl_clone_free_cb);
1381 if (!sh->flow_tbls) {
1382 DRV_LOG(ERR, "flow tables with hash creation failed.");
1386 #ifndef HAVE_MLX5DV_DR
1387 struct rte_flow_error error;
1388 struct rte_eth_dev *dev = &rte_eth_devices[priv->dev_data->port_id];
1391 * In case we have not DR support, the zero tables should be created
1392 * because DV expect to see them even if they cannot be created by
1395 if (!flow_dv_tbl_resource_get(dev, 0, 0, 0, 0,
1396 NULL, 0, 1, 0, &error) ||
1397 !flow_dv_tbl_resource_get(dev, 0, 1, 0, 0,
1398 NULL, 0, 1, 0, &error) ||
1399 !flow_dv_tbl_resource_get(dev, 0, 0, 1, 0,
1400 NULL, 0, 1, 0, &error)) {
1406 mlx5_free_table_hash_list(priv);
1407 #endif /* HAVE_MLX5DV_DR */
1413 * Retrieve integer value from environment variable.
1416 * Environment variable name.
1419 * Integer value, 0 if the variable is not set.
1422 mlx5_getenv_int(const char *name)
1424 const char *val = getenv(name);
1432 * DPDK callback to add udp tunnel port
1435 * A pointer to eth_dev
1436 * @param[in] udp_tunnel
1437 * A pointer to udp tunnel
1440 * 0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1443 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1444 struct rte_eth_udp_tunnel *udp_tunnel)
1446 MLX5_ASSERT(udp_tunnel != NULL);
1447 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1448 udp_tunnel->udp_port == 4789)
1450 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1451 udp_tunnel->udp_port == 4790)
1457 * Initialize process private data structure.
1460 * Pointer to Ethernet device structure.
1463 * 0 on success, a negative errno value otherwise and rte_errno is set.
1466 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1468 struct mlx5_priv *priv = dev->data->dev_private;
1469 struct mlx5_proc_priv *ppriv;
1472 mlx5_proc_priv_uninit(dev);
1474 * UAR register table follows the process private structure. BlueFlame
1475 * registers for Tx queues are stored in the table.
1478 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1479 ppriv = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, ppriv_size,
1480 RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1485 ppriv->uar_table_sz = priv->txqs_n;
1486 dev->process_private = ppriv;
1491 * Un-initialize process private data structure.
1494 * Pointer to Ethernet device structure.
1497 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1499 if (!dev->process_private)
1501 mlx5_free(dev->process_private);
1502 dev->process_private = NULL;
1506 * DPDK callback to close the device.
1508 * Destroy all queues and objects, free memory.
1511 * Pointer to Ethernet device structure.
1514 mlx5_dev_close(struct rte_eth_dev *dev)
1516 struct mlx5_priv *priv = dev->data->dev_private;
1520 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1521 /* Check if process_private released. */
1522 if (!dev->process_private)
1524 mlx5_tx_uar_uninit_secondary(dev);
1525 mlx5_proc_priv_uninit(dev);
1526 rte_eth_dev_release_port(dev);
1531 DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1533 ((priv->sh->ctx != NULL) ?
1534 mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
1536 * If default mreg copy action is removed at the stop stage,
1537 * the search will return none and nothing will be done anymore.
1539 mlx5_flow_stop_default(dev);
1540 mlx5_traffic_disable(dev);
1542 * If all the flows are already flushed in the device stop stage,
1543 * then this will return directly without any action.
1545 mlx5_flow_list_flush(dev, MLX5_FLOW_TYPE_GEN, true);
1546 mlx5_action_handle_flush(dev);
1547 mlx5_flow_meter_flush(dev, NULL);
1548 /* Prevent crashes when queues are still in use. */
1549 dev->rx_pkt_burst = removed_rx_burst;
1550 dev->tx_pkt_burst = removed_tx_burst;
1552 /* Disable datapath on secondary process. */
1553 mlx5_mp_os_req_stop_rxtx(dev);
1554 /* Free the eCPRI flex parser resource. */
1555 mlx5_flex_parser_ecpri_release(dev);
1556 if (priv->rxqs != NULL) {
1557 /* XXX race condition if mlx5_rx_burst() is still running. */
1558 rte_delay_us_sleep(1000);
1559 for (i = 0; (i != priv->rxqs_n); ++i)
1560 mlx5_rxq_release(dev, i);
1564 if (priv->txqs != NULL) {
1565 /* XXX race condition if mlx5_tx_burst() is still running. */
1566 rte_delay_us_sleep(1000);
1567 for (i = 0; (i != priv->txqs_n); ++i)
1568 mlx5_txq_release(dev, i);
1572 mlx5_proc_priv_uninit(dev);
1573 if (priv->q_counters) {
1574 mlx5_devx_cmd_destroy(priv->q_counters);
1575 priv->q_counters = NULL;
1577 if (priv->drop_queue.hrxq)
1578 mlx5_drop_action_destroy(dev);
1579 if (priv->mreg_cp_tbl)
1580 mlx5_hlist_destroy(priv->mreg_cp_tbl);
1581 mlx5_mprq_free_mp(dev);
1582 if (priv->sh->ct_mng)
1583 mlx5_flow_aso_ct_mng_close(priv->sh);
1584 mlx5_os_free_shared_dr(priv);
1585 if (priv->rss_conf.rss_key != NULL)
1586 mlx5_free(priv->rss_conf.rss_key);
1587 if (priv->reta_idx != NULL)
1588 mlx5_free(priv->reta_idx);
1589 if (priv->config.vf)
1590 mlx5_os_mac_addr_flush(dev);
1591 if (priv->nl_socket_route >= 0)
1592 close(priv->nl_socket_route);
1593 if (priv->nl_socket_rdma >= 0)
1594 close(priv->nl_socket_rdma);
1595 if (priv->vmwa_context)
1596 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1597 ret = mlx5_hrxq_verify(dev);
1599 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1600 dev->data->port_id);
1601 ret = mlx5_ind_table_obj_verify(dev);
1603 DRV_LOG(WARNING, "port %u some indirection table still remain",
1604 dev->data->port_id);
1605 ret = mlx5_rxq_obj_verify(dev);
1607 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1608 dev->data->port_id);
1609 ret = mlx5_rxq_verify(dev);
1611 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1612 dev->data->port_id);
1613 ret = mlx5_txq_obj_verify(dev);
1615 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1616 dev->data->port_id);
1617 ret = mlx5_txq_verify(dev);
1619 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1620 dev->data->port_id);
1621 ret = mlx5_flow_verify(dev);
1623 DRV_LOG(WARNING, "port %u some flows still remain",
1624 dev->data->port_id);
1626 mlx5_list_destroy(priv->hrxqs);
1628 * Free the shared context in last turn, because the cleanup
1629 * routines above may use some shared fields, like
1630 * mlx5_os_mac_addr_flush() uses ibdev_path for retrieveing
1631 * ifindex if Netlink fails.
1633 mlx5_free_shared_dev_ctx(priv->sh);
1634 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1638 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1639 struct mlx5_priv *opriv =
1640 rte_eth_devices[port_id].data->dev_private;
1643 opriv->domain_id != priv->domain_id ||
1644 &rte_eth_devices[port_id] == dev)
1650 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1652 memset(priv, 0, sizeof(*priv));
1653 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1655 * Reset mac_addrs to NULL such that it is not freed as part of
1656 * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1657 * it is freed when dev_private is freed.
1659 dev->data->mac_addrs = NULL;
1663 const struct eth_dev_ops mlx5_dev_ops = {
1664 .dev_configure = mlx5_dev_configure,
1665 .dev_start = mlx5_dev_start,
1666 .dev_stop = mlx5_dev_stop,
1667 .dev_set_link_down = mlx5_set_link_down,
1668 .dev_set_link_up = mlx5_set_link_up,
1669 .dev_close = mlx5_dev_close,
1670 .promiscuous_enable = mlx5_promiscuous_enable,
1671 .promiscuous_disable = mlx5_promiscuous_disable,
1672 .allmulticast_enable = mlx5_allmulticast_enable,
1673 .allmulticast_disable = mlx5_allmulticast_disable,
1674 .link_update = mlx5_link_update,
1675 .stats_get = mlx5_stats_get,
1676 .stats_reset = mlx5_stats_reset,
1677 .xstats_get = mlx5_xstats_get,
1678 .xstats_reset = mlx5_xstats_reset,
1679 .xstats_get_names = mlx5_xstats_get_names,
1680 .fw_version_get = mlx5_fw_version_get,
1681 .dev_infos_get = mlx5_dev_infos_get,
1682 .representor_info_get = mlx5_representor_info_get,
1683 .read_clock = mlx5_txpp_read_clock,
1684 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1685 .vlan_filter_set = mlx5_vlan_filter_set,
1686 .rx_queue_setup = mlx5_rx_queue_setup,
1687 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1688 .tx_queue_setup = mlx5_tx_queue_setup,
1689 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1690 .rx_queue_release = mlx5_rx_queue_release,
1691 .tx_queue_release = mlx5_tx_queue_release,
1692 .rx_queue_start = mlx5_rx_queue_start,
1693 .rx_queue_stop = mlx5_rx_queue_stop,
1694 .tx_queue_start = mlx5_tx_queue_start,
1695 .tx_queue_stop = mlx5_tx_queue_stop,
1696 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1697 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1698 .mac_addr_remove = mlx5_mac_addr_remove,
1699 .mac_addr_add = mlx5_mac_addr_add,
1700 .mac_addr_set = mlx5_mac_addr_set,
1701 .set_mc_addr_list = mlx5_set_mc_addr_list,
1702 .mtu_set = mlx5_dev_set_mtu,
1703 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1704 .vlan_offload_set = mlx5_vlan_offload_set,
1705 .reta_update = mlx5_dev_rss_reta_update,
1706 .reta_query = mlx5_dev_rss_reta_query,
1707 .rss_hash_update = mlx5_rss_hash_update,
1708 .rss_hash_conf_get = mlx5_rss_hash_conf_get,
1709 .flow_ops_get = mlx5_flow_ops_get,
1710 .rxq_info_get = mlx5_rxq_info_get,
1711 .txq_info_get = mlx5_txq_info_get,
1712 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1713 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1714 .rx_queue_intr_enable = mlx5_rx_intr_enable,
1715 .rx_queue_intr_disable = mlx5_rx_intr_disable,
1716 .is_removed = mlx5_is_removed,
1717 .udp_tunnel_port_add = mlx5_udp_tunnel_port_add,
1718 .get_module_info = mlx5_get_module_info,
1719 .get_module_eeprom = mlx5_get_module_eeprom,
1720 .hairpin_cap_get = mlx5_hairpin_cap_get,
1721 .mtr_ops_get = mlx5_flow_meter_ops_get,
1722 .hairpin_bind = mlx5_hairpin_bind,
1723 .hairpin_unbind = mlx5_hairpin_unbind,
1724 .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1725 .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1726 .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1727 .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1728 .get_monitor_addr = mlx5_get_monitor_addr,
1731 /* Available operations from secondary process. */
1732 const struct eth_dev_ops mlx5_dev_sec_ops = {
1733 .stats_get = mlx5_stats_get,
1734 .stats_reset = mlx5_stats_reset,
1735 .xstats_get = mlx5_xstats_get,
1736 .xstats_reset = mlx5_xstats_reset,
1737 .xstats_get_names = mlx5_xstats_get_names,
1738 .fw_version_get = mlx5_fw_version_get,
1739 .dev_infos_get = mlx5_dev_infos_get,
1740 .read_clock = mlx5_txpp_read_clock,
1741 .rx_queue_start = mlx5_rx_queue_start,
1742 .rx_queue_stop = mlx5_rx_queue_stop,
1743 .tx_queue_start = mlx5_tx_queue_start,
1744 .tx_queue_stop = mlx5_tx_queue_stop,
1745 .rxq_info_get = mlx5_rxq_info_get,
1746 .txq_info_get = mlx5_txq_info_get,
1747 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1748 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1749 .get_module_info = mlx5_get_module_info,
1750 .get_module_eeprom = mlx5_get_module_eeprom,
1753 /* Available operations in flow isolated mode. */
1754 const struct eth_dev_ops mlx5_dev_ops_isolate = {
1755 .dev_configure = mlx5_dev_configure,
1756 .dev_start = mlx5_dev_start,
1757 .dev_stop = mlx5_dev_stop,
1758 .dev_set_link_down = mlx5_set_link_down,
1759 .dev_set_link_up = mlx5_set_link_up,
1760 .dev_close = mlx5_dev_close,
1761 .promiscuous_enable = mlx5_promiscuous_enable,
1762 .promiscuous_disable = mlx5_promiscuous_disable,
1763 .allmulticast_enable = mlx5_allmulticast_enable,
1764 .allmulticast_disable = mlx5_allmulticast_disable,
1765 .link_update = mlx5_link_update,
1766 .stats_get = mlx5_stats_get,
1767 .stats_reset = mlx5_stats_reset,
1768 .xstats_get = mlx5_xstats_get,
1769 .xstats_reset = mlx5_xstats_reset,
1770 .xstats_get_names = mlx5_xstats_get_names,
1771 .fw_version_get = mlx5_fw_version_get,
1772 .dev_infos_get = mlx5_dev_infos_get,
1773 .read_clock = mlx5_txpp_read_clock,
1774 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1775 .vlan_filter_set = mlx5_vlan_filter_set,
1776 .rx_queue_setup = mlx5_rx_queue_setup,
1777 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1778 .tx_queue_setup = mlx5_tx_queue_setup,
1779 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1780 .rx_queue_release = mlx5_rx_queue_release,
1781 .tx_queue_release = mlx5_tx_queue_release,
1782 .rx_queue_start = mlx5_rx_queue_start,
1783 .rx_queue_stop = mlx5_rx_queue_stop,
1784 .tx_queue_start = mlx5_tx_queue_start,
1785 .tx_queue_stop = mlx5_tx_queue_stop,
1786 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1787 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1788 .mac_addr_remove = mlx5_mac_addr_remove,
1789 .mac_addr_add = mlx5_mac_addr_add,
1790 .mac_addr_set = mlx5_mac_addr_set,
1791 .set_mc_addr_list = mlx5_set_mc_addr_list,
1792 .mtu_set = mlx5_dev_set_mtu,
1793 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1794 .vlan_offload_set = mlx5_vlan_offload_set,
1795 .flow_ops_get = mlx5_flow_ops_get,
1796 .rxq_info_get = mlx5_rxq_info_get,
1797 .txq_info_get = mlx5_txq_info_get,
1798 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1799 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1800 .rx_queue_intr_enable = mlx5_rx_intr_enable,
1801 .rx_queue_intr_disable = mlx5_rx_intr_disable,
1802 .is_removed = mlx5_is_removed,
1803 .get_module_info = mlx5_get_module_info,
1804 .get_module_eeprom = mlx5_get_module_eeprom,
1805 .hairpin_cap_get = mlx5_hairpin_cap_get,
1806 .mtr_ops_get = mlx5_flow_meter_ops_get,
1807 .hairpin_bind = mlx5_hairpin_bind,
1808 .hairpin_unbind = mlx5_hairpin_unbind,
1809 .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1810 .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1811 .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1812 .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1813 .get_monitor_addr = mlx5_get_monitor_addr,
1817 * Verify and store value for device argument.
1820 * Key argument to verify.
1822 * Value associated with key.
1827 * 0 on success, a negative errno value otherwise and rte_errno is set.
1830 mlx5_args_check(const char *key, const char *val, void *opaque)
1832 struct mlx5_dev_config *config = opaque;
1836 /* No-op, port representors are processed in mlx5_dev_spawn(). */
1837 if (!strcmp(MLX5_REPRESENTOR, key))
1840 tmp = strtol(val, NULL, 0);
1843 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1846 if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
1847 /* Negative values are acceptable for some keys only. */
1849 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
1852 mod = tmp >= 0 ? tmp : -tmp;
1853 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1854 if (tmp > MLX5_CQE_RESP_FORMAT_L34H_STRIDX) {
1855 DRV_LOG(ERR, "invalid CQE compression "
1856 "format parameter");
1860 config->cqe_comp = !!tmp;
1861 config->cqe_comp_fmt = tmp;
1862 } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1863 config->hw_padding = !!tmp;
1864 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1865 config->mprq.enabled = !!tmp;
1866 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1867 config->mprq.stride_num_n = tmp;
1868 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1869 config->mprq.stride_size_n = tmp;
1870 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1871 config->mprq.max_memcpy_len = tmp;
1872 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1873 config->mprq.min_rxqs_num = tmp;
1874 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1875 DRV_LOG(WARNING, "%s: deprecated parameter,"
1876 " converted to txq_inline_max", key);
1877 config->txq_inline_max = tmp;
1878 } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1879 config->txq_inline_max = tmp;
1880 } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1881 config->txq_inline_min = tmp;
1882 } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1883 config->txq_inline_mpw = tmp;
1884 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1885 config->txqs_inline = tmp;
1886 } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1887 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1888 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1889 config->mps = !!tmp;
1890 } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1891 if (tmp != MLX5_TXDB_CACHED &&
1892 tmp != MLX5_TXDB_NCACHED &&
1893 tmp != MLX5_TXDB_HEURISTIC) {
1894 DRV_LOG(ERR, "invalid Tx doorbell "
1895 "mapping parameter");
1900 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1901 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1902 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1903 DRV_LOG(WARNING, "%s: deprecated parameter,"
1904 " converted to txq_inline_mpw", key);
1905 config->txq_inline_mpw = tmp;
1906 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1907 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1908 } else if (strcmp(MLX5_TX_PP, key) == 0) {
1910 DRV_LOG(ERR, "Zero Tx packet pacing parameter");
1914 config->tx_pp = tmp;
1915 } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
1916 config->tx_skew = tmp;
1917 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1918 config->rx_vec_en = !!tmp;
1919 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1920 config->l3_vxlan_en = !!tmp;
1921 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1922 config->vf_nl_en = !!tmp;
1923 } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1924 config->dv_esw_en = !!tmp;
1925 } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1926 config->dv_flow_en = !!tmp;
1927 } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1928 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1929 tmp != MLX5_XMETA_MODE_META16 &&
1930 tmp != MLX5_XMETA_MODE_META32 &&
1931 tmp != MLX5_XMETA_MODE_MISS_INFO) {
1932 DRV_LOG(ERR, "invalid extensive "
1933 "metadata parameter");
1937 if (tmp != MLX5_XMETA_MODE_MISS_INFO)
1938 config->dv_xmeta_en = tmp;
1940 config->dv_miss_info = 1;
1941 } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
1942 config->lacp_by_user = !!tmp;
1943 } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1944 config->mr_ext_memseg_en = !!tmp;
1945 } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1946 config->max_dump_files_num = tmp;
1947 } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1948 config->lro.timeout = tmp;
1949 } else if (strcmp(RTE_DEVARGS_KEY_CLASS, key) == 0) {
1950 DRV_LOG(DEBUG, "class argument is %s.", val);
1951 } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1952 config->log_hp_size = tmp;
1953 } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1954 if (tmp != MLX5_RCM_NONE &&
1955 tmp != MLX5_RCM_LIGHT &&
1956 tmp != MLX5_RCM_AGGR) {
1957 DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1961 config->reclaim_mode = tmp;
1962 } else if (strcmp(MLX5_SYS_MEM_EN, key) == 0) {
1963 config->sys_mem_en = !!tmp;
1964 } else if (strcmp(MLX5_DECAP_EN, key) == 0) {
1965 config->decap_en = !!tmp;
1966 } else if (strcmp(MLX5_ALLOW_DUPLICATE_PATTERN, key) == 0) {
1967 config->allow_duplicate_pattern = !!tmp;
1969 DRV_LOG(WARNING, "%s: unknown parameter", key);
1977 * Parse device parameters.
1980 * Pointer to device configuration structure.
1982 * Device arguments structure.
1985 * 0 on success, a negative errno value otherwise and rte_errno is set.
1988 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1990 const char **params = (const char *[]){
1991 MLX5_RXQ_CQE_COMP_EN,
1992 MLX5_RXQ_PKT_PAD_EN,
1994 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1995 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1996 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1999 MLX5_TXQ_INLINE_MIN,
2000 MLX5_TXQ_INLINE_MAX,
2001 MLX5_TXQ_INLINE_MPW,
2002 MLX5_TXQS_MIN_INLINE,
2005 MLX5_TXQ_MPW_HDR_DSEG_EN,
2006 MLX5_TXQ_MAX_INLINE_LEN,
2018 MLX5_MR_EXT_MEMSEG_EN,
2020 MLX5_MAX_DUMP_FILES_NUM,
2021 MLX5_LRO_TIMEOUT_USEC,
2022 RTE_DEVARGS_KEY_CLASS,
2027 MLX5_ALLOW_DUPLICATE_PATTERN,
2030 struct rte_kvargs *kvlist;
2034 if (devargs == NULL)
2036 /* Following UGLY cast is done to pass checkpatch. */
2037 kvlist = rte_kvargs_parse(devargs->args, params);
2038 if (kvlist == NULL) {
2042 /* Process parameters. */
2043 for (i = 0; (params[i] != NULL); ++i) {
2044 if (rte_kvargs_count(kvlist, params[i])) {
2045 ret = rte_kvargs_process(kvlist, params[i],
2046 mlx5_args_check, config);
2049 rte_kvargs_free(kvlist);
2054 rte_kvargs_free(kvlist);
2059 * Configures the minimal amount of data to inline into WQE
2060 * while sending packets.
2062 * - the txq_inline_min has the maximal priority, if this
2063 * key is specified in devargs
2064 * - if DevX is enabled the inline mode is queried from the
2065 * device (HCA attributes and NIC vport context if needed).
2066 * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
2067 * and none (0 bytes) for other NICs
2070 * Verbs device parameters (name, port, switch_info) to spawn.
2072 * Device configuration parameters.
2075 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
2076 struct mlx5_dev_config *config)
2078 if (config->txq_inline_min != MLX5_ARG_UNSET) {
2079 /* Application defines size of inlined data explicitly. */
2080 switch (spawn->pci_dev->id.device_id) {
2081 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2082 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2083 if (config->txq_inline_min <
2084 (int)MLX5_INLINE_HSIZE_L2) {
2086 "txq_inline_mix aligned to minimal"
2087 " ConnectX-4 required value %d",
2088 (int)MLX5_INLINE_HSIZE_L2);
2089 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2095 if (config->hca_attr.eth_net_offloads) {
2096 /* We have DevX enabled, inline mode queried successfully. */
2097 switch (config->hca_attr.wqe_inline_mode) {
2098 case MLX5_CAP_INLINE_MODE_L2:
2099 /* outer L2 header must be inlined. */
2100 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2102 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
2103 /* No inline data are required by NIC. */
2104 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2105 config->hw_vlan_insert =
2106 config->hca_attr.wqe_vlan_insert;
2107 DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
2109 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
2110 /* inline mode is defined by NIC vport context. */
2111 if (!config->hca_attr.eth_virt)
2113 switch (config->hca_attr.vport_inline_mode) {
2114 case MLX5_INLINE_MODE_NONE:
2115 config->txq_inline_min =
2116 MLX5_INLINE_HSIZE_NONE;
2118 case MLX5_INLINE_MODE_L2:
2119 config->txq_inline_min =
2120 MLX5_INLINE_HSIZE_L2;
2122 case MLX5_INLINE_MODE_IP:
2123 config->txq_inline_min =
2124 MLX5_INLINE_HSIZE_L3;
2126 case MLX5_INLINE_MODE_TCP_UDP:
2127 config->txq_inline_min =
2128 MLX5_INLINE_HSIZE_L4;
2130 case MLX5_INLINE_MODE_INNER_L2:
2131 config->txq_inline_min =
2132 MLX5_INLINE_HSIZE_INNER_L2;
2134 case MLX5_INLINE_MODE_INNER_IP:
2135 config->txq_inline_min =
2136 MLX5_INLINE_HSIZE_INNER_L3;
2138 case MLX5_INLINE_MODE_INNER_TCP_UDP:
2139 config->txq_inline_min =
2140 MLX5_INLINE_HSIZE_INNER_L4;
2146 * We get here if we are unable to deduce
2147 * inline data size with DevX. Try PCI ID
2148 * to determine old NICs.
2150 switch (spawn->pci_dev->id.device_id) {
2151 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2152 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2153 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
2154 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
2155 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2156 config->hw_vlan_insert = 0;
2158 case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
2159 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
2160 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
2161 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
2163 * These NICs support VLAN insertion from WQE and
2164 * report the wqe_vlan_insert flag. But there is the bug
2165 * and PFC control may be broken, so disable feature.
2167 config->hw_vlan_insert = 0;
2168 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2171 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2175 DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
2179 * Configures the metadata mask fields in the shared context.
2182 * Pointer to Ethernet device.
2185 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
2187 struct mlx5_priv *priv = dev->data->dev_private;
2188 struct mlx5_dev_ctx_shared *sh = priv->sh;
2189 uint32_t meta, mark, reg_c0;
2191 reg_c0 = ~priv->vport_meta_mask;
2192 switch (priv->config.dv_xmeta_en) {
2193 case MLX5_XMETA_MODE_LEGACY:
2195 mark = MLX5_FLOW_MARK_MASK;
2197 case MLX5_XMETA_MODE_META16:
2198 meta = reg_c0 >> rte_bsf32(reg_c0);
2199 mark = MLX5_FLOW_MARK_MASK;
2201 case MLX5_XMETA_MODE_META32:
2203 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
2211 if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
2212 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
2213 sh->dv_mark_mask, mark);
2215 sh->dv_mark_mask = mark;
2216 if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
2217 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
2218 sh->dv_meta_mask, meta);
2220 sh->dv_meta_mask = meta;
2221 if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
2222 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
2223 sh->dv_meta_mask, reg_c0);
2225 sh->dv_regc0_mask = reg_c0;
2226 DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
2227 DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
2228 DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
2229 DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
2233 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
2235 static const char *const dynf_names[] = {
2236 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
2237 RTE_MBUF_DYNFLAG_METADATA_NAME,
2238 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
2242 if (n < RTE_DIM(dynf_names))
2244 for (i = 0; i < RTE_DIM(dynf_names); i++) {
2245 if (names[i] == NULL)
2247 strcpy(names[i], dynf_names[i]);
2249 return RTE_DIM(dynf_names);
2253 * Comparison callback to sort device data.
2255 * This is meant to be used with qsort().
2258 * Pointer to pointer to first data object.
2260 * Pointer to pointer to second data object.
2263 * 0 if both objects are equal, less than 0 if the first argument is less
2264 * than the second, greater than 0 otherwise.
2267 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
2268 struct mlx5_dev_config *config)
2270 struct mlx5_dev_ctx_shared *sh = priv->sh;
2271 struct mlx5_dev_config *sh_conf = NULL;
2275 /* Nothing to compare for the single/first device. */
2276 if (sh->refcnt == 1)
2278 /* Find the device with shared context. */
2279 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
2280 struct mlx5_priv *opriv =
2281 rte_eth_devices[port_id].data->dev_private;
2283 if (opriv && opriv != priv && opriv->sh == sh) {
2284 sh_conf = &opriv->config;
2290 if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
2291 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
2292 " for shared %s context", sh->ibdev_name);
2296 if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
2297 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
2298 " for shared %s context", sh->ibdev_name);
2306 * Look for the ethernet device belonging to mlx5 driver.
2308 * @param[in] port_id
2309 * port_id to start looking for device.
2310 * @param[in] pci_dev
2311 * Pointer to the hint PCI device. When device is being probed
2312 * the its siblings (master and preceding representors might
2313 * not have assigned driver yet (because the mlx5_os_pci_probe()
2314 * is not completed yet, for this case match on hint PCI
2315 * device may be used to detect sibling device.
2318 * port_id of found device, RTE_MAX_ETHPORT if not found.
2321 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
2323 while (port_id < RTE_MAX_ETHPORTS) {
2324 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
2326 if (dev->state != RTE_ETH_DEV_UNUSED &&
2328 (dev->device == &pci_dev->device ||
2329 (dev->device->driver &&
2330 dev->device->driver->name &&
2331 !strcmp(dev->device->driver->name, MLX5_PCI_DRIVER_NAME))))
2335 if (port_id >= RTE_MAX_ETHPORTS)
2336 return RTE_MAX_ETHPORTS;
2341 * DPDK callback to remove a PCI device.
2343 * This function removes all Ethernet devices belong to a given PCI device.
2345 * @param[in] pci_dev
2346 * Pointer to the PCI device.
2349 * 0 on success, the function cannot fail.
2352 mlx5_pci_remove(struct rte_pci_device *pci_dev)
2357 RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
2359 * mlx5_dev_close() is not registered to secondary process,
2360 * call the close function explicitly for secondary process.
2362 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
2363 ret |= mlx5_dev_close(&rte_eth_devices[port_id]);
2365 ret |= rte_eth_dev_close(port_id);
2367 return ret == 0 ? 0 : -EIO;
2370 static const struct rte_pci_id mlx5_pci_id_map[] = {
2372 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2373 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
2376 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2377 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
2380 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2381 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
2384 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2385 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
2388 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2389 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
2392 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2393 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
2396 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2397 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
2400 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2401 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
2404 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2405 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
2408 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2409 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
2412 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2413 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
2416 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2417 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
2420 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2421 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
2424 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2425 PCI_DEVICE_ID_MELLANOX_CONNECTXVF)
2428 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2429 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
2432 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2433 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
2436 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2437 PCI_DEVICE_ID_MELLANOX_CONNECTX7)
2440 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2441 PCI_DEVICE_ID_MELLANOX_CONNECTX7BF)
2448 static struct mlx5_pci_driver mlx5_driver = {
2449 .driver_class = MLX5_CLASS_ETH,
2452 .name = MLX5_PCI_DRIVER_NAME,
2454 .id_table = mlx5_pci_id_map,
2455 .probe = mlx5_os_pci_probe,
2456 .remove = mlx5_pci_remove,
2457 .dma_map = mlx5_dma_map,
2458 .dma_unmap = mlx5_dma_unmap,
2459 .drv_flags = PCI_DRV_FLAGS,
2463 /* Initialize driver log type. */
2464 RTE_LOG_REGISTER_DEFAULT(mlx5_logtype, NOTICE)
2467 * Driver initialization routine.
2469 RTE_INIT(rte_mlx5_pmd_init)
2471 pthread_mutex_init(&mlx5_dev_ctx_list_mutex, NULL);
2473 /* Build the static tables for Verbs conversion. */
2474 mlx5_set_ptype_table();
2475 mlx5_set_cksum_table();
2476 mlx5_set_swp_types_table();
2478 mlx5_pci_driver_register(&mlx5_driver);
2481 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
2482 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
2483 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");