drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <stdint.h>
  10 #include <stdlib.h>
  11 #include <errno.h>
  12
  13 #include <rte_malloc.h>
  14 #include <ethdev_driver.h>
  15 #include <rte_pci.h>
  16 #include <rte_bus_pci.h>
  17 #include <rte_common.h>
  18 #include <rte_kvargs.h>
  19 #include <rte_rwlock.h>
  20 #include <rte_spinlock.h>
  21 #include <rte_string_fns.h>
  22 #include <rte_alarm.h>
  23 #include <rte_cycles.h>
  24
  25 #include <mlx5_glue.h>
  26 #include <mlx5_devx_cmds.h>
  27 #include <mlx5_common.h>
  28 #include <mlx5_common_os.h>
  29 #include <mlx5_common_mp.h>
  30 #include <mlx5_malloc.h>
  31
  32 #include "mlx5_defs.h"
  33 #include "mlx5.h"
  34 #include "mlx5_utils.h"
  35 #include "mlx5_rxtx.h"
  36 #include "mlx5_rx.h"
  37 #include "mlx5_tx.h"
  38 #include "mlx5_autoconf.h"
  39 #include "mlx5_flow.h"
  40 #include "mlx5_flow_os.h"
  41 #include "rte_pmd_mlx5.h"
  42
  43 #define MLX5_ETH_DRIVER_NAME mlx5_eth
  44
  45 /* Driver type key for new device global syntax. */
  46 #define MLX5_DRIVER_KEY "driver"
  47
  48 /* Device parameter to enable RX completion queue compression. */
  49 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  50
  51 /* Device parameter to enable padding Rx packet to cacheline size. */
  52 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
  53
  54 /* Device parameter to enable Multi-Packet Rx queue. */
  55 #define MLX5_RX_MPRQ_EN "mprq_en"
  56
  57 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
  58 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
  59
  60 /* Device parameter to configure log 2 of the stride size for MPRQ. */
  61 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
  62
  63 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
  64 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
  65
  66 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
  67 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
  68
  69 /* Device parameter to configure inline send. Deprecated, ignored.*/
  70 #define MLX5_TXQ_INLINE "txq_inline"
  71
  72 /* Device parameter to limit packet size to inline with ordinary SEND. */
  73 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
  74
  75 /* Device parameter to configure minimal data size to inline. */
  76 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
  77
  78 /* Device parameter to limit packet size to inline with Enhanced MPW. */
  79 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
  80
  81 /*
  82  * Device parameter to configure the number of TX queues threshold for
  83  * enabling inline send.
  84  */
  85 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  86
  87 /*
  88  * Device parameter to configure the number of TX queues threshold for
  89  * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
  90  */
  91 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
  92
  93 /* Device parameter to enable multi-packet send WQEs. */
  94 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
  95
  96 /*
  97  * Device parameter to force doorbell register mapping
  98  * to non-cahed region eliminating the extra write memory barrier.
  99  */
 100 #define MLX5_TX_DB_NC "tx_db_nc"
 101
 102 /*
 103  * Device parameter to include 2 dsegs in the title WQEBB.
 104  * Deprecated, ignored.
 105  */
 106 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
 107
 108 /*
 109  * Device parameter to limit the size of inlining packet.
 110  * Deprecated, ignored.
 111  */
 112 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
 113
 114 /*
 115  * Device parameter to enable Tx scheduling on timestamps
 116  * and specify the packet pacing granularity in nanoseconds.
 117  */
 118 #define MLX5_TX_PP "tx_pp"
 119
 120 /*
 121  * Device parameter to specify skew in nanoseconds on Tx datapath,
 122  * it represents the time between SQ start WQE processing and
 123  * appearing actual packet data on the wire.
 124  */
 125 #define MLX5_TX_SKEW "tx_skew"
 126
 127 /*
 128  * Device parameter to enable hardware Tx vector.
 129  * Deprecated, ignored (no vectorized Tx routines anymore).
 130  */
 131 #define MLX5_TX_VEC_EN "tx_vec_en"
 132
 133 /* Device parameter to enable hardware Rx vector. */
 134 #define MLX5_RX_VEC_EN "rx_vec_en"
 135
 136 /* Allow L3 VXLAN flow creation. */
 137 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
 138
 139 /* Activate DV E-Switch flow steering. */
 140 #define MLX5_DV_ESW_EN "dv_esw_en"
 141
 142 /* Activate DV flow steering. */
 143 #define MLX5_DV_FLOW_EN "dv_flow_en"
 144
 145 /* Enable extensive flow metadata support. */
 146 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
 147
 148 /* Device parameter to let the user manage the lacp traffic of bonded device */
 149 #define MLX5_LACP_BY_USER "lacp_by_user"
 150
 151 /* Activate Netlink support in VF mode. */
 152 #define MLX5_VF_NL_EN "vf_nl_en"
 153
 154 /* Enable extending memsegs when creating a MR. */
 155 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
 156
 157 /* Select port representors to instantiate. */
 158 #define MLX5_REPRESENTOR "representor"
 159
 160 /* Device parameter to configure the maximum number of dump files per queue. */
 161 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
 162
 163 /* Configure timeout of LRO session (in microseconds). */
 164 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
 165
 166 /*
 167  * Device parameter to configure the total data buffer size for a single
 168  * hairpin queue (logarithm value).
 169  */
 170 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
 171
 172 /* Flow memory reclaim mode. */
 173 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
 174
 175 /* The default memory allocator used in PMD. */
 176 #define MLX5_SYS_MEM_EN "sys_mem_en"
 177 /* Decap will be used or not. */
 178 #define MLX5_DECAP_EN "decap_en"
 179
 180 /* Device parameter to configure allow or prevent duplicate rules pattern. */
 181 #define MLX5_ALLOW_DUPLICATE_PATTERN "allow_duplicate_pattern"
 182
 183 /* Device parameter to configure implicit registration of mempool memory. */
 184 #define MLX5_MR_MEMPOOL_REG_EN "mr_mempool_reg_en"
 185
 186 /* Shared memory between primary and secondary processes. */
 187 struct mlx5_shared_data *mlx5_shared_data;
 188
 189 /** Driver-specific log messages type. */
 190 int mlx5_logtype;
 191
 192 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
 193                                                 LIST_HEAD_INITIALIZER();
 194 static pthread_mutex_t mlx5_dev_ctx_list_mutex;
 195 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
 196 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
 197         [MLX5_IPOOL_DECAP_ENCAP] = {
 198                 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
 199                 .trunk_size = 64,
 200                 .grow_trunk = 3,
 201                 .grow_shift = 2,
 202                 .need_lock = 1,
 203                 .release_mem_en = 1,
 204                 .malloc = mlx5_malloc,
 205                 .free = mlx5_free,
 206                 .type = "mlx5_encap_decap_ipool",
 207         },
 208         [MLX5_IPOOL_PUSH_VLAN] = {
 209                 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
 210                 .trunk_size = 64,
 211                 .grow_trunk = 3,
 212                 .grow_shift = 2,
 213                 .need_lock = 1,
 214                 .release_mem_en = 1,
 215                 .malloc = mlx5_malloc,
 216                 .free = mlx5_free,
 217                 .type = "mlx5_push_vlan_ipool",
 218         },
 219         [MLX5_IPOOL_TAG] = {
 220                 .size = sizeof(struct mlx5_flow_dv_tag_resource),
 221                 .trunk_size = 64,
 222                 .grow_trunk = 3,
 223                 .grow_shift = 2,
 224                 .need_lock = 1,
 225                 .release_mem_en = 0,
 226                 .per_core_cache = (1 << 16),
 227                 .malloc = mlx5_malloc,
 228                 .free = mlx5_free,
 229                 .type = "mlx5_tag_ipool",
 230         },
 231         [MLX5_IPOOL_PORT_ID] = {
 232                 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
 233                 .trunk_size = 64,
 234                 .grow_trunk = 3,
 235                 .grow_shift = 2,
 236                 .need_lock = 1,
 237                 .release_mem_en = 1,
 238                 .malloc = mlx5_malloc,
 239                 .free = mlx5_free,
 240                 .type = "mlx5_port_id_ipool",
 241         },
 242         [MLX5_IPOOL_JUMP] = {
 243                 .size = sizeof(struct mlx5_flow_tbl_data_entry),
 244                 .trunk_size = 64,
 245                 .grow_trunk = 3,
 246                 .grow_shift = 2,
 247                 .need_lock = 1,
 248                 .release_mem_en = 1,
 249                 .malloc = mlx5_malloc,
 250                 .free = mlx5_free,
 251                 .type = "mlx5_jump_ipool",
 252         },
 253         [MLX5_IPOOL_SAMPLE] = {
 254                 .size = sizeof(struct mlx5_flow_dv_sample_resource),
 255                 .trunk_size = 64,
 256                 .grow_trunk = 3,
 257                 .grow_shift = 2,
 258                 .need_lock = 1,
 259                 .release_mem_en = 1,
 260                 .malloc = mlx5_malloc,
 261                 .free = mlx5_free,
 262                 .type = "mlx5_sample_ipool",
 263         },
 264         [MLX5_IPOOL_DEST_ARRAY] = {
 265                 .size = sizeof(struct mlx5_flow_dv_dest_array_resource),
 266                 .trunk_size = 64,
 267                 .grow_trunk = 3,
 268                 .grow_shift = 2,
 269                 .need_lock = 1,
 270                 .release_mem_en = 1,
 271                 .malloc = mlx5_malloc,
 272                 .free = mlx5_free,
 273                 .type = "mlx5_dest_array_ipool",
 274         },
 275         [MLX5_IPOOL_TUNNEL_ID] = {
 276                 .size = sizeof(struct mlx5_flow_tunnel),
 277                 .trunk_size = MLX5_MAX_TUNNELS,
 278                 .need_lock = 1,
 279                 .release_mem_en = 1,
 280                 .type = "mlx5_tunnel_offload",
 281         },
 282         [MLX5_IPOOL_TNL_TBL_ID] = {
 283                 .size = 0,
 284                 .need_lock = 1,
 285                 .type = "mlx5_flow_tnl_tbl_ipool",
 286         },
 287 #endif
 288         [MLX5_IPOOL_MTR] = {
 289                 /**
 290                  * The ipool index should grow continually from small to big,
 291                  * for meter idx, so not set grow_trunk to avoid meter index
 292                  * not jump continually.
 293                  */
 294                 .size = sizeof(struct mlx5_legacy_flow_meter),
 295                 .trunk_size = 64,
 296                 .need_lock = 1,
 297                 .release_mem_en = 1,
 298                 .malloc = mlx5_malloc,
 299                 .free = mlx5_free,
 300                 .type = "mlx5_meter_ipool",
 301         },
 302         [MLX5_IPOOL_MCP] = {
 303                 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
 304                 .trunk_size = 64,
 305                 .grow_trunk = 3,
 306                 .grow_shift = 2,
 307                 .need_lock = 1,
 308                 .release_mem_en = 1,
 309                 .malloc = mlx5_malloc,
 310                 .free = mlx5_free,
 311                 .type = "mlx5_mcp_ipool",
 312         },
 313         [MLX5_IPOOL_HRXQ] = {
 314                 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
 315                 .trunk_size = 64,
 316                 .grow_trunk = 3,
 317                 .grow_shift = 2,
 318                 .need_lock = 1,
 319                 .release_mem_en = 1,
 320                 .malloc = mlx5_malloc,
 321                 .free = mlx5_free,
 322                 .type = "mlx5_hrxq_ipool",
 323         },
 324         [MLX5_IPOOL_MLX5_FLOW] = {
 325                 /*
 326                  * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
 327                  * It set in run time according to PCI function configuration.
 328                  */
 329                 .size = 0,
 330                 .trunk_size = 64,
 331                 .grow_trunk = 3,
 332                 .grow_shift = 2,
 333                 .need_lock = 1,
 334                 .release_mem_en = 0,
 335                 .per_core_cache = 1 << 19,
 336                 .malloc = mlx5_malloc,
 337                 .free = mlx5_free,
 338                 .type = "mlx5_flow_handle_ipool",
 339         },
 340         [MLX5_IPOOL_RTE_FLOW] = {
 341                 .size = sizeof(struct rte_flow),
 342                 .trunk_size = 4096,
 343                 .need_lock = 1,
 344                 .release_mem_en = 1,
 345                 .malloc = mlx5_malloc,
 346                 .free = mlx5_free,
 347                 .type = "rte_flow_ipool",
 348         },
 349         [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID] = {
 350                 .size = 0,
 351                 .need_lock = 1,
 352                 .type = "mlx5_flow_rss_id_ipool",
 353         },
 354         [MLX5_IPOOL_RSS_SHARED_ACTIONS] = {
 355                 .size = sizeof(struct mlx5_shared_action_rss),
 356                 .trunk_size = 64,
 357                 .grow_trunk = 3,
 358                 .grow_shift = 2,
 359                 .need_lock = 1,
 360                 .release_mem_en = 1,
 361                 .malloc = mlx5_malloc,
 362                 .free = mlx5_free,
 363                 .type = "mlx5_shared_action_rss",
 364         },
 365         [MLX5_IPOOL_MTR_POLICY] = {
 366                 /**
 367                  * The ipool index should grow continually from small to big,
 368                  * for policy idx, so not set grow_trunk to avoid policy index
 369                  * not jump continually.
 370                  */
 371                 .size = sizeof(struct mlx5_flow_meter_sub_policy),
 372                 .trunk_size = 64,
 373                 .need_lock = 1,
 374                 .release_mem_en = 1,
 375                 .malloc = mlx5_malloc,
 376                 .free = mlx5_free,
 377                 .type = "mlx5_meter_policy_ipool",
 378         },
 379 };
 380
 381 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
 382 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
 383
 384 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 1024
 385
 386 /**
 387  * Decide whether representor ID is a HPF(host PF) port on BF2.
 388  *
 389  * @param dev
 390  *   Pointer to Ethernet device structure.
 391  *
 392  * @return
 393  *   Non-zero if HPF, otherwise 0.
 394  */
 395 bool
 396 mlx5_is_hpf(struct rte_eth_dev *dev)
 397 {
 398         struct mlx5_priv *priv = dev->data->dev_private;
 399         uint16_t repr = MLX5_REPRESENTOR_REPR(priv->representor_id);
 400         int type = MLX5_REPRESENTOR_TYPE(priv->representor_id);
 401
 402         return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_VF &&
 403                MLX5_REPRESENTOR_REPR(-1) == repr;
 404 }
 405
 406 /**
 407  * Decide whether representor ID is a SF port representor.
 408  *
 409  * @param dev
 410  *   Pointer to Ethernet device structure.
 411  *
 412  * @return
 413  *   Non-zero if HPF, otherwise 0.
 414  */
 415 bool
 416 mlx5_is_sf_repr(struct rte_eth_dev *dev)
 417 {
 418         struct mlx5_priv *priv = dev->data->dev_private;
 419         int type = MLX5_REPRESENTOR_TYPE(priv->representor_id);
 420
 421         return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_SF;
 422 }
 423
 424 /**
 425  * Initialize the ASO aging management structure.
 426  *
 427  * @param[in] sh
 428  *   Pointer to mlx5_dev_ctx_shared object to free
 429  *
 430  * @return
 431  *   0 on success, a negative errno value otherwise and rte_errno is set.
 432  */
 433 int
 434 mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh)
 435 {
 436         int err;
 437
 438         if (sh->aso_age_mng)
 439                 return 0;
 440         sh->aso_age_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->aso_age_mng),
 441                                       RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 442         if (!sh->aso_age_mng) {
 443                 DRV_LOG(ERR, "aso_age_mng allocation was failed.");
 444                 rte_errno = ENOMEM;
 445                 return -ENOMEM;
 446         }
 447         err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_FLOW_HIT);
 448         if (err) {
 449                 mlx5_free(sh->aso_age_mng);
 450                 return -1;
 451         }
 452         rte_rwlock_init(&sh->aso_age_mng->resize_rwl);
 453         rte_spinlock_init(&sh->aso_age_mng->free_sl);
 454         LIST_INIT(&sh->aso_age_mng->free);
 455         return 0;
 456 }
 457
 458 /**
 459  * Close and release all the resources of the ASO aging management structure.
 460  *
 461  * @param[in] sh
 462  *   Pointer to mlx5_dev_ctx_shared object to free.
 463  */
 464 static void
 465 mlx5_flow_aso_age_mng_close(struct mlx5_dev_ctx_shared *sh)
 466 {
 467         int i, j;
 468
 469         mlx5_aso_flow_hit_queue_poll_stop(sh);
 470         mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_FLOW_HIT);
 471         if (sh->aso_age_mng->pools) {
 472                 struct mlx5_aso_age_pool *pool;
 473
 474                 for (i = 0; i < sh->aso_age_mng->next; ++i) {
 475                         pool = sh->aso_age_mng->pools[i];
 476                         claim_zero(mlx5_devx_cmd_destroy
 477                                                 (pool->flow_hit_aso_obj));
 478                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j)
 479                                 if (pool->actions[j].dr_action)
 480                                         claim_zero
 481                                             (mlx5_flow_os_destroy_flow_action
 482                                               (pool->actions[j].dr_action));
 483                         mlx5_free(pool);
 484                 }
 485                 mlx5_free(sh->aso_age_mng->pools);
 486         }
 487         mlx5_free(sh->aso_age_mng);
 488 }
 489
 490 /**
 491  * Initialize the shared aging list information per port.
 492  *
 493  * @param[in] sh
 494  *   Pointer to mlx5_dev_ctx_shared object.
 495  */
 496 static void
 497 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
 498 {
 499         uint32_t i;
 500         struct mlx5_age_info *age_info;
 501
 502         for (i = 0; i < sh->max_port; i++) {
 503                 age_info = &sh->port[i].age_info;
 504                 age_info->flags = 0;
 505                 TAILQ_INIT(&age_info->aged_counters);
 506                 LIST_INIT(&age_info->aged_aso);
 507                 rte_spinlock_init(&age_info->aged_sl);
 508                 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
 509         }
 510 }
 511
 512 /**
 513  * Initialize the counters management structure.
 514  *
 515  * @param[in] sh
 516  *   Pointer to mlx5_dev_ctx_shared object to free
 517  */
 518 static void
 519 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
 520 {
 521         struct mlx5_hca_attr *attr = &sh->cdev->config.hca_attr;
 522         int i;
 523
 524         memset(&sh->cmng, 0, sizeof(sh->cmng));
 525         TAILQ_INIT(&sh->cmng.flow_counters);
 526         sh->cmng.min_id = MLX5_CNT_BATCH_OFFSET;
 527         sh->cmng.max_id = -1;
 528         sh->cmng.last_pool_idx = POOL_IDX_INVALID;
 529         rte_spinlock_init(&sh->cmng.pool_update_sl);
 530         for (i = 0; i < MLX5_COUNTER_TYPE_MAX; i++) {
 531                 TAILQ_INIT(&sh->cmng.counters[i]);
 532                 rte_spinlock_init(&sh->cmng.csl[i]);
 533         }
 534         if (sh->devx && !haswell_broadwell_cpu) {
 535                 sh->cmng.relaxed_ordering_write = attr->relaxed_ordering_write;
 536                 sh->cmng.relaxed_ordering_read = attr->relaxed_ordering_read;
 537         }
 538 }
 539
 540 /**
 541  * Destroy all the resources allocated for a counter memory management.
 542  *
 543  * @param[in] mng
 544  *   Pointer to the memory management structure.
 545  */
 546 static void
 547 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
 548 {
 549         uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
 550
 551         LIST_REMOVE(mng, next);
 552         claim_zero(mlx5_devx_cmd_destroy(mng->dm));
 553         claim_zero(mlx5_os_umem_dereg(mng->umem));
 554         mlx5_free(mem);
 555 }
 556
 557 /**
 558  * Close and release all the resources of the counters management.
 559  *
 560  * @param[in] sh
 561  *   Pointer to mlx5_dev_ctx_shared object to free.
 562  */
 563 static void
 564 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
 565 {
 566         struct mlx5_counter_stats_mem_mng *mng;
 567         int i, j;
 568         int retries = 1024;
 569
 570         rte_errno = 0;
 571         while (--retries) {
 572                 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
 573                 if (rte_errno != EINPROGRESS)
 574                         break;
 575                 rte_pause();
 576         }
 577
 578         if (sh->cmng.pools) {
 579                 struct mlx5_flow_counter_pool *pool;
 580                 uint16_t n_valid = sh->cmng.n_valid;
 581                 bool fallback = sh->cmng.counter_fallback;
 582
 583                 for (i = 0; i < n_valid; ++i) {
 584                         pool = sh->cmng.pools[i];
 585                         if (!fallback && pool->min_dcs)
 586                                 claim_zero(mlx5_devx_cmd_destroy
 587                                                                (pool->min_dcs));
 588                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
 589                                 struct mlx5_flow_counter *cnt =
 590                                                 MLX5_POOL_GET_CNT(pool, j);
 591
 592                                 if (cnt->action)
 593                                         claim_zero
 594                                          (mlx5_flow_os_destroy_flow_action
 595                                           (cnt->action));
 596                                 if (fallback && MLX5_POOL_GET_CNT
 597                                     (pool, j)->dcs_when_free)
 598                                         claim_zero(mlx5_devx_cmd_destroy
 599                                                    (cnt->dcs_when_free));
 600                         }
 601                         mlx5_free(pool);
 602                 }
 603                 mlx5_free(sh->cmng.pools);
 604         }
 605         mng = LIST_FIRST(&sh->cmng.mem_mngs);
 606         while (mng) {
 607                 mlx5_flow_destroy_counter_stat_mem_mng(mng);
 608                 mng = LIST_FIRST(&sh->cmng.mem_mngs);
 609         }
 610         memset(&sh->cmng, 0, sizeof(sh->cmng));
 611 }
 612
 613 /**
 614  * Initialize the aso flow meters management structure.
 615  *
 616  * @param[in] sh
 617  *   Pointer to mlx5_dev_ctx_shared object to free
 618  */
 619 int
 620 mlx5_aso_flow_mtrs_mng_init(struct mlx5_dev_ctx_shared *sh)
 621 {
 622         if (!sh->mtrmng) {
 623                 sh->mtrmng = mlx5_malloc(MLX5_MEM_ZERO,
 624                         sizeof(*sh->mtrmng),
 625                         RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 626                 if (!sh->mtrmng) {
 627                         DRV_LOG(ERR,
 628                         "meter management allocation was failed.");
 629                         rte_errno = ENOMEM;
 630                         return -ENOMEM;
 631                 }
 632                 if (sh->meter_aso_en) {
 633                         rte_spinlock_init(&sh->mtrmng->pools_mng.mtrsl);
 634                         rte_rwlock_init(&sh->mtrmng->pools_mng.resize_mtrwl);
 635                         LIST_INIT(&sh->mtrmng->pools_mng.meters);
 636                 }
 637                 sh->mtrmng->def_policy_id = MLX5_INVALID_POLICY_ID;
 638         }
 639         return 0;
 640 }
 641
 642 /**
 643  * Close and release all the resources of
 644  * the ASO flow meter management structure.
 645  *
 646  * @param[in] sh
 647  *   Pointer to mlx5_dev_ctx_shared object to free.
 648  */
 649 static void
 650 mlx5_aso_flow_mtrs_mng_close(struct mlx5_dev_ctx_shared *sh)
 651 {
 652         struct mlx5_aso_mtr_pool *mtr_pool;
 653         struct mlx5_flow_mtr_mng *mtrmng = sh->mtrmng;
 654         uint32_t idx;
 655 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
 656         struct mlx5_aso_mtr *aso_mtr;
 657         int i;
 658 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
 659
 660         if (sh->meter_aso_en) {
 661                 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_POLICER);
 662                 idx = mtrmng->pools_mng.n_valid;
 663                 while (idx--) {
 664                         mtr_pool = mtrmng->pools_mng.pools[idx];
 665 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
 666                         for (i = 0; i < MLX5_ASO_MTRS_PER_POOL; i++) {
 667                                 aso_mtr = &mtr_pool->mtrs[i];
 668                                 if (aso_mtr->fm.meter_action)
 669                                         claim_zero
 670                                         (mlx5_glue->destroy_flow_action
 671                                         (aso_mtr->fm.meter_action));
 672                         }
 673 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
 674                         claim_zero(mlx5_devx_cmd_destroy
 675                                                 (mtr_pool->devx_obj));
 676                         mtrmng->pools_mng.n_valid--;
 677                         mlx5_free(mtr_pool);
 678                 }
 679                 mlx5_free(sh->mtrmng->pools_mng.pools);
 680         }
 681         mlx5_free(sh->mtrmng);
 682         sh->mtrmng = NULL;
 683 }
 684
 685 /* Send FLOW_AGED event if needed. */
 686 void
 687 mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh)
 688 {
 689         struct mlx5_age_info *age_info;
 690         uint32_t i;
 691
 692         for (i = 0; i < sh->max_port; i++) {
 693                 age_info = &sh->port[i].age_info;
 694                 if (!MLX5_AGE_GET(age_info, MLX5_AGE_EVENT_NEW))
 695                         continue;
 696                 MLX5_AGE_UNSET(age_info, MLX5_AGE_EVENT_NEW);
 697                 if (MLX5_AGE_GET(age_info, MLX5_AGE_TRIGGER)) {
 698                         MLX5_AGE_UNSET(age_info, MLX5_AGE_TRIGGER);
 699                         rte_eth_dev_callback_process
 700                                 (&rte_eth_devices[sh->port[i].devx_ih_port_id],
 701                                 RTE_ETH_EVENT_FLOW_AGED, NULL);
 702                 }
 703         }
 704 }
 705
 706 /*
 707  * Initialize the ASO connection tracking structure.
 708  *
 709  * @param[in] sh
 710  *   Pointer to mlx5_dev_ctx_shared object.
 711  *
 712  * @return
 713  *   0 on success, a negative errno value otherwise and rte_errno is set.
 714  */
 715 int
 716 mlx5_flow_aso_ct_mng_init(struct mlx5_dev_ctx_shared *sh)
 717 {
 718         int err;
 719
 720         if (sh->ct_mng)
 721                 return 0;
 722         sh->ct_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->ct_mng),
 723                                  RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 724         if (!sh->ct_mng) {
 725                 DRV_LOG(ERR, "ASO CT management allocation failed.");
 726                 rte_errno = ENOMEM;
 727                 return -rte_errno;
 728         }
 729         err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_CONNECTION_TRACKING);
 730         if (err) {
 731                 mlx5_free(sh->ct_mng);
 732                 /* rte_errno should be extracted from the failure. */
 733                 rte_errno = EINVAL;
 734                 return -rte_errno;
 735         }
 736         rte_spinlock_init(&sh->ct_mng->ct_sl);
 737         rte_rwlock_init(&sh->ct_mng->resize_rwl);
 738         LIST_INIT(&sh->ct_mng->free_cts);
 739         return 0;
 740 }
 741
 742 /*
 743  * Close and release all the resources of the
 744  * ASO connection tracking management structure.
 745  *
 746  * @param[in] sh
 747  *   Pointer to mlx5_dev_ctx_shared object to free.
 748  */
 749 static void
 750 mlx5_flow_aso_ct_mng_close(struct mlx5_dev_ctx_shared *sh)
 751 {
 752         struct mlx5_aso_ct_pools_mng *mng = sh->ct_mng;
 753         struct mlx5_aso_ct_pool *ct_pool;
 754         struct mlx5_aso_ct_action *ct;
 755         uint32_t idx;
 756         uint32_t val;
 757         uint32_t cnt;
 758         int i;
 759
 760         mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_CONNECTION_TRACKING);
 761         idx = mng->next;
 762         while (idx--) {
 763                 cnt = 0;
 764                 ct_pool = mng->pools[idx];
 765                 for (i = 0; i < MLX5_ASO_CT_ACTIONS_PER_POOL; i++) {
 766                         ct = &ct_pool->actions[i];
 767                         val = __atomic_fetch_sub(&ct->refcnt, 1,
 768                                                  __ATOMIC_RELAXED);
 769                         MLX5_ASSERT(val == 1);
 770                         if (val > 1)
 771                                 cnt++;
 772 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
 773                         if (ct->dr_action_orig)
 774                                 claim_zero(mlx5_glue->destroy_flow_action
 775                                                         (ct->dr_action_orig));
 776                         if (ct->dr_action_rply)
 777                                 claim_zero(mlx5_glue->destroy_flow_action
 778                                                         (ct->dr_action_rply));
 779 #endif
 780                 }
 781                 claim_zero(mlx5_devx_cmd_destroy(ct_pool->devx_obj));
 782                 if (cnt) {
 783                         DRV_LOG(DEBUG, "%u ASO CT objects are being used in the pool %u",
 784                                 cnt, i);
 785                 }
 786                 mlx5_free(ct_pool);
 787                 /* in case of failure. */
 788                 mng->next--;
 789         }
 790         mlx5_free(mng->pools);
 791         mlx5_free(mng);
 792         /* Management structure must be cleared to 0s during allocation. */
 793         sh->ct_mng = NULL;
 794 }
 795
 796 /**
 797  * Initialize the flow resources' indexed mempool.
 798  *
 799  * @param[in] sh
 800  *   Pointer to mlx5_dev_ctx_shared object.
 801  * @param[in] config
 802  *   Pointer to user dev config.
 803  */
 804 static void
 805 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
 806                        const struct mlx5_dev_config *config)
 807 {
 808         uint8_t i;
 809         struct mlx5_indexed_pool_config cfg;
 810
 811         for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
 812                 cfg = mlx5_ipool_cfg[i];
 813                 switch (i) {
 814                 default:
 815                         break;
 816                 /*
 817                  * Set MLX5_IPOOL_MLX5_FLOW ipool size
 818                  * according to PCI function flow configuration.
 819                  */
 820                 case MLX5_IPOOL_MLX5_FLOW:
 821                         cfg.size = config->dv_flow_en ?
 822                                 sizeof(struct mlx5_flow_handle) :
 823                                 MLX5_FLOW_HANDLE_VERBS_SIZE;
 824                         break;
 825                 }
 826                 if (config->reclaim_mode) {
 827                         cfg.release_mem_en = 1;
 828                         cfg.per_core_cache = 0;
 829                 } else {
 830                         cfg.release_mem_en = 0;
 831                 }
 832                 sh->ipool[i] = mlx5_ipool_create(&cfg);
 833         }
 834 }
 835
 836
 837 /**
 838  * Release the flow resources' indexed mempool.
 839  *
 840  * @param[in] sh
 841  *   Pointer to mlx5_dev_ctx_shared object.
 842  */
 843 static void
 844 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
 845 {
 846         uint8_t i;
 847
 848         for (i = 0; i < MLX5_IPOOL_MAX; ++i)
 849                 mlx5_ipool_destroy(sh->ipool[i]);
 850         for (i = 0; i < MLX5_MAX_MODIFY_NUM; ++i)
 851                 if (sh->mdh_ipools[i])
 852                         mlx5_ipool_destroy(sh->mdh_ipools[i]);
 853 }
 854
 855 /*
 856  * Check if dynamic flex parser for eCPRI already exists.
 857  *
 858  * @param dev
 859  *   Pointer to Ethernet device structure.
 860  *
 861  * @return
 862  *   true on exists, false on not.
 863  */
 864 bool
 865 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
 866 {
 867         struct mlx5_priv *priv = dev->data->dev_private;
 868         struct mlx5_ecpri_parser_profile *prf = &priv->sh->ecpri_parser;
 869
 870         return !!prf->obj;
 871 }
 872
 873 /*
 874  * Allocation of a flex parser for eCPRI. Once created, this parser related
 875  * resources will be held until the device is closed.
 876  *
 877  * @param dev
 878  *   Pointer to Ethernet device structure.
 879  *
 880  * @return
 881  *   0 on success, a negative errno value otherwise and rte_errno is set.
 882  */
 883 int
 884 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
 885 {
 886         struct mlx5_priv *priv = dev->data->dev_private;
 887         struct mlx5_ecpri_parser_profile *prf = &priv->sh->ecpri_parser;
 888         struct mlx5_devx_graph_node_attr node = {
 889                 .modify_field_select = 0,
 890         };
 891         uint32_t ids[8];
 892         int ret;
 893
 894         if (!priv->config.hca_attr.parse_graph_flex_node) {
 895                 DRV_LOG(ERR, "Dynamic flex parser is not supported "
 896                         "for device %s.", priv->dev_data->name);
 897                 return -ENOTSUP;
 898         }
 899         node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED;
 900         /* 8 bytes now: 4B common header + 4B message body header. */
 901         node.header_length_base_value = 0x8;
 902         /* After MAC layer: Ether / VLAN. */
 903         node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC;
 904         /* Type of compared condition should be 0xAEFE in the L2 layer. */
 905         node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI;
 906         /* Sample #0: type in common header. */
 907         node.sample[0].flow_match_sample_en = 1;
 908         /* Fixed offset. */
 909         node.sample[0].flow_match_sample_offset_mode = 0x0;
 910         /* Only the 2nd byte will be used. */
 911         node.sample[0].flow_match_sample_field_base_offset = 0x0;
 912         /* Sample #1: message payload. */
 913         node.sample[1].flow_match_sample_en = 1;
 914         /* Fixed offset. */
 915         node.sample[1].flow_match_sample_offset_mode = 0x0;
 916         /*
 917          * Only the first two bytes will be used right now, and its offset will
 918          * start after the common header that with the length of a DW(u32).
 919          */
 920         node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);
 921         prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->cdev->ctx, &node);
 922         if (!prf->obj) {
 923                 DRV_LOG(ERR, "Failed to create flex parser node object.");
 924                 return (rte_errno == 0) ? -ENODEV : -rte_errno;
 925         }
 926         prf->num = 2;
 927         ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num);
 928         if (ret) {
 929                 DRV_LOG(ERR, "Failed to query sample IDs.");
 930                 return (rte_errno == 0) ? -ENODEV : -rte_errno;
 931         }
 932         prf->offset[0] = 0x0;
 933         prf->offset[1] = sizeof(uint32_t);
 934         prf->ids[0] = ids[0];
 935         prf->ids[1] = ids[1];
 936         return 0;
 937 }
 938
 939 /*
 940  * Destroy the flex parser node, including the parser itself, input / output
 941  * arcs and DW samples. Resources could be reused then.
 942  *
 943  * @param dev
 944  *   Pointer to Ethernet device structure.
 945  */
 946 static void
 947 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
 948 {
 949         struct mlx5_priv *priv = dev->data->dev_private;
 950         struct mlx5_ecpri_parser_profile *prf = &priv->sh->ecpri_parser;
 951
 952         if (prf->obj)
 953                 mlx5_devx_cmd_destroy(prf->obj);
 954         prf->obj = NULL;
 955 }
 956
 957 uint32_t
 958 mlx5_get_supported_sw_parsing_offloads(const struct mlx5_hca_attr *attr)
 959 {
 960         uint32_t sw_parsing_offloads = 0;
 961
 962         if (attr->swp) {
 963                 sw_parsing_offloads |= MLX5_SW_PARSING_CAP;
 964                 if (attr->swp_csum)
 965                         sw_parsing_offloads |= MLX5_SW_PARSING_CSUM_CAP;
 966
 967                 if (attr->swp_lso)
 968                         sw_parsing_offloads |= MLX5_SW_PARSING_TSO_CAP;
 969         }
 970         return sw_parsing_offloads;
 971 }
 972
 973 uint32_t
 974 mlx5_get_supported_tunneling_offloads(const struct mlx5_hca_attr *attr)
 975 {
 976         uint32_t tn_offloads = 0;
 977
 978         if (attr->tunnel_stateless_vxlan)
 979                 tn_offloads |= MLX5_TUNNELED_OFFLOADS_VXLAN_CAP;
 980         if (attr->tunnel_stateless_gre)
 981                 tn_offloads |= MLX5_TUNNELED_OFFLOADS_GRE_CAP;
 982         if (attr->tunnel_stateless_geneve_rx)
 983                 tn_offloads |= MLX5_TUNNELED_OFFLOADS_GENEVE_CAP;
 984         return tn_offloads;
 985 }
 986
 987 /*
 988  * Allocate Rx and Tx UARs in robust fashion.
 989  * This routine handles the following UAR allocation issues:
 990  *
 991  *  - tries to allocate the UAR with the most appropriate memory
 992  *    mapping type from the ones supported by the host
 993  *
 994  *  - tries to allocate the UAR with non-NULL base address
 995  *    OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as
 996  *    UAR base address if UAR was not the first object in the UAR page.
 997  *    It caused the PMD failure and we should try to get another UAR
 998  *    till we get the first one with non-NULL base address returned.
 999  */
1000 static int
1001 mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh,
1002                      const struct mlx5_common_dev_config *config)
1003 {
1004         uint32_t uar_mapping, retry;
1005         int err = 0;
1006         void *base_addr;
1007
1008         for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
1009 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
1010                 /* Control the mapping type according to the settings. */
1011                 uar_mapping = (config->dbnc == MLX5_TXDB_NCACHED) ?
1012                               MLX5DV_UAR_ALLOC_TYPE_NC :
1013                               MLX5DV_UAR_ALLOC_TYPE_BF;
1014 #else
1015                 RTE_SET_USED(config);
1016                 /*
1017                  * It seems we have no way to control the memory mapping type
1018                  * for the UAR, the default "Write-Combining" type is supposed.
1019                  * The UAR initialization on queue creation queries the
1020                  * actual mapping type done by Verbs/kernel and setups the
1021                  * PMD datapath accordingly.
1022                  */
1023                 uar_mapping = 0;
1024 #endif
1025                 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->cdev->ctx,
1026                                                        uar_mapping);
1027 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
1028                 if (!sh->tx_uar &&
1029                     uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
1030                         if (config->dbnc == MLX5_TXDB_CACHED ||
1031                             config->dbnc == MLX5_TXDB_HEURISTIC)
1032                                 DRV_LOG(WARNING, "Devarg tx_db_nc setting "
1033                                                  "is not supported by DevX");
1034                         /*
1035                          * In some environments like virtual machine
1036                          * the Write Combining mapped might be not supported
1037                          * and UAR allocation fails. We try "Non-Cached"
1038                          * mapping for the case. The tx_burst routines take
1039                          * the UAR mapping type into account on UAR setup
1040                          * on queue creation.
1041                          */
1042                         DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (BF)");
1043                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
1044                         sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->cdev->ctx,
1045                                                                uar_mapping);
1046                 } else if (!sh->tx_uar &&
1047                            uar_mapping == MLX5DV_UAR_ALLOC_TYPE_NC) {
1048                         if (config->dbnc == MLX5_TXDB_NCACHED)
1049                                 DRV_LOG(WARNING, "Devarg tx_db_nc settings "
1050                                                  "is not supported by DevX");
1051                         /*
1052                          * If Verbs/kernel does not support "Non-Cached"
1053                          * try the "Write-Combining".
1054                          */
1055                         DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (NC)");
1056                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_BF;
1057                         sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->cdev->ctx,
1058                                                                uar_mapping);
1059                 }
1060 #endif
1061                 if (!sh->tx_uar) {
1062                         DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (BF/NC)");
1063                         err = ENOMEM;
1064                         goto exit;
1065                 }
1066                 base_addr = mlx5_os_get_devx_uar_base_addr(sh->tx_uar);
1067                 if (base_addr)
1068                         break;
1069                 /*
1070                  * The UARs are allocated by rdma_core within the
1071                  * IB device context, on context closure all UARs
1072                  * will be freed, should be no memory/object leakage.
1073                  */
1074                 DRV_LOG(DEBUG, "Retrying to allocate Tx DevX UAR");
1075                 sh->tx_uar = NULL;
1076         }
1077         /* Check whether we finally succeeded with valid UAR allocation. */
1078         if (!sh->tx_uar) {
1079                 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (NULL base)");
1080                 err = ENOMEM;
1081                 goto exit;
1082         }
1083         for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
1084                 uar_mapping = 0;
1085                 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar(sh->cdev->ctx,
1086                                                             uar_mapping);
1087 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
1088                 if (!sh->devx_rx_uar &&
1089                     uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
1090                         /*
1091                          * Rx UAR is used to control interrupts only,
1092                          * should be no datapath noticeable impact,
1093                          * can try "Non-Cached" mapping safely.
1094                          */
1095                         DRV_LOG(DEBUG, "Failed to allocate Rx DevX UAR (BF)");
1096                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
1097                         sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
1098                                                    (sh->cdev->ctx, uar_mapping);
1099                 }
1100 #endif
1101                 if (!sh->devx_rx_uar) {
1102                         DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (BF/NC)");
1103                         err = ENOMEM;
1104                         goto exit;
1105                 }
1106                 base_addr = mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar);
1107                 if (base_addr)
1108                         break;
1109                 /*
1110                  * The UARs are allocated by rdma_core within the
1111                  * IB device context, on context closure all UARs
1112                  * will be freed, should be no memory/object leakage.
1113                  */
1114                 DRV_LOG(DEBUG, "Retrying to allocate Rx DevX UAR");
1115                 sh->devx_rx_uar = NULL;
1116         }
1117         /* Check whether we finally succeeded with valid UAR allocation. */
1118         if (!sh->devx_rx_uar) {
1119                 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (NULL base)");
1120                 err = ENOMEM;
1121         }
1122 exit:
1123         return err;
1124 }
1125
1126 /**
1127  * rte_mempool_walk() callback to unregister Rx mempools.
1128  * It used when implicit mempool registration is disabled.
1129  *
1130  * @param mp
1131  *   The mempool being walked.
1132  * @param arg
1133  *   Pointer to the device shared context.
1134  */
1135 static void
1136 mlx5_dev_ctx_shared_rx_mempool_unregister_cb(struct rte_mempool *mp, void *arg)
1137 {
1138         struct mlx5_dev_ctx_shared *sh = arg;
1139
1140         mlx5_dev_mempool_unregister(sh->cdev, mp);
1141 }
1142
1143 /**
1144  * Callback used when implicit mempool registration is disabled
1145  * in order to track Rx mempool destruction.
1146  *
1147  * @param event
1148  *   Mempool life cycle event.
1149  * @param mp
1150  *   An Rx mempool registered explicitly when the port is started.
1151  * @param arg
1152  *   Pointer to a device shared context.
1153  */
1154 static void
1155 mlx5_dev_ctx_shared_rx_mempool_event_cb(enum rte_mempool_event event,
1156                                         struct rte_mempool *mp, void *arg)
1157 {
1158         struct mlx5_dev_ctx_shared *sh = arg;
1159
1160         if (event == RTE_MEMPOOL_EVENT_DESTROY)
1161                 mlx5_dev_mempool_unregister(sh->cdev, mp);
1162 }
1163
1164 int
1165 mlx5_dev_ctx_shared_mempool_subscribe(struct rte_eth_dev *dev)
1166 {
1167         struct mlx5_priv *priv = dev->data->dev_private;
1168         struct mlx5_dev_ctx_shared *sh = priv->sh;
1169         int ret;
1170
1171         /* Check if we only need to track Rx mempool destruction. */
1172         if (!sh->cdev->config.mr_mempool_reg_en) {
1173                 ret = rte_mempool_event_callback_register
1174                                 (mlx5_dev_ctx_shared_rx_mempool_event_cb, sh);
1175                 return ret == 0 || rte_errno == EEXIST ? 0 : ret;
1176         }
1177         return mlx5_dev_mempool_subscribe(sh->cdev);
1178 }
1179
1180 /**
1181  * Set up multiple TISs with different affinities according to
1182  * number of bonding ports
1183  *
1184  * @param priv
1185  * Pointer of shared context.
1186  *
1187  * @return
1188  * Zero on success, -1 otherwise.
1189  */
1190 static int
1191 mlx5_setup_tis(struct mlx5_dev_ctx_shared *sh)
1192 {
1193         int i;
1194         struct mlx5_devx_lag_context lag_ctx = { 0 };
1195         struct mlx5_devx_tis_attr tis_attr = { 0 };
1196
1197         tis_attr.transport_domain = sh->td->id;
1198         if (sh->bond.n_port) {
1199                 if (!mlx5_devx_cmd_query_lag(sh->cdev->ctx, &lag_ctx)) {
1200                         sh->lag.tx_remap_affinity[0] =
1201                                 lag_ctx.tx_remap_affinity_1;
1202                         sh->lag.tx_remap_affinity[1] =
1203                                 lag_ctx.tx_remap_affinity_2;
1204                         sh->lag.affinity_mode = lag_ctx.port_select_mode;
1205                 } else {
1206                         DRV_LOG(ERR, "Failed to query lag affinity.");
1207                         return -1;
1208                 }
1209                 if (sh->lag.affinity_mode == MLX5_LAG_MODE_TIS) {
1210                         for (i = 0; i < sh->bond.n_port; i++) {
1211                                 tis_attr.lag_tx_port_affinity =
1212                                         MLX5_IFC_LAG_MAP_TIS_AFFINITY(i,
1213                                                         sh->bond.n_port);
1214                                 sh->tis[i] = mlx5_devx_cmd_create_tis(sh->cdev->ctx,
1215                                                 &tis_attr);
1216                                 if (!sh->tis[i]) {
1217                                         DRV_LOG(ERR, "Failed to TIS %d/%d for bonding device"
1218                                                 " %s.", i, sh->bond.n_port,
1219                                                 sh->ibdev_name);
1220                                         return -1;
1221                                 }
1222                         }
1223                         DRV_LOG(DEBUG, "LAG number of ports : %d, affinity_1 & 2 : pf%d & %d.\n",
1224                                 sh->bond.n_port, lag_ctx.tx_remap_affinity_1,
1225                                 lag_ctx.tx_remap_affinity_2);
1226                         return 0;
1227                 }
1228                 if (sh->lag.affinity_mode == MLX5_LAG_MODE_HASH)
1229                         DRV_LOG(INFO, "Device %s enabled HW hash based LAG.",
1230                                         sh->ibdev_name);
1231         }
1232         tis_attr.lag_tx_port_affinity = 0;
1233         sh->tis[0] = mlx5_devx_cmd_create_tis(sh->cdev->ctx, &tis_attr);
1234         if (!sh->tis[0]) {
1235                 DRV_LOG(ERR, "Failed to TIS 0 for bonding device"
1236                         " %s.", sh->ibdev_name);
1237                 return -1;
1238         }
1239         return 0;
1240 }
1241
1242 /**
1243  * Allocate shared device context. If there is multiport device the
1244  * master and representors will share this context, if there is single
1245  * port dedicated device, the context will be used by only given
1246  * port due to unification.
1247  *
1248  * Routine first searches the context for the specified device name,
1249  * if found the shared context assumed and reference counter is incremented.
1250  * If no context found the new one is created and initialized with specified
1251  * device context and parameters.
1252  *
1253  * @param[in] spawn
1254  *   Pointer to the device attributes (name, port, etc).
1255  * @param[in] config
1256  *   Pointer to device configuration structure.
1257  *
1258  * @return
1259  *   Pointer to mlx5_dev_ctx_shared object on success,
1260  *   otherwise NULL and rte_errno is set.
1261  */
1262 struct mlx5_dev_ctx_shared *
1263 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
1264                           const struct mlx5_dev_config *config)
1265 {
1266         struct mlx5_dev_ctx_shared *sh;
1267         int err = 0;
1268         uint32_t i;
1269
1270         MLX5_ASSERT(spawn);
1271         /* Secondary process should not create the shared context. */
1272         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1273         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1274         /* Search for IB context by device name. */
1275         LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
1276                 if (!strcmp(sh->ibdev_name, spawn->phys_dev_name)) {
1277                         sh->refcnt++;
1278                         goto exit;
1279                 }
1280         }
1281         /* No device found, we have to create new shared context. */
1282         MLX5_ASSERT(spawn->max_port);
1283         sh = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
1284                          sizeof(struct mlx5_dev_ctx_shared) +
1285                          spawn->max_port *
1286                          sizeof(struct mlx5_dev_shared_port),
1287                          RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
1288         if (!sh) {
1289                 DRV_LOG(ERR, "shared context allocation failure");
1290                 rte_errno  = ENOMEM;
1291                 goto exit;
1292         }
1293         pthread_mutex_init(&sh->txpp.mutex, NULL);
1294         sh->numa_node = spawn->cdev->dev->numa_node;
1295         sh->cdev = spawn->cdev;
1296         sh->devx = sh->cdev->config.devx;
1297         if (spawn->bond_info)
1298                 sh->bond = *spawn->bond_info;
1299         err = mlx5_os_get_dev_attr(sh->cdev, &sh->device_attr);
1300         if (err) {
1301                 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
1302                 goto error;
1303         }
1304         sh->refcnt = 1;
1305         sh->max_port = spawn->max_port;
1306         sh->reclaim_mode = config->reclaim_mode;
1307         strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->cdev->ctx),
1308                 sizeof(sh->ibdev_name) - 1);
1309         strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->cdev->ctx),
1310                 sizeof(sh->ibdev_path) - 1);
1311         /*
1312          * Setting port_id to max unallowed value means
1313          * there is no interrupt subhandler installed for
1314          * the given port index i.
1315          */
1316         for (i = 0; i < sh->max_port; i++) {
1317                 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
1318                 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
1319         }
1320         if (sh->devx) {
1321                 sh->td = mlx5_devx_cmd_create_td(sh->cdev->ctx);
1322                 if (!sh->td) {
1323                         DRV_LOG(ERR, "TD allocation failure");
1324                         err = ENOMEM;
1325                         goto error;
1326                 }
1327                 if (mlx5_setup_tis(sh)) {
1328                         DRV_LOG(ERR, "TIS allocation failure");
1329                         err = ENOMEM;
1330                         goto error;
1331                 }
1332                 err = mlx5_alloc_rxtx_uars(sh, &sh->cdev->config);
1333                 if (err)
1334                         goto error;
1335                 MLX5_ASSERT(sh->tx_uar);
1336                 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->tx_uar));
1337
1338                 MLX5_ASSERT(sh->devx_rx_uar);
1339                 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar));
1340         }
1341 #ifndef RTE_ARCH_64
1342         /* Initialize UAR access locks for 32bit implementations. */
1343         rte_spinlock_init(&sh->uar_lock_cq);
1344         for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
1345                 rte_spinlock_init(&sh->uar_lock[i]);
1346 #endif
1347         mlx5_os_dev_shared_handler_install(sh);
1348         if (LIST_EMPTY(&mlx5_dev_ctx_list)) {
1349                 err = mlx5_flow_os_init_workspace_once();
1350                 if (err)
1351                         goto error;
1352         }
1353         mlx5_flow_aging_init(sh);
1354         mlx5_flow_counters_mng_init(sh);
1355         mlx5_flow_ipool_create(sh, config);
1356         /* Add context to the global device list. */
1357         LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
1358         rte_spinlock_init(&sh->geneve_tlv_opt_sl);
1359 exit:
1360         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1361         return sh;
1362 error:
1363         pthread_mutex_destroy(&sh->txpp.mutex);
1364         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1365         MLX5_ASSERT(sh);
1366         if (sh->td)
1367                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1368         i = 0;
1369         do {
1370                 if (sh->tis[i])
1371                         claim_zero(mlx5_devx_cmd_destroy(sh->tis[i]));
1372         } while (++i < (uint32_t)sh->bond.n_port);
1373         if (sh->devx_rx_uar)
1374                 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1375         if (sh->tx_uar)
1376                 mlx5_glue->devx_free_uar(sh->tx_uar);
1377         mlx5_free(sh);
1378         MLX5_ASSERT(err > 0);
1379         rte_errno = err;
1380         return NULL;
1381 }
1382
1383 /**
1384  * Free shared IB device context. Decrement counter and if zero free
1385  * all allocated resources and close handles.
1386  *
1387  * @param[in] sh
1388  *   Pointer to mlx5_dev_ctx_shared object to free
1389  */
1390 void
1391 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
1392 {
1393         int ret;
1394         int i = 0;
1395
1396         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1397 #ifdef RTE_LIBRTE_MLX5_DEBUG
1398         /* Check the object presence in the list. */
1399         struct mlx5_dev_ctx_shared *lctx;
1400
1401         LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
1402                 if (lctx == sh)
1403                         break;
1404         MLX5_ASSERT(lctx);
1405         if (lctx != sh) {
1406                 DRV_LOG(ERR, "Freeing non-existing shared IB context");
1407                 goto exit;
1408         }
1409 #endif
1410         MLX5_ASSERT(sh);
1411         MLX5_ASSERT(sh->refcnt);
1412         /* Secondary process should not free the shared context. */
1413         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1414         if (--sh->refcnt)
1415                 goto exit;
1416         /* Stop watching for mempool events and unregister all mempools. */
1417         if (!sh->cdev->config.mr_mempool_reg_en) {
1418                 ret = rte_mempool_event_callback_unregister
1419                                 (mlx5_dev_ctx_shared_rx_mempool_event_cb, sh);
1420                 if (ret == 0)
1421                         rte_mempool_walk
1422                              (mlx5_dev_ctx_shared_rx_mempool_unregister_cb, sh);
1423         }
1424         /* Remove context from the global device list. */
1425         LIST_REMOVE(sh, next);
1426         /* Release resources on the last device removal. */
1427         if (LIST_EMPTY(&mlx5_dev_ctx_list)) {
1428                 mlx5_os_net_cleanup();
1429                 mlx5_flow_os_release_workspace();
1430         }
1431         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1432         if (sh->flex_parsers_dv) {
1433                 mlx5_list_destroy(sh->flex_parsers_dv);
1434                 sh->flex_parsers_dv = NULL;
1435         }
1436         /*
1437          *  Ensure there is no async event handler installed.
1438          *  Only primary process handles async device events.
1439          **/
1440         mlx5_flow_counters_mng_close(sh);
1441         if (sh->aso_age_mng) {
1442                 mlx5_flow_aso_age_mng_close(sh);
1443                 sh->aso_age_mng = NULL;
1444         }
1445         if (sh->mtrmng)
1446                 mlx5_aso_flow_mtrs_mng_close(sh);
1447         mlx5_flow_ipool_destroy(sh);
1448         mlx5_os_dev_shared_handler_uninstall(sh);
1449         if (sh->tx_uar) {
1450                 mlx5_glue->devx_free_uar(sh->tx_uar);
1451                 sh->tx_uar = NULL;
1452         }
1453         do {
1454                 if (sh->tis[i])
1455                         claim_zero(mlx5_devx_cmd_destroy(sh->tis[i]));
1456         } while (++i < sh->bond.n_port);
1457         if (sh->td)
1458                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1459         if (sh->devx_rx_uar)
1460                 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1461         MLX5_ASSERT(sh->geneve_tlv_option_resource == NULL);
1462         pthread_mutex_destroy(&sh->txpp.mutex);
1463         mlx5_free(sh);
1464         return;
1465 exit:
1466         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1467 }
1468
1469 /**
1470  * Destroy table hash list.
1471  *
1472  * @param[in] priv
1473  *   Pointer to the private device data structure.
1474  */
1475 void
1476 mlx5_free_table_hash_list(struct mlx5_priv *priv)
1477 {
1478         struct mlx5_dev_ctx_shared *sh = priv->sh;
1479
1480         if (!sh->flow_tbls)
1481                 return;
1482         mlx5_hlist_destroy(sh->flow_tbls);
1483         sh->flow_tbls = NULL;
1484 }
1485
1486 /**
1487  * Initialize flow table hash list and create the root tables entry
1488  * for each domain.
1489  *
1490  * @param[in] priv
1491  *   Pointer to the private device data structure.
1492  *
1493  * @return
1494  *   Zero on success, positive error code otherwise.
1495  */
1496 int
1497 mlx5_alloc_table_hash_list(struct mlx5_priv *priv __rte_unused)
1498 {
1499         int err = 0;
1500         /* Tables are only used in DV and DR modes. */
1501 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
1502         struct mlx5_dev_ctx_shared *sh = priv->sh;
1503         char s[MLX5_NAME_SIZE];
1504
1505         MLX5_ASSERT(sh);
1506         snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1507         sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE,
1508                                           false, true, sh,
1509                                           flow_dv_tbl_create_cb,
1510                                           flow_dv_tbl_match_cb,
1511                                           flow_dv_tbl_remove_cb,
1512                                           flow_dv_tbl_clone_cb,
1513                                           flow_dv_tbl_clone_free_cb);
1514         if (!sh->flow_tbls) {
1515                 DRV_LOG(ERR, "flow tables with hash creation failed.");
1516                 err = ENOMEM;
1517                 return err;
1518         }
1519 #ifndef HAVE_MLX5DV_DR
1520         struct rte_flow_error error;
1521         struct rte_eth_dev *dev = &rte_eth_devices[priv->dev_data->port_id];
1522
1523         /*
1524          * In case we have not DR support, the zero tables should be created
1525          * because DV expect to see them even if they cannot be created by
1526          * RDMA-CORE.
1527          */
1528         if (!flow_dv_tbl_resource_get(dev, 0, 0, 0, 0,
1529                 NULL, 0, 1, 0, &error) ||
1530             !flow_dv_tbl_resource_get(dev, 0, 1, 0, 0,
1531                 NULL, 0, 1, 0, &error) ||
1532             !flow_dv_tbl_resource_get(dev, 0, 0, 1, 0,
1533                 NULL, 0, 1, 0, &error)) {
1534                 err = ENOMEM;
1535                 goto error;
1536         }
1537         return err;
1538 error:
1539         mlx5_free_table_hash_list(priv);
1540 #endif /* HAVE_MLX5DV_DR */
1541 #endif
1542         return err;
1543 }
1544
1545 /**
1546  * Retrieve integer value from environment variable.
1547  *
1548  * @param[in] name
1549  *   Environment variable name.
1550  *
1551  * @return
1552  *   Integer value, 0 if the variable is not set.
1553  */
1554 int
1555 mlx5_getenv_int(const char *name)
1556 {
1557         const char *val = getenv(name);
1558
1559         if (val == NULL)
1560                 return 0;
1561         return atoi(val);
1562 }
1563
1564 /**
1565  * DPDK callback to add udp tunnel port
1566  *
1567  * @param[in] dev
1568  *   A pointer to eth_dev
1569  * @param[in] udp_tunnel
1570  *   A pointer to udp tunnel
1571  *
1572  * @return
1573  *   0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1574  */
1575 int
1576 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1577                          struct rte_eth_udp_tunnel *udp_tunnel)
1578 {
1579         MLX5_ASSERT(udp_tunnel != NULL);
1580         if (udp_tunnel->prot_type == RTE_ETH_TUNNEL_TYPE_VXLAN &&
1581             udp_tunnel->udp_port == 4789)
1582                 return 0;
1583         if (udp_tunnel->prot_type == RTE_ETH_TUNNEL_TYPE_VXLAN_GPE &&
1584             udp_tunnel->udp_port == 4790)
1585                 return 0;
1586         return -ENOTSUP;
1587 }
1588
1589 /**
1590  * Initialize process private data structure.
1591  *
1592  * @param dev
1593  *   Pointer to Ethernet device structure.
1594  *
1595  * @return
1596  *   0 on success, a negative errno value otherwise and rte_errno is set.
1597  */
1598 int
1599 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1600 {
1601         struct mlx5_priv *priv = dev->data->dev_private;
1602         struct mlx5_proc_priv *ppriv;
1603         size_t ppriv_size;
1604
1605         mlx5_proc_priv_uninit(dev);
1606         /*
1607          * UAR register table follows the process private structure. BlueFlame
1608          * registers for Tx queues are stored in the table.
1609          */
1610         ppriv_size =
1611                 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1612         ppriv = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, ppriv_size,
1613                             RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1614         if (!ppriv) {
1615                 rte_errno = ENOMEM;
1616                 return -rte_errno;
1617         }
1618         ppriv->uar_table_sz = priv->txqs_n;
1619         dev->process_private = ppriv;
1620         return 0;
1621 }
1622
1623 /**
1624  * Un-initialize process private data structure.
1625  *
1626  * @param dev
1627  *   Pointer to Ethernet device structure.
1628  */
1629 void
1630 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1631 {
1632         if (!dev->process_private)
1633                 return;
1634         mlx5_free(dev->process_private);
1635         dev->process_private = NULL;
1636 }
1637
1638 /**
1639  * DPDK callback to close the device.
1640  *
1641  * Destroy all queues and objects, free memory.
1642  *
1643  * @param dev
1644  *   Pointer to Ethernet device structure.
1645  */
1646 int
1647 mlx5_dev_close(struct rte_eth_dev *dev)
1648 {
1649         struct mlx5_priv *priv = dev->data->dev_private;
1650         unsigned int i;
1651         int ret;
1652
1653         if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1654                 /* Check if process_private released. */
1655                 if (!dev->process_private)
1656                         return 0;
1657                 mlx5_tx_uar_uninit_secondary(dev);
1658                 mlx5_proc_priv_uninit(dev);
1659                 rte_eth_dev_release_port(dev);
1660                 return 0;
1661         }
1662         if (!priv->sh)
1663                 return 0;
1664         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1665                 dev->data->port_id,
1666                 ((priv->sh->cdev->ctx != NULL) ?
1667                 mlx5_os_get_ctx_device_name(priv->sh->cdev->ctx) : ""));
1668         /*
1669          * If default mreg copy action is removed at the stop stage,
1670          * the search will return none and nothing will be done anymore.
1671          */
1672         mlx5_flow_stop_default(dev);
1673         mlx5_traffic_disable(dev);
1674         /*
1675          * If all the flows are already flushed in the device stop stage,
1676          * then this will return directly without any action.
1677          */
1678         mlx5_flow_list_flush(dev, MLX5_FLOW_TYPE_GEN, true);
1679         mlx5_action_handle_flush(dev);
1680         mlx5_flow_meter_flush(dev, NULL);
1681         /* Prevent crashes when queues are still in use. */
1682         dev->rx_pkt_burst = removed_rx_burst;
1683         dev->tx_pkt_burst = removed_tx_burst;
1684         rte_wmb();
1685         /* Disable datapath on secondary process. */
1686         mlx5_mp_os_req_stop_rxtx(dev);
1687         /* Free the eCPRI flex parser resource. */
1688         mlx5_flex_parser_ecpri_release(dev);
1689         mlx5_flex_item_port_cleanup(dev);
1690         if (priv->rxqs != NULL) {
1691                 /* XXX race condition if mlx5_rx_burst() is still running. */
1692                 rte_delay_us_sleep(1000);
1693                 for (i = 0; (i != priv->rxqs_n); ++i)
1694                         mlx5_rxq_release(dev, i);
1695                 priv->rxqs_n = 0;
1696                 priv->rxqs = NULL;
1697         }
1698         if (priv->representor) {
1699                 /* Each representor has a dedicated interrupts handler */
1700                 mlx5_free(dev->intr_handle);
1701                 dev->intr_handle = NULL;
1702         }
1703         if (priv->txqs != NULL) {
1704                 /* XXX race condition if mlx5_tx_burst() is still running. */
1705                 rte_delay_us_sleep(1000);
1706                 for (i = 0; (i != priv->txqs_n); ++i)
1707                         mlx5_txq_release(dev, i);
1708                 priv->txqs_n = 0;
1709                 priv->txqs = NULL;
1710         }
1711         mlx5_proc_priv_uninit(dev);
1712         if (priv->q_counters) {
1713                 mlx5_devx_cmd_destroy(priv->q_counters);
1714                 priv->q_counters = NULL;
1715         }
1716         if (priv->drop_queue.hrxq)
1717                 mlx5_drop_action_destroy(dev);
1718         if (priv->mreg_cp_tbl)
1719                 mlx5_hlist_destroy(priv->mreg_cp_tbl);
1720         mlx5_mprq_free_mp(dev);
1721         if (priv->sh->ct_mng)
1722                 mlx5_flow_aso_ct_mng_close(priv->sh);
1723         mlx5_os_free_shared_dr(priv);
1724         if (priv->rss_conf.rss_key != NULL)
1725                 mlx5_free(priv->rss_conf.rss_key);
1726         if (priv->reta_idx != NULL)
1727                 mlx5_free(priv->reta_idx);
1728         if (priv->config.vf)
1729                 mlx5_os_mac_addr_flush(dev);
1730         if (priv->nl_socket_route >= 0)
1731                 close(priv->nl_socket_route);
1732         if (priv->nl_socket_rdma >= 0)
1733                 close(priv->nl_socket_rdma);
1734         if (priv->vmwa_context)
1735                 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1736         ret = mlx5_hrxq_verify(dev);
1737         if (ret)
1738                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1739                         dev->data->port_id);
1740         ret = mlx5_ind_table_obj_verify(dev);
1741         if (ret)
1742                 DRV_LOG(WARNING, "port %u some indirection table still remain",
1743                         dev->data->port_id);
1744         ret = mlx5_rxq_obj_verify(dev);
1745         if (ret)
1746                 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1747                         dev->data->port_id);
1748         ret = mlx5_rxq_verify(dev);
1749         if (ret)
1750                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1751                         dev->data->port_id);
1752         ret = mlx5_txq_obj_verify(dev);
1753         if (ret)
1754                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1755                         dev->data->port_id);
1756         ret = mlx5_txq_verify(dev);
1757         if (ret)
1758                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1759                         dev->data->port_id);
1760         ret = mlx5_flow_verify(dev);
1761         if (ret)
1762                 DRV_LOG(WARNING, "port %u some flows still remain",
1763                         dev->data->port_id);
1764         if (priv->hrxqs)
1765                 mlx5_list_destroy(priv->hrxqs);
1766         /*
1767          * Free the shared context in last turn, because the cleanup
1768          * routines above may use some shared fields, like
1769          * mlx5_os_mac_addr_flush() uses ibdev_path for retrieveing
1770          * ifindex if Netlink fails.
1771          */
1772         mlx5_free_shared_dev_ctx(priv->sh);
1773         if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1774                 unsigned int c = 0;
1775                 uint16_t port_id;
1776
1777                 MLX5_ETH_FOREACH_DEV(port_id, dev->device) {
1778                         struct mlx5_priv *opriv =
1779                                 rte_eth_devices[port_id].data->dev_private;
1780
1781                         if (!opriv ||
1782                             opriv->domain_id != priv->domain_id ||
1783                             &rte_eth_devices[port_id] == dev)
1784                                 continue;
1785                         ++c;
1786                         break;
1787                 }
1788                 if (!c)
1789                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1790         }
1791         memset(priv, 0, sizeof(*priv));
1792         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1793         /*
1794          * Reset mac_addrs to NULL such that it is not freed as part of
1795          * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1796          * it is freed when dev_private is freed.
1797          */
1798         dev->data->mac_addrs = NULL;
1799         return 0;
1800 }
1801
1802 const struct eth_dev_ops mlx5_dev_ops = {
1803         .dev_configure = mlx5_dev_configure,
1804         .dev_start = mlx5_dev_start,
1805         .dev_stop = mlx5_dev_stop,
1806         .dev_set_link_down = mlx5_set_link_down,
1807         .dev_set_link_up = mlx5_set_link_up,
1808         .dev_close = mlx5_dev_close,
1809         .promiscuous_enable = mlx5_promiscuous_enable,
1810         .promiscuous_disable = mlx5_promiscuous_disable,
1811         .allmulticast_enable = mlx5_allmulticast_enable,
1812         .allmulticast_disable = mlx5_allmulticast_disable,
1813         .link_update = mlx5_link_update,
1814         .stats_get = mlx5_stats_get,
1815         .stats_reset = mlx5_stats_reset,
1816         .xstats_get = mlx5_xstats_get,
1817         .xstats_reset = mlx5_xstats_reset,
1818         .xstats_get_names = mlx5_xstats_get_names,
1819         .fw_version_get = mlx5_fw_version_get,
1820         .dev_infos_get = mlx5_dev_infos_get,
1821         .representor_info_get = mlx5_representor_info_get,
1822         .read_clock = mlx5_txpp_read_clock,
1823         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1824         .vlan_filter_set = mlx5_vlan_filter_set,
1825         .rx_queue_setup = mlx5_rx_queue_setup,
1826         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1827         .tx_queue_setup = mlx5_tx_queue_setup,
1828         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1829         .rx_queue_release = mlx5_rx_queue_release,
1830         .tx_queue_release = mlx5_tx_queue_release,
1831         .rx_queue_start = mlx5_rx_queue_start,
1832         .rx_queue_stop = mlx5_rx_queue_stop,
1833         .tx_queue_start = mlx5_tx_queue_start,
1834         .tx_queue_stop = mlx5_tx_queue_stop,
1835         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1836         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1837         .mac_addr_remove = mlx5_mac_addr_remove,
1838         .mac_addr_add = mlx5_mac_addr_add,
1839         .mac_addr_set = mlx5_mac_addr_set,
1840         .set_mc_addr_list = mlx5_set_mc_addr_list,
1841         .mtu_set = mlx5_dev_set_mtu,
1842         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1843         .vlan_offload_set = mlx5_vlan_offload_set,
1844         .reta_update = mlx5_dev_rss_reta_update,
1845         .reta_query = mlx5_dev_rss_reta_query,
1846         .rss_hash_update = mlx5_rss_hash_update,
1847         .rss_hash_conf_get = mlx5_rss_hash_conf_get,
1848         .flow_ops_get = mlx5_flow_ops_get,
1849         .rxq_info_get = mlx5_rxq_info_get,
1850         .txq_info_get = mlx5_txq_info_get,
1851         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1852         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1853         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1854         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1855         .is_removed = mlx5_is_removed,
1856         .udp_tunnel_port_add  = mlx5_udp_tunnel_port_add,
1857         .get_module_info = mlx5_get_module_info,
1858         .get_module_eeprom = mlx5_get_module_eeprom,
1859         .hairpin_cap_get = mlx5_hairpin_cap_get,
1860         .mtr_ops_get = mlx5_flow_meter_ops_get,
1861         .hairpin_bind = mlx5_hairpin_bind,
1862         .hairpin_unbind = mlx5_hairpin_unbind,
1863         .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1864         .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1865         .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1866         .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1867         .get_monitor_addr = mlx5_get_monitor_addr,
1868 };
1869
1870 /* Available operations from secondary process. */
1871 const struct eth_dev_ops mlx5_dev_sec_ops = {
1872         .stats_get = mlx5_stats_get,
1873         .stats_reset = mlx5_stats_reset,
1874         .xstats_get = mlx5_xstats_get,
1875         .xstats_reset = mlx5_xstats_reset,
1876         .xstats_get_names = mlx5_xstats_get_names,
1877         .fw_version_get = mlx5_fw_version_get,
1878         .dev_infos_get = mlx5_dev_infos_get,
1879         .representor_info_get = mlx5_representor_info_get,
1880         .read_clock = mlx5_txpp_read_clock,
1881         .rx_queue_start = mlx5_rx_queue_start,
1882         .rx_queue_stop = mlx5_rx_queue_stop,
1883         .tx_queue_start = mlx5_tx_queue_start,
1884         .tx_queue_stop = mlx5_tx_queue_stop,
1885         .rxq_info_get = mlx5_rxq_info_get,
1886         .txq_info_get = mlx5_txq_info_get,
1887         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1888         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1889         .get_module_info = mlx5_get_module_info,
1890         .get_module_eeprom = mlx5_get_module_eeprom,
1891 };
1892
1893 /* Available operations in flow isolated mode. */
1894 const struct eth_dev_ops mlx5_dev_ops_isolate = {
1895         .dev_configure = mlx5_dev_configure,
1896         .dev_start = mlx5_dev_start,
1897         .dev_stop = mlx5_dev_stop,
1898         .dev_set_link_down = mlx5_set_link_down,
1899         .dev_set_link_up = mlx5_set_link_up,
1900         .dev_close = mlx5_dev_close,
1901         .promiscuous_enable = mlx5_promiscuous_enable,
1902         .promiscuous_disable = mlx5_promiscuous_disable,
1903         .allmulticast_enable = mlx5_allmulticast_enable,
1904         .allmulticast_disable = mlx5_allmulticast_disable,
1905         .link_update = mlx5_link_update,
1906         .stats_get = mlx5_stats_get,
1907         .stats_reset = mlx5_stats_reset,
1908         .xstats_get = mlx5_xstats_get,
1909         .xstats_reset = mlx5_xstats_reset,
1910         .xstats_get_names = mlx5_xstats_get_names,
1911         .fw_version_get = mlx5_fw_version_get,
1912         .dev_infos_get = mlx5_dev_infos_get,
1913         .representor_info_get = mlx5_representor_info_get,
1914         .read_clock = mlx5_txpp_read_clock,
1915         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1916         .vlan_filter_set = mlx5_vlan_filter_set,
1917         .rx_queue_setup = mlx5_rx_queue_setup,
1918         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1919         .tx_queue_setup = mlx5_tx_queue_setup,
1920         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1921         .rx_queue_release = mlx5_rx_queue_release,
1922         .tx_queue_release = mlx5_tx_queue_release,
1923         .rx_queue_start = mlx5_rx_queue_start,
1924         .rx_queue_stop = mlx5_rx_queue_stop,
1925         .tx_queue_start = mlx5_tx_queue_start,
1926         .tx_queue_stop = mlx5_tx_queue_stop,
1927         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1928         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1929         .mac_addr_remove = mlx5_mac_addr_remove,
1930         .mac_addr_add = mlx5_mac_addr_add,
1931         .mac_addr_set = mlx5_mac_addr_set,
1932         .set_mc_addr_list = mlx5_set_mc_addr_list,
1933         .mtu_set = mlx5_dev_set_mtu,
1934         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1935         .vlan_offload_set = mlx5_vlan_offload_set,
1936         .flow_ops_get = mlx5_flow_ops_get,
1937         .rxq_info_get = mlx5_rxq_info_get,
1938         .txq_info_get = mlx5_txq_info_get,
1939         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1940         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1941         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1942         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1943         .is_removed = mlx5_is_removed,
1944         .get_module_info = mlx5_get_module_info,
1945         .get_module_eeprom = mlx5_get_module_eeprom,
1946         .hairpin_cap_get = mlx5_hairpin_cap_get,
1947         .mtr_ops_get = mlx5_flow_meter_ops_get,
1948         .hairpin_bind = mlx5_hairpin_bind,
1949         .hairpin_unbind = mlx5_hairpin_unbind,
1950         .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1951         .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1952         .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1953         .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1954         .get_monitor_addr = mlx5_get_monitor_addr,
1955 };
1956
1957 /**
1958  * Verify and store value for device argument.
1959  *
1960  * @param[in] key
1961  *   Key argument to verify.
1962  * @param[in] val
1963  *   Value associated with key.
1964  * @param opaque
1965  *   User data.
1966  *
1967  * @return
1968  *   0 on success, a negative errno value otherwise and rte_errno is set.
1969  */
1970 static int
1971 mlx5_args_check(const char *key, const char *val, void *opaque)
1972 {
1973         struct mlx5_dev_config *config = opaque;
1974         unsigned long mod;
1975         signed long tmp;
1976
1977         /* No-op, port representors are processed in mlx5_dev_spawn(). */
1978         if (!strcmp(MLX5_DRIVER_KEY, key) || !strcmp(MLX5_REPRESENTOR, key) ||
1979             !strcmp(MLX5_SYS_MEM_EN, key) || !strcmp(MLX5_TX_DB_NC, key) ||
1980             !strcmp(MLX5_MR_MEMPOOL_REG_EN, key) ||
1981             !strcmp(MLX5_MR_EXT_MEMSEG_EN, key))
1982                 return 0;
1983         errno = 0;
1984         tmp = strtol(val, NULL, 0);
1985         if (errno) {
1986                 rte_errno = errno;
1987                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1988                 return -rte_errno;
1989         }
1990         if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
1991                 /* Negative values are acceptable for some keys only. */
1992                 rte_errno = EINVAL;
1993                 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
1994                 return -rte_errno;
1995         }
1996         mod = tmp >= 0 ? tmp : -tmp;
1997         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1998                 if (tmp > MLX5_CQE_RESP_FORMAT_L34H_STRIDX) {
1999                         DRV_LOG(ERR, "invalid CQE compression "
2000                                      "format parameter");
2001                         rte_errno = EINVAL;
2002                         return -rte_errno;
2003                 }
2004                 config->cqe_comp = !!tmp;
2005                 config->cqe_comp_fmt = tmp;
2006         } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
2007                 config->hw_padding = !!tmp;
2008         } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
2009                 config->mprq.enabled = !!tmp;
2010         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
2011                 config->mprq.stride_num_n = tmp;
2012         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
2013                 config->mprq.stride_size_n = tmp;
2014         } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
2015                 config->mprq.max_memcpy_len = tmp;
2016         } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
2017                 config->mprq.min_rxqs_num = tmp;
2018         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
2019                 DRV_LOG(WARNING, "%s: deprecated parameter,"
2020                                  " converted to txq_inline_max", key);
2021                 config->txq_inline_max = tmp;
2022         } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
2023                 config->txq_inline_max = tmp;
2024         } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
2025                 config->txq_inline_min = tmp;
2026         } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
2027                 config->txq_inline_mpw = tmp;
2028         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
2029                 config->txqs_inline = tmp;
2030         } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
2031                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
2032         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
2033                 config->mps = !!tmp;
2034         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
2035                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
2036         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
2037                 DRV_LOG(WARNING, "%s: deprecated parameter,"
2038                                  " converted to txq_inline_mpw", key);
2039                 config->txq_inline_mpw = tmp;
2040         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
2041                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
2042         } else if (strcmp(MLX5_TX_PP, key) == 0) {
2043                 if (!mod) {
2044                         DRV_LOG(ERR, "Zero Tx packet pacing parameter");
2045                         rte_errno = EINVAL;
2046                         return -rte_errno;
2047                 }
2048                 config->tx_pp = tmp;
2049         } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
2050                 config->tx_skew = tmp;
2051         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
2052                 config->rx_vec_en = !!tmp;
2053         } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
2054                 config->l3_vxlan_en = !!tmp;
2055         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
2056                 config->vf_nl_en = !!tmp;
2057         } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
2058                 config->dv_esw_en = !!tmp;
2059         } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
2060                 config->dv_flow_en = !!tmp;
2061         } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
2062                 if (tmp != MLX5_XMETA_MODE_LEGACY &&
2063                     tmp != MLX5_XMETA_MODE_META16 &&
2064                     tmp != MLX5_XMETA_MODE_META32 &&
2065                     tmp != MLX5_XMETA_MODE_MISS_INFO) {
2066                         DRV_LOG(ERR, "invalid extensive "
2067                                      "metadata parameter");
2068                         rte_errno = EINVAL;
2069                         return -rte_errno;
2070                 }
2071                 if (tmp != MLX5_XMETA_MODE_MISS_INFO)
2072                         config->dv_xmeta_en = tmp;
2073                 else
2074                         config->dv_miss_info = 1;
2075         } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
2076                 config->lacp_by_user = !!tmp;
2077         } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
2078                 config->max_dump_files_num = tmp;
2079         } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
2080                 config->lro.timeout = tmp;
2081         } else if (strcmp(RTE_DEVARGS_KEY_CLASS, key) == 0) {
2082                 DRV_LOG(DEBUG, "class argument is %s.", val);
2083         } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
2084                 config->log_hp_size = tmp;
2085         } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
2086                 if (tmp != MLX5_RCM_NONE &&
2087                     tmp != MLX5_RCM_LIGHT &&
2088                     tmp != MLX5_RCM_AGGR) {
2089                         DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
2090                         rte_errno = EINVAL;
2091                         return -rte_errno;
2092                 }
2093                 config->reclaim_mode = tmp;
2094         } else if (strcmp(MLX5_DECAP_EN, key) == 0) {
2095                 config->decap_en = !!tmp;
2096         } else if (strcmp(MLX5_ALLOW_DUPLICATE_PATTERN, key) == 0) {
2097                 config->allow_duplicate_pattern = !!tmp;
2098         } else {
2099                 DRV_LOG(WARNING, "%s: unknown parameter", key);
2100                 rte_errno = EINVAL;
2101                 return -rte_errno;
2102         }
2103         return 0;
2104 }
2105
2106 /**
2107  * Parse device parameters.
2108  *
2109  * @param config
2110  *   Pointer to device configuration structure.
2111  * @param devargs
2112  *   Device arguments structure.
2113  *
2114  * @return
2115  *   0 on success, a negative errno value otherwise and rte_errno is set.
2116  */
2117 int
2118 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
2119 {
2120         const char **params = (const char *[]){
2121                 MLX5_DRIVER_KEY,
2122                 MLX5_RXQ_CQE_COMP_EN,
2123                 MLX5_RXQ_PKT_PAD_EN,
2124                 MLX5_RX_MPRQ_EN,
2125                 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
2126                 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
2127                 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
2128                 MLX5_RXQS_MIN_MPRQ,
2129                 MLX5_TXQ_INLINE,
2130                 MLX5_TXQ_INLINE_MIN,
2131                 MLX5_TXQ_INLINE_MAX,
2132                 MLX5_TXQ_INLINE_MPW,
2133                 MLX5_TXQS_MIN_INLINE,
2134                 MLX5_TXQS_MAX_VEC,
2135                 MLX5_TXQ_MPW_EN,
2136                 MLX5_TXQ_MPW_HDR_DSEG_EN,
2137                 MLX5_TXQ_MAX_INLINE_LEN,
2138                 MLX5_TX_DB_NC,
2139                 MLX5_TX_PP,
2140                 MLX5_TX_SKEW,
2141                 MLX5_TX_VEC_EN,
2142                 MLX5_RX_VEC_EN,
2143                 MLX5_L3_VXLAN_EN,
2144                 MLX5_VF_NL_EN,
2145                 MLX5_DV_ESW_EN,
2146                 MLX5_DV_FLOW_EN,
2147                 MLX5_DV_XMETA_EN,
2148                 MLX5_LACP_BY_USER,
2149                 MLX5_MR_EXT_MEMSEG_EN,
2150                 MLX5_REPRESENTOR,
2151                 MLX5_MAX_DUMP_FILES_NUM,
2152                 MLX5_LRO_TIMEOUT_USEC,
2153                 RTE_DEVARGS_KEY_CLASS,
2154                 MLX5_HP_BUF_SIZE,
2155                 MLX5_RECLAIM_MEM,
2156                 MLX5_SYS_MEM_EN,
2157                 MLX5_DECAP_EN,
2158                 MLX5_ALLOW_DUPLICATE_PATTERN,
2159                 MLX5_MR_MEMPOOL_REG_EN,
2160                 NULL,
2161         };
2162         struct rte_kvargs *kvlist;
2163         int ret = 0;
2164         int i;
2165
2166         if (devargs == NULL)
2167                 return 0;
2168         /* Following UGLY cast is done to pass checkpatch. */
2169         kvlist = rte_kvargs_parse(devargs->args, params);
2170         if (kvlist == NULL) {
2171                 rte_errno = EINVAL;
2172                 return -rte_errno;
2173         }
2174         /* Process parameters. */
2175         for (i = 0; (params[i] != NULL); ++i) {
2176                 if (rte_kvargs_count(kvlist, params[i])) {
2177                         ret = rte_kvargs_process(kvlist, params[i],
2178                                                  mlx5_args_check, config);
2179                         if (ret) {
2180                                 rte_errno = EINVAL;
2181                                 rte_kvargs_free(kvlist);
2182                                 return -rte_errno;
2183                         }
2184                 }
2185         }
2186         rte_kvargs_free(kvlist);
2187         return 0;
2188 }
2189
2190 /**
2191  * Configures the minimal amount of data to inline into WQE
2192  * while sending packets.
2193  *
2194  * - the txq_inline_min has the maximal priority, if this
2195  *   key is specified in devargs
2196  * - if DevX is enabled the inline mode is queried from the
2197  *   device (HCA attributes and NIC vport context if needed).
2198  * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
2199  *   and none (0 bytes) for other NICs
2200  *
2201  * @param spawn
2202  *   Verbs device parameters (name, port, switch_info) to spawn.
2203  * @param config
2204  *   Device configuration parameters.
2205  */
2206 void
2207 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
2208                     struct mlx5_dev_config *config)
2209 {
2210         if (config->txq_inline_min != MLX5_ARG_UNSET) {
2211                 /* Application defines size of inlined data explicitly. */
2212                 if (spawn->pci_dev != NULL) {
2213                         switch (spawn->pci_dev->id.device_id) {
2214                         case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2215                         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2216                                 if (config->txq_inline_min <
2217                                                (int)MLX5_INLINE_HSIZE_L2) {
2218                                         DRV_LOG(DEBUG,
2219                                                 "txq_inline_mix aligned to minimal ConnectX-4 required value %d",
2220                                                 (int)MLX5_INLINE_HSIZE_L2);
2221                                         config->txq_inline_min =
2222                                                         MLX5_INLINE_HSIZE_L2;
2223                                 }
2224                                 break;
2225                         }
2226                 }
2227                 goto exit;
2228         }
2229         if (config->hca_attr.eth_net_offloads) {
2230                 /* We have DevX enabled, inline mode queried successfully. */
2231                 switch (config->hca_attr.wqe_inline_mode) {
2232                 case MLX5_CAP_INLINE_MODE_L2:
2233                         /* outer L2 header must be inlined. */
2234                         config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2235                         goto exit;
2236                 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
2237                         /* No inline data are required by NIC. */
2238                         config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2239                         config->hw_vlan_insert =
2240                                 config->hca_attr.wqe_vlan_insert;
2241                         DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
2242                         goto exit;
2243                 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
2244                         /* inline mode is defined by NIC vport context. */
2245                         if (!config->hca_attr.eth_virt)
2246                                 break;
2247                         switch (config->hca_attr.vport_inline_mode) {
2248                         case MLX5_INLINE_MODE_NONE:
2249                                 config->txq_inline_min =
2250                                         MLX5_INLINE_HSIZE_NONE;
2251                                 goto exit;
2252                         case MLX5_INLINE_MODE_L2:
2253                                 config->txq_inline_min =
2254                                         MLX5_INLINE_HSIZE_L2;
2255                                 goto exit;
2256                         case MLX5_INLINE_MODE_IP:
2257                                 config->txq_inline_min =
2258                                         MLX5_INLINE_HSIZE_L3;
2259                                 goto exit;
2260                         case MLX5_INLINE_MODE_TCP_UDP:
2261                                 config->txq_inline_min =
2262                                         MLX5_INLINE_HSIZE_L4;
2263                                 goto exit;
2264                         case MLX5_INLINE_MODE_INNER_L2:
2265                                 config->txq_inline_min =
2266                                         MLX5_INLINE_HSIZE_INNER_L2;
2267                                 goto exit;
2268                         case MLX5_INLINE_MODE_INNER_IP:
2269                                 config->txq_inline_min =
2270                                         MLX5_INLINE_HSIZE_INNER_L3;
2271                                 goto exit;
2272                         case MLX5_INLINE_MODE_INNER_TCP_UDP:
2273                                 config->txq_inline_min =
2274                                         MLX5_INLINE_HSIZE_INNER_L4;
2275                                 goto exit;
2276                         }
2277                 }
2278         }
2279         if (spawn->pci_dev == NULL) {
2280                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2281                 goto exit;
2282         }
2283         /*
2284          * We get here if we are unable to deduce
2285          * inline data size with DevX. Try PCI ID
2286          * to determine old NICs.
2287          */
2288         switch (spawn->pci_dev->id.device_id) {
2289         case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2290         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2291         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
2292         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
2293                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2294                 config->hw_vlan_insert = 0;
2295                 break;
2296         case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
2297         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
2298         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
2299         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
2300                 /*
2301                  * These NICs support VLAN insertion from WQE and
2302                  * report the wqe_vlan_insert flag. But there is the bug
2303                  * and PFC control may be broken, so disable feature.
2304                  */
2305                 config->hw_vlan_insert = 0;
2306                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2307                 break;
2308         default:
2309                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2310                 break;
2311         }
2312 exit:
2313         DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
2314 }
2315
2316 /**
2317  * Configures the metadata mask fields in the shared context.
2318  *
2319  * @param [in] dev
2320  *   Pointer to Ethernet device.
2321  */
2322 void
2323 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
2324 {
2325         struct mlx5_priv *priv = dev->data->dev_private;
2326         struct mlx5_dev_ctx_shared *sh = priv->sh;
2327         uint32_t meta, mark, reg_c0;
2328
2329         reg_c0 = ~priv->vport_meta_mask;
2330         switch (priv->config.dv_xmeta_en) {
2331         case MLX5_XMETA_MODE_LEGACY:
2332                 meta = UINT32_MAX;
2333                 mark = MLX5_FLOW_MARK_MASK;
2334                 break;
2335         case MLX5_XMETA_MODE_META16:
2336                 meta = reg_c0 >> rte_bsf32(reg_c0);
2337                 mark = MLX5_FLOW_MARK_MASK;
2338                 break;
2339         case MLX5_XMETA_MODE_META32:
2340                 meta = UINT32_MAX;
2341                 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
2342                 break;
2343         default:
2344                 meta = 0;
2345                 mark = 0;
2346                 MLX5_ASSERT(false);
2347                 break;
2348         }
2349         if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
2350                 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
2351                                  sh->dv_mark_mask, mark);
2352         else
2353                 sh->dv_mark_mask = mark;
2354         if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
2355                 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
2356                                  sh->dv_meta_mask, meta);
2357         else
2358                 sh->dv_meta_mask = meta;
2359         if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
2360                 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
2361                                  sh->dv_meta_mask, reg_c0);
2362         else
2363                 sh->dv_regc0_mask = reg_c0;
2364         DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
2365         DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
2366         DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
2367         DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
2368 }
2369
2370 int
2371 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
2372 {
2373         static const char *const dynf_names[] = {
2374                 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
2375                 RTE_MBUF_DYNFLAG_METADATA_NAME,
2376                 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
2377         };
2378         unsigned int i;
2379
2380         if (n < RTE_DIM(dynf_names))
2381                 return -ENOMEM;
2382         for (i = 0; i < RTE_DIM(dynf_names); i++) {
2383                 if (names[i] == NULL)
2384                         return -EINVAL;
2385                 strcpy(names[i], dynf_names[i]);
2386         }
2387         return RTE_DIM(dynf_names);
2388 }
2389
2390 /**
2391  * Comparison callback to sort device data.
2392  *
2393  * This is meant to be used with qsort().
2394  *
2395  * @param a[in]
2396  *   Pointer to pointer to first data object.
2397  * @param b[in]
2398  *   Pointer to pointer to second data object.
2399  *
2400  * @return
2401  *   0 if both objects are equal, less than 0 if the first argument is less
2402  *   than the second, greater than 0 otherwise.
2403  */
2404 int
2405 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
2406                               struct mlx5_dev_config *config,
2407                               struct rte_device *dpdk_dev)
2408 {
2409         struct mlx5_dev_ctx_shared *sh = priv->sh;
2410         struct mlx5_dev_config *sh_conf = NULL;
2411         uint16_t port_id;
2412
2413         MLX5_ASSERT(sh);
2414         /* Nothing to compare for the single/first device. */
2415         if (sh->refcnt == 1)
2416                 return 0;
2417         /* Find the device with shared context. */
2418         MLX5_ETH_FOREACH_DEV(port_id, dpdk_dev) {
2419                 struct mlx5_priv *opriv =
2420                         rte_eth_devices[port_id].data->dev_private;
2421
2422                 if (opriv && opriv != priv && opriv->sh == sh) {
2423                         sh_conf = &opriv->config;
2424                         break;
2425                 }
2426         }
2427         if (!sh_conf)
2428                 return 0;
2429         if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
2430                 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
2431                              " for shared %s context", sh->ibdev_name);
2432                 rte_errno = EINVAL;
2433                 return rte_errno;
2434         }
2435         if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
2436                 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
2437                              " for shared %s context", sh->ibdev_name);
2438                 rte_errno = EINVAL;
2439                 return rte_errno;
2440         }
2441         return 0;
2442 }
2443
2444 /**
2445  * Look for the ethernet device belonging to mlx5 driver.
2446  *
2447  * @param[in] port_id
2448  *   port_id to start looking for device.
2449  * @param[in] odev
2450  *   Pointer to the hint device. When device is being probed
2451  *   the its siblings (master and preceding representors might
2452  *   not have assigned driver yet (because the mlx5_os_pci_probe()
2453  *   is not completed yet, for this case match on hint
2454  *   device may be used to detect sibling device.
2455  *
2456  * @return
2457  *   port_id of found device, RTE_MAX_ETHPORT if not found.
2458  */
2459 uint16_t
2460 mlx5_eth_find_next(uint16_t port_id, struct rte_device *odev)
2461 {
2462         while (port_id < RTE_MAX_ETHPORTS) {
2463                 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
2464
2465                 if (dev->state != RTE_ETH_DEV_UNUSED &&
2466                     dev->device &&
2467                     (dev->device == odev ||
2468                      (dev->device->driver &&
2469                      dev->device->driver->name &&
2470                      ((strcmp(dev->device->driver->name,
2471                               MLX5_PCI_DRIVER_NAME) == 0) ||
2472                       (strcmp(dev->device->driver->name,
2473                               MLX5_AUXILIARY_DRIVER_NAME) == 0)))))
2474                         break;
2475                 port_id++;
2476         }
2477         if (port_id >= RTE_MAX_ETHPORTS)
2478                 return RTE_MAX_ETHPORTS;
2479         return port_id;
2480 }
2481
2482 /**
2483  * Callback to remove a device.
2484  *
2485  * This function removes all Ethernet devices belong to a given device.
2486  *
2487  * @param[in] cdev
2488  *   Pointer to the generic device.
2489  *
2490  * @return
2491  *   0 on success, the function cannot fail.
2492  */
2493 int
2494 mlx5_net_remove(struct mlx5_common_device *cdev)
2495 {
2496         uint16_t port_id;
2497         int ret = 0;
2498
2499         RTE_ETH_FOREACH_DEV_OF(port_id, cdev->dev) {
2500                 /*
2501                  * mlx5_dev_close() is not registered to secondary process,
2502                  * call the close function explicitly for secondary process.
2503                  */
2504                 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
2505                         ret |= mlx5_dev_close(&rte_eth_devices[port_id]);
2506                 else
2507                         ret |= rte_eth_dev_close(port_id);
2508         }
2509         return ret == 0 ? 0 : -EIO;
2510 }
2511
2512 static const struct rte_pci_id mlx5_pci_id_map[] = {
2513         {
2514                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2515                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
2516         },
2517         {
2518                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2519                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
2520         },
2521         {
2522                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2523                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
2524         },
2525         {
2526                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2527                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
2528         },
2529         {
2530                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2531                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
2532         },
2533         {
2534                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2535                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
2536         },
2537         {
2538                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2539                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
2540         },
2541         {
2542                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2543                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
2544         },
2545         {
2546                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2547                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
2548         },
2549         {
2550                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2551                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
2552         },
2553         {
2554                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2555                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
2556         },
2557         {
2558                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2559                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
2560         },
2561         {
2562                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2563                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
2564         },
2565         {
2566                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2567                                 PCI_DEVICE_ID_MELLANOX_CONNECTXVF)
2568         },
2569         {
2570                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2571                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
2572         },
2573         {
2574                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2575                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
2576         },
2577         {
2578                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2579                                 PCI_DEVICE_ID_MELLANOX_CONNECTX7)
2580         },
2581         {
2582                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2583                                 PCI_DEVICE_ID_MELLANOX_CONNECTX7BF)
2584         },
2585         {
2586                 .vendor_id = 0
2587         }
2588 };
2589
2590 static struct mlx5_class_driver mlx5_net_driver = {
2591         .drv_class = MLX5_CLASS_ETH,
2592         .name = RTE_STR(MLX5_ETH_DRIVER_NAME),
2593         .id_table = mlx5_pci_id_map,
2594         .probe = mlx5_os_net_probe,
2595         .remove = mlx5_net_remove,
2596         .probe_again = 1,
2597         .intr_lsc = 1,
2598         .intr_rmv = 1,
2599 };
2600
2601 /* Initialize driver log type. */
2602 RTE_LOG_REGISTER_DEFAULT(mlx5_logtype, NOTICE)
2603
2604 /**
2605  * Driver initialization routine.
2606  */
2607 RTE_INIT(rte_mlx5_pmd_init)
2608 {
2609         pthread_mutex_init(&mlx5_dev_ctx_list_mutex, NULL);
2610         mlx5_common_init();
2611         /* Build the static tables for Verbs conversion. */
2612         mlx5_set_ptype_table();
2613         mlx5_set_cksum_table();
2614         mlx5_set_swp_types_table();
2615         if (mlx5_glue)
2616                 mlx5_class_driver_register(&mlx5_net_driver);
2617 }
2618
2619 RTE_PMD_EXPORT_NAME(MLX5_ETH_DRIVER_NAME, __COUNTER__);
2620 RTE_PMD_REGISTER_PCI_TABLE(MLX5_ETH_DRIVER_NAME, mlx5_pci_id_map);
2621 RTE_PMD_REGISTER_KMOD_DEP(MLX5_ETH_DRIVER_NAME, "* ib_uverbs & mlx5_core & mlx5_ib");