drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <stdint.h>
  10 #include <stdlib.h>
  11 #include <errno.h>
  12 #include <net/if.h>
  13 #include <sys/mman.h>
  14 #include <linux/rtnetlink.h>
  15
  16 /* Verbs header. */
  17 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  18 #ifdef PEDANTIC
  19 #pragma GCC diagnostic ignored "-Wpedantic"
  20 #endif
  21 #include <infiniband/verbs.h>
  22 #ifdef PEDANTIC
  23 #pragma GCC diagnostic error "-Wpedantic"
  24 #endif
  25
  26 #include <rte_malloc.h>
  27 #include <rte_ethdev_driver.h>
  28 #include <rte_ethdev_pci.h>
  29 #include <rte_pci.h>
  30 #include <rte_bus_pci.h>
  31 #include <rte_common.h>
  32 #include <rte_kvargs.h>
  33 #include <rte_rwlock.h>
  34 #include <rte_spinlock.h>
  35 #include <rte_string_fns.h>
  36 #include <rte_alarm.h>
  37
  38 #include <mlx5_glue.h>
  39 #include <mlx5_devx_cmds.h>
  40 #include <mlx5_common.h>
  41 #include <mlx5_common_os.h>
  42 #include <mlx5_common_mp.h>
  43
  44 #include "mlx5_defs.h"
  45 #include "mlx5.h"
  46 #include "mlx5_utils.h"
  47 #include "mlx5_rxtx.h"
  48 #include "mlx5_autoconf.h"
  49 #include "mlx5_mr.h"
  50 #include "mlx5_flow.h"
  51 #include "rte_pmd_mlx5.h"
  52
  53 /* Device parameter to enable RX completion queue compression. */
  54 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  55
  56 /* Device parameter to enable RX completion entry padding to 128B. */
  57 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
  58
  59 /* Device parameter to enable padding Rx packet to cacheline size. */
  60 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
  61
  62 /* Device parameter to enable Multi-Packet Rx queue. */
  63 #define MLX5_RX_MPRQ_EN "mprq_en"
  64
  65 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
  66 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
  67
  68 /* Device parameter to configure log 2 of the stride size for MPRQ. */
  69 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
  70
  71 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
  72 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
  73
  74 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
  75 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
  76
  77 /* Device parameter to configure inline send. Deprecated, ignored.*/
  78 #define MLX5_TXQ_INLINE "txq_inline"
  79
  80 /* Device parameter to limit packet size to inline with ordinary SEND. */
  81 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
  82
  83 /* Device parameter to configure minimal data size to inline. */
  84 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
  85
  86 /* Device parameter to limit packet size to inline with Enhanced MPW. */
  87 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
  88
  89 /*
  90  * Device parameter to configure the number of TX queues threshold for
  91  * enabling inline send.
  92  */
  93 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  94
  95 /*
  96  * Device parameter to configure the number of TX queues threshold for
  97  * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
  98  */
  99 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
 100
 101 /* Device parameter to enable multi-packet send WQEs. */
 102 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
 103
 104 /*
 105  * Device parameter to force doorbell register mapping
 106  * to non-cahed region eliminating the extra write memory barrier.
 107  */
 108 #define MLX5_TX_DB_NC "tx_db_nc"
 109
 110 /*
 111  * Device parameter to include 2 dsegs in the title WQEBB.
 112  * Deprecated, ignored.
 113  */
 114 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
 115
 116 /*
 117  * Device parameter to limit the size of inlining packet.
 118  * Deprecated, ignored.
 119  */
 120 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
 121
 122 /*
 123  * Device parameter to enable hardware Tx vector.
 124  * Deprecated, ignored (no vectorized Tx routines anymore).
 125  */
 126 #define MLX5_TX_VEC_EN "tx_vec_en"
 127
 128 /* Device parameter to enable hardware Rx vector. */
 129 #define MLX5_RX_VEC_EN "rx_vec_en"
 130
 131 /* Allow L3 VXLAN flow creation. */
 132 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
 133
 134 /* Activate DV E-Switch flow steering. */
 135 #define MLX5_DV_ESW_EN "dv_esw_en"
 136
 137 /* Activate DV flow steering. */
 138 #define MLX5_DV_FLOW_EN "dv_flow_en"
 139
 140 /* Enable extensive flow metadata support. */
 141 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
 142
 143 /* Activate Netlink support in VF mode. */
 144 #define MLX5_VF_NL_EN "vf_nl_en"
 145
 146 /* Enable extending memsegs when creating a MR. */
 147 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
 148
 149 /* Select port representors to instantiate. */
 150 #define MLX5_REPRESENTOR "representor"
 151
 152 /* Device parameter to configure the maximum number of dump files per queue. */
 153 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
 154
 155 /* Configure timeout of LRO session (in microseconds). */
 156 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
 157
 158 /*
 159  * Device parameter to configure the total data buffer size for a single
 160  * hairpin queue (logarithm value).
 161  */
 162 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
 163
 164 /* Flow memory reclaim mode. */
 165 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
 166
 167 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
 168
 169 /* Shared memory between primary and secondary processes. */
 170 struct mlx5_shared_data *mlx5_shared_data;
 171
 172 /* Spinlock for mlx5_shared_data allocation. */
 173 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
 174
 175 /* Process local data for secondary processes. */
 176 static struct mlx5_local_data mlx5_local_data;
 177 /** Driver-specific log messages type. */
 178 int mlx5_logtype;
 179
 180 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
 181                                                 LIST_HEAD_INITIALIZER();
 182 static pthread_mutex_t mlx5_dev_ctx_list_mutex = PTHREAD_MUTEX_INITIALIZER;
 183
 184 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
 185 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 186         {
 187                 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
 188                 .trunk_size = 64,
 189                 .grow_trunk = 3,
 190                 .grow_shift = 2,
 191                 .need_lock = 0,
 192                 .release_mem_en = 1,
 193                 .malloc = rte_malloc_socket,
 194                 .free = rte_free,
 195                 .type = "mlx5_encap_decap_ipool",
 196         },
 197         {
 198                 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
 199                 .trunk_size = 64,
 200                 .grow_trunk = 3,
 201                 .grow_shift = 2,
 202                 .need_lock = 0,
 203                 .release_mem_en = 1,
 204                 .malloc = rte_malloc_socket,
 205                 .free = rte_free,
 206                 .type = "mlx5_push_vlan_ipool",
 207         },
 208         {
 209                 .size = sizeof(struct mlx5_flow_dv_tag_resource),
 210                 .trunk_size = 64,
 211                 .grow_trunk = 3,
 212                 .grow_shift = 2,
 213                 .need_lock = 0,
 214                 .release_mem_en = 1,
 215                 .malloc = rte_malloc_socket,
 216                 .free = rte_free,
 217                 .type = "mlx5_tag_ipool",
 218         },
 219         {
 220                 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
 221                 .trunk_size = 64,
 222                 .grow_trunk = 3,
 223                 .grow_shift = 2,
 224                 .need_lock = 0,
 225                 .release_mem_en = 1,
 226                 .malloc = rte_malloc_socket,
 227                 .free = rte_free,
 228                 .type = "mlx5_port_id_ipool",
 229         },
 230         {
 231                 .size = sizeof(struct mlx5_flow_tbl_data_entry),
 232                 .trunk_size = 64,
 233                 .grow_trunk = 3,
 234                 .grow_shift = 2,
 235                 .need_lock = 0,
 236                 .release_mem_en = 1,
 237                 .malloc = rte_malloc_socket,
 238                 .free = rte_free,
 239                 .type = "mlx5_jump_ipool",
 240         },
 241 #endif
 242         {
 243                 .size = sizeof(struct mlx5_flow_meter),
 244                 .trunk_size = 64,
 245                 .grow_trunk = 3,
 246                 .grow_shift = 2,
 247                 .need_lock = 0,
 248                 .release_mem_en = 1,
 249                 .malloc = rte_malloc_socket,
 250                 .free = rte_free,
 251                 .type = "mlx5_meter_ipool",
 252         },
 253         {
 254                 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
 255                 .trunk_size = 64,
 256                 .grow_trunk = 3,
 257                 .grow_shift = 2,
 258                 .need_lock = 0,
 259                 .release_mem_en = 1,
 260                 .malloc = rte_malloc_socket,
 261                 .free = rte_free,
 262                 .type = "mlx5_mcp_ipool",
 263         },
 264         {
 265                 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
 266                 .trunk_size = 64,
 267                 .grow_trunk = 3,
 268                 .grow_shift = 2,
 269                 .need_lock = 0,
 270                 .release_mem_en = 1,
 271                 .malloc = rte_malloc_socket,
 272                 .free = rte_free,
 273                 .type = "mlx5_hrxq_ipool",
 274         },
 275         {
 276                 /*
 277                  * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
 278                  * It set in run time according to PCI function configuration.
 279                  */
 280                 .size = 0,
 281                 .trunk_size = 64,
 282                 .grow_trunk = 3,
 283                 .grow_shift = 2,
 284                 .need_lock = 0,
 285                 .release_mem_en = 1,
 286                 .malloc = rte_malloc_socket,
 287                 .free = rte_free,
 288                 .type = "mlx5_flow_handle_ipool",
 289         },
 290         {
 291                 .size = sizeof(struct rte_flow),
 292                 .trunk_size = 4096,
 293                 .need_lock = 1,
 294                 .release_mem_en = 1,
 295                 .malloc = rte_malloc_socket,
 296                 .free = rte_free,
 297                 .type = "rte_flow_ipool",
 298         },
 299 };
 300
 301
 302 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
 303 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
 304
 305 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
 306
 307 /**
 308  * Allocate ID pool structure.
 309  *
 310  * @param[in] max_id
 311  *   The maximum id can be allocated from the pool.
 312  *
 313  * @return
 314  *   Pointer to pool object, NULL value otherwise.
 315  */
 316 struct mlx5_flow_id_pool *
 317 mlx5_flow_id_pool_alloc(uint32_t max_id)
 318 {
 319         struct mlx5_flow_id_pool *pool;
 320         void *mem;
 321
 322         pool = rte_zmalloc("id pool allocation", sizeof(*pool),
 323                            RTE_CACHE_LINE_SIZE);
 324         if (!pool) {
 325                 DRV_LOG(ERR, "can't allocate id pool");
 326                 rte_errno  = ENOMEM;
 327                 return NULL;
 328         }
 329         mem = rte_zmalloc("", MLX5_FLOW_MIN_ID_POOL_SIZE * sizeof(uint32_t),
 330                           RTE_CACHE_LINE_SIZE);
 331         if (!mem) {
 332                 DRV_LOG(ERR, "can't allocate mem for id pool");
 333                 rte_errno  = ENOMEM;
 334                 goto error;
 335         }
 336         pool->free_arr = mem;
 337         pool->curr = pool->free_arr;
 338         pool->last = pool->free_arr + MLX5_FLOW_MIN_ID_POOL_SIZE;
 339         pool->base_index = 0;
 340         pool->max_id = max_id;
 341         return pool;
 342 error:
 343         rte_free(pool);
 344         return NULL;
 345 }
 346
 347 /**
 348  * Release ID pool structure.
 349  *
 350  * @param[in] pool
 351  *   Pointer to flow id pool object to free.
 352  */
 353 void
 354 mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool)
 355 {
 356         rte_free(pool->free_arr);
 357         rte_free(pool);
 358 }
 359
 360 /**
 361  * Generate ID.
 362  *
 363  * @param[in] pool
 364  *   Pointer to flow id pool.
 365  * @param[out] id
 366  *   The generated ID.
 367  *
 368  * @return
 369  *   0 on success, error value otherwise.
 370  */
 371 uint32_t
 372 mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id)
 373 {
 374         if (pool->curr == pool->free_arr) {
 375                 if (pool->base_index == pool->max_id) {
 376                         rte_errno  = ENOMEM;
 377                         DRV_LOG(ERR, "no free id");
 378                         return -rte_errno;
 379                 }
 380                 *id = ++pool->base_index;
 381                 return 0;
 382         }
 383         *id = *(--pool->curr);
 384         return 0;
 385 }
 386
 387 /**
 388  * Release ID.
 389  *
 390  * @param[in] pool
 391  *   Pointer to flow id pool.
 392  * @param[out] id
 393  *   The generated ID.
 394  *
 395  * @return
 396  *   0 on success, error value otherwise.
 397  */
 398 uint32_t
 399 mlx5_flow_id_release(struct mlx5_flow_id_pool *pool, uint32_t id)
 400 {
 401         uint32_t size;
 402         uint32_t size2;
 403         void *mem;
 404
 405         if (pool->curr == pool->last) {
 406                 size = pool->curr - pool->free_arr;
 407                 size2 = size * MLX5_ID_GENERATION_ARRAY_FACTOR;
 408                 MLX5_ASSERT(size2 > size);
 409                 mem = rte_malloc("", size2 * sizeof(uint32_t), 0);
 410                 if (!mem) {
 411                         DRV_LOG(ERR, "can't allocate mem for id pool");
 412                         rte_errno  = ENOMEM;
 413                         return -rte_errno;
 414                 }
 415                 memcpy(mem, pool->free_arr, size * sizeof(uint32_t));
 416                 rte_free(pool->free_arr);
 417                 pool->free_arr = mem;
 418                 pool->curr = pool->free_arr + size;
 419                 pool->last = pool->free_arr + size2;
 420         }
 421         *pool->curr = id;
 422         pool->curr++;
 423         return 0;
 424 }
 425
 426 /**
 427  * Initialize the shared aging list information per port.
 428  *
 429  * @param[in] sh
 430  *   Pointer to mlx5_dev_ctx_shared object.
 431  */
 432 static void
 433 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
 434 {
 435         uint32_t i;
 436         struct mlx5_age_info *age_info;
 437
 438         for (i = 0; i < sh->max_port; i++) {
 439                 age_info = &sh->port[i].age_info;
 440                 age_info->flags = 0;
 441                 TAILQ_INIT(&age_info->aged_counters);
 442                 rte_spinlock_init(&age_info->aged_sl);
 443                 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
 444         }
 445 }
 446
 447 /**
 448  * Initialize the counters management structure.
 449  *
 450  * @param[in] sh
 451  *   Pointer to mlx5_dev_ctx_shared object to free
 452  */
 453 static void
 454 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
 455 {
 456         int i;
 457
 458         memset(&sh->cmng, 0, sizeof(sh->cmng));
 459         TAILQ_INIT(&sh->cmng.flow_counters);
 460         for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
 461                 sh->cmng.ccont[i].min_id = MLX5_CNT_BATCH_OFFSET;
 462                 sh->cmng.ccont[i].max_id = -1;
 463                 sh->cmng.ccont[i].last_pool_idx = POOL_IDX_INVALID;
 464                 TAILQ_INIT(&sh->cmng.ccont[i].pool_list);
 465                 rte_spinlock_init(&sh->cmng.ccont[i].resize_sl);
 466                 TAILQ_INIT(&sh->cmng.ccont[i].counters);
 467                 rte_spinlock_init(&sh->cmng.ccont[i].csl);
 468         }
 469 }
 470
 471 /**
 472  * Destroy all the resources allocated for a counter memory management.
 473  *
 474  * @param[in] mng
 475  *   Pointer to the memory management structure.
 476  */
 477 static void
 478 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
 479 {
 480         uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
 481
 482         LIST_REMOVE(mng, next);
 483         claim_zero(mlx5_devx_cmd_destroy(mng->dm));
 484         claim_zero(mlx5_glue->devx_umem_dereg(mng->umem));
 485         rte_free(mem);
 486 }
 487
 488 /**
 489  * Close and release all the resources of the counters management.
 490  *
 491  * @param[in] sh
 492  *   Pointer to mlx5_dev_ctx_shared object to free.
 493  */
 494 static void
 495 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
 496 {
 497         struct mlx5_counter_stats_mem_mng *mng;
 498         int i;
 499         int j;
 500         int retries = 1024;
 501
 502         rte_errno = 0;
 503         while (--retries) {
 504                 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
 505                 if (rte_errno != EINPROGRESS)
 506                         break;
 507                 rte_pause();
 508         }
 509         for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
 510                 struct mlx5_flow_counter_pool *pool;
 511                 uint32_t batch = !!(i > 1);
 512
 513                 if (!sh->cmng.ccont[i].pools)
 514                         continue;
 515                 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
 516                 while (pool) {
 517                         if (batch && pool->min_dcs)
 518                                 claim_zero(mlx5_devx_cmd_destroy
 519                                                                (pool->min_dcs));
 520                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
 521                                 if (MLX5_POOL_GET_CNT(pool, j)->action)
 522                                         claim_zero
 523                                          (mlx5_glue->destroy_flow_action
 524                                           (MLX5_POOL_GET_CNT
 525                                           (pool, j)->action));
 526                                 if (!batch && MLX5_GET_POOL_CNT_EXT
 527                                     (pool, j)->dcs)
 528                                         claim_zero(mlx5_devx_cmd_destroy
 529                                                    (MLX5_GET_POOL_CNT_EXT
 530                                                     (pool, j)->dcs));
 531                         }
 532                         TAILQ_REMOVE(&sh->cmng.ccont[i].pool_list, pool, next);
 533                         rte_free(pool);
 534                         pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
 535                 }
 536                 rte_free(sh->cmng.ccont[i].pools);
 537         }
 538         mng = LIST_FIRST(&sh->cmng.mem_mngs);
 539         while (mng) {
 540                 mlx5_flow_destroy_counter_stat_mem_mng(mng);
 541                 mng = LIST_FIRST(&sh->cmng.mem_mngs);
 542         }
 543         memset(&sh->cmng, 0, sizeof(sh->cmng));
 544 }
 545
 546 /**
 547  * Initialize the flow resources' indexed mempool.
 548  *
 549  * @param[in] sh
 550  *   Pointer to mlx5_dev_ctx_shared object.
 551  * @param[in] sh
 552  *   Pointer to user dev config.
 553  */
 554 static void
 555 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
 556                        const struct mlx5_dev_config *config)
 557 {
 558         uint8_t i;
 559         struct mlx5_indexed_pool_config cfg;
 560
 561         for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
 562                 cfg = mlx5_ipool_cfg[i];
 563                 switch (i) {
 564                 default:
 565                         break;
 566                 /*
 567                  * Set MLX5_IPOOL_MLX5_FLOW ipool size
 568                  * according to PCI function flow configuration.
 569                  */
 570                 case MLX5_IPOOL_MLX5_FLOW:
 571                         cfg.size = config->dv_flow_en ?
 572                                 sizeof(struct mlx5_flow_handle) :
 573                                 MLX5_FLOW_HANDLE_VERBS_SIZE;
 574                         break;
 575                 }
 576                 if (config->reclaim_mode)
 577                         cfg.release_mem_en = 1;
 578                 sh->ipool[i] = mlx5_ipool_create(&cfg);
 579         }
 580 }
 581
 582 /**
 583  * Release the flow resources' indexed mempool.
 584  *
 585  * @param[in] sh
 586  *   Pointer to mlx5_dev_ctx_shared object.
 587  */
 588 static void
 589 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
 590 {
 591         uint8_t i;
 592
 593         for (i = 0; i < MLX5_IPOOL_MAX; ++i)
 594                 mlx5_ipool_destroy(sh->ipool[i]);
 595 }
 596
 597 /**
 598  * Allocate shared device context. If there is multiport device the
 599  * master and representors will share this context, if there is single
 600  * port dedicated device, the context will be used by only given
 601  * port due to unification.
 602  *
 603  * Routine first searches the context for the specified device name,
 604  * if found the shared context assumed and reference counter is incremented.
 605  * If no context found the new one is created and initialized with specified
 606  * device context and parameters.
 607  *
 608  * @param[in] spawn
 609  *   Pointer to the device attributes (name, port, etc).
 610  * @param[in] config
 611  *   Pointer to device configuration structure.
 612  *
 613  * @return
 614  *   Pointer to mlx5_dev_ctx_shared object on success,
 615  *   otherwise NULL and rte_errno is set.
 616  */
 617 struct mlx5_dev_ctx_shared *
 618 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
 619                            const struct mlx5_dev_config *config)
 620 {
 621         struct mlx5_dev_ctx_shared *sh;
 622         int err = 0;
 623         uint32_t i;
 624         struct mlx5_devx_tis_attr tis_attr = { 0 };
 625
 626         MLX5_ASSERT(spawn);
 627         /* Secondary process should not create the shared context. */
 628         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 629         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
 630         /* Search for IB context by device name. */
 631         LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
 632                 if (!strcmp(sh->ibdev_name,
 633                         mlx5_os_get_dev_device_name(spawn->phys_dev))) {
 634                         sh->refcnt++;
 635                         goto exit;
 636                 }
 637         }
 638         /* No device found, we have to create new shared context. */
 639         MLX5_ASSERT(spawn->max_port);
 640         sh = rte_zmalloc("ethdev shared ib context",
 641                          sizeof(struct mlx5_dev_ctx_shared) +
 642                          spawn->max_port *
 643                          sizeof(struct mlx5_dev_shared_port),
 644                          RTE_CACHE_LINE_SIZE);
 645         if (!sh) {
 646                 DRV_LOG(ERR, "shared context allocation failure");
 647                 rte_errno  = ENOMEM;
 648                 goto exit;
 649         }
 650         err = mlx5_os_open_device(spawn, config, sh);
 651         if (!sh->ctx)
 652                 goto error;
 653         err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
 654         if (err) {
 655                 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
 656                 goto error;
 657         }
 658         sh->refcnt = 1;
 659         sh->max_port = spawn->max_port;
 660         strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
 661                 sizeof(sh->ibdev_name) - 1);
 662         strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
 663                 sizeof(sh->ibdev_path) - 1);
 664         /*
 665          * Setting port_id to max unallowed value means
 666          * there is no interrupt subhandler installed for
 667          * the given port index i.
 668          */
 669         for (i = 0; i < sh->max_port; i++) {
 670                 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
 671                 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
 672         }
 673         sh->pd = mlx5_glue->alloc_pd(sh->ctx);
 674         if (sh->pd == NULL) {
 675                 DRV_LOG(ERR, "PD allocation failure");
 676                 err = ENOMEM;
 677                 goto error;
 678         }
 679         if (sh->devx) {
 680                 err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
 681                 if (err) {
 682                         DRV_LOG(ERR, "Fail to extract pdn from PD");
 683                         goto error;
 684                 }
 685                 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
 686                 if (!sh->td) {
 687                         DRV_LOG(ERR, "TD allocation failure");
 688                         err = ENOMEM;
 689                         goto error;
 690                 }
 691                 tis_attr.transport_domain = sh->td->id;
 692                 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
 693                 if (!sh->tis) {
 694                         DRV_LOG(ERR, "TIS allocation failure");
 695                         err = ENOMEM;
 696                         goto error;
 697                 }
 698         }
 699         sh->flow_id_pool = mlx5_flow_id_pool_alloc
 700                                         ((1 << HAIRPIN_FLOW_ID_BITS) - 1);
 701         if (!sh->flow_id_pool) {
 702                 DRV_LOG(ERR, "can't create flow id pool");
 703                 err = ENOMEM;
 704                 goto error;
 705         }
 706         /*
 707          * Once the device is added to the list of memory event
 708          * callback, its global MR cache table cannot be expanded
 709          * on the fly because of deadlock. If it overflows, lookup
 710          * should be done by searching MR list linearly, which is slow.
 711          *
 712          * At this point the device is not added to the memory
 713          * event list yet, context is just being created.
 714          */
 715         err = mlx5_mr_btree_init(&sh->share_cache.cache,
 716                                  MLX5_MR_BTREE_CACHE_N * 2,
 717                                  spawn->pci_dev->device.numa_node);
 718         if (err) {
 719                 err = rte_errno;
 720                 goto error;
 721         }
 722         mlx5_os_set_reg_mr_cb(&sh->share_cache.reg_mr_cb,
 723                               &sh->share_cache.dereg_mr_cb);
 724         mlx5_os_dev_shared_handler_install(sh);
 725         sh->cnt_id_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_DWORD);
 726         if (!sh->cnt_id_tbl) {
 727                 err = rte_errno;
 728                 goto error;
 729         }
 730         mlx5_flow_aging_init(sh);
 731         mlx5_flow_counters_mng_init(sh);
 732         mlx5_flow_ipool_create(sh, config);
 733         /* Add device to memory callback list. */
 734         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
 735         LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
 736                          sh, mem_event_cb);
 737         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
 738         /* Add context to the global device list. */
 739         LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
 740 exit:
 741         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
 742         return sh;
 743 error:
 744         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
 745         MLX5_ASSERT(sh);
 746         if (sh->cnt_id_tbl) {
 747                 mlx5_l3t_destroy(sh->cnt_id_tbl);
 748                 sh->cnt_id_tbl = NULL;
 749         }
 750         if (sh->tis)
 751                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
 752         if (sh->td)
 753                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
 754         if (sh->pd)
 755                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
 756         if (sh->ctx)
 757                 claim_zero(mlx5_glue->close_device(sh->ctx));
 758         if (sh->flow_id_pool)
 759                 mlx5_flow_id_pool_release(sh->flow_id_pool);
 760         rte_free(sh);
 761         MLX5_ASSERT(err > 0);
 762         rte_errno = err;
 763         return NULL;
 764 }
 765
 766 /**
 767  * Free shared IB device context. Decrement counter and if zero free
 768  * all allocated resources and close handles.
 769  *
 770  * @param[in] sh
 771  *   Pointer to mlx5_dev_ctx_shared object to free
 772  */
 773 void
 774 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
 775 {
 776         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
 777 #ifdef RTE_LIBRTE_MLX5_DEBUG
 778         /* Check the object presence in the list. */
 779         struct mlx5_dev_ctx_shared *lctx;
 780
 781         LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
 782                 if (lctx == sh)
 783                         break;
 784         MLX5_ASSERT(lctx);
 785         if (lctx != sh) {
 786                 DRV_LOG(ERR, "Freeing non-existing shared IB context");
 787                 goto exit;
 788         }
 789 #endif
 790         MLX5_ASSERT(sh);
 791         MLX5_ASSERT(sh->refcnt);
 792         /* Secondary process should not free the shared context. */
 793         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 794         if (--sh->refcnt)
 795                 goto exit;
 796         /* Remove from memory callback device list. */
 797         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
 798         LIST_REMOVE(sh, mem_event_cb);
 799         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
 800         /* Release created Memory Regions. */
 801         mlx5_mr_release_cache(&sh->share_cache);
 802         /* Remove context from the global device list. */
 803         LIST_REMOVE(sh, next);
 804         /*
 805          *  Ensure there is no async event handler installed.
 806          *  Only primary process handles async device events.
 807          **/
 808         mlx5_flow_counters_mng_close(sh);
 809         mlx5_flow_ipool_destroy(sh);
 810         mlx5_os_dev_shared_handler_uninstall(sh);
 811         if (sh->cnt_id_tbl) {
 812                 mlx5_l3t_destroy(sh->cnt_id_tbl);
 813                 sh->cnt_id_tbl = NULL;
 814         }
 815         if (sh->pd)
 816                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
 817         if (sh->tis)
 818                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
 819         if (sh->td)
 820                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
 821         if (sh->ctx)
 822                 claim_zero(mlx5_glue->close_device(sh->ctx));
 823         if (sh->flow_id_pool)
 824                 mlx5_flow_id_pool_release(sh->flow_id_pool);
 825         rte_free(sh);
 826 exit:
 827         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
 828 }
 829
 830 /**
 831  * Destroy table hash list and all the root entries per domain.
 832  *
 833  * @param[in] priv
 834  *   Pointer to the private device data structure.
 835  */
 836 void
 837 mlx5_free_table_hash_list(struct mlx5_priv *priv)
 838 {
 839         struct mlx5_dev_ctx_shared *sh = priv->sh;
 840         struct mlx5_flow_tbl_data_entry *tbl_data;
 841         union mlx5_flow_tbl_key table_key = {
 842                 {
 843                         .table_id = 0,
 844                         .reserved = 0,
 845                         .domain = 0,
 846                         .direction = 0,
 847                 }
 848         };
 849         struct mlx5_hlist_entry *pos;
 850
 851         if (!sh->flow_tbls)
 852                 return;
 853         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 854         if (pos) {
 855                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 856                                         entry);
 857                 MLX5_ASSERT(tbl_data);
 858                 mlx5_hlist_remove(sh->flow_tbls, pos);
 859                 rte_free(tbl_data);
 860         }
 861         table_key.direction = 1;
 862         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 863         if (pos) {
 864                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 865                                         entry);
 866                 MLX5_ASSERT(tbl_data);
 867                 mlx5_hlist_remove(sh->flow_tbls, pos);
 868                 rte_free(tbl_data);
 869         }
 870         table_key.direction = 0;
 871         table_key.domain = 1;
 872         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 873         if (pos) {
 874                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 875                                         entry);
 876                 MLX5_ASSERT(tbl_data);
 877                 mlx5_hlist_remove(sh->flow_tbls, pos);
 878                 rte_free(tbl_data);
 879         }
 880         mlx5_hlist_destroy(sh->flow_tbls, NULL, NULL);
 881 }
 882
 883 /**
 884  * Initialize flow table hash list and create the root tables entry
 885  * for each domain.
 886  *
 887  * @param[in] priv
 888  *   Pointer to the private device data structure.
 889  *
 890  * @return
 891  *   Zero on success, positive error code otherwise.
 892  */
 893 int
 894 mlx5_alloc_table_hash_list(struct mlx5_priv *priv)
 895 {
 896         struct mlx5_dev_ctx_shared *sh = priv->sh;
 897         char s[MLX5_HLIST_NAMESIZE];
 898         int err = 0;
 899
 900         MLX5_ASSERT(sh);
 901         snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
 902         sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE);
 903         if (!sh->flow_tbls) {
 904                 DRV_LOG(ERR, "flow tables with hash creation failed.");
 905                 err = ENOMEM;
 906                 return err;
 907         }
 908 #ifndef HAVE_MLX5DV_DR
 909         /*
 910          * In case we have not DR support, the zero tables should be created
 911          * because DV expect to see them even if they cannot be created by
 912          * RDMA-CORE.
 913          */
 914         union mlx5_flow_tbl_key table_key = {
 915                 {
 916                         .table_id = 0,
 917                         .reserved = 0,
 918                         .domain = 0,
 919                         .direction = 0,
 920                 }
 921         };
 922         struct mlx5_flow_tbl_data_entry *tbl_data = rte_zmalloc(NULL,
 923                                                           sizeof(*tbl_data), 0);
 924
 925         if (!tbl_data) {
 926                 err = ENOMEM;
 927                 goto error;
 928         }
 929         tbl_data->entry.key = table_key.v64;
 930         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
 931         if (err)
 932                 goto error;
 933         rte_atomic32_init(&tbl_data->tbl.refcnt);
 934         rte_atomic32_inc(&tbl_data->tbl.refcnt);
 935         table_key.direction = 1;
 936         tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
 937         if (!tbl_data) {
 938                 err = ENOMEM;
 939                 goto error;
 940         }
 941         tbl_data->entry.key = table_key.v64;
 942         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
 943         if (err)
 944                 goto error;
 945         rte_atomic32_init(&tbl_data->tbl.refcnt);
 946         rte_atomic32_inc(&tbl_data->tbl.refcnt);
 947         table_key.direction = 0;
 948         table_key.domain = 1;
 949         tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
 950         if (!tbl_data) {
 951                 err = ENOMEM;
 952                 goto error;
 953         }
 954         tbl_data->entry.key = table_key.v64;
 955         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
 956         if (err)
 957                 goto error;
 958         rte_atomic32_init(&tbl_data->tbl.refcnt);
 959         rte_atomic32_inc(&tbl_data->tbl.refcnt);
 960         return err;
 961 error:
 962         mlx5_free_table_hash_list(priv);
 963 #endif /* HAVE_MLX5DV_DR */
 964         return err;
 965 }
 966
 967 /**
 968  * Initialize shared data between primary and secondary process.
 969  *
 970  * A memzone is reserved by primary process and secondary processes attach to
 971  * the memzone.
 972  *
 973  * @return
 974  *   0 on success, a negative errno value otherwise and rte_errno is set.
 975  */
 976 static int
 977 mlx5_init_shared_data(void)
 978 {
 979         const struct rte_memzone *mz;
 980         int ret = 0;
 981
 982         rte_spinlock_lock(&mlx5_shared_data_lock);
 983         if (mlx5_shared_data == NULL) {
 984                 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
 985                         /* Allocate shared memory. */
 986                         mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
 987                                                  sizeof(*mlx5_shared_data),
 988                                                  SOCKET_ID_ANY, 0);
 989                         if (mz == NULL) {
 990                                 DRV_LOG(ERR,
 991                                         "Cannot allocate mlx5 shared data");
 992                                 ret = -rte_errno;
 993                                 goto error;
 994                         }
 995                         mlx5_shared_data = mz->addr;
 996                         memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data));
 997                         rte_spinlock_init(&mlx5_shared_data->lock);
 998                 } else {
 999                         /* Lookup allocated shared memory. */
1000                         mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA);
1001                         if (mz == NULL) {
1002                                 DRV_LOG(ERR,
1003                                         "Cannot attach mlx5 shared data");
1004                                 ret = -rte_errno;
1005                                 goto error;
1006                         }
1007                         mlx5_shared_data = mz->addr;
1008                         memset(&mlx5_local_data, 0, sizeof(mlx5_local_data));
1009                 }
1010         }
1011 error:
1012         rte_spinlock_unlock(&mlx5_shared_data_lock);
1013         return ret;
1014 }
1015
1016 /**
1017  * Retrieve integer value from environment variable.
1018  *
1019  * @param[in] name
1020  *   Environment variable name.
1021  *
1022  * @return
1023  *   Integer value, 0 if the variable is not set.
1024  */
1025 int
1026 mlx5_getenv_int(const char *name)
1027 {
1028         const char *val = getenv(name);
1029
1030         if (val == NULL)
1031                 return 0;
1032         return atoi(val);
1033 }
1034
1035 /**
1036  * DPDK callback to add udp tunnel port
1037  *
1038  * @param[in] dev
1039  *   A pointer to eth_dev
1040  * @param[in] udp_tunnel
1041  *   A pointer to udp tunnel
1042  *
1043  * @return
1044  *   0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1045  */
1046 int
1047 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1048                          struct rte_eth_udp_tunnel *udp_tunnel)
1049 {
1050         MLX5_ASSERT(udp_tunnel != NULL);
1051         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1052             udp_tunnel->udp_port == 4789)
1053                 return 0;
1054         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1055             udp_tunnel->udp_port == 4790)
1056                 return 0;
1057         return -ENOTSUP;
1058 }
1059
1060 /**
1061  * Initialize process private data structure.
1062  *
1063  * @param dev
1064  *   Pointer to Ethernet device structure.
1065  *
1066  * @return
1067  *   0 on success, a negative errno value otherwise and rte_errno is set.
1068  */
1069 int
1070 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1071 {
1072         struct mlx5_priv *priv = dev->data->dev_private;
1073         struct mlx5_proc_priv *ppriv;
1074         size_t ppriv_size;
1075
1076         /*
1077          * UAR register table follows the process private structure. BlueFlame
1078          * registers for Tx queues are stored in the table.
1079          */
1080         ppriv_size =
1081                 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1082         ppriv = rte_malloc_socket("mlx5_proc_priv", ppriv_size,
1083                                   RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1084         if (!ppriv) {
1085                 rte_errno = ENOMEM;
1086                 return -rte_errno;
1087         }
1088         ppriv->uar_table_sz = ppriv_size;
1089         dev->process_private = ppriv;
1090         return 0;
1091 }
1092
1093 /**
1094  * Un-initialize process private data structure.
1095  *
1096  * @param dev
1097  *   Pointer to Ethernet device structure.
1098  */
1099 static void
1100 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1101 {
1102         if (!dev->process_private)
1103                 return;
1104         rte_free(dev->process_private);
1105         dev->process_private = NULL;
1106 }
1107
1108 /**
1109  * DPDK callback to close the device.
1110  *
1111  * Destroy all queues and objects, free memory.
1112  *
1113  * @param dev
1114  *   Pointer to Ethernet device structure.
1115  */
1116 void
1117 mlx5_dev_close(struct rte_eth_dev *dev)
1118 {
1119         struct mlx5_priv *priv = dev->data->dev_private;
1120         unsigned int i;
1121         int ret;
1122
1123         if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1124                 /* Check if process_private released. */
1125                 if (!dev->process_private)
1126                         return;
1127                 mlx5_tx_uar_uninit_secondary(dev);
1128                 mlx5_proc_priv_uninit(dev);
1129                 rte_eth_dev_release_port(dev);
1130                 return;
1131         }
1132         if (!priv->sh)
1133                 return;
1134         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1135                 dev->data->port_id,
1136                 ((priv->sh->ctx != NULL) ?
1137                 mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
1138         /*
1139          * If default mreg copy action is removed at the stop stage,
1140          * the search will return none and nothing will be done anymore.
1141          */
1142         mlx5_flow_stop_default(dev);
1143         mlx5_traffic_disable(dev);
1144         /*
1145          * If all the flows are already flushed in the device stop stage,
1146          * then this will return directly without any action.
1147          */
1148         mlx5_flow_list_flush(dev, &priv->flows, true);
1149         mlx5_flow_meter_flush(dev, NULL);
1150         /* Free the intermediate buffers for flow creation. */
1151         mlx5_flow_free_intermediate(dev);
1152         /* Prevent crashes when queues are still in use. */
1153         dev->rx_pkt_burst = removed_rx_burst;
1154         dev->tx_pkt_burst = removed_tx_burst;
1155         rte_wmb();
1156         /* Disable datapath on secondary process. */
1157         mlx5_mp_req_stop_rxtx(dev);
1158         if (priv->rxqs != NULL) {
1159                 /* XXX race condition if mlx5_rx_burst() is still running. */
1160                 usleep(1000);
1161                 for (i = 0; (i != priv->rxqs_n); ++i)
1162                         mlx5_rxq_release(dev, i);
1163                 priv->rxqs_n = 0;
1164                 priv->rxqs = NULL;
1165         }
1166         if (priv->txqs != NULL) {
1167                 /* XXX race condition if mlx5_tx_burst() is still running. */
1168                 usleep(1000);
1169                 for (i = 0; (i != priv->txqs_n); ++i)
1170                         mlx5_txq_release(dev, i);
1171                 priv->txqs_n = 0;
1172                 priv->txqs = NULL;
1173         }
1174         mlx5_proc_priv_uninit(dev);
1175         if (priv->mreg_cp_tbl)
1176                 mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
1177         mlx5_mprq_free_mp(dev);
1178         mlx5_os_free_shared_dr(priv);
1179         if (priv->rss_conf.rss_key != NULL)
1180                 rte_free(priv->rss_conf.rss_key);
1181         if (priv->reta_idx != NULL)
1182                 rte_free(priv->reta_idx);
1183         if (priv->config.vf)
1184                 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev),
1185                                        dev->data->mac_addrs,
1186                                        MLX5_MAX_MAC_ADDRESSES, priv->mac_own);
1187         if (priv->nl_socket_route >= 0)
1188                 close(priv->nl_socket_route);
1189         if (priv->nl_socket_rdma >= 0)
1190                 close(priv->nl_socket_rdma);
1191         if (priv->vmwa_context)
1192                 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1193         ret = mlx5_hrxq_verify(dev);
1194         if (ret)
1195                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1196                         dev->data->port_id);
1197         ret = mlx5_ind_table_obj_verify(dev);
1198         if (ret)
1199                 DRV_LOG(WARNING, "port %u some indirection table still remain",
1200                         dev->data->port_id);
1201         ret = mlx5_rxq_obj_verify(dev);
1202         if (ret)
1203                 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1204                         dev->data->port_id);
1205         ret = mlx5_rxq_verify(dev);
1206         if (ret)
1207                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1208                         dev->data->port_id);
1209         ret = mlx5_txq_obj_verify(dev);
1210         if (ret)
1211                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1212                         dev->data->port_id);
1213         ret = mlx5_txq_verify(dev);
1214         if (ret)
1215                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1216                         dev->data->port_id);
1217         ret = mlx5_flow_verify(dev);
1218         if (ret)
1219                 DRV_LOG(WARNING, "port %u some flows still remain",
1220                         dev->data->port_id);
1221         /*
1222          * Free the shared context in last turn, because the cleanup
1223          * routines above may use some shared fields, like
1224          * mlx5_nl_mac_addr_flush() uses ibdev_path for retrieveing
1225          * ifindex if Netlink fails.
1226          */
1227         mlx5_free_shared_dev_ctx(priv->sh);
1228         if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1229                 unsigned int c = 0;
1230                 uint16_t port_id;
1231
1232                 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1233                         struct mlx5_priv *opriv =
1234                                 rte_eth_devices[port_id].data->dev_private;
1235
1236                         if (!opriv ||
1237                             opriv->domain_id != priv->domain_id ||
1238                             &rte_eth_devices[port_id] == dev)
1239                                 continue;
1240                         ++c;
1241                         break;
1242                 }
1243                 if (!c)
1244                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1245         }
1246         memset(priv, 0, sizeof(*priv));
1247         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1248         /*
1249          * Reset mac_addrs to NULL such that it is not freed as part of
1250          * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1251          * it is freed when dev_private is freed.
1252          */
1253         dev->data->mac_addrs = NULL;
1254 }
1255
1256 /**
1257  * Verify and store value for device argument.
1258  *
1259  * @param[in] key
1260  *   Key argument to verify.
1261  * @param[in] val
1262  *   Value associated with key.
1263  * @param opaque
1264  *   User data.
1265  *
1266  * @return
1267  *   0 on success, a negative errno value otherwise and rte_errno is set.
1268  */
1269 static int
1270 mlx5_args_check(const char *key, const char *val, void *opaque)
1271 {
1272         struct mlx5_dev_config *config = opaque;
1273         unsigned long tmp;
1274
1275         /* No-op, port representors are processed in mlx5_dev_spawn(). */
1276         if (!strcmp(MLX5_REPRESENTOR, key))
1277                 return 0;
1278         errno = 0;
1279         tmp = strtoul(val, NULL, 0);
1280         if (errno) {
1281                 rte_errno = errno;
1282                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1283                 return -rte_errno;
1284         }
1285         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1286                 config->cqe_comp = !!tmp;
1287         } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
1288                 config->cqe_pad = !!tmp;
1289         } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1290                 config->hw_padding = !!tmp;
1291         } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1292                 config->mprq.enabled = !!tmp;
1293         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1294                 config->mprq.stride_num_n = tmp;
1295         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1296                 config->mprq.stride_size_n = tmp;
1297         } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1298                 config->mprq.max_memcpy_len = tmp;
1299         } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1300                 config->mprq.min_rxqs_num = tmp;
1301         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1302                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1303                                  " converted to txq_inline_max", key);
1304                 config->txq_inline_max = tmp;
1305         } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1306                 config->txq_inline_max = tmp;
1307         } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1308                 config->txq_inline_min = tmp;
1309         } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1310                 config->txq_inline_mpw = tmp;
1311         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1312                 config->txqs_inline = tmp;
1313         } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1314                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1315         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1316                 config->mps = !!tmp;
1317         } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1318                 if (tmp != MLX5_TXDB_CACHED &&
1319                     tmp != MLX5_TXDB_NCACHED &&
1320                     tmp != MLX5_TXDB_HEURISTIC) {
1321                         DRV_LOG(ERR, "invalid Tx doorbell "
1322                                      "mapping parameter");
1323                         rte_errno = EINVAL;
1324                         return -rte_errno;
1325                 }
1326                 config->dbnc = tmp;
1327         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1328                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1329         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1330                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1331                                  " converted to txq_inline_mpw", key);
1332                 config->txq_inline_mpw = tmp;
1333         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1334                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1335         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1336                 config->rx_vec_en = !!tmp;
1337         } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1338                 config->l3_vxlan_en = !!tmp;
1339         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1340                 config->vf_nl_en = !!tmp;
1341         } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1342                 config->dv_esw_en = !!tmp;
1343         } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1344                 config->dv_flow_en = !!tmp;
1345         } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1346                 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1347                     tmp != MLX5_XMETA_MODE_META16 &&
1348                     tmp != MLX5_XMETA_MODE_META32) {
1349                         DRV_LOG(ERR, "invalid extensive "
1350                                      "metadata parameter");
1351                         rte_errno = EINVAL;
1352                         return -rte_errno;
1353                 }
1354                 config->dv_xmeta_en = tmp;
1355         } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1356                 config->mr_ext_memseg_en = !!tmp;
1357         } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1358                 config->max_dump_files_num = tmp;
1359         } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1360                 config->lro.timeout = tmp;
1361         } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1362                 DRV_LOG(DEBUG, "class argument is %s.", val);
1363         } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1364                 config->log_hp_size = tmp;
1365         } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1366                 if (tmp != MLX5_RCM_NONE &&
1367                     tmp != MLX5_RCM_LIGHT &&
1368                     tmp != MLX5_RCM_AGGR) {
1369                         DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1370                         rte_errno = EINVAL;
1371                         return -rte_errno;
1372                 }
1373                 config->reclaim_mode = tmp;
1374         } else {
1375                 DRV_LOG(WARNING, "%s: unknown parameter", key);
1376                 rte_errno = EINVAL;
1377                 return -rte_errno;
1378         }
1379         return 0;
1380 }
1381
1382 /**
1383  * Parse device parameters.
1384  *
1385  * @param config
1386  *   Pointer to device configuration structure.
1387  * @param devargs
1388  *   Device arguments structure.
1389  *
1390  * @return
1391  *   0 on success, a negative errno value otherwise and rte_errno is set.
1392  */
1393 int
1394 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1395 {
1396         const char **params = (const char *[]){
1397                 MLX5_RXQ_CQE_COMP_EN,
1398                 MLX5_RXQ_CQE_PAD_EN,
1399                 MLX5_RXQ_PKT_PAD_EN,
1400                 MLX5_RX_MPRQ_EN,
1401                 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1402                 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1403                 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1404                 MLX5_RXQS_MIN_MPRQ,
1405                 MLX5_TXQ_INLINE,
1406                 MLX5_TXQ_INLINE_MIN,
1407                 MLX5_TXQ_INLINE_MAX,
1408                 MLX5_TXQ_INLINE_MPW,
1409                 MLX5_TXQS_MIN_INLINE,
1410                 MLX5_TXQS_MAX_VEC,
1411                 MLX5_TXQ_MPW_EN,
1412                 MLX5_TXQ_MPW_HDR_DSEG_EN,
1413                 MLX5_TXQ_MAX_INLINE_LEN,
1414                 MLX5_TX_DB_NC,
1415                 MLX5_TX_VEC_EN,
1416                 MLX5_RX_VEC_EN,
1417                 MLX5_L3_VXLAN_EN,
1418                 MLX5_VF_NL_EN,
1419                 MLX5_DV_ESW_EN,
1420                 MLX5_DV_FLOW_EN,
1421                 MLX5_DV_XMETA_EN,
1422                 MLX5_MR_EXT_MEMSEG_EN,
1423                 MLX5_REPRESENTOR,
1424                 MLX5_MAX_DUMP_FILES_NUM,
1425                 MLX5_LRO_TIMEOUT_USEC,
1426                 MLX5_CLASS_ARG_NAME,
1427                 MLX5_HP_BUF_SIZE,
1428                 MLX5_RECLAIM_MEM,
1429                 NULL,
1430         };
1431         struct rte_kvargs *kvlist;
1432         int ret = 0;
1433         int i;
1434
1435         if (devargs == NULL)
1436                 return 0;
1437         /* Following UGLY cast is done to pass checkpatch. */
1438         kvlist = rte_kvargs_parse(devargs->args, params);
1439         if (kvlist == NULL) {
1440                 rte_errno = EINVAL;
1441                 return -rte_errno;
1442         }
1443         /* Process parameters. */
1444         for (i = 0; (params[i] != NULL); ++i) {
1445                 if (rte_kvargs_count(kvlist, params[i])) {
1446                         ret = rte_kvargs_process(kvlist, params[i],
1447                                                  mlx5_args_check, config);
1448                         if (ret) {
1449                                 rte_errno = EINVAL;
1450                                 rte_kvargs_free(kvlist);
1451                                 return -rte_errno;
1452                         }
1453                 }
1454         }
1455         rte_kvargs_free(kvlist);
1456         return 0;
1457 }
1458
1459 /**
1460  * PMD global initialization.
1461  *
1462  * Independent from individual device, this function initializes global
1463  * per-PMD data structures distinguishing primary and secondary processes.
1464  * Hence, each initialization is called once per a process.
1465  *
1466  * @return
1467  *   0 on success, a negative errno value otherwise and rte_errno is set.
1468  */
1469 int
1470 mlx5_init_once(void)
1471 {
1472         struct mlx5_shared_data *sd;
1473         struct mlx5_local_data *ld = &mlx5_local_data;
1474         int ret = 0;
1475
1476         if (mlx5_init_shared_data())
1477                 return -rte_errno;
1478         sd = mlx5_shared_data;
1479         MLX5_ASSERT(sd);
1480         rte_spinlock_lock(&sd->lock);
1481         switch (rte_eal_process_type()) {
1482         case RTE_PROC_PRIMARY:
1483                 if (sd->init_done)
1484                         break;
1485                 LIST_INIT(&sd->mem_event_cb_list);
1486                 rte_rwlock_init(&sd->mem_event_rwlock);
1487                 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
1488                                                 mlx5_mr_mem_event_cb, NULL);
1489                 ret = mlx5_mp_init_primary(MLX5_MP_NAME,
1490                                            mlx5_mp_primary_handle);
1491                 if (ret)
1492                         goto out;
1493                 sd->init_done = true;
1494                 break;
1495         case RTE_PROC_SECONDARY:
1496                 if (ld->init_done)
1497                         break;
1498                 ret = mlx5_mp_init_secondary(MLX5_MP_NAME,
1499                                              mlx5_mp_secondary_handle);
1500                 if (ret)
1501                         goto out;
1502                 ++sd->secondary_cnt;
1503                 ld->init_done = true;
1504                 break;
1505         default:
1506                 break;
1507         }
1508 out:
1509         rte_spinlock_unlock(&sd->lock);
1510         return ret;
1511 }
1512
1513 /**
1514  * Configures the minimal amount of data to inline into WQE
1515  * while sending packets.
1516  *
1517  * - the txq_inline_min has the maximal priority, if this
1518  *   key is specified in devargs
1519  * - if DevX is enabled the inline mode is queried from the
1520  *   device (HCA attributes and NIC vport context if needed).
1521  * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1522  *   and none (0 bytes) for other NICs
1523  *
1524  * @param spawn
1525  *   Verbs device parameters (name, port, switch_info) to spawn.
1526  * @param config
1527  *   Device configuration parameters.
1528  */
1529 void
1530 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1531                     struct mlx5_dev_config *config)
1532 {
1533         if (config->txq_inline_min != MLX5_ARG_UNSET) {
1534                 /* Application defines size of inlined data explicitly. */
1535                 switch (spawn->pci_dev->id.device_id) {
1536                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1537                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1538                         if (config->txq_inline_min <
1539                                        (int)MLX5_INLINE_HSIZE_L2) {
1540                                 DRV_LOG(DEBUG,
1541                                         "txq_inline_mix aligned to minimal"
1542                                         " ConnectX-4 required value %d",
1543                                         (int)MLX5_INLINE_HSIZE_L2);
1544                                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1545                         }
1546                         break;
1547                 }
1548                 goto exit;
1549         }
1550         if (config->hca_attr.eth_net_offloads) {
1551                 /* We have DevX enabled, inline mode queried successfully. */
1552                 switch (config->hca_attr.wqe_inline_mode) {
1553                 case MLX5_CAP_INLINE_MODE_L2:
1554                         /* outer L2 header must be inlined. */
1555                         config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1556                         goto exit;
1557                 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1558                         /* No inline data are required by NIC. */
1559                         config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1560                         config->hw_vlan_insert =
1561                                 config->hca_attr.wqe_vlan_insert;
1562                         DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1563                         goto exit;
1564                 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1565                         /* inline mode is defined by NIC vport context. */
1566                         if (!config->hca_attr.eth_virt)
1567                                 break;
1568                         switch (config->hca_attr.vport_inline_mode) {
1569                         case MLX5_INLINE_MODE_NONE:
1570                                 config->txq_inline_min =
1571                                         MLX5_INLINE_HSIZE_NONE;
1572                                 goto exit;
1573                         case MLX5_INLINE_MODE_L2:
1574                                 config->txq_inline_min =
1575                                         MLX5_INLINE_HSIZE_L2;
1576                                 goto exit;
1577                         case MLX5_INLINE_MODE_IP:
1578                                 config->txq_inline_min =
1579                                         MLX5_INLINE_HSIZE_L3;
1580                                 goto exit;
1581                         case MLX5_INLINE_MODE_TCP_UDP:
1582                                 config->txq_inline_min =
1583                                         MLX5_INLINE_HSIZE_L4;
1584                                 goto exit;
1585                         case MLX5_INLINE_MODE_INNER_L2:
1586                                 config->txq_inline_min =
1587                                         MLX5_INLINE_HSIZE_INNER_L2;
1588                                 goto exit;
1589                         case MLX5_INLINE_MODE_INNER_IP:
1590                                 config->txq_inline_min =
1591                                         MLX5_INLINE_HSIZE_INNER_L3;
1592                                 goto exit;
1593                         case MLX5_INLINE_MODE_INNER_TCP_UDP:
1594                                 config->txq_inline_min =
1595                                         MLX5_INLINE_HSIZE_INNER_L4;
1596                                 goto exit;
1597                         }
1598                 }
1599         }
1600         /*
1601          * We get here if we are unable to deduce
1602          * inline data size with DevX. Try PCI ID
1603          * to determine old NICs.
1604          */
1605         switch (spawn->pci_dev->id.device_id) {
1606         case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1607         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1608         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
1609         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1610                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1611                 config->hw_vlan_insert = 0;
1612                 break;
1613         case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
1614         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1615         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
1616         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1617                 /*
1618                  * These NICs support VLAN insertion from WQE and
1619                  * report the wqe_vlan_insert flag. But there is the bug
1620                  * and PFC control may be broken, so disable feature.
1621                  */
1622                 config->hw_vlan_insert = 0;
1623                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1624                 break;
1625         default:
1626                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1627                 break;
1628         }
1629 exit:
1630         DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
1631 }
1632
1633 /**
1634  * Configures the metadata mask fields in the shared context.
1635  *
1636  * @param [in] dev
1637  *   Pointer to Ethernet device.
1638  */
1639 void
1640 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
1641 {
1642         struct mlx5_priv *priv = dev->data->dev_private;
1643         struct mlx5_dev_ctx_shared *sh = priv->sh;
1644         uint32_t meta, mark, reg_c0;
1645
1646         reg_c0 = ~priv->vport_meta_mask;
1647         switch (priv->config.dv_xmeta_en) {
1648         case MLX5_XMETA_MODE_LEGACY:
1649                 meta = UINT32_MAX;
1650                 mark = MLX5_FLOW_MARK_MASK;
1651                 break;
1652         case MLX5_XMETA_MODE_META16:
1653                 meta = reg_c0 >> rte_bsf32(reg_c0);
1654                 mark = MLX5_FLOW_MARK_MASK;
1655                 break;
1656         case MLX5_XMETA_MODE_META32:
1657                 meta = UINT32_MAX;
1658                 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
1659                 break;
1660         default:
1661                 meta = 0;
1662                 mark = 0;
1663                 MLX5_ASSERT(false);
1664                 break;
1665         }
1666         if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
1667                 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
1668                                  sh->dv_mark_mask, mark);
1669         else
1670                 sh->dv_mark_mask = mark;
1671         if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
1672                 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
1673                                  sh->dv_meta_mask, meta);
1674         else
1675                 sh->dv_meta_mask = meta;
1676         if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
1677                 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
1678                                  sh->dv_meta_mask, reg_c0);
1679         else
1680                 sh->dv_regc0_mask = reg_c0;
1681         DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
1682         DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
1683         DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
1684         DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
1685 }
1686
1687 int
1688 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
1689 {
1690         static const char *const dynf_names[] = {
1691                 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
1692                 RTE_MBUF_DYNFLAG_METADATA_NAME
1693         };
1694         unsigned int i;
1695
1696         if (n < RTE_DIM(dynf_names))
1697                 return -ENOMEM;
1698         for (i = 0; i < RTE_DIM(dynf_names); i++) {
1699                 if (names[i] == NULL)
1700                         return -EINVAL;
1701                 strcpy(names[i], dynf_names[i]);
1702         }
1703         return RTE_DIM(dynf_names);
1704 }
1705
1706 /**
1707  * Comparison callback to sort device data.
1708  *
1709  * This is meant to be used with qsort().
1710  *
1711  * @param a[in]
1712  *   Pointer to pointer to first data object.
1713  * @param b[in]
1714  *   Pointer to pointer to second data object.
1715  *
1716  * @return
1717  *   0 if both objects are equal, less than 0 if the first argument is less
1718  *   than the second, greater than 0 otherwise.
1719  */
1720 int
1721 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
1722                               struct mlx5_dev_config *config)
1723 {
1724         struct mlx5_dev_ctx_shared *sh = priv->sh;
1725         struct mlx5_dev_config *sh_conf = NULL;
1726         uint16_t port_id;
1727
1728         MLX5_ASSERT(sh);
1729         /* Nothing to compare for the single/first device. */
1730         if (sh->refcnt == 1)
1731                 return 0;
1732         /* Find the device with shared context. */
1733         MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1734                 struct mlx5_priv *opriv =
1735                         rte_eth_devices[port_id].data->dev_private;
1736
1737                 if (opriv && opriv != priv && opriv->sh == sh) {
1738                         sh_conf = &opriv->config;
1739                         break;
1740                 }
1741         }
1742         if (!sh_conf)
1743                 return 0;
1744         if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
1745                 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
1746                              " for shared %s context", sh->ibdev_name);
1747                 rte_errno = EINVAL;
1748                 return rte_errno;
1749         }
1750         if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
1751                 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
1752                              " for shared %s context", sh->ibdev_name);
1753                 rte_errno = EINVAL;
1754                 return rte_errno;
1755         }
1756         return 0;
1757 }
1758
1759 /**
1760  * Look for the ethernet device belonging to mlx5 driver.
1761  *
1762  * @param[in] port_id
1763  *   port_id to start looking for device.
1764  * @param[in] pci_dev
1765  *   Pointer to the hint PCI device. When device is being probed
1766  *   the its siblings (master and preceding representors might
1767  *   not have assigned driver yet (because the mlx5_os_pci_probe()
1768  *   is not completed yet, for this case match on hint PCI
1769  *   device may be used to detect sibling device.
1770  *
1771  * @return
1772  *   port_id of found device, RTE_MAX_ETHPORT if not found.
1773  */
1774 uint16_t
1775 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
1776 {
1777         while (port_id < RTE_MAX_ETHPORTS) {
1778                 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
1779
1780                 if (dev->state != RTE_ETH_DEV_UNUSED &&
1781                     dev->device &&
1782                     (dev->device == &pci_dev->device ||
1783                      (dev->device->driver &&
1784                      dev->device->driver->name &&
1785                      !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
1786                         break;
1787                 port_id++;
1788         }
1789         if (port_id >= RTE_MAX_ETHPORTS)
1790                 return RTE_MAX_ETHPORTS;
1791         return port_id;
1792 }
1793
1794 /**
1795  * DPDK callback to remove a PCI device.
1796  *
1797  * This function removes all Ethernet devices belong to a given PCI device.
1798  *
1799  * @param[in] pci_dev
1800  *   Pointer to the PCI device.
1801  *
1802  * @return
1803  *   0 on success, the function cannot fail.
1804  */
1805 static int
1806 mlx5_pci_remove(struct rte_pci_device *pci_dev)
1807 {
1808         uint16_t port_id;
1809
1810         RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
1811                 /*
1812                  * mlx5_dev_close() is not registered to secondary process,
1813                  * call the close function explicitly for secondary process.
1814                  */
1815                 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
1816                         mlx5_dev_close(&rte_eth_devices[port_id]);
1817                 else
1818                         rte_eth_dev_close(port_id);
1819         }
1820         return 0;
1821 }
1822
1823 static const struct rte_pci_id mlx5_pci_id_map[] = {
1824         {
1825                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1826                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
1827         },
1828         {
1829                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1830                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
1831         },
1832         {
1833                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1834                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
1835         },
1836         {
1837                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1838                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
1839         },
1840         {
1841                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1842                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
1843         },
1844         {
1845                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1846                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
1847         },
1848         {
1849                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1850                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
1851         },
1852         {
1853                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1854                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
1855         },
1856         {
1857                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1858                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
1859         },
1860         {
1861                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1862                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
1863         },
1864         {
1865                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1866                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
1867         },
1868         {
1869                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1870                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
1871         },
1872         {
1873                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1874                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
1875         },
1876         {
1877                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1878                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF)
1879         },
1880         {
1881                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1882                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
1883         },
1884         {
1885                 .vendor_id = 0
1886         }
1887 };
1888
1889 struct rte_pci_driver mlx5_driver = {
1890         .driver = {
1891                 .name = MLX5_DRIVER_NAME
1892         },
1893         .id_table = mlx5_pci_id_map,
1894         .probe = mlx5_os_pci_probe,
1895         .remove = mlx5_pci_remove,
1896         .dma_map = mlx5_dma_map,
1897         .dma_unmap = mlx5_dma_unmap,
1898         .drv_flags = PCI_DRV_FLAGS,
1899 };
1900
1901 /**
1902  * Driver initialization routine.
1903  */
1904 RTE_INIT(rte_mlx5_pmd_init)
1905 {
1906         /* Initialize driver log type. */
1907         mlx5_logtype = rte_log_register("pmd.net.mlx5");
1908         if (mlx5_logtype >= 0)
1909                 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE);
1910
1911         /* Build the static tables for Verbs conversion. */
1912         mlx5_set_ptype_table();
1913         mlx5_set_cksum_table();
1914         mlx5_set_swp_types_table();
1915         if (mlx5_glue)
1916                 rte_pci_register(&mlx5_driver);
1917 }
1918
1919 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
1920 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
1921 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");