1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
16 #include <linux/netlink.h>
17 #include <linux/rtnetlink.h>
20 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
22 #pragma GCC diagnostic ignored "-Wpedantic"
24 #include <infiniband/verbs.h>
26 #pragma GCC diagnostic error "-Wpedantic"
29 #include <rte_malloc.h>
30 #include <rte_ethdev_driver.h>
31 #include <rte_ethdev_pci.h>
33 #include <rte_bus_pci.h>
34 #include <rte_common.h>
35 #include <rte_config.h>
36 #include <rte_eal_memconfig.h>
37 #include <rte_kvargs.h>
38 #include <rte_rwlock.h>
39 #include <rte_spinlock.h>
40 #include <rte_string_fns.h>
43 #include "mlx5_utils.h"
44 #include "mlx5_rxtx.h"
45 #include "mlx5_autoconf.h"
46 #include "mlx5_defs.h"
47 #include "mlx5_glue.h"
50 /* Device parameter to enable RX completion queue compression. */
51 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
53 /* Device parameter to enable Multi-Packet Rx queue. */
54 #define MLX5_RX_MPRQ_EN "mprq_en"
56 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
57 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
59 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
60 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
62 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
63 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
65 /* Device parameter to configure inline send. */
66 #define MLX5_TXQ_INLINE "txq_inline"
69 * Device parameter to configure the number of TX queues threshold for
70 * enabling inline send.
72 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
74 /* Device parameter to enable multi-packet send WQEs. */
75 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
77 /* Device parameter to include 2 dsegs in the title WQEBB. */
78 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
80 /* Device parameter to limit the size of inlining packet. */
81 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
83 /* Device parameter to enable hardware Tx vector. */
84 #define MLX5_TX_VEC_EN "tx_vec_en"
86 /* Device parameter to enable hardware Rx vector. */
87 #define MLX5_RX_VEC_EN "rx_vec_en"
89 /* Allow L3 VXLAN flow creation. */
90 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
92 /* Activate Netlink support in VF mode. */
93 #define MLX5_VF_NL_EN "vf_nl_en"
95 /* Select port representors to instantiate. */
96 #define MLX5_REPRESENTOR "representor"
98 #ifndef HAVE_IBV_MLX5_MOD_MPW
99 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2)
100 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3)
103 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP
104 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4)
107 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
109 /* Shared memory between primary and secondary processes. */
110 struct mlx5_shared_data *mlx5_shared_data;
112 /* Spinlock for mlx5_shared_data allocation. */
113 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
115 /** Driver-specific log messages type. */
119 * Prepare shared data between primary and secondary process.
122 mlx5_prepare_shared_data(void)
124 const struct rte_memzone *mz;
126 rte_spinlock_lock(&mlx5_shared_data_lock);
127 if (mlx5_shared_data == NULL) {
128 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
129 /* Allocate shared memory. */
130 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
131 sizeof(*mlx5_shared_data),
134 /* Lookup allocated shared memory. */
135 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA);
138 rte_panic("Cannot allocate mlx5 shared data\n");
139 mlx5_shared_data = mz->addr;
140 /* Initialize shared data. */
141 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
142 LIST_INIT(&mlx5_shared_data->mem_event_cb_list);
143 rte_rwlock_init(&mlx5_shared_data->mem_event_rwlock);
145 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
146 mlx5_mr_mem_event_cb, NULL);
148 rte_spinlock_unlock(&mlx5_shared_data_lock);
152 * Retrieve integer value from environment variable.
155 * Environment variable name.
158 * Integer value, 0 if the variable is not set.
161 mlx5_getenv_int(const char *name)
163 const char *val = getenv(name);
171 * Verbs callback to allocate a memory. This function should allocate the space
172 * according to the size provided residing inside a huge page.
173 * Please note that all allocation must respect the alignment from libmlx5
174 * (i.e. currently sysconf(_SC_PAGESIZE)).
177 * The size in bytes of the memory to allocate.
179 * A pointer to the callback data.
182 * Allocated buffer, NULL otherwise and rte_errno is set.
185 mlx5_alloc_verbs_buf(size_t size, void *data)
187 struct priv *priv = data;
189 size_t alignment = sysconf(_SC_PAGESIZE);
190 unsigned int socket = SOCKET_ID_ANY;
192 if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) {
193 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
195 socket = ctrl->socket;
196 } else if (priv->verbs_alloc_ctx.type ==
197 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) {
198 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
200 socket = ctrl->socket;
202 assert(data != NULL);
203 ret = rte_malloc_socket(__func__, size, alignment, socket);
210 * Verbs callback to free a memory.
213 * A pointer to the memory to free.
215 * A pointer to the callback data.
218 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused)
220 assert(data != NULL);
225 * DPDK callback to close the device.
227 * Destroy all queues and objects, free memory.
230 * Pointer to Ethernet device structure.
233 mlx5_dev_close(struct rte_eth_dev *dev)
235 struct priv *priv = dev->data->dev_private;
239 DRV_LOG(DEBUG, "port %u closing device \"%s\"",
241 ((priv->ctx != NULL) ? priv->ctx->device->name : ""));
242 /* In case mlx5_dev_stop() has not been called. */
243 mlx5_dev_interrupt_handler_uninstall(dev);
244 mlx5_traffic_disable(dev);
245 mlx5_flow_flush(dev, NULL);
246 /* Prevent crashes when queues are still in use. */
247 dev->rx_pkt_burst = removed_rx_burst;
248 dev->tx_pkt_burst = removed_tx_burst;
249 if (priv->rxqs != NULL) {
250 /* XXX race condition if mlx5_rx_burst() is still running. */
252 for (i = 0; (i != priv->rxqs_n); ++i)
253 mlx5_rxq_release(dev, i);
257 if (priv->txqs != NULL) {
258 /* XXX race condition if mlx5_tx_burst() is still running. */
260 for (i = 0; (i != priv->txqs_n); ++i)
261 mlx5_txq_release(dev, i);
265 mlx5_mprq_free_mp(dev);
266 mlx5_mr_release(dev);
267 if (priv->pd != NULL) {
268 assert(priv->ctx != NULL);
269 claim_zero(mlx5_glue->dealloc_pd(priv->pd));
270 claim_zero(mlx5_glue->close_device(priv->ctx));
272 assert(priv->ctx == NULL);
273 if (priv->rss_conf.rss_key != NULL)
274 rte_free(priv->rss_conf.rss_key);
275 if (priv->reta_idx != NULL)
276 rte_free(priv->reta_idx);
277 if (priv->primary_socket)
278 mlx5_socket_uninit(dev);
280 mlx5_nl_mac_addr_flush(dev);
281 if (priv->nl_socket_route >= 0)
282 close(priv->nl_socket_route);
283 if (priv->nl_socket_rdma >= 0)
284 close(priv->nl_socket_rdma);
285 if (priv->mnl_socket)
286 mlx5_nl_flow_socket_destroy(priv->mnl_socket);
287 ret = mlx5_hrxq_ibv_verify(dev);
289 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
291 ret = mlx5_ind_table_ibv_verify(dev);
293 DRV_LOG(WARNING, "port %u some indirection table still remain",
295 ret = mlx5_rxq_ibv_verify(dev);
297 DRV_LOG(WARNING, "port %u some Verbs Rx queue still remain",
299 ret = mlx5_rxq_verify(dev);
301 DRV_LOG(WARNING, "port %u some Rx queues still remain",
303 ret = mlx5_txq_ibv_verify(dev);
305 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
307 ret = mlx5_txq_verify(dev);
309 DRV_LOG(WARNING, "port %u some Tx queues still remain",
311 ret = mlx5_flow_verify(dev);
313 DRV_LOG(WARNING, "port %u some flows still remain",
315 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
317 unsigned int i = mlx5_dev_to_port_id(dev->device, NULL, 0);
320 i = RTE_MIN(mlx5_dev_to_port_id(dev->device, port_id, i), i);
323 rte_eth_devices[port_id[i]].data->dev_private;
326 opriv->domain_id != priv->domain_id ||
327 &rte_eth_devices[port_id[i]] == dev)
332 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
334 memset(priv, 0, sizeof(*priv));
335 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
338 const struct eth_dev_ops mlx5_dev_ops = {
339 .dev_configure = mlx5_dev_configure,
340 .dev_start = mlx5_dev_start,
341 .dev_stop = mlx5_dev_stop,
342 .dev_set_link_down = mlx5_set_link_down,
343 .dev_set_link_up = mlx5_set_link_up,
344 .dev_close = mlx5_dev_close,
345 .promiscuous_enable = mlx5_promiscuous_enable,
346 .promiscuous_disable = mlx5_promiscuous_disable,
347 .allmulticast_enable = mlx5_allmulticast_enable,
348 .allmulticast_disable = mlx5_allmulticast_disable,
349 .link_update = mlx5_link_update,
350 .stats_get = mlx5_stats_get,
351 .stats_reset = mlx5_stats_reset,
352 .xstats_get = mlx5_xstats_get,
353 .xstats_reset = mlx5_xstats_reset,
354 .xstats_get_names = mlx5_xstats_get_names,
355 .dev_infos_get = mlx5_dev_infos_get,
356 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
357 .vlan_filter_set = mlx5_vlan_filter_set,
358 .rx_queue_setup = mlx5_rx_queue_setup,
359 .tx_queue_setup = mlx5_tx_queue_setup,
360 .rx_queue_release = mlx5_rx_queue_release,
361 .tx_queue_release = mlx5_tx_queue_release,
362 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
363 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
364 .mac_addr_remove = mlx5_mac_addr_remove,
365 .mac_addr_add = mlx5_mac_addr_add,
366 .mac_addr_set = mlx5_mac_addr_set,
367 .set_mc_addr_list = mlx5_set_mc_addr_list,
368 .mtu_set = mlx5_dev_set_mtu,
369 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
370 .vlan_offload_set = mlx5_vlan_offload_set,
371 .reta_update = mlx5_dev_rss_reta_update,
372 .reta_query = mlx5_dev_rss_reta_query,
373 .rss_hash_update = mlx5_rss_hash_update,
374 .rss_hash_conf_get = mlx5_rss_hash_conf_get,
375 .filter_ctrl = mlx5_dev_filter_ctrl,
376 .rx_descriptor_status = mlx5_rx_descriptor_status,
377 .tx_descriptor_status = mlx5_tx_descriptor_status,
378 .rx_queue_intr_enable = mlx5_rx_intr_enable,
379 .rx_queue_intr_disable = mlx5_rx_intr_disable,
380 .is_removed = mlx5_is_removed,
383 static const struct eth_dev_ops mlx5_dev_sec_ops = {
384 .stats_get = mlx5_stats_get,
385 .stats_reset = mlx5_stats_reset,
386 .xstats_get = mlx5_xstats_get,
387 .xstats_reset = mlx5_xstats_reset,
388 .xstats_get_names = mlx5_xstats_get_names,
389 .dev_infos_get = mlx5_dev_infos_get,
390 .rx_descriptor_status = mlx5_rx_descriptor_status,
391 .tx_descriptor_status = mlx5_tx_descriptor_status,
394 /* Available operators in flow isolated mode. */
395 const struct eth_dev_ops mlx5_dev_ops_isolate = {
396 .dev_configure = mlx5_dev_configure,
397 .dev_start = mlx5_dev_start,
398 .dev_stop = mlx5_dev_stop,
399 .dev_set_link_down = mlx5_set_link_down,
400 .dev_set_link_up = mlx5_set_link_up,
401 .dev_close = mlx5_dev_close,
402 .link_update = mlx5_link_update,
403 .stats_get = mlx5_stats_get,
404 .stats_reset = mlx5_stats_reset,
405 .xstats_get = mlx5_xstats_get,
406 .xstats_reset = mlx5_xstats_reset,
407 .xstats_get_names = mlx5_xstats_get_names,
408 .dev_infos_get = mlx5_dev_infos_get,
409 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
410 .vlan_filter_set = mlx5_vlan_filter_set,
411 .rx_queue_setup = mlx5_rx_queue_setup,
412 .tx_queue_setup = mlx5_tx_queue_setup,
413 .rx_queue_release = mlx5_rx_queue_release,
414 .tx_queue_release = mlx5_tx_queue_release,
415 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
416 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
417 .mac_addr_remove = mlx5_mac_addr_remove,
418 .mac_addr_add = mlx5_mac_addr_add,
419 .mac_addr_set = mlx5_mac_addr_set,
420 .set_mc_addr_list = mlx5_set_mc_addr_list,
421 .mtu_set = mlx5_dev_set_mtu,
422 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
423 .vlan_offload_set = mlx5_vlan_offload_set,
424 .filter_ctrl = mlx5_dev_filter_ctrl,
425 .rx_descriptor_status = mlx5_rx_descriptor_status,
426 .tx_descriptor_status = mlx5_tx_descriptor_status,
427 .rx_queue_intr_enable = mlx5_rx_intr_enable,
428 .rx_queue_intr_disable = mlx5_rx_intr_disable,
429 .is_removed = mlx5_is_removed,
433 * Verify and store value for device argument.
436 * Key argument to verify.
438 * Value associated with key.
443 * 0 on success, a negative errno value otherwise and rte_errno is set.
446 mlx5_args_check(const char *key, const char *val, void *opaque)
448 struct mlx5_dev_config *config = opaque;
451 /* No-op, port representors are processed in mlx5_dev_spawn(). */
452 if (!strcmp(MLX5_REPRESENTOR, key))
455 tmp = strtoul(val, NULL, 0);
458 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
461 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
462 config->cqe_comp = !!tmp;
463 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
464 config->mprq.enabled = !!tmp;
465 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
466 config->mprq.stride_num_n = tmp;
467 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
468 config->mprq.max_memcpy_len = tmp;
469 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
470 config->mprq.min_rxqs_num = tmp;
471 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
472 config->txq_inline = tmp;
473 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
474 config->txqs_inline = tmp;
475 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
476 config->mps = !!tmp ? config->mps : 0;
477 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
478 config->mpw_hdr_dseg = !!tmp;
479 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
480 config->inline_max_packet_sz = tmp;
481 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
482 config->tx_vec_en = !!tmp;
483 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
484 config->rx_vec_en = !!tmp;
485 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
486 config->l3_vxlan_en = !!tmp;
487 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
488 config->vf_nl_en = !!tmp;
490 DRV_LOG(WARNING, "%s: unknown parameter", key);
498 * Parse device parameters.
501 * Pointer to device configuration structure.
503 * Device arguments structure.
506 * 0 on success, a negative errno value otherwise and rte_errno is set.
509 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
511 const char **params = (const char *[]){
512 MLX5_RXQ_CQE_COMP_EN,
514 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
515 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
518 MLX5_TXQS_MIN_INLINE,
520 MLX5_TXQ_MPW_HDR_DSEG_EN,
521 MLX5_TXQ_MAX_INLINE_LEN,
529 struct rte_kvargs *kvlist;
535 /* Following UGLY cast is done to pass checkpatch. */
536 kvlist = rte_kvargs_parse(devargs->args, params);
539 /* Process parameters. */
540 for (i = 0; (params[i] != NULL); ++i) {
541 if (rte_kvargs_count(kvlist, params[i])) {
542 ret = rte_kvargs_process(kvlist, params[i],
543 mlx5_args_check, config);
546 rte_kvargs_free(kvlist);
551 rte_kvargs_free(kvlist);
555 static struct rte_pci_driver mlx5_driver;
558 * Reserved UAR address space for TXQ UAR(hw doorbell) mapping, process
559 * local resource used by both primary and secondary to avoid duplicate
561 * The space has to be available on both primary and secondary process,
562 * TXQ UAR maps to this area using fixed mmap w/o double check.
564 static void *uar_base;
567 find_lower_va_bound(const struct rte_memseg_list *msl __rte_unused,
568 const struct rte_memseg *ms, void *arg)
575 *addr = RTE_MIN(*addr, ms->addr);
581 * Reserve UAR address space for primary process.
584 * Pointer to Ethernet device.
587 * 0 on success, a negative errno value otherwise and rte_errno is set.
590 mlx5_uar_init_primary(struct rte_eth_dev *dev)
592 struct priv *priv = dev->data->dev_private;
593 void *addr = (void *)0;
595 if (uar_base) { /* UAR address space mapped. */
596 priv->uar_base = uar_base;
599 /* find out lower bound of hugepage segments */
600 rte_memseg_walk(find_lower_va_bound, &addr);
602 /* keep distance to hugepages to minimize potential conflicts. */
603 addr = RTE_PTR_SUB(addr, (uintptr_t)(MLX5_UAR_OFFSET + MLX5_UAR_SIZE));
604 /* anonymous mmap, no real memory consumption. */
605 addr = mmap(addr, MLX5_UAR_SIZE,
606 PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
607 if (addr == MAP_FAILED) {
609 "port %u failed to reserve UAR address space, please"
610 " adjust MLX5_UAR_SIZE or try --base-virtaddr",
615 /* Accept either same addr or a new addr returned from mmap if target
618 DRV_LOG(INFO, "port %u reserved UAR address space: %p",
619 dev->data->port_id, addr);
620 priv->uar_base = addr; /* for primary and secondary UAR re-mmap. */
621 uar_base = addr; /* process local, don't reserve again. */
626 * Reserve UAR address space for secondary process, align with
630 * Pointer to Ethernet device.
633 * 0 on success, a negative errno value otherwise and rte_errno is set.
636 mlx5_uar_init_secondary(struct rte_eth_dev *dev)
638 struct priv *priv = dev->data->dev_private;
641 assert(priv->uar_base);
642 if (uar_base) { /* already reserved. */
643 assert(uar_base == priv->uar_base);
646 /* anonymous mmap, no real memory consumption. */
647 addr = mmap(priv->uar_base, MLX5_UAR_SIZE,
648 PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
649 if (addr == MAP_FAILED) {
650 DRV_LOG(ERR, "port %u UAR mmap failed: %p size: %llu",
651 dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE);
655 if (priv->uar_base != addr) {
657 "port %u UAR address %p size %llu occupied, please"
658 " adjust MLX5_UAR_OFFSET or try EAL parameter"
660 dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE);
664 uar_base = addr; /* process local, don't reserve again */
665 DRV_LOG(INFO, "port %u reserved UAR address space: %p",
666 dev->data->port_id, addr);
671 * Spawn an Ethernet device from Verbs information.
674 * Backing DPDK device.
678 * If nonzero, enable VF-specific features.
679 * @param[in] switch_info
680 * Switch properties of Ethernet device.
683 * A valid Ethernet device object on success, NULL otherwise and rte_errno
684 * is set. The following error is defined:
686 * EBUSY: device is not supposed to be spawned.
688 static struct rte_eth_dev *
689 mlx5_dev_spawn(struct rte_device *dpdk_dev,
690 struct ibv_device *ibv_dev,
692 const struct mlx5_switch_info *switch_info)
694 struct ibv_context *ctx;
695 struct ibv_device_attr_ex attr;
696 struct ibv_port_attr port_attr;
697 struct ibv_pd *pd = NULL;
698 struct mlx5dv_context dv_attr = { .comp_mask = 0 };
699 struct mlx5_dev_config config = {
704 .txq_inline = MLX5_ARG_UNSET,
705 .txqs_inline = MLX5_ARG_UNSET,
706 .inline_max_packet_sz = MLX5_ARG_UNSET,
710 .stride_num_n = MLX5_MPRQ_STRIDE_NUM_N,
711 .max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN,
712 .min_rxqs_num = MLX5_MPRQ_MIN_RXQS,
715 struct rte_eth_dev *eth_dev = NULL;
716 struct priv *priv = NULL;
719 unsigned int cqe_comp;
720 unsigned int tunnel_en = 0;
721 unsigned int mpls_en = 0;
722 unsigned int swp = 0;
723 unsigned int mprq = 0;
724 unsigned int mprq_min_stride_size_n = 0;
725 unsigned int mprq_max_stride_size_n = 0;
726 unsigned int mprq_min_stride_num_n = 0;
727 unsigned int mprq_max_stride_num_n = 0;
728 #ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT
729 struct ibv_counter_set_description cs_desc = { .counter_type = 0 };
731 struct ether_addr mac;
732 char name[RTE_ETH_NAME_MAX_LEN];
733 int own_domain_id = 0;
736 /* Determine if this port representor is supposed to be spawned. */
737 if (switch_info->representor && dpdk_dev->devargs) {
738 struct rte_eth_devargs eth_da;
740 err = rte_eth_devargs_parse(dpdk_dev->devargs->args, ð_da);
743 DRV_LOG(ERR, "failed to process device arguments: %s",
744 strerror(rte_errno));
747 for (i = 0; i < eth_da.nb_representor_ports; ++i)
748 if (eth_da.representor_ports[i] ==
749 (uint16_t)switch_info->port_name)
751 if (i == eth_da.nb_representor_ports) {
756 /* Prepare shared data between primary and secondary process. */
757 mlx5_prepare_shared_data();
759 ctx = mlx5_glue->open_device(ibv_dev);
761 rte_errno = errno ? errno : ENODEV;
764 #ifdef HAVE_IBV_MLX5_MOD_SWP
765 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP;
768 * Multi-packet send is supported by ConnectX-4 Lx PF as well
769 * as all ConnectX-5 devices.
771 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
772 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS;
774 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
775 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ;
777 mlx5_glue->dv_query_device(ctx, &dv_attr);
778 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
779 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) {
780 DRV_LOG(DEBUG, "enhanced MPW is supported");
781 mps = MLX5_MPW_ENHANCED;
783 DRV_LOG(DEBUG, "MPW is supported");
787 DRV_LOG(DEBUG, "MPW isn't supported");
788 mps = MLX5_MPW_DISABLED;
791 #ifdef HAVE_IBV_MLX5_MOD_SWP
792 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP)
793 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads;
794 DRV_LOG(DEBUG, "SWP support: %u", swp);
797 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
798 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) {
799 struct mlx5dv_striding_rq_caps mprq_caps =
800 dv_attr.striding_rq_caps;
802 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d",
803 mprq_caps.min_single_stride_log_num_of_bytes);
804 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d",
805 mprq_caps.max_single_stride_log_num_of_bytes);
806 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d",
807 mprq_caps.min_single_wqe_log_num_of_strides);
808 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d",
809 mprq_caps.max_single_wqe_log_num_of_strides);
810 DRV_LOG(DEBUG, "\tsupported_qpts: %d",
811 mprq_caps.supported_qpts);
812 DRV_LOG(DEBUG, "device supports Multi-Packet RQ");
814 mprq_min_stride_size_n =
815 mprq_caps.min_single_stride_log_num_of_bytes;
816 mprq_max_stride_size_n =
817 mprq_caps.max_single_stride_log_num_of_bytes;
818 mprq_min_stride_num_n =
819 mprq_caps.min_single_wqe_log_num_of_strides;
820 mprq_max_stride_num_n =
821 mprq_caps.max_single_wqe_log_num_of_strides;
822 config.mprq.stride_num_n = RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,
823 mprq_min_stride_num_n);
826 if (RTE_CACHE_LINE_SIZE == 128 &&
827 !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP))
831 config.cqe_comp = cqe_comp;
832 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
833 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) {
834 tunnel_en = ((dv_attr.tunnel_offloads_caps &
835 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) &&
836 (dv_attr.tunnel_offloads_caps &
837 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE));
839 DRV_LOG(DEBUG, "tunnel offloading is %ssupported",
840 tunnel_en ? "" : "not ");
843 "tunnel offloading disabled due to old OFED/rdma-core version");
845 config.tunnel_en = tunnel_en;
846 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
847 mpls_en = ((dv_attr.tunnel_offloads_caps &
848 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) &&
849 (dv_attr.tunnel_offloads_caps &
850 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP));
851 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported",
852 mpls_en ? "" : "not ");
854 DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to"
855 " old OFED/rdma-core version or firmware configuration");
857 config.mpls_en = mpls_en;
858 err = mlx5_glue->query_device_ex(ctx, NULL, &attr);
860 DEBUG("ibv_query_device_ex() failed");
863 if (!switch_info->representor)
864 rte_strlcpy(name, dpdk_dev->name, sizeof(name));
866 snprintf(name, sizeof(name), "%s_representor_%u",
867 dpdk_dev->name, switch_info->port_name);
868 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name);
869 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
870 eth_dev = rte_eth_dev_attach_secondary(name);
871 if (eth_dev == NULL) {
872 DRV_LOG(ERR, "can not attach rte ethdev");
877 eth_dev->device = dpdk_dev;
878 eth_dev->dev_ops = &mlx5_dev_sec_ops;
879 err = mlx5_uar_init_secondary(eth_dev);
884 /* Receive command fd from primary process */
885 err = mlx5_socket_connect(eth_dev);
890 /* Remap UAR for Tx queues. */
891 err = mlx5_tx_uar_remap(eth_dev, err);
897 * Ethdev pointer is still required as input since
898 * the primary device is not accessible from the
901 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev);
902 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev);
903 claim_zero(mlx5_glue->close_device(ctx));
906 /* Check port status. */
907 err = mlx5_glue->query_port(ctx, 1, &port_attr);
909 DRV_LOG(ERR, "port query failed: %s", strerror(err));
912 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
913 DRV_LOG(ERR, "port is not configured in Ethernet mode");
917 if (port_attr.state != IBV_PORT_ACTIVE)
918 DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)",
919 mlx5_glue->port_state_str(port_attr.state),
921 /* Allocate protection domain. */
922 pd = mlx5_glue->alloc_pd(ctx);
924 DRV_LOG(ERR, "PD allocation failure");
928 priv = rte_zmalloc("ethdev private structure",
930 RTE_CACHE_LINE_SIZE);
932 DRV_LOG(ERR, "priv allocation failure");
937 strncpy(priv->ibdev_name, priv->ctx->device->name,
938 sizeof(priv->ibdev_name));
939 strncpy(priv->ibdev_path, priv->ctx->device->ibdev_path,
940 sizeof(priv->ibdev_path));
941 priv->device_attr = attr;
943 priv->mtu = ETHER_MTU;
945 /* Initialize UAR access locks for 32bit implementations. */
946 rte_spinlock_init(&priv->uar_lock_cq);
947 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
948 rte_spinlock_init(&priv->uar_lock[i]);
950 /* Some internal functions rely on Netlink sockets, open them now. */
951 priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA);
952 priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE);
954 priv->representor = !!switch_info->representor;
955 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
956 priv->representor_id =
957 switch_info->representor ? switch_info->port_name : -1;
959 * Look for sibling devices in order to reuse their switch domain
960 * if any, otherwise allocate one.
962 i = mlx5_dev_to_port_id(dpdk_dev, NULL, 0);
966 i = RTE_MIN(mlx5_dev_to_port_id(dpdk_dev, port_id, i), i);
968 const struct priv *opriv =
969 rte_eth_devices[port_id[i]].data->dev_private;
973 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID)
975 priv->domain_id = opriv->domain_id;
979 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
980 err = rte_eth_switch_domain_alloc(&priv->domain_id);
983 DRV_LOG(ERR, "unable to allocate switch domain: %s",
984 strerror(rte_errno));
989 err = mlx5_args(&config, dpdk_dev->devargs);
992 DRV_LOG(ERR, "failed to process device arguments: %s",
993 strerror(rte_errno));
996 config.hw_csum = !!(attr.device_cap_flags_ex & IBV_DEVICE_RAW_IP_CSUM);
997 DRV_LOG(DEBUG, "checksum offloading is %ssupported",
998 (config.hw_csum ? "" : "not "));
999 #ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT
1000 config.flow_counter_en = !!attr.max_counter_sets;
1001 mlx5_glue->describe_counter_set(ctx, 0, &cs_desc);
1002 DRV_LOG(DEBUG, "counter type = %d, num of cs = %ld, attributes = %d",
1003 cs_desc.counter_type, cs_desc.num_of_cs,
1004 cs_desc.attributes);
1006 config.ind_table_max_size =
1007 attr.rss_caps.max_rwq_indirection_table_size;
1009 * Remove this check once DPDK supports larger/variable
1010 * indirection tables.
1012 if (config.ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512)
1013 config.ind_table_max_size = ETH_RSS_RETA_SIZE_512;
1014 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u",
1015 config.ind_table_max_size);
1016 config.hw_vlan_strip = !!(attr.raw_packet_caps &
1017 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
1018 DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
1019 (config.hw_vlan_strip ? "" : "not "));
1020 config.hw_fcs_strip = !!(attr.raw_packet_caps &
1021 IBV_RAW_PACKET_CAP_SCATTER_FCS);
1022 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported",
1023 (config.hw_fcs_strip ? "" : "not "));
1024 #ifdef HAVE_IBV_WQ_FLAG_RX_END_PADDING
1025 config.hw_padding = !!attr.rx_pad_end_addr_align;
1027 DRV_LOG(DEBUG, "hardware Rx end alignment padding is %ssupported",
1028 (config.hw_padding ? "" : "not "));
1029 config.tso = (attr.tso_caps.max_tso > 0 &&
1030 (attr.tso_caps.supported_qpts &
1031 (1 << IBV_QPT_RAW_PACKET)));
1033 config.tso_max_payload_sz = attr.tso_caps.max_tso;
1034 if (config.mps && !mps) {
1036 "multi-packet send not supported on this device"
1037 " (" MLX5_TXQ_MPW_EN ")");
1041 DRV_LOG(INFO, "%sMPS is %s",
1042 config.mps == MLX5_MPW_ENHANCED ? "enhanced " : "",
1043 config.mps != MLX5_MPW_DISABLED ? "enabled" : "disabled");
1044 if (config.cqe_comp && !cqe_comp) {
1045 DRV_LOG(WARNING, "Rx CQE compression isn't supported");
1046 config.cqe_comp = 0;
1048 if (config.mprq.enabled && mprq) {
1049 if (config.mprq.stride_num_n > mprq_max_stride_num_n ||
1050 config.mprq.stride_num_n < mprq_min_stride_num_n) {
1051 config.mprq.stride_num_n =
1052 RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,
1053 mprq_min_stride_num_n);
1055 "the number of strides"
1056 " for Multi-Packet RQ is out of range,"
1057 " setting default value (%u)",
1058 1 << config.mprq.stride_num_n);
1060 config.mprq.min_stride_size_n = mprq_min_stride_size_n;
1061 config.mprq.max_stride_size_n = mprq_max_stride_size_n;
1062 } else if (config.mprq.enabled && !mprq) {
1063 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported");
1064 config.mprq.enabled = 0;
1066 eth_dev = rte_eth_dev_allocate(name);
1067 if (eth_dev == NULL) {
1068 DRV_LOG(ERR, "can not allocate rte ethdev");
1072 if (priv->representor)
1073 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR;
1074 eth_dev->data->dev_private = priv;
1075 priv->dev_data = eth_dev->data;
1076 eth_dev->data->mac_addrs = priv->mac;
1077 eth_dev->device = dpdk_dev;
1078 eth_dev->device->driver = &mlx5_driver.driver;
1079 err = mlx5_uar_init_primary(eth_dev);
1084 /* Configure the first MAC address by default. */
1085 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) {
1087 "port %u cannot get MAC address, is mlx5_en"
1088 " loaded? (errno: %s)",
1089 eth_dev->data->port_id, strerror(rte_errno));
1094 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x",
1095 eth_dev->data->port_id,
1096 mac.addr_bytes[0], mac.addr_bytes[1],
1097 mac.addr_bytes[2], mac.addr_bytes[3],
1098 mac.addr_bytes[4], mac.addr_bytes[5]);
1101 char ifname[IF_NAMESIZE];
1103 if (mlx5_get_ifname(eth_dev, &ifname) == 0)
1104 DRV_LOG(DEBUG, "port %u ifname is \"%s\"",
1105 eth_dev->data->port_id, ifname);
1107 DRV_LOG(DEBUG, "port %u ifname is unknown",
1108 eth_dev->data->port_id);
1111 /* Get actual MTU if possible. */
1112 err = mlx5_get_mtu(eth_dev, &priv->mtu);
1117 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id,
1119 /* Initialize burst functions to prevent crashes before link-up. */
1120 eth_dev->rx_pkt_burst = removed_rx_burst;
1121 eth_dev->tx_pkt_burst = removed_tx_burst;
1122 eth_dev->dev_ops = &mlx5_dev_ops;
1123 /* Register MAC address. */
1124 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
1125 if (vf && config.vf_nl_en)
1126 mlx5_nl_mac_addr_sync(eth_dev);
1127 priv->mnl_socket = mlx5_nl_flow_socket_create();
1128 if (!priv->mnl_socket) {
1131 "flow rules relying on switch offloads will not be"
1132 " supported: cannot open libmnl socket: %s",
1133 strerror(rte_errno));
1135 struct rte_flow_error error;
1136 unsigned int ifindex = mlx5_ifindex(eth_dev);
1141 "cannot retrieve network interface index";
1143 err = mlx5_nl_flow_init(priv->mnl_socket, ifindex,
1148 "flow rules relying on switch offloads will"
1149 " not be supported: %s: %s",
1150 error.message, strerror(rte_errno));
1151 mlx5_nl_flow_socket_destroy(priv->mnl_socket);
1152 priv->mnl_socket = NULL;
1155 TAILQ_INIT(&priv->flows);
1156 TAILQ_INIT(&priv->ctrl_flows);
1157 /* Hint libmlx5 to use PMD allocator for data plane resources */
1158 struct mlx5dv_ctx_allocators alctr = {
1159 .alloc = &mlx5_alloc_verbs_buf,
1160 .free = &mlx5_free_verbs_buf,
1163 mlx5_glue->dv_set_context_attr(ctx, MLX5DV_CTX_ATTR_BUF_ALLOCATORS,
1164 (void *)((uintptr_t)&alctr));
1165 /* Bring Ethernet device up. */
1166 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up",
1167 eth_dev->data->port_id);
1168 mlx5_set_link_up(eth_dev);
1170 * Even though the interrupt handler is not installed yet,
1171 * interrupts will still trigger on the asyn_fd from
1172 * Verbs context returned by ibv_open_device().
1174 mlx5_link_update(eth_dev, 0);
1175 /* Store device configuration on private structure. */
1176 priv->config = config;
1177 /* Supported Verbs flow priority number detection. */
1178 err = mlx5_flow_discover_priorities(eth_dev);
1181 priv->config.flow_prio = err;
1183 * Once the device is added to the list of memory event
1184 * callback, its global MR cache table cannot be expanded
1185 * on the fly because of deadlock. If it overflows, lookup
1186 * should be done by searching MR list linearly, which is slow.
1188 err = mlx5_mr_btree_init(&priv->mr.cache,
1189 MLX5_MR_BTREE_CACHE_N * 2,
1190 eth_dev->device->numa_node);
1195 /* Add device to memory callback list. */
1196 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1197 LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
1198 priv, mem_event_cb);
1199 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1203 if (priv->nl_socket_route >= 0)
1204 close(priv->nl_socket_route);
1205 if (priv->nl_socket_rdma >= 0)
1206 close(priv->nl_socket_rdma);
1207 if (priv->mnl_socket)
1208 mlx5_nl_flow_socket_destroy(priv->mnl_socket);
1210 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1214 claim_zero(mlx5_glue->dealloc_pd(pd));
1216 rte_eth_dev_release_port(eth_dev);
1218 claim_zero(mlx5_glue->close_device(ctx));
1224 /** Data associated with devices to spawn. */
1225 struct mlx5_dev_spawn_data {
1226 unsigned int ifindex; /**< Network interface index. */
1227 struct mlx5_switch_info info; /**< Switch information. */
1228 struct ibv_device *ibv_dev; /**< Associated IB device. */
1229 struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */
1233 * Comparison callback to sort device data.
1235 * This is meant to be used with qsort().
1238 * Pointer to pointer to first data object.
1240 * Pointer to pointer to second data object.
1243 * 0 if both objects are equal, less than 0 if the first argument is less
1244 * than the second, greater than 0 otherwise.
1247 mlx5_dev_spawn_data_cmp(const void *a, const void *b)
1249 const struct mlx5_switch_info *si_a =
1250 &((const struct mlx5_dev_spawn_data *)a)->info;
1251 const struct mlx5_switch_info *si_b =
1252 &((const struct mlx5_dev_spawn_data *)b)->info;
1255 /* Master device first. */
1256 ret = si_b->master - si_a->master;
1259 /* Then representor devices. */
1260 ret = si_b->representor - si_a->representor;
1263 /* Unidentified devices come last in no specific order. */
1264 if (!si_a->representor)
1266 /* Order representors by name. */
1267 return si_a->port_name - si_b->port_name;
1271 * DPDK callback to register a PCI device.
1273 * This function spawns Ethernet devices out of a given PCI device.
1275 * @param[in] pci_drv
1276 * PCI driver structure (mlx5_driver).
1277 * @param[in] pci_dev
1278 * PCI device information.
1281 * 0 on success, a negative errno value otherwise and rte_errno is set.
1284 mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1285 struct rte_pci_device *pci_dev)
1287 struct ibv_device **ibv_list;
1292 assert(pci_drv == &mlx5_driver);
1294 ibv_list = mlx5_glue->get_device_list(&ret);
1296 rte_errno = errno ? errno : ENOSYS;
1297 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?");
1301 struct ibv_device *ibv_match[ret + 1];
1304 struct rte_pci_addr pci_addr;
1306 DRV_LOG(DEBUG, "checking device \"%s\"", ibv_list[ret]->name);
1307 if (mlx5_ibv_device_to_pci_addr(ibv_list[ret], &pci_addr))
1309 if (pci_dev->addr.domain != pci_addr.domain ||
1310 pci_dev->addr.bus != pci_addr.bus ||
1311 pci_dev->addr.devid != pci_addr.devid ||
1312 pci_dev->addr.function != pci_addr.function)
1314 DRV_LOG(INFO, "PCI information matches for device \"%s\"",
1315 ibv_list[ret]->name);
1316 ibv_match[n++] = ibv_list[ret];
1318 ibv_match[n] = NULL;
1320 struct mlx5_dev_spawn_data list[n];
1321 int nl_route = n ? mlx5_nl_init(NETLINK_ROUTE) : -1;
1322 int nl_rdma = n ? mlx5_nl_init(NETLINK_RDMA) : -1;
1327 * The existence of several matching entries (n > 1) means port
1328 * representors have been instantiated. No existing Verbs call nor
1329 * /sys entries can tell them apart, this can only be done through
1330 * Netlink calls assuming kernel drivers are recent enough to
1333 * In the event of identification failure through Netlink, try again
1334 * through sysfs, then either:
1336 * 1. No device matches (n == 0), complain and bail out.
1337 * 2. A single IB device matches (n == 1) and is not a representor,
1338 * assume no switch support.
1339 * 3. Otherwise no safe assumptions can be made; complain louder and
1342 for (i = 0; i != n; ++i) {
1343 list[i].ibv_dev = ibv_match[i];
1344 list[i].eth_dev = NULL;
1346 list[i].ifindex = 0;
1348 list[i].ifindex = mlx5_nl_ifindex
1349 (nl_rdma, list[i].ibv_dev->name);
1352 mlx5_nl_switch_info(nl_route, list[i].ifindex,
1354 ((!list[i].info.representor && !list[i].info.master) &&
1355 mlx5_sysfs_switch_info(list[i].ifindex, &list[i].info))) {
1356 list[i].ifindex = 0;
1357 memset(&list[i].info, 0, sizeof(list[i].info));
1365 /* Count unidentified devices. */
1366 for (u = 0, i = 0; i != n; ++i)
1367 if (!list[i].info.master && !list[i].info.representor)
1370 if (n == 1 && u == 1) {
1372 DRV_LOG(INFO, "no switch support detected");
1376 "unable to tell which of the matching devices"
1377 " is the master (lack of kernel support?)");
1382 * Sort list to probe devices in natural order for users convenience
1383 * (i.e. master first, then representors from lowest to highest ID).
1386 qsort(list, n, sizeof(*list), mlx5_dev_spawn_data_cmp);
1387 switch (pci_dev->id.device_id) {
1388 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1389 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1390 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1391 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1397 for (i = 0; i != n; ++i) {
1400 list[i].eth_dev = mlx5_dev_spawn
1401 (&pci_dev->device, list[i].ibv_dev, vf, &list[i].info);
1402 if (!list[i].eth_dev) {
1403 if (rte_errno != EBUSY)
1405 /* Device is disabled, ignore it. */
1408 restore = list[i].eth_dev->data->dev_flags;
1409 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev);
1410 /* Restore non-PCI flags cleared by the above call. */
1411 list[i].eth_dev->data->dev_flags |= restore;
1412 rte_eth_dev_probing_finish(list[i].eth_dev);
1414 mlx5_glue->free_device_list(ibv_list);
1417 "no Verbs device matches PCI device " PCI_PRI_FMT ","
1418 " are kernel drivers loaded?",
1419 pci_dev->addr.domain, pci_dev->addr.bus,
1420 pci_dev->addr.devid, pci_dev->addr.function);
1423 } else if (i != n) {
1425 "probe of PCI device " PCI_PRI_FMT " aborted after"
1426 " encountering an error: %s",
1427 pci_dev->addr.domain, pci_dev->addr.bus,
1428 pci_dev->addr.devid, pci_dev->addr.function,
1429 strerror(rte_errno));
1433 if (!list[i].eth_dev)
1435 mlx5_dev_close(list[i].eth_dev);
1436 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
1437 rte_free(list[i].eth_dev->data->dev_private);
1438 claim_zero(rte_eth_dev_release_port(list[i].eth_dev));
1440 /* Restore original error. */
1448 static const struct rte_pci_id mlx5_pci_id_map[] = {
1450 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1451 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
1454 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1455 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
1458 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1459 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
1462 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1463 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
1466 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1467 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
1470 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1471 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
1474 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1475 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
1478 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1479 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
1482 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1483 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
1490 static struct rte_pci_driver mlx5_driver = {
1492 .name = MLX5_DRIVER_NAME
1494 .id_table = mlx5_pci_id_map,
1495 .probe = mlx5_pci_probe,
1496 .drv_flags = RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV,
1499 #ifdef RTE_LIBRTE_MLX5_DLOPEN_DEPS
1502 * Suffix RTE_EAL_PMD_PATH with "-glue".
1504 * This function performs a sanity check on RTE_EAL_PMD_PATH before
1505 * suffixing its last component.
1508 * Output buffer, should be large enough otherwise NULL is returned.
1513 * Pointer to @p buf or @p NULL in case suffix cannot be appended.
1516 mlx5_glue_path(char *buf, size_t size)
1518 static const char *const bad[] = { "/", ".", "..", NULL };
1519 const char *path = RTE_EAL_PMD_PATH;
1520 size_t len = strlen(path);
1524 while (len && path[len - 1] == '/')
1526 for (off = len; off && path[off - 1] != '/'; --off)
1528 for (i = 0; bad[i]; ++i)
1529 if (!strncmp(path + off, bad[i], (int)(len - off)))
1531 i = snprintf(buf, size, "%.*s-glue", (int)len, path);
1532 if (i == -1 || (size_t)i >= size)
1537 "unable to append \"-glue\" to last component of"
1538 " RTE_EAL_PMD_PATH (\"" RTE_EAL_PMD_PATH "\"),"
1539 " please re-configure DPDK");
1544 * Initialization routine for run-time dependency on rdma-core.
1547 mlx5_glue_init(void)
1549 char glue_path[sizeof(RTE_EAL_PMD_PATH) - 1 + sizeof("-glue")];
1550 const char *path[] = {
1552 * A basic security check is necessary before trusting
1553 * MLX5_GLUE_PATH, which may override RTE_EAL_PMD_PATH.
1555 (geteuid() == getuid() && getegid() == getgid() ?
1556 getenv("MLX5_GLUE_PATH") : NULL),
1558 * When RTE_EAL_PMD_PATH is set, use its glue-suffixed
1559 * variant, otherwise let dlopen() look up libraries on its
1562 (*RTE_EAL_PMD_PATH ?
1563 mlx5_glue_path(glue_path, sizeof(glue_path)) : ""),
1566 void *handle = NULL;
1570 while (!handle && i != RTE_DIM(path)) {
1579 end = strpbrk(path[i], ":;");
1581 end = path[i] + strlen(path[i]);
1582 len = end - path[i];
1587 ret = snprintf(name, sizeof(name), "%.*s%s" MLX5_GLUE,
1589 (!len || *(end - 1) == '/') ? "" : "/");
1592 if (sizeof(name) != (size_t)ret + 1)
1594 DRV_LOG(DEBUG, "looking for rdma-core glue as \"%s\"",
1596 handle = dlopen(name, RTLD_LAZY);
1607 DRV_LOG(WARNING, "cannot load glue library: %s", dlmsg);
1610 sym = dlsym(handle, "mlx5_glue");
1611 if (!sym || !*sym) {
1615 DRV_LOG(ERR, "cannot resolve glue symbol: %s", dlmsg);
1624 "cannot initialize PMD due to missing run-time dependency on"
1625 " rdma-core libraries (libibverbs, libmlx5)");
1632 * Driver initialization routine.
1634 RTE_INIT(rte_mlx5_pmd_init)
1636 /* Initialize driver log type. */
1637 mlx5_logtype = rte_log_register("pmd.net.mlx5");
1638 if (mlx5_logtype >= 0)
1639 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE);
1641 /* Build the static tables for Verbs conversion. */
1642 mlx5_set_ptype_table();
1643 mlx5_set_cksum_table();
1644 mlx5_set_swp_types_table();
1646 * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use
1647 * huge pages. Calling ibv_fork_init() during init allows
1648 * applications to use fork() safely for purposes other than
1649 * using this PMD, which is not supported in forked processes.
1651 setenv("RDMAV_HUGEPAGES_SAFE", "1", 1);
1652 /* Match the size of Rx completion entry to the size of a cacheline. */
1653 if (RTE_CACHE_LINE_SIZE == 128)
1654 setenv("MLX5_CQE_SIZE", "128", 0);
1656 * MLX5_DEVICE_FATAL_CLEANUP tells ibv_destroy functions to
1657 * cleanup all the Verbs resources even when the device was removed.
1659 setenv("MLX5_DEVICE_FATAL_CLEANUP", "1", 1);
1660 #ifdef RTE_LIBRTE_MLX5_DLOPEN_DEPS
1661 if (mlx5_glue_init())
1666 /* Glue structure must not contain any NULL pointers. */
1670 for (i = 0; i != sizeof(*mlx5_glue) / sizeof(void *); ++i)
1671 assert(((const void *const *)mlx5_glue)[i]);
1674 if (strcmp(mlx5_glue->version, MLX5_GLUE_VERSION)) {
1676 "rdma-core glue \"%s\" mismatch: \"%s\" is required",
1677 mlx5_glue->version, MLX5_GLUE_VERSION);
1680 mlx5_glue->fork_init();
1681 rte_pci_register(&mlx5_driver);
1684 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
1685 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
1686 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");