1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
13 #include <rte_malloc.h>
14 #include <rte_ethdev_driver.h>
15 #include <rte_ethdev_pci.h>
17 #include <rte_bus_pci.h>
18 #include <rte_common.h>
19 #include <rte_kvargs.h>
20 #include <rte_rwlock.h>
21 #include <rte_spinlock.h>
22 #include <rte_string_fns.h>
23 #include <rte_alarm.h>
25 #include <mlx5_glue.h>
26 #include <mlx5_devx_cmds.h>
27 #include <mlx5_common.h>
28 #include <mlx5_common_os.h>
29 #include <mlx5_common_mp.h>
30 #include <mlx5_common_pci.h>
31 #include <mlx5_malloc.h>
33 #include "mlx5_defs.h"
35 #include "mlx5_utils.h"
36 #include "mlx5_rxtx.h"
37 #include "mlx5_autoconf.h"
39 #include "mlx5_flow.h"
40 #include "rte_pmd_mlx5.h"
42 /* Device parameter to enable RX completion queue compression. */
43 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
45 /* Device parameter to enable RX completion entry padding to 128B. */
46 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
48 /* Device parameter to enable padding Rx packet to cacheline size. */
49 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
51 /* Device parameter to enable Multi-Packet Rx queue. */
52 #define MLX5_RX_MPRQ_EN "mprq_en"
54 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
55 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
57 /* Device parameter to configure log 2 of the stride size for MPRQ. */
58 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
60 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
61 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
63 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
64 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
66 /* Device parameter to configure inline send. Deprecated, ignored.*/
67 #define MLX5_TXQ_INLINE "txq_inline"
69 /* Device parameter to limit packet size to inline with ordinary SEND. */
70 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
72 /* Device parameter to configure minimal data size to inline. */
73 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
75 /* Device parameter to limit packet size to inline with Enhanced MPW. */
76 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
79 * Device parameter to configure the number of TX queues threshold for
80 * enabling inline send.
82 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
85 * Device parameter to configure the number of TX queues threshold for
86 * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
88 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
90 /* Device parameter to enable multi-packet send WQEs. */
91 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
94 * Device parameter to force doorbell register mapping
95 * to non-cahed region eliminating the extra write memory barrier.
97 #define MLX5_TX_DB_NC "tx_db_nc"
100 * Device parameter to include 2 dsegs in the title WQEBB.
101 * Deprecated, ignored.
103 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
106 * Device parameter to limit the size of inlining packet.
107 * Deprecated, ignored.
109 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
112 * Device parameter to enable Tx scheduling on timestamps
113 * and specify the packet pacing granularity in nanoseconds.
115 #define MLX5_TX_PP "tx_pp"
118 * Device parameter to specify skew in nanoseconds on Tx datapath,
119 * it represents the time between SQ start WQE processing and
120 * appearing actual packet data on the wire.
122 #define MLX5_TX_SKEW "tx_skew"
125 * Device parameter to enable hardware Tx vector.
126 * Deprecated, ignored (no vectorized Tx routines anymore).
128 #define MLX5_TX_VEC_EN "tx_vec_en"
130 /* Device parameter to enable hardware Rx vector. */
131 #define MLX5_RX_VEC_EN "rx_vec_en"
133 /* Allow L3 VXLAN flow creation. */
134 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
136 /* Activate DV E-Switch flow steering. */
137 #define MLX5_DV_ESW_EN "dv_esw_en"
139 /* Activate DV flow steering. */
140 #define MLX5_DV_FLOW_EN "dv_flow_en"
142 /* Enable extensive flow metadata support. */
143 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
145 /* Device parameter to let the user manage the lacp traffic of bonded device */
146 #define MLX5_LACP_BY_USER "lacp_by_user"
148 /* Activate Netlink support in VF mode. */
149 #define MLX5_VF_NL_EN "vf_nl_en"
151 /* Enable extending memsegs when creating a MR. */
152 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
154 /* Select port representors to instantiate. */
155 #define MLX5_REPRESENTOR "representor"
157 /* Device parameter to configure the maximum number of dump files per queue. */
158 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
160 /* Configure timeout of LRO session (in microseconds). */
161 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
164 * Device parameter to configure the total data buffer size for a single
165 * hairpin queue (logarithm value).
167 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
169 /* Flow memory reclaim mode. */
170 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
172 /* The default memory allocator used in PMD. */
173 #define MLX5_SYS_MEM_EN "sys_mem_en"
174 /* Decap will be used or not. */
175 #define MLX5_DECAP_EN "decap_en"
177 /* Shared memory between primary and secondary processes. */
178 struct mlx5_shared_data *mlx5_shared_data;
180 /** Driver-specific log messages type. */
183 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
184 LIST_HEAD_INITIALIZER();
185 static pthread_mutex_t mlx5_dev_ctx_list_mutex = PTHREAD_MUTEX_INITIALIZER;
187 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
188 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
190 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
196 .malloc = mlx5_malloc,
198 .type = "mlx5_encap_decap_ipool",
201 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
207 .malloc = mlx5_malloc,
209 .type = "mlx5_push_vlan_ipool",
212 .size = sizeof(struct mlx5_flow_dv_tag_resource),
218 .malloc = mlx5_malloc,
220 .type = "mlx5_tag_ipool",
223 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
229 .malloc = mlx5_malloc,
231 .type = "mlx5_port_id_ipool",
234 .size = sizeof(struct mlx5_flow_tbl_data_entry),
240 .malloc = mlx5_malloc,
242 .type = "mlx5_jump_ipool",
246 .size = sizeof(struct mlx5_flow_meter),
252 .malloc = mlx5_malloc,
254 .type = "mlx5_meter_ipool",
257 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
263 .malloc = mlx5_malloc,
265 .type = "mlx5_mcp_ipool",
268 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
274 .malloc = mlx5_malloc,
276 .type = "mlx5_hrxq_ipool",
280 * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
281 * It set in run time according to PCI function configuration.
289 .malloc = mlx5_malloc,
291 .type = "mlx5_flow_handle_ipool",
294 .size = sizeof(struct rte_flow),
298 .malloc = mlx5_malloc,
300 .type = "rte_flow_ipool",
305 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
306 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
308 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
311 * Allocate ID pool structure.
314 * The maximum id can be allocated from the pool.
317 * Pointer to pool object, NULL value otherwise.
319 struct mlx5_flow_id_pool *
320 mlx5_flow_id_pool_alloc(uint32_t max_id)
322 struct mlx5_flow_id_pool *pool;
325 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool),
326 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
328 DRV_LOG(ERR, "can't allocate id pool");
332 mem = mlx5_malloc(MLX5_MEM_ZERO,
333 MLX5_FLOW_MIN_ID_POOL_SIZE * sizeof(uint32_t),
334 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
336 DRV_LOG(ERR, "can't allocate mem for id pool");
340 pool->free_arr = mem;
341 pool->curr = pool->free_arr;
342 pool->last = pool->free_arr + MLX5_FLOW_MIN_ID_POOL_SIZE;
343 pool->base_index = 0;
344 pool->max_id = max_id;
352 * Release ID pool structure.
355 * Pointer to flow id pool object to free.
358 mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool)
360 mlx5_free(pool->free_arr);
368 * Pointer to flow id pool.
373 * 0 on success, error value otherwise.
376 mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id)
378 if (pool->curr == pool->free_arr) {
379 if (pool->base_index == pool->max_id) {
381 DRV_LOG(ERR, "no free id");
384 *id = ++pool->base_index;
387 *id = *(--pool->curr);
395 * Pointer to flow id pool.
400 * 0 on success, error value otherwise.
403 mlx5_flow_id_release(struct mlx5_flow_id_pool *pool, uint32_t id)
409 if (pool->curr == pool->last) {
410 size = pool->curr - pool->free_arr;
411 size2 = size * MLX5_ID_GENERATION_ARRAY_FACTOR;
412 MLX5_ASSERT(size2 > size);
413 mem = mlx5_malloc(0, size2 * sizeof(uint32_t), 0,
416 DRV_LOG(ERR, "can't allocate mem for id pool");
420 memcpy(mem, pool->free_arr, size * sizeof(uint32_t));
421 mlx5_free(pool->free_arr);
422 pool->free_arr = mem;
423 pool->curr = pool->free_arr + size;
424 pool->last = pool->free_arr + size2;
432 * Initialize the shared aging list information per port.
435 * Pointer to mlx5_dev_ctx_shared object.
438 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
441 struct mlx5_age_info *age_info;
443 for (i = 0; i < sh->max_port; i++) {
444 age_info = &sh->port[i].age_info;
446 TAILQ_INIT(&age_info->aged_counters);
447 rte_spinlock_init(&age_info->aged_sl);
448 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
453 * Initialize the counters management structure.
456 * Pointer to mlx5_dev_ctx_shared object to free
459 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
463 memset(&sh->cmng, 0, sizeof(sh->cmng));
464 TAILQ_INIT(&sh->cmng.flow_counters);
465 for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
466 sh->cmng.ccont[i].min_id = MLX5_CNT_BATCH_OFFSET;
467 sh->cmng.ccont[i].max_id = -1;
468 sh->cmng.ccont[i].last_pool_idx = POOL_IDX_INVALID;
469 TAILQ_INIT(&sh->cmng.ccont[i].pool_list);
470 rte_spinlock_init(&sh->cmng.ccont[i].resize_sl);
471 TAILQ_INIT(&sh->cmng.ccont[i].counters);
472 rte_spinlock_init(&sh->cmng.ccont[i].csl);
477 * Destroy all the resources allocated for a counter memory management.
480 * Pointer to the memory management structure.
483 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
485 uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
487 LIST_REMOVE(mng, next);
488 claim_zero(mlx5_devx_cmd_destroy(mng->dm));
489 claim_zero(mlx5_glue->devx_umem_dereg(mng->umem));
494 * Close and release all the resources of the counters management.
497 * Pointer to mlx5_dev_ctx_shared object to free.
500 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
502 struct mlx5_counter_stats_mem_mng *mng;
509 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
510 if (rte_errno != EINPROGRESS)
514 for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
515 struct mlx5_flow_counter_pool *pool;
516 uint32_t batch = !!(i > 1);
518 if (!sh->cmng.ccont[i].pools)
520 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
522 if (batch && pool->min_dcs)
523 claim_zero(mlx5_devx_cmd_destroy
525 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
526 if (MLX5_POOL_GET_CNT(pool, j)->action)
528 (mlx5_glue->destroy_flow_action
531 if (!batch && MLX5_GET_POOL_CNT_EXT
533 claim_zero(mlx5_devx_cmd_destroy
534 (MLX5_GET_POOL_CNT_EXT
537 TAILQ_REMOVE(&sh->cmng.ccont[i].pool_list, pool, next);
539 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
541 mlx5_free(sh->cmng.ccont[i].pools);
543 mng = LIST_FIRST(&sh->cmng.mem_mngs);
545 mlx5_flow_destroy_counter_stat_mem_mng(mng);
546 mng = LIST_FIRST(&sh->cmng.mem_mngs);
548 memset(&sh->cmng, 0, sizeof(sh->cmng));
552 * Initialize the flow resources' indexed mempool.
555 * Pointer to mlx5_dev_ctx_shared object.
557 * Pointer to user dev config.
560 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
561 const struct mlx5_dev_config *config)
564 struct mlx5_indexed_pool_config cfg;
566 for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
567 cfg = mlx5_ipool_cfg[i];
572 * Set MLX5_IPOOL_MLX5_FLOW ipool size
573 * according to PCI function flow configuration.
575 case MLX5_IPOOL_MLX5_FLOW:
576 cfg.size = config->dv_flow_en ?
577 sizeof(struct mlx5_flow_handle) :
578 MLX5_FLOW_HANDLE_VERBS_SIZE;
581 if (config->reclaim_mode)
582 cfg.release_mem_en = 1;
583 sh->ipool[i] = mlx5_ipool_create(&cfg);
588 * Release the flow resources' indexed mempool.
591 * Pointer to mlx5_dev_ctx_shared object.
594 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
598 for (i = 0; i < MLX5_IPOOL_MAX; ++i)
599 mlx5_ipool_destroy(sh->ipool[i]);
603 * Check if dynamic flex parser for eCPRI already exists.
606 * Pointer to Ethernet device structure.
609 * true on exists, false on not.
612 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
614 struct mlx5_priv *priv = dev->data->dev_private;
615 struct mlx5_flex_parser_profiles *prf =
616 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
622 * Allocation of a flex parser for eCPRI. Once created, this parser related
623 * resources will be held until the device is closed.
626 * Pointer to Ethernet device structure.
629 * 0 on success, a negative errno value otherwise and rte_errno is set.
632 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
634 struct mlx5_priv *priv = dev->data->dev_private;
635 struct mlx5_flex_parser_profiles *prf =
636 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
637 struct mlx5_devx_graph_node_attr node = {
638 .modify_field_select = 0,
643 if (!priv->config.hca_attr.parse_graph_flex_node) {
644 DRV_LOG(ERR, "Dynamic flex parser is not supported "
645 "for device %s.", priv->dev_data->name);
648 node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED;
649 /* 8 bytes now: 4B common header + 4B message body header. */
650 node.header_length_base_value = 0x8;
651 /* After MAC layer: Ether / VLAN. */
652 node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC;
653 /* Type of compared condition should be 0xAEFE in the L2 layer. */
654 node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI;
655 /* Sample #0: type in common header. */
656 node.sample[0].flow_match_sample_en = 1;
658 node.sample[0].flow_match_sample_offset_mode = 0x0;
659 /* Only the 2nd byte will be used. */
660 node.sample[0].flow_match_sample_field_base_offset = 0x0;
661 /* Sample #1: message payload. */
662 node.sample[1].flow_match_sample_en = 1;
664 node.sample[1].flow_match_sample_offset_mode = 0x0;
666 * Only the first two bytes will be used right now, and its offset will
667 * start after the common header that with the length of a DW(u32).
669 node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);
670 prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->ctx, &node);
672 DRV_LOG(ERR, "Failed to create flex parser node object.");
673 return (rte_errno == 0) ? -ENODEV : -rte_errno;
676 ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num);
678 DRV_LOG(ERR, "Failed to query sample IDs.");
679 return (rte_errno == 0) ? -ENODEV : -rte_errno;
681 prf->offset[0] = 0x0;
682 prf->offset[1] = sizeof(uint32_t);
683 prf->ids[0] = ids[0];
684 prf->ids[1] = ids[1];
689 * Destroy the flex parser node, including the parser itself, input / output
690 * arcs and DW samples. Resources could be reused then.
693 * Pointer to Ethernet device structure.
696 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
698 struct mlx5_priv *priv = dev->data->dev_private;
699 struct mlx5_flex_parser_profiles *prf =
700 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
703 mlx5_devx_cmd_destroy(prf->obj);
708 * Allocate Rx and Tx UARs in robust fashion.
709 * This routine handles the following UAR allocation issues:
711 * - tries to allocate the UAR with the most appropriate memory
712 * mapping type from the ones supported by the host
714 * - tries to allocate the UAR with non-NULL base address
715 * OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as
716 * UAR base address if UAR was not the first object in the UAR page.
717 * It caused the PMD failure and we should try to get another UAR
718 * till we get the first one with non-NULL base address returned.
721 mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh,
722 const struct mlx5_dev_config *config)
724 uint32_t uar_mapping, retry;
728 for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
729 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
730 /* Control the mapping type according to the settings. */
731 uar_mapping = (config->dbnc == MLX5_TXDB_NCACHED) ?
732 MLX5DV_UAR_ALLOC_TYPE_NC :
733 MLX5DV_UAR_ALLOC_TYPE_BF;
735 RTE_SET_USED(config);
737 * It seems we have no way to control the memory mapping type
738 * for the UAR, the default "Write-Combining" type is supposed.
739 * The UAR initialization on queue creation queries the
740 * actual mapping type done by Verbs/kernel and setups the
741 * PMD datapath accordingly.
745 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->ctx, uar_mapping);
746 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
748 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
749 if (config->dbnc == MLX5_TXDB_CACHED ||
750 config->dbnc == MLX5_TXDB_HEURISTIC)
751 DRV_LOG(WARNING, "Devarg tx_db_nc setting "
752 "is not supported by DevX");
754 * In some environments like virtual machine
755 * the Write Combining mapped might be not supported
756 * and UAR allocation fails. We try "Non-Cached"
757 * mapping for the case. The tx_burst routines take
758 * the UAR mapping type into account on UAR setup
761 DRV_LOG(WARNING, "Failed to allocate Tx DevX UAR (BF)");
762 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
763 sh->tx_uar = mlx5_glue->devx_alloc_uar
764 (sh->ctx, uar_mapping);
765 } else if (!sh->tx_uar &&
766 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_NC) {
767 if (config->dbnc == MLX5_TXDB_NCACHED)
768 DRV_LOG(WARNING, "Devarg tx_db_nc settings "
769 "is not supported by DevX");
771 * If Verbs/kernel does not support "Non-Cached"
772 * try the "Write-Combining".
774 DRV_LOG(WARNING, "Failed to allocate Tx DevX UAR (NC)");
775 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_BF;
776 sh->tx_uar = mlx5_glue->devx_alloc_uar
777 (sh->ctx, uar_mapping);
781 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (BF/NC)");
785 base_addr = mlx5_os_get_devx_uar_base_addr(sh->tx_uar);
789 * The UARs are allocated by rdma_core within the
790 * IB device context, on context closure all UARs
791 * will be freed, should be no memory/object leakage.
793 DRV_LOG(WARNING, "Retrying to allocate Tx DevX UAR");
796 /* Check whether we finally succeeded with valid UAR allocation. */
798 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (NULL base)");
802 for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
804 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
805 (sh->ctx, uar_mapping);
806 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
807 if (!sh->devx_rx_uar &&
808 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
810 * Rx UAR is used to control interrupts only,
811 * should be no datapath noticeable impact,
812 * can try "Non-Cached" mapping safely.
814 DRV_LOG(WARNING, "Failed to allocate Rx DevX UAR (BF)");
815 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
816 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
817 (sh->ctx, uar_mapping);
820 if (!sh->devx_rx_uar) {
821 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (BF/NC)");
825 base_addr = mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar);
829 * The UARs are allocated by rdma_core within the
830 * IB device context, on context closure all UARs
831 * will be freed, should be no memory/object leakage.
833 DRV_LOG(WARNING, "Retrying to allocate Rx DevX UAR");
834 sh->devx_rx_uar = NULL;
836 /* Check whether we finally succeeded with valid UAR allocation. */
837 if (!sh->devx_rx_uar) {
838 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (NULL base)");
846 * Allocate shared device context. If there is multiport device the
847 * master and representors will share this context, if there is single
848 * port dedicated device, the context will be used by only given
849 * port due to unification.
851 * Routine first searches the context for the specified device name,
852 * if found the shared context assumed and reference counter is incremented.
853 * If no context found the new one is created and initialized with specified
854 * device context and parameters.
857 * Pointer to the device attributes (name, port, etc).
859 * Pointer to device configuration structure.
862 * Pointer to mlx5_dev_ctx_shared object on success,
863 * otherwise NULL and rte_errno is set.
865 struct mlx5_dev_ctx_shared *
866 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
867 const struct mlx5_dev_config *config)
869 struct mlx5_dev_ctx_shared *sh;
872 struct mlx5_devx_tis_attr tis_attr = { 0 };
875 /* Secondary process should not create the shared context. */
876 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
877 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
878 /* Search for IB context by device name. */
879 LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
880 if (!strcmp(sh->ibdev_name,
881 mlx5_os_get_dev_device_name(spawn->phys_dev))) {
886 /* No device found, we have to create new shared context. */
887 MLX5_ASSERT(spawn->max_port);
888 sh = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
889 sizeof(struct mlx5_dev_ctx_shared) +
891 sizeof(struct mlx5_dev_shared_port),
892 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
894 DRV_LOG(ERR, "shared context allocation failure");
898 err = mlx5_os_open_device(spawn, config, sh);
901 err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
903 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
907 sh->max_port = spawn->max_port;
908 strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
909 sizeof(sh->ibdev_name) - 1);
910 strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
911 sizeof(sh->ibdev_path) - 1);
913 * Setting port_id to max unallowed value means
914 * there is no interrupt subhandler installed for
915 * the given port index i.
917 for (i = 0; i < sh->max_port; i++) {
918 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
919 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
921 sh->pd = mlx5_glue->alloc_pd(sh->ctx);
922 if (sh->pd == NULL) {
923 DRV_LOG(ERR, "PD allocation failure");
928 uint32_t lcore = (uint32_t)rte_lcore_to_cpu_id(-1);
930 /* Query the EQN for this core. */
931 err = mlx5_glue->devx_query_eqn(sh->ctx, lcore, &sh->eqn);
934 DRV_LOG(ERR, "Failed to query event queue number %d.",
938 err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
940 DRV_LOG(ERR, "Fail to extract pdn from PD");
943 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
945 DRV_LOG(ERR, "TD allocation failure");
949 tis_attr.transport_domain = sh->td->id;
950 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
952 DRV_LOG(ERR, "TIS allocation failure");
956 err = mlx5_alloc_rxtx_uars(sh, config);
959 MLX5_ASSERT(sh->tx_uar);
960 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->tx_uar));
962 MLX5_ASSERT(sh->devx_rx_uar);
963 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar));
965 sh->flow_id_pool = mlx5_flow_id_pool_alloc
966 ((1 << HAIRPIN_FLOW_ID_BITS) - 1);
967 if (!sh->flow_id_pool) {
968 DRV_LOG(ERR, "can't create flow id pool");
973 /* Initialize UAR access locks for 32bit implementations. */
974 rte_spinlock_init(&sh->uar_lock_cq);
975 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
976 rte_spinlock_init(&sh->uar_lock[i]);
979 * Once the device is added to the list of memory event
980 * callback, its global MR cache table cannot be expanded
981 * on the fly because of deadlock. If it overflows, lookup
982 * should be done by searching MR list linearly, which is slow.
984 * At this point the device is not added to the memory
985 * event list yet, context is just being created.
987 err = mlx5_mr_btree_init(&sh->share_cache.cache,
988 MLX5_MR_BTREE_CACHE_N * 2,
989 spawn->pci_dev->device.numa_node);
994 mlx5_os_set_reg_mr_cb(&sh->share_cache.reg_mr_cb,
995 &sh->share_cache.dereg_mr_cb);
996 mlx5_os_dev_shared_handler_install(sh);
997 sh->cnt_id_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_DWORD);
998 if (!sh->cnt_id_tbl) {
1002 mlx5_flow_aging_init(sh);
1003 mlx5_flow_counters_mng_init(sh);
1004 mlx5_flow_ipool_create(sh, config);
1005 /* Add device to memory callback list. */
1006 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1007 LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
1009 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1010 /* Add context to the global device list. */
1011 LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
1013 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1016 pthread_mutex_destroy(&sh->txpp.mutex);
1017 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1020 mlx5_l3t_destroy(sh->cnt_id_tbl);
1022 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1024 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1025 if (sh->devx_rx_uar)
1026 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1028 mlx5_glue->devx_free_uar(sh->tx_uar);
1030 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
1032 claim_zero(mlx5_glue->close_device(sh->ctx));
1033 if (sh->flow_id_pool)
1034 mlx5_flow_id_pool_release(sh->flow_id_pool);
1036 MLX5_ASSERT(err > 0);
1042 * Free shared IB device context. Decrement counter and if zero free
1043 * all allocated resources and close handles.
1046 * Pointer to mlx5_dev_ctx_shared object to free
1049 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
1051 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1052 #ifdef RTE_LIBRTE_MLX5_DEBUG
1053 /* Check the object presence in the list. */
1054 struct mlx5_dev_ctx_shared *lctx;
1056 LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
1061 DRV_LOG(ERR, "Freeing non-existing shared IB context");
1066 MLX5_ASSERT(sh->refcnt);
1067 /* Secondary process should not free the shared context. */
1068 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1071 /* Remove from memory callback device list. */
1072 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1073 LIST_REMOVE(sh, mem_event_cb);
1074 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1075 /* Release created Memory Regions. */
1076 mlx5_mr_release_cache(&sh->share_cache);
1077 /* Remove context from the global device list. */
1078 LIST_REMOVE(sh, next);
1079 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1081 * Ensure there is no async event handler installed.
1082 * Only primary process handles async device events.
1084 mlx5_flow_counters_mng_close(sh);
1085 mlx5_flow_ipool_destroy(sh);
1086 mlx5_os_dev_shared_handler_uninstall(sh);
1087 if (sh->cnt_id_tbl) {
1088 mlx5_l3t_destroy(sh->cnt_id_tbl);
1089 sh->cnt_id_tbl = NULL;
1092 mlx5_glue->devx_free_uar(sh->tx_uar);
1096 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
1098 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1100 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1101 if (sh->devx_rx_uar)
1102 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1104 claim_zero(mlx5_glue->close_device(sh->ctx));
1105 if (sh->flow_id_pool)
1106 mlx5_flow_id_pool_release(sh->flow_id_pool);
1107 pthread_mutex_destroy(&sh->txpp.mutex);
1111 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1115 * Destroy table hash list and all the root entries per domain.
1118 * Pointer to the private device data structure.
1121 mlx5_free_table_hash_list(struct mlx5_priv *priv)
1123 struct mlx5_dev_ctx_shared *sh = priv->sh;
1124 struct mlx5_flow_tbl_data_entry *tbl_data;
1125 union mlx5_flow_tbl_key table_key = {
1133 struct mlx5_hlist_entry *pos;
1137 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
1139 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
1141 MLX5_ASSERT(tbl_data);
1142 mlx5_hlist_remove(sh->flow_tbls, pos);
1143 mlx5_free(tbl_data);
1145 table_key.direction = 1;
1146 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
1148 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
1150 MLX5_ASSERT(tbl_data);
1151 mlx5_hlist_remove(sh->flow_tbls, pos);
1152 mlx5_free(tbl_data);
1154 table_key.direction = 0;
1155 table_key.domain = 1;
1156 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
1158 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
1160 MLX5_ASSERT(tbl_data);
1161 mlx5_hlist_remove(sh->flow_tbls, pos);
1162 mlx5_free(tbl_data);
1164 mlx5_hlist_destroy(sh->flow_tbls, NULL, NULL);
1168 * Initialize flow table hash list and create the root tables entry
1172 * Pointer to the private device data structure.
1175 * Zero on success, positive error code otherwise.
1178 mlx5_alloc_table_hash_list(struct mlx5_priv *priv)
1180 struct mlx5_dev_ctx_shared *sh = priv->sh;
1181 char s[MLX5_HLIST_NAMESIZE];
1185 snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1186 sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE);
1187 if (!sh->flow_tbls) {
1188 DRV_LOG(ERR, "flow tables with hash creation failed.");
1192 #ifndef HAVE_MLX5DV_DR
1194 * In case we have not DR support, the zero tables should be created
1195 * because DV expect to see them even if they cannot be created by
1198 union mlx5_flow_tbl_key table_key = {
1206 struct mlx5_flow_tbl_data_entry *tbl_data = mlx5_malloc(MLX5_MEM_ZERO,
1207 sizeof(*tbl_data), 0,
1214 tbl_data->entry.key = table_key.v64;
1215 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1218 rte_atomic32_init(&tbl_data->tbl.refcnt);
1219 rte_atomic32_inc(&tbl_data->tbl.refcnt);
1220 table_key.direction = 1;
1221 tbl_data = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tbl_data), 0,
1227 tbl_data->entry.key = table_key.v64;
1228 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1231 rte_atomic32_init(&tbl_data->tbl.refcnt);
1232 rte_atomic32_inc(&tbl_data->tbl.refcnt);
1233 table_key.direction = 0;
1234 table_key.domain = 1;
1235 tbl_data = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tbl_data), 0,
1241 tbl_data->entry.key = table_key.v64;
1242 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1245 rte_atomic32_init(&tbl_data->tbl.refcnt);
1246 rte_atomic32_inc(&tbl_data->tbl.refcnt);
1249 mlx5_free_table_hash_list(priv);
1250 #endif /* HAVE_MLX5DV_DR */
1255 * Retrieve integer value from environment variable.
1258 * Environment variable name.
1261 * Integer value, 0 if the variable is not set.
1264 mlx5_getenv_int(const char *name)
1266 const char *val = getenv(name);
1274 * DPDK callback to add udp tunnel port
1277 * A pointer to eth_dev
1278 * @param[in] udp_tunnel
1279 * A pointer to udp tunnel
1282 * 0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1285 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1286 struct rte_eth_udp_tunnel *udp_tunnel)
1288 MLX5_ASSERT(udp_tunnel != NULL);
1289 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1290 udp_tunnel->udp_port == 4789)
1292 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1293 udp_tunnel->udp_port == 4790)
1299 * Initialize process private data structure.
1302 * Pointer to Ethernet device structure.
1305 * 0 on success, a negative errno value otherwise and rte_errno is set.
1308 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1310 struct mlx5_priv *priv = dev->data->dev_private;
1311 struct mlx5_proc_priv *ppriv;
1315 * UAR register table follows the process private structure. BlueFlame
1316 * registers for Tx queues are stored in the table.
1319 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1320 ppriv = mlx5_malloc(MLX5_MEM_RTE, ppriv_size, RTE_CACHE_LINE_SIZE,
1321 dev->device->numa_node);
1326 ppriv->uar_table_sz = ppriv_size;
1327 dev->process_private = ppriv;
1332 * Un-initialize process private data structure.
1335 * Pointer to Ethernet device structure.
1338 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1340 if (!dev->process_private)
1342 mlx5_free(dev->process_private);
1343 dev->process_private = NULL;
1347 * DPDK callback to close the device.
1349 * Destroy all queues and objects, free memory.
1352 * Pointer to Ethernet device structure.
1355 mlx5_dev_close(struct rte_eth_dev *dev)
1357 struct mlx5_priv *priv = dev->data->dev_private;
1361 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1362 /* Check if process_private released. */
1363 if (!dev->process_private)
1365 mlx5_tx_uar_uninit_secondary(dev);
1366 mlx5_proc_priv_uninit(dev);
1367 rte_eth_dev_release_port(dev);
1372 DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1374 ((priv->sh->ctx != NULL) ?
1375 mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
1377 * If default mreg copy action is removed at the stop stage,
1378 * the search will return none and nothing will be done anymore.
1380 mlx5_flow_stop_default(dev);
1381 mlx5_traffic_disable(dev);
1383 * If all the flows are already flushed in the device stop stage,
1384 * then this will return directly without any action.
1386 mlx5_flow_list_flush(dev, &priv->flows, true);
1387 mlx5_flow_meter_flush(dev, NULL);
1388 /* Free the intermediate buffers for flow creation. */
1389 mlx5_flow_free_intermediate(dev);
1390 /* Prevent crashes when queues are still in use. */
1391 dev->rx_pkt_burst = removed_rx_burst;
1392 dev->tx_pkt_burst = removed_tx_burst;
1394 /* Disable datapath on secondary process. */
1395 mlx5_mp_os_req_stop_rxtx(dev);
1396 /* Free the eCPRI flex parser resource. */
1397 mlx5_flex_parser_ecpri_release(dev);
1398 if (priv->rxqs != NULL) {
1399 /* XXX race condition if mlx5_rx_burst() is still running. */
1401 for (i = 0; (i != priv->rxqs_n); ++i)
1402 mlx5_rxq_release(dev, i);
1406 if (priv->txqs != NULL) {
1407 /* XXX race condition if mlx5_tx_burst() is still running. */
1409 for (i = 0; (i != priv->txqs_n); ++i)
1410 mlx5_txq_release(dev, i);
1414 mlx5_proc_priv_uninit(dev);
1415 if (priv->mreg_cp_tbl)
1416 mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
1417 mlx5_mprq_free_mp(dev);
1418 mlx5_os_free_shared_dr(priv);
1419 if (priv->rss_conf.rss_key != NULL)
1420 mlx5_free(priv->rss_conf.rss_key);
1421 if (priv->reta_idx != NULL)
1422 mlx5_free(priv->reta_idx);
1423 if (priv->config.vf)
1424 mlx5_os_mac_addr_flush(dev);
1425 if (priv->nl_socket_route >= 0)
1426 close(priv->nl_socket_route);
1427 if (priv->nl_socket_rdma >= 0)
1428 close(priv->nl_socket_rdma);
1429 if (priv->vmwa_context)
1430 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1431 ret = mlx5_hrxq_verify(dev);
1433 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1434 dev->data->port_id);
1435 ret = mlx5_ind_table_obj_verify(dev);
1437 DRV_LOG(WARNING, "port %u some indirection table still remain",
1438 dev->data->port_id);
1439 ret = mlx5_rxq_obj_verify(dev);
1441 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1442 dev->data->port_id);
1443 ret = mlx5_rxq_verify(dev);
1445 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1446 dev->data->port_id);
1447 ret = mlx5_txq_obj_verify(dev);
1449 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1450 dev->data->port_id);
1451 ret = mlx5_txq_verify(dev);
1453 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1454 dev->data->port_id);
1455 ret = mlx5_flow_verify(dev);
1457 DRV_LOG(WARNING, "port %u some flows still remain",
1458 dev->data->port_id);
1460 * Free the shared context in last turn, because the cleanup
1461 * routines above may use some shared fields, like
1462 * mlx5_os_mac_addr_flush() uses ibdev_path for retrieveing
1463 * ifindex if Netlink fails.
1465 mlx5_free_shared_dev_ctx(priv->sh);
1466 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1470 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1471 struct mlx5_priv *opriv =
1472 rte_eth_devices[port_id].data->dev_private;
1475 opriv->domain_id != priv->domain_id ||
1476 &rte_eth_devices[port_id] == dev)
1482 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1484 memset(priv, 0, sizeof(*priv));
1485 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1487 * Reset mac_addrs to NULL such that it is not freed as part of
1488 * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1489 * it is freed when dev_private is freed.
1491 dev->data->mac_addrs = NULL;
1496 * Verify and store value for device argument.
1499 * Key argument to verify.
1501 * Value associated with key.
1506 * 0 on success, a negative errno value otherwise and rte_errno is set.
1509 mlx5_args_check(const char *key, const char *val, void *opaque)
1511 struct mlx5_dev_config *config = opaque;
1515 /* No-op, port representors are processed in mlx5_dev_spawn(). */
1516 if (!strcmp(MLX5_REPRESENTOR, key))
1519 tmp = strtol(val, NULL, 0);
1522 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1525 if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
1526 /* Negative values are acceptable for some keys only. */
1528 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
1531 mod = tmp >= 0 ? tmp : -tmp;
1532 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1533 config->cqe_comp = !!tmp;
1534 } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
1535 config->cqe_pad = !!tmp;
1536 } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1537 config->hw_padding = !!tmp;
1538 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1539 config->mprq.enabled = !!tmp;
1540 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1541 config->mprq.stride_num_n = tmp;
1542 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1543 config->mprq.stride_size_n = tmp;
1544 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1545 config->mprq.max_memcpy_len = tmp;
1546 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1547 config->mprq.min_rxqs_num = tmp;
1548 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1549 DRV_LOG(WARNING, "%s: deprecated parameter,"
1550 " converted to txq_inline_max", key);
1551 config->txq_inline_max = tmp;
1552 } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1553 config->txq_inline_max = tmp;
1554 } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1555 config->txq_inline_min = tmp;
1556 } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1557 config->txq_inline_mpw = tmp;
1558 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1559 config->txqs_inline = tmp;
1560 } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1561 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1562 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1563 config->mps = !!tmp;
1564 } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1565 if (tmp != MLX5_TXDB_CACHED &&
1566 tmp != MLX5_TXDB_NCACHED &&
1567 tmp != MLX5_TXDB_HEURISTIC) {
1568 DRV_LOG(ERR, "invalid Tx doorbell "
1569 "mapping parameter");
1574 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1575 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1576 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1577 DRV_LOG(WARNING, "%s: deprecated parameter,"
1578 " converted to txq_inline_mpw", key);
1579 config->txq_inline_mpw = tmp;
1580 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1581 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1582 } else if (strcmp(MLX5_TX_PP, key) == 0) {
1584 DRV_LOG(ERR, "Zero Tx packet pacing parameter");
1588 config->tx_pp = tmp;
1589 } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
1590 config->tx_skew = tmp;
1591 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1592 config->rx_vec_en = !!tmp;
1593 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1594 config->l3_vxlan_en = !!tmp;
1595 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1596 config->vf_nl_en = !!tmp;
1597 } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1598 config->dv_esw_en = !!tmp;
1599 } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1600 config->dv_flow_en = !!tmp;
1601 } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1602 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1603 tmp != MLX5_XMETA_MODE_META16 &&
1604 tmp != MLX5_XMETA_MODE_META32) {
1605 DRV_LOG(ERR, "invalid extensive "
1606 "metadata parameter");
1610 config->dv_xmeta_en = tmp;
1611 } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
1612 config->lacp_by_user = !!tmp;
1613 } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1614 config->mr_ext_memseg_en = !!tmp;
1615 } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1616 config->max_dump_files_num = tmp;
1617 } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1618 config->lro.timeout = tmp;
1619 } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1620 DRV_LOG(DEBUG, "class argument is %s.", val);
1621 } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1622 config->log_hp_size = tmp;
1623 } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1624 if (tmp != MLX5_RCM_NONE &&
1625 tmp != MLX5_RCM_LIGHT &&
1626 tmp != MLX5_RCM_AGGR) {
1627 DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1631 config->reclaim_mode = tmp;
1632 } else if (strcmp(MLX5_SYS_MEM_EN, key) == 0) {
1633 config->sys_mem_en = !!tmp;
1634 } else if (strcmp(MLX5_DECAP_EN, key) == 0) {
1635 config->decap_en = !!tmp;
1637 DRV_LOG(WARNING, "%s: unknown parameter", key);
1645 * Parse device parameters.
1648 * Pointer to device configuration structure.
1650 * Device arguments structure.
1653 * 0 on success, a negative errno value otherwise and rte_errno is set.
1656 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1658 const char **params = (const char *[]){
1659 MLX5_RXQ_CQE_COMP_EN,
1660 MLX5_RXQ_CQE_PAD_EN,
1661 MLX5_RXQ_PKT_PAD_EN,
1663 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1664 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1665 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1668 MLX5_TXQ_INLINE_MIN,
1669 MLX5_TXQ_INLINE_MAX,
1670 MLX5_TXQ_INLINE_MPW,
1671 MLX5_TXQS_MIN_INLINE,
1674 MLX5_TXQ_MPW_HDR_DSEG_EN,
1675 MLX5_TXQ_MAX_INLINE_LEN,
1687 MLX5_MR_EXT_MEMSEG_EN,
1689 MLX5_MAX_DUMP_FILES_NUM,
1690 MLX5_LRO_TIMEOUT_USEC,
1691 MLX5_CLASS_ARG_NAME,
1698 struct rte_kvargs *kvlist;
1702 if (devargs == NULL)
1704 /* Following UGLY cast is done to pass checkpatch. */
1705 kvlist = rte_kvargs_parse(devargs->args, params);
1706 if (kvlist == NULL) {
1710 /* Process parameters. */
1711 for (i = 0; (params[i] != NULL); ++i) {
1712 if (rte_kvargs_count(kvlist, params[i])) {
1713 ret = rte_kvargs_process(kvlist, params[i],
1714 mlx5_args_check, config);
1717 rte_kvargs_free(kvlist);
1722 rte_kvargs_free(kvlist);
1727 * Configures the minimal amount of data to inline into WQE
1728 * while sending packets.
1730 * - the txq_inline_min has the maximal priority, if this
1731 * key is specified in devargs
1732 * - if DevX is enabled the inline mode is queried from the
1733 * device (HCA attributes and NIC vport context if needed).
1734 * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1735 * and none (0 bytes) for other NICs
1738 * Verbs device parameters (name, port, switch_info) to spawn.
1740 * Device configuration parameters.
1743 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1744 struct mlx5_dev_config *config)
1746 if (config->txq_inline_min != MLX5_ARG_UNSET) {
1747 /* Application defines size of inlined data explicitly. */
1748 switch (spawn->pci_dev->id.device_id) {
1749 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1750 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1751 if (config->txq_inline_min <
1752 (int)MLX5_INLINE_HSIZE_L2) {
1754 "txq_inline_mix aligned to minimal"
1755 " ConnectX-4 required value %d",
1756 (int)MLX5_INLINE_HSIZE_L2);
1757 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1763 if (config->hca_attr.eth_net_offloads) {
1764 /* We have DevX enabled, inline mode queried successfully. */
1765 switch (config->hca_attr.wqe_inline_mode) {
1766 case MLX5_CAP_INLINE_MODE_L2:
1767 /* outer L2 header must be inlined. */
1768 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1770 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1771 /* No inline data are required by NIC. */
1772 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1773 config->hw_vlan_insert =
1774 config->hca_attr.wqe_vlan_insert;
1775 DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1777 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1778 /* inline mode is defined by NIC vport context. */
1779 if (!config->hca_attr.eth_virt)
1781 switch (config->hca_attr.vport_inline_mode) {
1782 case MLX5_INLINE_MODE_NONE:
1783 config->txq_inline_min =
1784 MLX5_INLINE_HSIZE_NONE;
1786 case MLX5_INLINE_MODE_L2:
1787 config->txq_inline_min =
1788 MLX5_INLINE_HSIZE_L2;
1790 case MLX5_INLINE_MODE_IP:
1791 config->txq_inline_min =
1792 MLX5_INLINE_HSIZE_L3;
1794 case MLX5_INLINE_MODE_TCP_UDP:
1795 config->txq_inline_min =
1796 MLX5_INLINE_HSIZE_L4;
1798 case MLX5_INLINE_MODE_INNER_L2:
1799 config->txq_inline_min =
1800 MLX5_INLINE_HSIZE_INNER_L2;
1802 case MLX5_INLINE_MODE_INNER_IP:
1803 config->txq_inline_min =
1804 MLX5_INLINE_HSIZE_INNER_L3;
1806 case MLX5_INLINE_MODE_INNER_TCP_UDP:
1807 config->txq_inline_min =
1808 MLX5_INLINE_HSIZE_INNER_L4;
1814 * We get here if we are unable to deduce
1815 * inline data size with DevX. Try PCI ID
1816 * to determine old NICs.
1818 switch (spawn->pci_dev->id.device_id) {
1819 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1820 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1821 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
1822 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1823 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1824 config->hw_vlan_insert = 0;
1826 case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
1827 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1828 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
1829 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1831 * These NICs support VLAN insertion from WQE and
1832 * report the wqe_vlan_insert flag. But there is the bug
1833 * and PFC control may be broken, so disable feature.
1835 config->hw_vlan_insert = 0;
1836 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1839 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1843 DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
1847 * Configures the metadata mask fields in the shared context.
1850 * Pointer to Ethernet device.
1853 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
1855 struct mlx5_priv *priv = dev->data->dev_private;
1856 struct mlx5_dev_ctx_shared *sh = priv->sh;
1857 uint32_t meta, mark, reg_c0;
1859 reg_c0 = ~priv->vport_meta_mask;
1860 switch (priv->config.dv_xmeta_en) {
1861 case MLX5_XMETA_MODE_LEGACY:
1863 mark = MLX5_FLOW_MARK_MASK;
1865 case MLX5_XMETA_MODE_META16:
1866 meta = reg_c0 >> rte_bsf32(reg_c0);
1867 mark = MLX5_FLOW_MARK_MASK;
1869 case MLX5_XMETA_MODE_META32:
1871 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
1879 if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
1880 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
1881 sh->dv_mark_mask, mark);
1883 sh->dv_mark_mask = mark;
1884 if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
1885 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
1886 sh->dv_meta_mask, meta);
1888 sh->dv_meta_mask = meta;
1889 if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
1890 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
1891 sh->dv_meta_mask, reg_c0);
1893 sh->dv_regc0_mask = reg_c0;
1894 DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
1895 DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
1896 DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
1897 DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
1901 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
1903 static const char *const dynf_names[] = {
1904 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
1905 RTE_MBUF_DYNFLAG_METADATA_NAME,
1906 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
1910 if (n < RTE_DIM(dynf_names))
1912 for (i = 0; i < RTE_DIM(dynf_names); i++) {
1913 if (names[i] == NULL)
1915 strcpy(names[i], dynf_names[i]);
1917 return RTE_DIM(dynf_names);
1921 * Comparison callback to sort device data.
1923 * This is meant to be used with qsort().
1926 * Pointer to pointer to first data object.
1928 * Pointer to pointer to second data object.
1931 * 0 if both objects are equal, less than 0 if the first argument is less
1932 * than the second, greater than 0 otherwise.
1935 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
1936 struct mlx5_dev_config *config)
1938 struct mlx5_dev_ctx_shared *sh = priv->sh;
1939 struct mlx5_dev_config *sh_conf = NULL;
1943 /* Nothing to compare for the single/first device. */
1944 if (sh->refcnt == 1)
1946 /* Find the device with shared context. */
1947 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1948 struct mlx5_priv *opriv =
1949 rte_eth_devices[port_id].data->dev_private;
1951 if (opriv && opriv != priv && opriv->sh == sh) {
1952 sh_conf = &opriv->config;
1958 if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
1959 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
1960 " for shared %s context", sh->ibdev_name);
1964 if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
1965 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
1966 " for shared %s context", sh->ibdev_name);
1974 * Look for the ethernet device belonging to mlx5 driver.
1976 * @param[in] port_id
1977 * port_id to start looking for device.
1978 * @param[in] pci_dev
1979 * Pointer to the hint PCI device. When device is being probed
1980 * the its siblings (master and preceding representors might
1981 * not have assigned driver yet (because the mlx5_os_pci_probe()
1982 * is not completed yet, for this case match on hint PCI
1983 * device may be used to detect sibling device.
1986 * port_id of found device, RTE_MAX_ETHPORT if not found.
1989 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
1991 while (port_id < RTE_MAX_ETHPORTS) {
1992 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
1994 if (dev->state != RTE_ETH_DEV_UNUSED &&
1996 (dev->device == &pci_dev->device ||
1997 (dev->device->driver &&
1998 dev->device->driver->name &&
1999 !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
2003 if (port_id >= RTE_MAX_ETHPORTS)
2004 return RTE_MAX_ETHPORTS;
2009 * DPDK callback to remove a PCI device.
2011 * This function removes all Ethernet devices belong to a given PCI device.
2013 * @param[in] pci_dev
2014 * Pointer to the PCI device.
2017 * 0 on success, the function cannot fail.
2020 mlx5_pci_remove(struct rte_pci_device *pci_dev)
2024 RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
2026 * mlx5_dev_close() is not registered to secondary process,
2027 * call the close function explicitly for secondary process.
2029 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
2030 mlx5_dev_close(&rte_eth_devices[port_id]);
2032 rte_eth_dev_close(port_id);
2037 static const struct rte_pci_id mlx5_pci_id_map[] = {
2039 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2040 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
2043 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2044 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
2047 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2048 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
2051 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2052 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
2055 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2056 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
2059 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2060 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
2063 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2064 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
2067 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2068 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
2071 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2072 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
2075 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2076 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
2079 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2080 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
2083 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2084 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
2087 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2088 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
2091 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2092 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF)
2095 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2096 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
2099 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2100 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
2107 static struct mlx5_pci_driver mlx5_driver = {
2108 .driver_class = MLX5_CLASS_NET,
2111 .name = MLX5_DRIVER_NAME,
2113 .id_table = mlx5_pci_id_map,
2114 .probe = mlx5_os_pci_probe,
2115 .remove = mlx5_pci_remove,
2116 .dma_map = mlx5_dma_map,
2117 .dma_unmap = mlx5_dma_unmap,
2118 .drv_flags = PCI_DRV_FLAGS,
2122 /* Initialize driver log type. */
2123 RTE_LOG_REGISTER(mlx5_logtype, pmd.net.mlx5, NOTICE)
2126 * Driver initialization routine.
2128 RTE_INIT(rte_mlx5_pmd_init)
2131 /* Build the static tables for Verbs conversion. */
2132 mlx5_set_ptype_table();
2133 mlx5_set_cksum_table();
2134 mlx5_set_swp_types_table();
2136 mlx5_pci_driver_register(&mlx5_driver);
2139 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
2140 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
2141 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");