drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <stdint.h>
  10 #include <stdlib.h>
  11 #include <errno.h>
  12 #include <net/if.h>
  13 #include <sys/mman.h>
  14 #include <linux/rtnetlink.h>
  15
  16 /* Verbs header. */
  17 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  18 #ifdef PEDANTIC
  19 #pragma GCC diagnostic ignored "-Wpedantic"
  20 #endif
  21 #include <infiniband/verbs.h>
  22 #ifdef PEDANTIC
  23 #pragma GCC diagnostic error "-Wpedantic"
  24 #endif
  25
  26 #include <rte_malloc.h>
  27 #include <rte_ethdev_driver.h>
  28 #include <rte_ethdev_pci.h>
  29 #include <rte_pci.h>
  30 #include <rte_bus_pci.h>
  31 #include <rte_common.h>
  32 #include <rte_kvargs.h>
  33 #include <rte_rwlock.h>
  34 #include <rte_spinlock.h>
  35 #include <rte_string_fns.h>
  36 #include <rte_alarm.h>
  37
  38 #include <mlx5_glue.h>
  39 #include <mlx5_devx_cmds.h>
  40 #include <mlx5_common.h>
  41
  42 #include "mlx5_defs.h"
  43 #include "mlx5.h"
  44 #include "mlx5_utils.h"
  45 #include "mlx5_rxtx.h"
  46 #include "mlx5_autoconf.h"
  47 #include "mlx5_mr.h"
  48 #include "mlx5_flow.h"
  49 #include "rte_pmd_mlx5.h"
  50
  51 /* Device parameter to enable RX completion queue compression. */
  52 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  53
  54 /* Device parameter to enable RX completion entry padding to 128B. */
  55 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
  56
  57 /* Device parameter to enable padding Rx packet to cacheline size. */
  58 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
  59
  60 /* Device parameter to enable Multi-Packet Rx queue. */
  61 #define MLX5_RX_MPRQ_EN "mprq_en"
  62
  63 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
  64 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
  65
  66 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
  67 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
  68
  69 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
  70 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
  71
  72 /* Device parameter to configure inline send. Deprecated, ignored.*/
  73 #define MLX5_TXQ_INLINE "txq_inline"
  74
  75 /* Device parameter to limit packet size to inline with ordinary SEND. */
  76 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
  77
  78 /* Device parameter to configure minimal data size to inline. */
  79 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
  80
  81 /* Device parameter to limit packet size to inline with Enhanced MPW. */
  82 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
  83
  84 /*
  85  * Device parameter to configure the number of TX queues threshold for
  86  * enabling inline send.
  87  */
  88 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  89
  90 /*
  91  * Device parameter to configure the number of TX queues threshold for
  92  * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
  93  */
  94 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
  95
  96 /* Device parameter to enable multi-packet send WQEs. */
  97 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
  98
  99 /*
 100  * Device parameter to force doorbell register mapping
 101  * to non-cahed region eliminating the extra write memory barrier.
 102  */
 103 #define MLX5_TX_DB_NC "tx_db_nc"
 104
 105 /*
 106  * Device parameter to include 2 dsegs in the title WQEBB.
 107  * Deprecated, ignored.
 108  */
 109 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
 110
 111 /*
 112  * Device parameter to limit the size of inlining packet.
 113  * Deprecated, ignored.
 114  */
 115 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
 116
 117 /*
 118  * Device parameter to enable hardware Tx vector.
 119  * Deprecated, ignored (no vectorized Tx routines anymore).
 120  */
 121 #define MLX5_TX_VEC_EN "tx_vec_en"
 122
 123 /* Device parameter to enable hardware Rx vector. */
 124 #define MLX5_RX_VEC_EN "rx_vec_en"
 125
 126 /* Allow L3 VXLAN flow creation. */
 127 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
 128
 129 /* Activate DV E-Switch flow steering. */
 130 #define MLX5_DV_ESW_EN "dv_esw_en"
 131
 132 /* Activate DV flow steering. */
 133 #define MLX5_DV_FLOW_EN "dv_flow_en"
 134
 135 /* Enable extensive flow metadata support. */
 136 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
 137
 138 /* Activate Netlink support in VF mode. */
 139 #define MLX5_VF_NL_EN "vf_nl_en"
 140
 141 /* Enable extending memsegs when creating a MR. */
 142 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
 143
 144 /* Select port representors to instantiate. */
 145 #define MLX5_REPRESENTOR "representor"
 146
 147 /* Device parameter to configure the maximum number of dump files per queue. */
 148 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
 149
 150 /* Configure timeout of LRO session (in microseconds). */
 151 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
 152
 153 /*
 154  * Device parameter to configure the total data buffer size for a single
 155  * hairpin queue (logarithm value).
 156  */
 157 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
 158
 159 #ifndef HAVE_IBV_MLX5_MOD_MPW
 160 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2)
 161 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3)
 162 #endif
 163
 164 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP
 165 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4)
 166 #endif
 167
 168 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
 169
 170 /* Shared memory between primary and secondary processes. */
 171 struct mlx5_shared_data *mlx5_shared_data;
 172
 173 /* Spinlock for mlx5_shared_data allocation. */
 174 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
 175
 176 /* Process local data for secondary processes. */
 177 static struct mlx5_local_data mlx5_local_data;
 178
 179 /** Driver-specific log messages type. */
 180 int mlx5_logtype;
 181
 182 /** Data associated with devices to spawn. */
 183 struct mlx5_dev_spawn_data {
 184         uint32_t ifindex; /**< Network interface index. */
 185         uint32_t max_port; /**< IB device maximal port index. */
 186         uint32_t ibv_port; /**< IB device physical port index. */
 187         int pf_bond; /**< bonding device PF index. < 0 - no bonding */
 188         struct mlx5_switch_info info; /**< Switch information. */
 189         struct ibv_device *ibv_dev; /**< Associated IB device. */
 190         struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */
 191         struct rte_pci_device *pci_dev; /**< Backend PCI device. */
 192 };
 193
 194 static LIST_HEAD(, mlx5_ibv_shared) mlx5_ibv_list = LIST_HEAD_INITIALIZER();
 195 static pthread_mutex_t mlx5_ibv_list_mutex = PTHREAD_MUTEX_INITIALIZER;
 196
 197 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
 198 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
 199
 200 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
 201 #define MLX5_TAGS_HLIST_ARRAY_SIZE 8192
 202
 203 /**
 204  * Allocate ID pool structure.
 205  *
 206  * @param[in] max_id
 207  *   The maximum id can be allocated from the pool.
 208  *
 209  * @return
 210  *   Pointer to pool object, NULL value otherwise.
 211  */
 212 struct mlx5_flow_id_pool *
 213 mlx5_flow_id_pool_alloc(uint32_t max_id)
 214 {
 215         struct mlx5_flow_id_pool *pool;
 216         void *mem;
 217
 218         pool = rte_zmalloc("id pool allocation", sizeof(*pool),
 219                            RTE_CACHE_LINE_SIZE);
 220         if (!pool) {
 221                 DRV_LOG(ERR, "can't allocate id pool");
 222                 rte_errno  = ENOMEM;
 223                 return NULL;
 224         }
 225         mem = rte_zmalloc("", MLX5_FLOW_MIN_ID_POOL_SIZE * sizeof(uint32_t),
 226                           RTE_CACHE_LINE_SIZE);
 227         if (!mem) {
 228                 DRV_LOG(ERR, "can't allocate mem for id pool");
 229                 rte_errno  = ENOMEM;
 230                 goto error;
 231         }
 232         pool->free_arr = mem;
 233         pool->curr = pool->free_arr;
 234         pool->last = pool->free_arr + MLX5_FLOW_MIN_ID_POOL_SIZE;
 235         pool->base_index = 0;
 236         pool->max_id = max_id;
 237         return pool;
 238 error:
 239         rte_free(pool);
 240         return NULL;
 241 }
 242
 243 /**
 244  * Release ID pool structure.
 245  *
 246  * @param[in] pool
 247  *   Pointer to flow id pool object to free.
 248  */
 249 void
 250 mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool)
 251 {
 252         rte_free(pool->free_arr);
 253         rte_free(pool);
 254 }
 255
 256 /**
 257  * Generate ID.
 258  *
 259  * @param[in] pool
 260  *   Pointer to flow id pool.
 261  * @param[out] id
 262  *   The generated ID.
 263  *
 264  * @return
 265  *   0 on success, error value otherwise.
 266  */
 267 uint32_t
 268 mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id)
 269 {
 270         if (pool->curr == pool->free_arr) {
 271                 if (pool->base_index == pool->max_id) {
 272                         rte_errno  = ENOMEM;
 273                         DRV_LOG(ERR, "no free id");
 274                         return -rte_errno;
 275                 }
 276                 *id = ++pool->base_index;
 277                 return 0;
 278         }
 279         *id = *(--pool->curr);
 280         return 0;
 281 }
 282
 283 /**
 284  * Release ID.
 285  *
 286  * @param[in] pool
 287  *   Pointer to flow id pool.
 288  * @param[out] id
 289  *   The generated ID.
 290  *
 291  * @return
 292  *   0 on success, error value otherwise.
 293  */
 294 uint32_t
 295 mlx5_flow_id_release(struct mlx5_flow_id_pool *pool, uint32_t id)
 296 {
 297         uint32_t size;
 298         uint32_t size2;
 299         void *mem;
 300
 301         if (pool->curr == pool->last) {
 302                 size = pool->curr - pool->free_arr;
 303                 size2 = size * MLX5_ID_GENERATION_ARRAY_FACTOR;
 304                 MLX5_ASSERT(size2 > size);
 305                 mem = rte_malloc("", size2 * sizeof(uint32_t), 0);
 306                 if (!mem) {
 307                         DRV_LOG(ERR, "can't allocate mem for id pool");
 308                         rte_errno  = ENOMEM;
 309                         return -rte_errno;
 310                 }
 311                 memcpy(mem, pool->free_arr, size * sizeof(uint32_t));
 312                 rte_free(pool->free_arr);
 313                 pool->free_arr = mem;
 314                 pool->curr = pool->free_arr + size;
 315                 pool->last = pool->free_arr + size2;
 316         }
 317         *pool->curr = id;
 318         pool->curr++;
 319         return 0;
 320 }
 321
 322 /**
 323  * Initialize the counters management structure.
 324  *
 325  * @param[in] sh
 326  *   Pointer to mlx5_ibv_shared object to free
 327  */
 328 static void
 329 mlx5_flow_counters_mng_init(struct mlx5_ibv_shared *sh)
 330 {
 331         uint8_t i;
 332
 333         TAILQ_INIT(&sh->cmng.flow_counters);
 334         for (i = 0; i < RTE_DIM(sh->cmng.ccont); ++i)
 335                 TAILQ_INIT(&sh->cmng.ccont[i].pool_list);
 336 }
 337
 338 /**
 339  * Destroy all the resources allocated for a counter memory management.
 340  *
 341  * @param[in] mng
 342  *   Pointer to the memory management structure.
 343  */
 344 static void
 345 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
 346 {
 347         uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
 348
 349         LIST_REMOVE(mng, next);
 350         claim_zero(mlx5_devx_cmd_destroy(mng->dm));
 351         claim_zero(mlx5_glue->devx_umem_dereg(mng->umem));
 352         rte_free(mem);
 353 }
 354
 355 /**
 356  * Close and release all the resources of the counters management.
 357  *
 358  * @param[in] sh
 359  *   Pointer to mlx5_ibv_shared object to free.
 360  */
 361 static void
 362 mlx5_flow_counters_mng_close(struct mlx5_ibv_shared *sh)
 363 {
 364         struct mlx5_counter_stats_mem_mng *mng;
 365         uint8_t i;
 366         int j;
 367         int retries = 1024;
 368
 369         rte_errno = 0;
 370         while (--retries) {
 371                 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
 372                 if (rte_errno != EINPROGRESS)
 373                         break;
 374                 rte_pause();
 375         }
 376         for (i = 0; i < RTE_DIM(sh->cmng.ccont); ++i) {
 377                 struct mlx5_flow_counter_pool *pool;
 378                 uint32_t batch = !!(i % 2);
 379
 380                 if (!sh->cmng.ccont[i].pools)
 381                         continue;
 382                 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
 383                 while (pool) {
 384                         if (batch) {
 385                                 if (pool->min_dcs)
 386                                         claim_zero
 387                                         (mlx5_devx_cmd_destroy(pool->min_dcs));
 388                         }
 389                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
 390                                 if (pool->counters_raw[j].action)
 391                                         claim_zero
 392                                         (mlx5_glue->destroy_flow_action
 393                                                (pool->counters_raw[j].action));
 394                                 if (!batch && MLX5_GET_POOL_CNT_EXT
 395                                     (pool, j)->dcs)
 396                                         claim_zero(mlx5_devx_cmd_destroy
 397                                                   (MLX5_GET_POOL_CNT_EXT
 398                                                   (pool, j)->dcs));
 399                         }
 400                         TAILQ_REMOVE(&sh->cmng.ccont[i].pool_list, pool,
 401                                      next);
 402                         rte_free(pool);
 403                         pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
 404                 }
 405                 rte_free(sh->cmng.ccont[i].pools);
 406         }
 407         mng = LIST_FIRST(&sh->cmng.mem_mngs);
 408         while (mng) {
 409                 mlx5_flow_destroy_counter_stat_mem_mng(mng);
 410                 mng = LIST_FIRST(&sh->cmng.mem_mngs);
 411         }
 412         memset(&sh->cmng, 0, sizeof(sh->cmng));
 413 }
 414
 415 /**
 416  * Extract pdn of PD object using DV API.
 417  *
 418  * @param[in] pd
 419  *   Pointer to the verbs PD object.
 420  * @param[out] pdn
 421  *   Pointer to the PD object number variable.
 422  *
 423  * @return
 424  *   0 on success, error value otherwise.
 425  */
 426 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 427 static int
 428 mlx5_get_pdn(struct ibv_pd *pd __rte_unused, uint32_t *pdn __rte_unused)
 429 {
 430         struct mlx5dv_obj obj;
 431         struct mlx5dv_pd pd_info;
 432         int ret = 0;
 433
 434         obj.pd.in = pd;
 435         obj.pd.out = &pd_info;
 436         ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD);
 437         if (ret) {
 438                 DRV_LOG(DEBUG, "Fail to get PD object info");
 439                 return ret;
 440         }
 441         *pdn = pd_info.pdn;
 442         return 0;
 443 }
 444 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
 445
 446 static int
 447 mlx5_config_doorbell_mapping_env(const struct mlx5_dev_config *config)
 448 {
 449         char *env;
 450         int value;
 451
 452         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 453         /* Get environment variable to store. */
 454         env = getenv(MLX5_SHUT_UP_BF);
 455         value = env ? !!strcmp(env, "0") : MLX5_ARG_UNSET;
 456         if (config->dbnc == MLX5_ARG_UNSET)
 457                 setenv(MLX5_SHUT_UP_BF, MLX5_SHUT_UP_BF_DEFAULT, 1);
 458         else
 459                 setenv(MLX5_SHUT_UP_BF,
 460                        config->dbnc == MLX5_TXDB_NCACHED ? "1" : "0", 1);
 461         return value;
 462 }
 463
 464 static void
 465 mlx5_restore_doorbell_mapping_env(int value)
 466 {
 467         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 468         /* Restore the original environment variable state. */
 469         if (value == MLX5_ARG_UNSET)
 470                 unsetenv(MLX5_SHUT_UP_BF);
 471         else
 472                 setenv(MLX5_SHUT_UP_BF, value ? "1" : "0", 1);
 473 }
 474
 475 /**
 476  * Allocate shared IB device context. If there is multiport device the
 477  * master and representors will share this context, if there is single
 478  * port dedicated IB device, the context will be used by only given
 479  * port due to unification.
 480  *
 481  * Routine first searches the context for the specified IB device name,
 482  * if found the shared context assumed and reference counter is incremented.
 483  * If no context found the new one is created and initialized with specified
 484  * IB device context and parameters.
 485  *
 486  * @param[in] spawn
 487  *   Pointer to the IB device attributes (name, port, etc).
 488  * @param[in] config
 489  *   Pointer to device configuration structure.
 490  *
 491  * @return
 492  *   Pointer to mlx5_ibv_shared object on success,
 493  *   otherwise NULL and rte_errno is set.
 494  */
 495 static struct mlx5_ibv_shared *
 496 mlx5_alloc_shared_ibctx(const struct mlx5_dev_spawn_data *spawn,
 497                         const struct mlx5_dev_config *config)
 498 {
 499         struct mlx5_ibv_shared *sh;
 500         int dbmap_env;
 501         int err = 0;
 502         uint32_t i;
 503 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 504         struct mlx5_devx_tis_attr tis_attr = { 0 };
 505 #endif
 506
 507         MLX5_ASSERT(spawn);
 508         /* Secondary process should not create the shared context. */
 509         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 510         pthread_mutex_lock(&mlx5_ibv_list_mutex);
 511         /* Search for IB context by device name. */
 512         LIST_FOREACH(sh, &mlx5_ibv_list, next) {
 513                 if (!strcmp(sh->ibdev_name, spawn->ibv_dev->name)) {
 514                         sh->refcnt++;
 515                         goto exit;
 516                 }
 517         }
 518         /* No device found, we have to create new shared context. */
 519         MLX5_ASSERT(spawn->max_port);
 520         sh = rte_zmalloc("ethdev shared ib context",
 521                          sizeof(struct mlx5_ibv_shared) +
 522                          spawn->max_port *
 523                          sizeof(struct mlx5_ibv_shared_port),
 524                          RTE_CACHE_LINE_SIZE);
 525         if (!sh) {
 526                 DRV_LOG(ERR, "shared context allocation failure");
 527                 rte_errno  = ENOMEM;
 528                 goto exit;
 529         }
 530         /*
 531          * Configure environment variable "MLX5_BF_SHUT_UP"
 532          * before the device creation. The rdma_core library
 533          * checks the variable at device creation and
 534          * stores the result internally.
 535          */
 536         dbmap_env = mlx5_config_doorbell_mapping_env(config);
 537         /* Try to open IB device with DV first, then usual Verbs. */
 538         errno = 0;
 539         sh->ctx = mlx5_glue->dv_open_device(spawn->ibv_dev);
 540         if (sh->ctx) {
 541                 sh->devx = 1;
 542                 DRV_LOG(DEBUG, "DevX is supported");
 543                 /* The device is created, no need for environment. */
 544                 mlx5_restore_doorbell_mapping_env(dbmap_env);
 545         } else {
 546                 /* The environment variable is still configured. */
 547                 sh->ctx = mlx5_glue->open_device(spawn->ibv_dev);
 548                 err = errno ? errno : ENODEV;
 549                 /*
 550                  * The environment variable is not needed anymore,
 551                  * all device creation attempts are completed.
 552                  */
 553                 mlx5_restore_doorbell_mapping_env(dbmap_env);
 554                 if (!sh->ctx)
 555                         goto error;
 556                 DRV_LOG(DEBUG, "DevX is NOT supported");
 557         }
 558         err = mlx5_glue->query_device_ex(sh->ctx, NULL, &sh->device_attr);
 559         if (err) {
 560                 DRV_LOG(DEBUG, "ibv_query_device_ex() failed");
 561                 goto error;
 562         }
 563         sh->refcnt = 1;
 564         sh->max_port = spawn->max_port;
 565         strncpy(sh->ibdev_name, sh->ctx->device->name,
 566                 sizeof(sh->ibdev_name));
 567         strncpy(sh->ibdev_path, sh->ctx->device->ibdev_path,
 568                 sizeof(sh->ibdev_path));
 569         pthread_mutex_init(&sh->intr_mutex, NULL);
 570         /*
 571          * Setting port_id to max unallowed value means
 572          * there is no interrupt subhandler installed for
 573          * the given port index i.
 574          */
 575         for (i = 0; i < sh->max_port; i++) {
 576                 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
 577                 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
 578         }
 579         sh->pd = mlx5_glue->alloc_pd(sh->ctx);
 580         if (sh->pd == NULL) {
 581                 DRV_LOG(ERR, "PD allocation failure");
 582                 err = ENOMEM;
 583                 goto error;
 584         }
 585 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 586         if (sh->devx) {
 587                 err = mlx5_get_pdn(sh->pd, &sh->pdn);
 588                 if (err) {
 589                         DRV_LOG(ERR, "Fail to extract pdn from PD");
 590                         goto error;
 591                 }
 592                 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
 593                 if (!sh->td) {
 594                         DRV_LOG(ERR, "TD allocation failure");
 595                         err = ENOMEM;
 596                         goto error;
 597                 }
 598                 tis_attr.transport_domain = sh->td->id;
 599                 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
 600                 if (!sh->tis) {
 601                         DRV_LOG(ERR, "TIS allocation failure");
 602                         err = ENOMEM;
 603                         goto error;
 604                 }
 605         }
 606         sh->flow_id_pool = mlx5_flow_id_pool_alloc(UINT32_MAX);
 607         if (!sh->flow_id_pool) {
 608                 DRV_LOG(ERR, "can't create flow id pool");
 609                 err = ENOMEM;
 610                 goto error;
 611         }
 612 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
 613         /*
 614          * Once the device is added to the list of memory event
 615          * callback, its global MR cache table cannot be expanded
 616          * on the fly because of deadlock. If it overflows, lookup
 617          * should be done by searching MR list linearly, which is slow.
 618          *
 619          * At this point the device is not added to the memory
 620          * event list yet, context is just being created.
 621          */
 622         err = mlx5_mr_btree_init(&sh->mr.cache,
 623                                  MLX5_MR_BTREE_CACHE_N * 2,
 624                                  spawn->pci_dev->device.numa_node);
 625         if (err) {
 626                 err = rte_errno;
 627                 goto error;
 628         }
 629         mlx5_flow_counters_mng_init(sh);
 630         /* Add device to memory callback list. */
 631         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
 632         LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
 633                          sh, mem_event_cb);
 634         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
 635         /* Add context to the global device list. */
 636         LIST_INSERT_HEAD(&mlx5_ibv_list, sh, next);
 637 exit:
 638         pthread_mutex_unlock(&mlx5_ibv_list_mutex);
 639         return sh;
 640 error:
 641         pthread_mutex_unlock(&mlx5_ibv_list_mutex);
 642         MLX5_ASSERT(sh);
 643         if (sh->tis)
 644                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
 645         if (sh->td)
 646                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
 647         if (sh->pd)
 648                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
 649         if (sh->ctx)
 650                 claim_zero(mlx5_glue->close_device(sh->ctx));
 651         if (sh->flow_id_pool)
 652                 mlx5_flow_id_pool_release(sh->flow_id_pool);
 653         rte_free(sh);
 654         MLX5_ASSERT(err > 0);
 655         rte_errno = err;
 656         return NULL;
 657 }
 658
 659 /**
 660  * Free shared IB device context. Decrement counter and if zero free
 661  * all allocated resources and close handles.
 662  *
 663  * @param[in] sh
 664  *   Pointer to mlx5_ibv_shared object to free
 665  */
 666 static void
 667 mlx5_free_shared_ibctx(struct mlx5_ibv_shared *sh)
 668 {
 669         pthread_mutex_lock(&mlx5_ibv_list_mutex);
 670 #ifdef RTE_LIBRTE_MLX5_DEBUG
 671         /* Check the object presence in the list. */
 672         struct mlx5_ibv_shared *lctx;
 673
 674         LIST_FOREACH(lctx, &mlx5_ibv_list, next)
 675                 if (lctx == sh)
 676                         break;
 677         MLX5_ASSERT(lctx);
 678         if (lctx != sh) {
 679                 DRV_LOG(ERR, "Freeing non-existing shared IB context");
 680                 goto exit;
 681         }
 682 #endif
 683         MLX5_ASSERT(sh);
 684         MLX5_ASSERT(sh->refcnt);
 685         /* Secondary process should not free the shared context. */
 686         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 687         if (--sh->refcnt)
 688                 goto exit;
 689         /* Remove from memory callback device list. */
 690         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
 691         LIST_REMOVE(sh, mem_event_cb);
 692         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
 693         /* Release created Memory Regions. */
 694         mlx5_mr_release(sh);
 695         /* Remove context from the global device list. */
 696         LIST_REMOVE(sh, next);
 697         /*
 698          *  Ensure there is no async event handler installed.
 699          *  Only primary process handles async device events.
 700          **/
 701         mlx5_flow_counters_mng_close(sh);
 702         MLX5_ASSERT(!sh->intr_cnt);
 703         if (sh->intr_cnt)
 704                 mlx5_intr_callback_unregister
 705                         (&sh->intr_handle, mlx5_dev_interrupt_handler, sh);
 706 #ifdef HAVE_MLX5_DEVX_ASYNC_SUPPORT
 707         if (sh->devx_intr_cnt) {
 708                 if (sh->intr_handle_devx.fd)
 709                         rte_intr_callback_unregister(&sh->intr_handle_devx,
 710                                           mlx5_dev_interrupt_handler_devx, sh);
 711                 if (sh->devx_comp)
 712                         mlx5dv_devx_destroy_cmd_comp(sh->devx_comp);
 713         }
 714 #endif
 715         pthread_mutex_destroy(&sh->intr_mutex);
 716         if (sh->pd)
 717                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
 718         if (sh->tis)
 719                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
 720         if (sh->td)
 721                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
 722         if (sh->ctx)
 723                 claim_zero(mlx5_glue->close_device(sh->ctx));
 724         if (sh->flow_id_pool)
 725                 mlx5_flow_id_pool_release(sh->flow_id_pool);
 726         rte_free(sh);
 727 exit:
 728         pthread_mutex_unlock(&mlx5_ibv_list_mutex);
 729 }
 730
 731 /**
 732  * Destroy table hash list and all the root entries per domain.
 733  *
 734  * @param[in] priv
 735  *   Pointer to the private device data structure.
 736  */
 737 static void
 738 mlx5_free_table_hash_list(struct mlx5_priv *priv)
 739 {
 740         struct mlx5_ibv_shared *sh = priv->sh;
 741         struct mlx5_flow_tbl_data_entry *tbl_data;
 742         union mlx5_flow_tbl_key table_key = {
 743                 {
 744                         .table_id = 0,
 745                         .reserved = 0,
 746                         .domain = 0,
 747                         .direction = 0,
 748                 }
 749         };
 750         struct mlx5_hlist_entry *pos;
 751
 752         if (!sh->flow_tbls)
 753                 return;
 754         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 755         if (pos) {
 756                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 757                                         entry);
 758                 MLX5_ASSERT(tbl_data);
 759                 mlx5_hlist_remove(sh->flow_tbls, pos);
 760                 rte_free(tbl_data);
 761         }
 762         table_key.direction = 1;
 763         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 764         if (pos) {
 765                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 766                                         entry);
 767                 MLX5_ASSERT(tbl_data);
 768                 mlx5_hlist_remove(sh->flow_tbls, pos);
 769                 rte_free(tbl_data);
 770         }
 771         table_key.direction = 0;
 772         table_key.domain = 1;
 773         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 774         if (pos) {
 775                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 776                                         entry);
 777                 MLX5_ASSERT(tbl_data);
 778                 mlx5_hlist_remove(sh->flow_tbls, pos);
 779                 rte_free(tbl_data);
 780         }
 781         mlx5_hlist_destroy(sh->flow_tbls, NULL, NULL);
 782 }
 783
 784 /**
 785  * Initialize flow table hash list and create the root tables entry
 786  * for each domain.
 787  *
 788  * @param[in] priv
 789  *   Pointer to the private device data structure.
 790  *
 791  * @return
 792  *   Zero on success, positive error code otherwise.
 793  */
 794 static int
 795 mlx5_alloc_table_hash_list(struct mlx5_priv *priv)
 796 {
 797         struct mlx5_ibv_shared *sh = priv->sh;
 798         char s[MLX5_HLIST_NAMESIZE];
 799         int err = 0;
 800
 801         MLX5_ASSERT(sh);
 802         snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
 803         sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE);
 804         if (!sh->flow_tbls) {
 805                 DRV_LOG(ERR, "flow tables with hash creation failed.\n");
 806                 err = ENOMEM;
 807                 return err;
 808         }
 809 #ifndef HAVE_MLX5DV_DR
 810         /*
 811          * In case we have not DR support, the zero tables should be created
 812          * because DV expect to see them even if they cannot be created by
 813          * RDMA-CORE.
 814          */
 815         union mlx5_flow_tbl_key table_key = {
 816                 {
 817                         .table_id = 0,
 818                         .reserved = 0,
 819                         .domain = 0,
 820                         .direction = 0,
 821                 }
 822         };
 823         struct mlx5_flow_tbl_data_entry *tbl_data = rte_zmalloc(NULL,
 824                                                           sizeof(*tbl_data), 0);
 825
 826         if (!tbl_data) {
 827                 err = ENOMEM;
 828                 goto error;
 829         }
 830         tbl_data->entry.key = table_key.v64;
 831         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
 832         if (err)
 833                 goto error;
 834         rte_atomic32_init(&tbl_data->tbl.refcnt);
 835         rte_atomic32_inc(&tbl_data->tbl.refcnt);
 836         table_key.direction = 1;
 837         tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
 838         if (!tbl_data) {
 839                 err = ENOMEM;
 840                 goto error;
 841         }
 842         tbl_data->entry.key = table_key.v64;
 843         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
 844         if (err)
 845                 goto error;
 846         rte_atomic32_init(&tbl_data->tbl.refcnt);
 847         rte_atomic32_inc(&tbl_data->tbl.refcnt);
 848         table_key.direction = 0;
 849         table_key.domain = 1;
 850         tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
 851         if (!tbl_data) {
 852                 err = ENOMEM;
 853                 goto error;
 854         }
 855         tbl_data->entry.key = table_key.v64;
 856         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
 857         if (err)
 858                 goto error;
 859         rte_atomic32_init(&tbl_data->tbl.refcnt);
 860         rte_atomic32_inc(&tbl_data->tbl.refcnt);
 861         return err;
 862 error:
 863         mlx5_free_table_hash_list(priv);
 864 #endif /* HAVE_MLX5DV_DR */
 865         return err;
 866 }
 867
 868 /**
 869  * Initialize DR related data within private structure.
 870  * Routine checks the reference counter and does actual
 871  * resources creation/initialization only if counter is zero.
 872  *
 873  * @param[in] priv
 874  *   Pointer to the private device data structure.
 875  *
 876  * @return
 877  *   Zero on success, positive error code otherwise.
 878  */
 879 static int
 880 mlx5_alloc_shared_dr(struct mlx5_priv *priv)
 881 {
 882         struct mlx5_ibv_shared *sh = priv->sh;
 883         char s[MLX5_HLIST_NAMESIZE];
 884         int err = 0;
 885
 886         if (!sh->flow_tbls)
 887                 err = mlx5_alloc_table_hash_list(priv);
 888         else
 889                 DRV_LOG(DEBUG, "sh->flow_tbls[%p] already created, reuse\n",
 890                         (void *)sh->flow_tbls);
 891         if (err)
 892                 return err;
 893         /* Create tags hash list table. */
 894         snprintf(s, sizeof(s), "%s_tags", sh->ibdev_name);
 895         sh->tag_table = mlx5_hlist_create(s, MLX5_TAGS_HLIST_ARRAY_SIZE);
 896         if (!sh->tag_table) {
 897                 DRV_LOG(ERR, "tags with hash creation failed.\n");
 898                 err = ENOMEM;
 899                 goto error;
 900         }
 901 #ifdef HAVE_MLX5DV_DR
 902         void *domain;
 903
 904         if (sh->dv_refcnt) {
 905                 /* Shared DV/DR structures is already initialized. */
 906                 sh->dv_refcnt++;
 907                 priv->dr_shared = 1;
 908                 return 0;
 909         }
 910         /* Reference counter is zero, we should initialize structures. */
 911         domain = mlx5_glue->dr_create_domain(sh->ctx,
 912                                              MLX5DV_DR_DOMAIN_TYPE_NIC_RX);
 913         if (!domain) {
 914                 DRV_LOG(ERR, "ingress mlx5dv_dr_create_domain failed");
 915                 err = errno;
 916                 goto error;
 917         }
 918         sh->rx_domain = domain;
 919         domain = mlx5_glue->dr_create_domain(sh->ctx,
 920                                              MLX5DV_DR_DOMAIN_TYPE_NIC_TX);
 921         if (!domain) {
 922                 DRV_LOG(ERR, "egress mlx5dv_dr_create_domain failed");
 923                 err = errno;
 924                 goto error;
 925         }
 926         pthread_mutex_init(&sh->dv_mutex, NULL);
 927         sh->tx_domain = domain;
 928 #ifdef HAVE_MLX5DV_DR_ESWITCH
 929         if (priv->config.dv_esw_en) {
 930                 domain  = mlx5_glue->dr_create_domain
 931                         (sh->ctx, MLX5DV_DR_DOMAIN_TYPE_FDB);
 932                 if (!domain) {
 933                         DRV_LOG(ERR, "FDB mlx5dv_dr_create_domain failed");
 934                         err = errno;
 935                         goto error;
 936                 }
 937                 sh->fdb_domain = domain;
 938                 sh->esw_drop_action = mlx5_glue->dr_create_flow_action_drop();
 939         }
 940 #endif
 941         sh->pop_vlan_action = mlx5_glue->dr_create_flow_action_pop_vlan();
 942 #endif /* HAVE_MLX5DV_DR */
 943         sh->dv_refcnt++;
 944         priv->dr_shared = 1;
 945         return 0;
 946 error:
 947         /* Rollback the created objects. */
 948         if (sh->rx_domain) {
 949                 mlx5_glue->dr_destroy_domain(sh->rx_domain);
 950                 sh->rx_domain = NULL;
 951         }
 952         if (sh->tx_domain) {
 953                 mlx5_glue->dr_destroy_domain(sh->tx_domain);
 954                 sh->tx_domain = NULL;
 955         }
 956         if (sh->fdb_domain) {
 957                 mlx5_glue->dr_destroy_domain(sh->fdb_domain);
 958                 sh->fdb_domain = NULL;
 959         }
 960         if (sh->esw_drop_action) {
 961                 mlx5_glue->destroy_flow_action(sh->esw_drop_action);
 962                 sh->esw_drop_action = NULL;
 963         }
 964         if (sh->pop_vlan_action) {
 965                 mlx5_glue->destroy_flow_action(sh->pop_vlan_action);
 966                 sh->pop_vlan_action = NULL;
 967         }
 968         if (sh->tag_table) {
 969                 /* tags should be destroyed with flow before. */
 970                 mlx5_hlist_destroy(sh->tag_table, NULL, NULL);
 971                 sh->tag_table = NULL;
 972         }
 973         mlx5_free_table_hash_list(priv);
 974         return err;
 975 }
 976
 977 /**
 978  * Destroy DR related data within private structure.
 979  *
 980  * @param[in] priv
 981  *   Pointer to the private device data structure.
 982  */
 983 static void
 984 mlx5_free_shared_dr(struct mlx5_priv *priv)
 985 {
 986         struct mlx5_ibv_shared *sh;
 987
 988         if (!priv->dr_shared)
 989                 return;
 990         priv->dr_shared = 0;
 991         sh = priv->sh;
 992         MLX5_ASSERT(sh);
 993 #ifdef HAVE_MLX5DV_DR
 994         MLX5_ASSERT(sh->dv_refcnt);
 995         if (sh->dv_refcnt && --sh->dv_refcnt)
 996                 return;
 997         if (sh->rx_domain) {
 998                 mlx5_glue->dr_destroy_domain(sh->rx_domain);
 999                 sh->rx_domain = NULL;
1000         }
1001         if (sh->tx_domain) {
1002                 mlx5_glue->dr_destroy_domain(sh->tx_domain);
1003                 sh->tx_domain = NULL;
1004         }
1005 #ifdef HAVE_MLX5DV_DR_ESWITCH
1006         if (sh->fdb_domain) {
1007                 mlx5_glue->dr_destroy_domain(sh->fdb_domain);
1008                 sh->fdb_domain = NULL;
1009         }
1010         if (sh->esw_drop_action) {
1011                 mlx5_glue->destroy_flow_action(sh->esw_drop_action);
1012                 sh->esw_drop_action = NULL;
1013         }
1014 #endif
1015         if (sh->pop_vlan_action) {
1016                 mlx5_glue->destroy_flow_action(sh->pop_vlan_action);
1017                 sh->pop_vlan_action = NULL;
1018         }
1019         pthread_mutex_destroy(&sh->dv_mutex);
1020 #endif /* HAVE_MLX5DV_DR */
1021         if (sh->tag_table) {
1022                 /* tags should be destroyed with flow before. */
1023                 mlx5_hlist_destroy(sh->tag_table, NULL, NULL);
1024                 sh->tag_table = NULL;
1025         }
1026         mlx5_free_table_hash_list(priv);
1027 }
1028
1029 /**
1030  * Initialize shared data between primary and secondary process.
1031  *
1032  * A memzone is reserved by primary process and secondary processes attach to
1033  * the memzone.
1034  *
1035  * @return
1036  *   0 on success, a negative errno value otherwise and rte_errno is set.
1037  */
1038 static int
1039 mlx5_init_shared_data(void)
1040 {
1041         const struct rte_memzone *mz;
1042         int ret = 0;
1043
1044         rte_spinlock_lock(&mlx5_shared_data_lock);
1045         if (mlx5_shared_data == NULL) {
1046                 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
1047                         /* Allocate shared memory. */
1048                         mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
1049                                                  sizeof(*mlx5_shared_data),
1050                                                  SOCKET_ID_ANY, 0);
1051                         if (mz == NULL) {
1052                                 DRV_LOG(ERR,
1053                                         "Cannot allocate mlx5 shared data");
1054                                 ret = -rte_errno;
1055                                 goto error;
1056                         }
1057                         mlx5_shared_data = mz->addr;
1058                         memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data));
1059                         rte_spinlock_init(&mlx5_shared_data->lock);
1060                 } else {
1061                         /* Lookup allocated shared memory. */
1062                         mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA);
1063                         if (mz == NULL) {
1064                                 DRV_LOG(ERR,
1065                                         "Cannot attach mlx5 shared data");
1066                                 ret = -rte_errno;
1067                                 goto error;
1068                         }
1069                         mlx5_shared_data = mz->addr;
1070                         memset(&mlx5_local_data, 0, sizeof(mlx5_local_data));
1071                 }
1072         }
1073 error:
1074         rte_spinlock_unlock(&mlx5_shared_data_lock);
1075         return ret;
1076 }
1077
1078 /**
1079  * Retrieve integer value from environment variable.
1080  *
1081  * @param[in] name
1082  *   Environment variable name.
1083  *
1084  * @return
1085  *   Integer value, 0 if the variable is not set.
1086  */
1087 int
1088 mlx5_getenv_int(const char *name)
1089 {
1090         const char *val = getenv(name);
1091
1092         if (val == NULL)
1093                 return 0;
1094         return atoi(val);
1095 }
1096
1097 /**
1098  * Verbs callback to allocate a memory. This function should allocate the space
1099  * according to the size provided residing inside a huge page.
1100  * Please note that all allocation must respect the alignment from libmlx5
1101  * (i.e. currently sysconf(_SC_PAGESIZE)).
1102  *
1103  * @param[in] size
1104  *   The size in bytes of the memory to allocate.
1105  * @param[in] data
1106  *   A pointer to the callback data.
1107  *
1108  * @return
1109  *   Allocated buffer, NULL otherwise and rte_errno is set.
1110  */
1111 static void *
1112 mlx5_alloc_verbs_buf(size_t size, void *data)
1113 {
1114         struct mlx5_priv *priv = data;
1115         void *ret;
1116         size_t alignment = sysconf(_SC_PAGESIZE);
1117         unsigned int socket = SOCKET_ID_ANY;
1118
1119         if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) {
1120                 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
1121
1122                 socket = ctrl->socket;
1123         } else if (priv->verbs_alloc_ctx.type ==
1124                    MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) {
1125                 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
1126
1127                 socket = ctrl->socket;
1128         }
1129         MLX5_ASSERT(data != NULL);
1130         ret = rte_malloc_socket(__func__, size, alignment, socket);
1131         if (!ret && size)
1132                 rte_errno = ENOMEM;
1133         return ret;
1134 }
1135
1136 /**
1137  * Verbs callback to free a memory.
1138  *
1139  * @param[in] ptr
1140  *   A pointer to the memory to free.
1141  * @param[in] data
1142  *   A pointer to the callback data.
1143  */
1144 static void
1145 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused)
1146 {
1147         MLX5_ASSERT(data != NULL);
1148         rte_free(ptr);
1149 }
1150
1151 /**
1152  * DPDK callback to add udp tunnel port
1153  *
1154  * @param[in] dev
1155  *   A pointer to eth_dev
1156  * @param[in] udp_tunnel
1157  *   A pointer to udp tunnel
1158  *
1159  * @return
1160  *   0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1161  */
1162 int
1163 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1164                          struct rte_eth_udp_tunnel *udp_tunnel)
1165 {
1166         MLX5_ASSERT(udp_tunnel != NULL);
1167         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1168             udp_tunnel->udp_port == 4789)
1169                 return 0;
1170         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1171             udp_tunnel->udp_port == 4790)
1172                 return 0;
1173         return -ENOTSUP;
1174 }
1175
1176 /**
1177  * Initialize process private data structure.
1178  *
1179  * @param dev
1180  *   Pointer to Ethernet device structure.
1181  *
1182  * @return
1183  *   0 on success, a negative errno value otherwise and rte_errno is set.
1184  */
1185 int
1186 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1187 {
1188         struct mlx5_priv *priv = dev->data->dev_private;
1189         struct mlx5_proc_priv *ppriv;
1190         size_t ppriv_size;
1191
1192         /*
1193          * UAR register table follows the process private structure. BlueFlame
1194          * registers for Tx queues are stored in the table.
1195          */
1196         ppriv_size =
1197                 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1198         ppriv = rte_malloc_socket("mlx5_proc_priv", ppriv_size,
1199                                   RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1200         if (!ppriv) {
1201                 rte_errno = ENOMEM;
1202                 return -rte_errno;
1203         }
1204         ppriv->uar_table_sz = ppriv_size;
1205         dev->process_private = ppriv;
1206         return 0;
1207 }
1208
1209 /**
1210  * Un-initialize process private data structure.
1211  *
1212  * @param dev
1213  *   Pointer to Ethernet device structure.
1214  */
1215 static void
1216 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1217 {
1218         if (!dev->process_private)
1219                 return;
1220         rte_free(dev->process_private);
1221         dev->process_private = NULL;
1222 }
1223
1224 /**
1225  * DPDK callback to close the device.
1226  *
1227  * Destroy all queues and objects, free memory.
1228  *
1229  * @param dev
1230  *   Pointer to Ethernet device structure.
1231  */
1232 static void
1233 mlx5_dev_close(struct rte_eth_dev *dev)
1234 {
1235         struct mlx5_priv *priv = dev->data->dev_private;
1236         unsigned int i;
1237         int ret;
1238
1239         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1240                 dev->data->port_id,
1241                 ((priv->sh->ctx != NULL) ? priv->sh->ctx->device->name : ""));
1242         /* In case mlx5_dev_stop() has not been called. */
1243         mlx5_dev_interrupt_handler_uninstall(dev);
1244         mlx5_dev_interrupt_handler_devx_uninstall(dev);
1245         /*
1246          * If default mreg copy action is removed at the stop stage,
1247          * the search will return none and nothing will be done anymore.
1248          */
1249         mlx5_flow_stop_default(dev);
1250         mlx5_traffic_disable(dev);
1251         /*
1252          * If all the flows are already flushed in the device stop stage,
1253          * then this will return directly without any action.
1254          */
1255         mlx5_flow_list_flush(dev, &priv->flows, true);
1256         mlx5_flow_meter_flush(dev, NULL);
1257         /* Free the intermediate buffers for flow creation. */
1258         mlx5_flow_free_intermediate(dev);
1259         /* Prevent crashes when queues are still in use. */
1260         dev->rx_pkt_burst = removed_rx_burst;
1261         dev->tx_pkt_burst = removed_tx_burst;
1262         rte_wmb();
1263         /* Disable datapath on secondary process. */
1264         mlx5_mp_req_stop_rxtx(dev);
1265         if (priv->rxqs != NULL) {
1266                 /* XXX race condition if mlx5_rx_burst() is still running. */
1267                 usleep(1000);
1268                 for (i = 0; (i != priv->rxqs_n); ++i)
1269                         mlx5_rxq_release(dev, i);
1270                 priv->rxqs_n = 0;
1271                 priv->rxqs = NULL;
1272         }
1273         if (priv->txqs != NULL) {
1274                 /* XXX race condition if mlx5_tx_burst() is still running. */
1275                 usleep(1000);
1276                 for (i = 0; (i != priv->txqs_n); ++i)
1277                         mlx5_txq_release(dev, i);
1278                 priv->txqs_n = 0;
1279                 priv->txqs = NULL;
1280         }
1281         mlx5_proc_priv_uninit(dev);
1282         if (priv->mreg_cp_tbl)
1283                 mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
1284         mlx5_mprq_free_mp(dev);
1285         mlx5_free_shared_dr(priv);
1286         if (priv->rss_conf.rss_key != NULL)
1287                 rte_free(priv->rss_conf.rss_key);
1288         if (priv->reta_idx != NULL)
1289                 rte_free(priv->reta_idx);
1290         if (priv->config.vf)
1291                 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev),
1292                                        dev->data->mac_addrs,
1293                                        MLX5_MAX_MAC_ADDRESSES, priv->mac_own);
1294         if (priv->nl_socket_route >= 0)
1295                 close(priv->nl_socket_route);
1296         if (priv->nl_socket_rdma >= 0)
1297                 close(priv->nl_socket_rdma);
1298         if (priv->vmwa_context)
1299                 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1300         if (priv->sh) {
1301                 /*
1302                  * Free the shared context in last turn, because the cleanup
1303                  * routines above may use some shared fields, like
1304                  * mlx5_nl_mac_addr_flush() uses ibdev_path for retrieveing
1305                  * ifindex if Netlink fails.
1306                  */
1307                 mlx5_free_shared_ibctx(priv->sh);
1308                 priv->sh = NULL;
1309         }
1310         ret = mlx5_hrxq_verify(dev);
1311         if (ret)
1312                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1313                         dev->data->port_id);
1314         ret = mlx5_ind_table_obj_verify(dev);
1315         if (ret)
1316                 DRV_LOG(WARNING, "port %u some indirection table still remain",
1317                         dev->data->port_id);
1318         ret = mlx5_rxq_obj_verify(dev);
1319         if (ret)
1320                 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1321                         dev->data->port_id);
1322         ret = mlx5_rxq_verify(dev);
1323         if (ret)
1324                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1325                         dev->data->port_id);
1326         ret = mlx5_txq_obj_verify(dev);
1327         if (ret)
1328                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1329                         dev->data->port_id);
1330         ret = mlx5_txq_verify(dev);
1331         if (ret)
1332                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1333                         dev->data->port_id);
1334         ret = mlx5_flow_verify(dev);
1335         if (ret)
1336                 DRV_LOG(WARNING, "port %u some flows still remain",
1337                         dev->data->port_id);
1338         if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1339                 unsigned int c = 0;
1340                 uint16_t port_id;
1341
1342                 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1343                         struct mlx5_priv *opriv =
1344                                 rte_eth_devices[port_id].data->dev_private;
1345
1346                         if (!opriv ||
1347                             opriv->domain_id != priv->domain_id ||
1348                             &rte_eth_devices[port_id] == dev)
1349                                 continue;
1350                         ++c;
1351                         break;
1352                 }
1353                 if (!c)
1354                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1355         }
1356         memset(priv, 0, sizeof(*priv));
1357         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1358         /*
1359          * Reset mac_addrs to NULL such that it is not freed as part of
1360          * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1361          * it is freed when dev_private is freed.
1362          */
1363         dev->data->mac_addrs = NULL;
1364 }
1365
1366 const struct eth_dev_ops mlx5_dev_ops = {
1367         .dev_configure = mlx5_dev_configure,
1368         .dev_start = mlx5_dev_start,
1369         .dev_stop = mlx5_dev_stop,
1370         .dev_set_link_down = mlx5_set_link_down,
1371         .dev_set_link_up = mlx5_set_link_up,
1372         .dev_close = mlx5_dev_close,
1373         .promiscuous_enable = mlx5_promiscuous_enable,
1374         .promiscuous_disable = mlx5_promiscuous_disable,
1375         .allmulticast_enable = mlx5_allmulticast_enable,
1376         .allmulticast_disable = mlx5_allmulticast_disable,
1377         .link_update = mlx5_link_update,
1378         .stats_get = mlx5_stats_get,
1379         .stats_reset = mlx5_stats_reset,
1380         .xstats_get = mlx5_xstats_get,
1381         .xstats_reset = mlx5_xstats_reset,
1382         .xstats_get_names = mlx5_xstats_get_names,
1383         .fw_version_get = mlx5_fw_version_get,
1384         .dev_infos_get = mlx5_dev_infos_get,
1385         .read_clock = mlx5_read_clock,
1386         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1387         .vlan_filter_set = mlx5_vlan_filter_set,
1388         .rx_queue_setup = mlx5_rx_queue_setup,
1389         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1390         .tx_queue_setup = mlx5_tx_queue_setup,
1391         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1392         .rx_queue_release = mlx5_rx_queue_release,
1393         .tx_queue_release = mlx5_tx_queue_release,
1394         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1395         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1396         .mac_addr_remove = mlx5_mac_addr_remove,
1397         .mac_addr_add = mlx5_mac_addr_add,
1398         .mac_addr_set = mlx5_mac_addr_set,
1399         .set_mc_addr_list = mlx5_set_mc_addr_list,
1400         .mtu_set = mlx5_dev_set_mtu,
1401         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1402         .vlan_offload_set = mlx5_vlan_offload_set,
1403         .reta_update = mlx5_dev_rss_reta_update,
1404         .reta_query = mlx5_dev_rss_reta_query,
1405         .rss_hash_update = mlx5_rss_hash_update,
1406         .rss_hash_conf_get = mlx5_rss_hash_conf_get,
1407         .filter_ctrl = mlx5_dev_filter_ctrl,
1408         .rx_descriptor_status = mlx5_rx_descriptor_status,
1409         .tx_descriptor_status = mlx5_tx_descriptor_status,
1410         .rxq_info_get = mlx5_rxq_info_get,
1411         .txq_info_get = mlx5_txq_info_get,
1412         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1413         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1414         .rx_queue_count = mlx5_rx_queue_count,
1415         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1416         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1417         .is_removed = mlx5_is_removed,
1418         .udp_tunnel_port_add  = mlx5_udp_tunnel_port_add,
1419         .get_module_info = mlx5_get_module_info,
1420         .get_module_eeprom = mlx5_get_module_eeprom,
1421         .hairpin_cap_get = mlx5_hairpin_cap_get,
1422         .mtr_ops_get = mlx5_flow_meter_ops_get,
1423 };
1424
1425 /* Available operations from secondary process. */
1426 static const struct eth_dev_ops mlx5_dev_sec_ops = {
1427         .stats_get = mlx5_stats_get,
1428         .stats_reset = mlx5_stats_reset,
1429         .xstats_get = mlx5_xstats_get,
1430         .xstats_reset = mlx5_xstats_reset,
1431         .xstats_get_names = mlx5_xstats_get_names,
1432         .fw_version_get = mlx5_fw_version_get,
1433         .dev_infos_get = mlx5_dev_infos_get,
1434         .rx_descriptor_status = mlx5_rx_descriptor_status,
1435         .tx_descriptor_status = mlx5_tx_descriptor_status,
1436         .rxq_info_get = mlx5_rxq_info_get,
1437         .txq_info_get = mlx5_txq_info_get,
1438         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1439         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1440         .get_module_info = mlx5_get_module_info,
1441         .get_module_eeprom = mlx5_get_module_eeprom,
1442 };
1443
1444 /* Available operations in flow isolated mode. */
1445 const struct eth_dev_ops mlx5_dev_ops_isolate = {
1446         .dev_configure = mlx5_dev_configure,
1447         .dev_start = mlx5_dev_start,
1448         .dev_stop = mlx5_dev_stop,
1449         .dev_set_link_down = mlx5_set_link_down,
1450         .dev_set_link_up = mlx5_set_link_up,
1451         .dev_close = mlx5_dev_close,
1452         .promiscuous_enable = mlx5_promiscuous_enable,
1453         .promiscuous_disable = mlx5_promiscuous_disable,
1454         .allmulticast_enable = mlx5_allmulticast_enable,
1455         .allmulticast_disable = mlx5_allmulticast_disable,
1456         .link_update = mlx5_link_update,
1457         .stats_get = mlx5_stats_get,
1458         .stats_reset = mlx5_stats_reset,
1459         .xstats_get = mlx5_xstats_get,
1460         .xstats_reset = mlx5_xstats_reset,
1461         .xstats_get_names = mlx5_xstats_get_names,
1462         .fw_version_get = mlx5_fw_version_get,
1463         .dev_infos_get = mlx5_dev_infos_get,
1464         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1465         .vlan_filter_set = mlx5_vlan_filter_set,
1466         .rx_queue_setup = mlx5_rx_queue_setup,
1467         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1468         .tx_queue_setup = mlx5_tx_queue_setup,
1469         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1470         .rx_queue_release = mlx5_rx_queue_release,
1471         .tx_queue_release = mlx5_tx_queue_release,
1472         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1473         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1474         .mac_addr_remove = mlx5_mac_addr_remove,
1475         .mac_addr_add = mlx5_mac_addr_add,
1476         .mac_addr_set = mlx5_mac_addr_set,
1477         .set_mc_addr_list = mlx5_set_mc_addr_list,
1478         .mtu_set = mlx5_dev_set_mtu,
1479         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1480         .vlan_offload_set = mlx5_vlan_offload_set,
1481         .filter_ctrl = mlx5_dev_filter_ctrl,
1482         .rx_descriptor_status = mlx5_rx_descriptor_status,
1483         .tx_descriptor_status = mlx5_tx_descriptor_status,
1484         .rxq_info_get = mlx5_rxq_info_get,
1485         .txq_info_get = mlx5_txq_info_get,
1486         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1487         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1488         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1489         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1490         .is_removed = mlx5_is_removed,
1491         .get_module_info = mlx5_get_module_info,
1492         .get_module_eeprom = mlx5_get_module_eeprom,
1493         .hairpin_cap_get = mlx5_hairpin_cap_get,
1494         .mtr_ops_get = mlx5_flow_meter_ops_get,
1495 };
1496
1497 /**
1498  * Verify and store value for device argument.
1499  *
1500  * @param[in] key
1501  *   Key argument to verify.
1502  * @param[in] val
1503  *   Value associated with key.
1504  * @param opaque
1505  *   User data.
1506  *
1507  * @return
1508  *   0 on success, a negative errno value otherwise and rte_errno is set.
1509  */
1510 static int
1511 mlx5_args_check(const char *key, const char *val, void *opaque)
1512 {
1513         struct mlx5_dev_config *config = opaque;
1514         unsigned long tmp;
1515
1516         /* No-op, port representors are processed in mlx5_dev_spawn(). */
1517         if (!strcmp(MLX5_REPRESENTOR, key))
1518                 return 0;
1519         errno = 0;
1520         tmp = strtoul(val, NULL, 0);
1521         if (errno) {
1522                 rte_errno = errno;
1523                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1524                 return -rte_errno;
1525         }
1526         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1527                 config->cqe_comp = !!tmp;
1528         } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
1529                 config->cqe_pad = !!tmp;
1530         } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1531                 config->hw_padding = !!tmp;
1532         } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1533                 config->mprq.enabled = !!tmp;
1534         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1535                 config->mprq.stride_num_n = tmp;
1536         } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1537                 config->mprq.max_memcpy_len = tmp;
1538         } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1539                 config->mprq.min_rxqs_num = tmp;
1540         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1541                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1542                                  " converted to txq_inline_max", key);
1543                 config->txq_inline_max = tmp;
1544         } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1545                 config->txq_inline_max = tmp;
1546         } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1547                 config->txq_inline_min = tmp;
1548         } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1549                 config->txq_inline_mpw = tmp;
1550         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1551                 config->txqs_inline = tmp;
1552         } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1553                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1554         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1555                 config->mps = !!tmp;
1556         } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1557                 if (tmp != MLX5_TXDB_CACHED &&
1558                     tmp != MLX5_TXDB_NCACHED &&
1559                     tmp != MLX5_TXDB_HEURISTIC) {
1560                         DRV_LOG(ERR, "invalid Tx doorbell "
1561                                      "mapping parameter");
1562                         rte_errno = EINVAL;
1563                         return -rte_errno;
1564                 }
1565                 config->dbnc = tmp;
1566         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1567                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1568         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1569                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1570                                  " converted to txq_inline_mpw", key);
1571                 config->txq_inline_mpw = tmp;
1572         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1573                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1574         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1575                 config->rx_vec_en = !!tmp;
1576         } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1577                 config->l3_vxlan_en = !!tmp;
1578         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1579                 config->vf_nl_en = !!tmp;
1580         } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1581                 config->dv_esw_en = !!tmp;
1582         } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1583                 config->dv_flow_en = !!tmp;
1584         } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1585                 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1586                     tmp != MLX5_XMETA_MODE_META16 &&
1587                     tmp != MLX5_XMETA_MODE_META32) {
1588                         DRV_LOG(ERR, "invalid extensive "
1589                                      "metadata parameter");
1590                         rte_errno = EINVAL;
1591                         return -rte_errno;
1592                 }
1593                 config->dv_xmeta_en = tmp;
1594         } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1595                 config->mr_ext_memseg_en = !!tmp;
1596         } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1597                 config->max_dump_files_num = tmp;
1598         } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1599                 config->lro.timeout = tmp;
1600         } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1601                 DRV_LOG(DEBUG, "class argument is %s.", val);
1602         } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1603                 config->log_hp_size = tmp;
1604         } else {
1605                 DRV_LOG(WARNING, "%s: unknown parameter", key);
1606                 rte_errno = EINVAL;
1607                 return -rte_errno;
1608         }
1609         return 0;
1610 }
1611
1612 /**
1613  * Parse device parameters.
1614  *
1615  * @param config
1616  *   Pointer to device configuration structure.
1617  * @param devargs
1618  *   Device arguments structure.
1619  *
1620  * @return
1621  *   0 on success, a negative errno value otherwise and rte_errno is set.
1622  */
1623 static int
1624 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1625 {
1626         const char **params = (const char *[]){
1627                 MLX5_RXQ_CQE_COMP_EN,
1628                 MLX5_RXQ_CQE_PAD_EN,
1629                 MLX5_RXQ_PKT_PAD_EN,
1630                 MLX5_RX_MPRQ_EN,
1631                 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1632                 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1633                 MLX5_RXQS_MIN_MPRQ,
1634                 MLX5_TXQ_INLINE,
1635                 MLX5_TXQ_INLINE_MIN,
1636                 MLX5_TXQ_INLINE_MAX,
1637                 MLX5_TXQ_INLINE_MPW,
1638                 MLX5_TXQS_MIN_INLINE,
1639                 MLX5_TXQS_MAX_VEC,
1640                 MLX5_TXQ_MPW_EN,
1641                 MLX5_TXQ_MPW_HDR_DSEG_EN,
1642                 MLX5_TXQ_MAX_INLINE_LEN,
1643                 MLX5_TX_DB_NC,
1644                 MLX5_TX_VEC_EN,
1645                 MLX5_RX_VEC_EN,
1646                 MLX5_L3_VXLAN_EN,
1647                 MLX5_VF_NL_EN,
1648                 MLX5_DV_ESW_EN,
1649                 MLX5_DV_FLOW_EN,
1650                 MLX5_DV_XMETA_EN,
1651                 MLX5_MR_EXT_MEMSEG_EN,
1652                 MLX5_REPRESENTOR,
1653                 MLX5_MAX_DUMP_FILES_NUM,
1654                 MLX5_LRO_TIMEOUT_USEC,
1655                 MLX5_CLASS_ARG_NAME,
1656                 MLX5_HP_BUF_SIZE,
1657                 NULL,
1658         };
1659         struct rte_kvargs *kvlist;
1660         int ret = 0;
1661         int i;
1662
1663         if (devargs == NULL)
1664                 return 0;
1665         /* Following UGLY cast is done to pass checkpatch. */
1666         kvlist = rte_kvargs_parse(devargs->args, params);
1667         if (kvlist == NULL) {
1668                 rte_errno = EINVAL;
1669                 return -rte_errno;
1670         }
1671         /* Process parameters. */
1672         for (i = 0; (params[i] != NULL); ++i) {
1673                 if (rte_kvargs_count(kvlist, params[i])) {
1674                         ret = rte_kvargs_process(kvlist, params[i],
1675                                                  mlx5_args_check, config);
1676                         if (ret) {
1677                                 rte_errno = EINVAL;
1678                                 rte_kvargs_free(kvlist);
1679                                 return -rte_errno;
1680                         }
1681                 }
1682         }
1683         rte_kvargs_free(kvlist);
1684         return 0;
1685 }
1686
1687 static struct rte_pci_driver mlx5_driver;
1688
1689 /**
1690  * PMD global initialization.
1691  *
1692  * Independent from individual device, this function initializes global
1693  * per-PMD data structures distinguishing primary and secondary processes.
1694  * Hence, each initialization is called once per a process.
1695  *
1696  * @return
1697  *   0 on success, a negative errno value otherwise and rte_errno is set.
1698  */
1699 static int
1700 mlx5_init_once(void)
1701 {
1702         struct mlx5_shared_data *sd;
1703         struct mlx5_local_data *ld = &mlx5_local_data;
1704         int ret = 0;
1705
1706         if (mlx5_init_shared_data())
1707                 return -rte_errno;
1708         sd = mlx5_shared_data;
1709         MLX5_ASSERT(sd);
1710         rte_spinlock_lock(&sd->lock);
1711         switch (rte_eal_process_type()) {
1712         case RTE_PROC_PRIMARY:
1713                 if (sd->init_done)
1714                         break;
1715                 LIST_INIT(&sd->mem_event_cb_list);
1716                 rte_rwlock_init(&sd->mem_event_rwlock);
1717                 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
1718                                                 mlx5_mr_mem_event_cb, NULL);
1719                 ret = mlx5_mp_init_primary();
1720                 if (ret)
1721                         goto out;
1722                 sd->init_done = true;
1723                 break;
1724         case RTE_PROC_SECONDARY:
1725                 if (ld->init_done)
1726                         break;
1727                 ret = mlx5_mp_init_secondary();
1728                 if (ret)
1729                         goto out;
1730                 ++sd->secondary_cnt;
1731                 ld->init_done = true;
1732                 break;
1733         default:
1734                 break;
1735         }
1736 out:
1737         rte_spinlock_unlock(&sd->lock);
1738         return ret;
1739 }
1740
1741 /**
1742  * Configures the minimal amount of data to inline into WQE
1743  * while sending packets.
1744  *
1745  * - the txq_inline_min has the maximal priority, if this
1746  *   key is specified in devargs
1747  * - if DevX is enabled the inline mode is queried from the
1748  *   device (HCA attributes and NIC vport context if needed).
1749  * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1750  *   and none (0 bytes) for other NICs
1751  *
1752  * @param spawn
1753  *   Verbs device parameters (name, port, switch_info) to spawn.
1754  * @param config
1755  *   Device configuration parameters.
1756  */
1757 static void
1758 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1759                     struct mlx5_dev_config *config)
1760 {
1761         if (config->txq_inline_min != MLX5_ARG_UNSET) {
1762                 /* Application defines size of inlined data explicitly. */
1763                 switch (spawn->pci_dev->id.device_id) {
1764                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1765                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1766                         if (config->txq_inline_min <
1767                                        (int)MLX5_INLINE_HSIZE_L2) {
1768                                 DRV_LOG(DEBUG,
1769                                         "txq_inline_mix aligned to minimal"
1770                                         " ConnectX-4 required value %d",
1771                                         (int)MLX5_INLINE_HSIZE_L2);
1772                                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1773                         }
1774                         break;
1775                 }
1776                 goto exit;
1777         }
1778         if (config->hca_attr.eth_net_offloads) {
1779                 /* We have DevX enabled, inline mode queried successfully. */
1780                 switch (config->hca_attr.wqe_inline_mode) {
1781                 case MLX5_CAP_INLINE_MODE_L2:
1782                         /* outer L2 header must be inlined. */
1783                         config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1784                         goto exit;
1785                 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1786                         /* No inline data are required by NIC. */
1787                         config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1788                         config->hw_vlan_insert =
1789                                 config->hca_attr.wqe_vlan_insert;
1790                         DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1791                         goto exit;
1792                 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1793                         /* inline mode is defined by NIC vport context. */
1794                         if (!config->hca_attr.eth_virt)
1795                                 break;
1796                         switch (config->hca_attr.vport_inline_mode) {
1797                         case MLX5_INLINE_MODE_NONE:
1798                                 config->txq_inline_min =
1799                                         MLX5_INLINE_HSIZE_NONE;
1800                                 goto exit;
1801                         case MLX5_INLINE_MODE_L2:
1802                                 config->txq_inline_min =
1803                                         MLX5_INLINE_HSIZE_L2;
1804                                 goto exit;
1805                         case MLX5_INLINE_MODE_IP:
1806                                 config->txq_inline_min =
1807                                         MLX5_INLINE_HSIZE_L3;
1808                                 goto exit;
1809                         case MLX5_INLINE_MODE_TCP_UDP:
1810                                 config->txq_inline_min =
1811                                         MLX5_INLINE_HSIZE_L4;
1812                                 goto exit;
1813                         case MLX5_INLINE_MODE_INNER_L2:
1814                                 config->txq_inline_min =
1815                                         MLX5_INLINE_HSIZE_INNER_L2;
1816                                 goto exit;
1817                         case MLX5_INLINE_MODE_INNER_IP:
1818                                 config->txq_inline_min =
1819                                         MLX5_INLINE_HSIZE_INNER_L3;
1820                                 goto exit;
1821                         case MLX5_INLINE_MODE_INNER_TCP_UDP:
1822                                 config->txq_inline_min =
1823                                         MLX5_INLINE_HSIZE_INNER_L4;
1824                                 goto exit;
1825                         }
1826                 }
1827         }
1828         /*
1829          * We get here if we are unable to deduce
1830          * inline data size with DevX. Try PCI ID
1831          * to determine old NICs.
1832          */
1833         switch (spawn->pci_dev->id.device_id) {
1834         case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1835         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1836         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
1837         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1838                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1839                 config->hw_vlan_insert = 0;
1840                 break;
1841         case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
1842         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1843         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
1844         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1845                 /*
1846                  * These NICs support VLAN insertion from WQE and
1847                  * report the wqe_vlan_insert flag. But there is the bug
1848                  * and PFC control may be broken, so disable feature.
1849                  */
1850                 config->hw_vlan_insert = 0;
1851                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1852                 break;
1853         default:
1854                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1855                 break;
1856         }
1857 exit:
1858         DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
1859 }
1860
1861 /**
1862  * Configures the metadata mask fields in the shared context.
1863  *
1864  * @param [in] dev
1865  *   Pointer to Ethernet device.
1866  */
1867 static void
1868 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
1869 {
1870         struct mlx5_priv *priv = dev->data->dev_private;
1871         struct mlx5_ibv_shared *sh = priv->sh;
1872         uint32_t meta, mark, reg_c0;
1873
1874         reg_c0 = ~priv->vport_meta_mask;
1875         switch (priv->config.dv_xmeta_en) {
1876         case MLX5_XMETA_MODE_LEGACY:
1877                 meta = UINT32_MAX;
1878                 mark = MLX5_FLOW_MARK_MASK;
1879                 break;
1880         case MLX5_XMETA_MODE_META16:
1881                 meta = reg_c0 >> rte_bsf32(reg_c0);
1882                 mark = MLX5_FLOW_MARK_MASK;
1883                 break;
1884         case MLX5_XMETA_MODE_META32:
1885                 meta = UINT32_MAX;
1886                 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
1887                 break;
1888         default:
1889                 meta = 0;
1890                 mark = 0;
1891                 MLX5_ASSERT(false);
1892                 break;
1893         }
1894         if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
1895                 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
1896                                  sh->dv_mark_mask, mark);
1897         else
1898                 sh->dv_mark_mask = mark;
1899         if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
1900                 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
1901                                  sh->dv_meta_mask, meta);
1902         else
1903                 sh->dv_meta_mask = meta;
1904         if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
1905                 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
1906                                  sh->dv_meta_mask, reg_c0);
1907         else
1908                 sh->dv_regc0_mask = reg_c0;
1909         DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
1910         DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
1911         DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
1912         DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
1913 }
1914
1915 /**
1916  * Allocate page of door-bells and register it using DevX API.
1917  *
1918  * @param [in] dev
1919  *   Pointer to Ethernet device.
1920  *
1921  * @return
1922  *   Pointer to new page on success, NULL otherwise.
1923  */
1924 static struct mlx5_devx_dbr_page *
1925 mlx5_alloc_dbr_page(struct rte_eth_dev *dev)
1926 {
1927         struct mlx5_priv *priv = dev->data->dev_private;
1928         struct mlx5_devx_dbr_page *page;
1929
1930         /* Allocate space for door-bell page and management data. */
1931         page = rte_calloc_socket(__func__, 1, sizeof(struct mlx5_devx_dbr_page),
1932                                  RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1933         if (!page) {
1934                 DRV_LOG(ERR, "port %u cannot allocate dbr page",
1935                         dev->data->port_id);
1936                 return NULL;
1937         }
1938         /* Register allocated memory. */
1939         page->umem = mlx5_glue->devx_umem_reg(priv->sh->ctx, page->dbrs,
1940                                               MLX5_DBR_PAGE_SIZE, 0);
1941         if (!page->umem) {
1942                 DRV_LOG(ERR, "port %u cannot umem reg dbr page",
1943                         dev->data->port_id);
1944                 rte_free(page);
1945                 return NULL;
1946         }
1947         return page;
1948 }
1949
1950 /**
1951  * Find the next available door-bell, allocate new page if needed.
1952  *
1953  * @param [in] dev
1954  *   Pointer to Ethernet device.
1955  * @param [out] dbr_page
1956  *   Door-bell page containing the page data.
1957  *
1958  * @return
1959  *   Door-bell address offset on success, a negative error value otherwise.
1960  */
1961 int64_t
1962 mlx5_get_dbr(struct rte_eth_dev *dev, struct mlx5_devx_dbr_page **dbr_page)
1963 {
1964         struct mlx5_priv *priv = dev->data->dev_private;
1965         struct mlx5_devx_dbr_page *page = NULL;
1966         uint32_t i, j;
1967
1968         LIST_FOREACH(page, &priv->dbrpgs, next)
1969                 if (page->dbr_count < MLX5_DBR_PER_PAGE)
1970                         break;
1971         if (!page) { /* No page with free door-bell exists. */
1972                 page = mlx5_alloc_dbr_page(dev);
1973                 if (!page) /* Failed to allocate new page. */
1974                         return (-1);
1975                 LIST_INSERT_HEAD(&priv->dbrpgs, page, next);
1976         }
1977         /* Loop to find bitmap part with clear bit. */
1978         for (i = 0;
1979              i < MLX5_DBR_BITMAP_SIZE && page->dbr_bitmap[i] == UINT64_MAX;
1980              i++)
1981                 ; /* Empty. */
1982         /* Find the first clear bit. */
1983         j = rte_bsf64(~page->dbr_bitmap[i]);
1984         MLX5_ASSERT(i < (MLX5_DBR_PER_PAGE / 64));
1985         page->dbr_bitmap[i] |= (1 << j);
1986         page->dbr_count++;
1987         *dbr_page = page;
1988         return (((i * 64) + j) * sizeof(uint64_t));
1989 }
1990
1991 /**
1992  * Release a door-bell record.
1993  *
1994  * @param [in] dev
1995  *   Pointer to Ethernet device.
1996  * @param [in] umem_id
1997  *   UMEM ID of page containing the door-bell record to release.
1998  * @param [in] offset
1999  *   Offset of door-bell record in page.
2000  *
2001  * @return
2002  *   0 on success, a negative error value otherwise.
2003  */
2004 int32_t
2005 mlx5_release_dbr(struct rte_eth_dev *dev, uint32_t umem_id, uint64_t offset)
2006 {
2007         struct mlx5_priv *priv = dev->data->dev_private;
2008         struct mlx5_devx_dbr_page *page = NULL;
2009         int ret = 0;
2010
2011         LIST_FOREACH(page, &priv->dbrpgs, next)
2012                 /* Find the page this address belongs to. */
2013                 if (page->umem->umem_id == umem_id)
2014                         break;
2015         if (!page)
2016                 return -EINVAL;
2017         page->dbr_count--;
2018         if (!page->dbr_count) {
2019                 /* Page not used, free it and remove from list. */
2020                 LIST_REMOVE(page, next);
2021                 if (page->umem)
2022                         ret = -mlx5_glue->devx_umem_dereg(page->umem);
2023                 rte_free(page);
2024         } else {
2025                 /* Mark in bitmap that this door-bell is not in use. */
2026                 offset /= MLX5_DBR_SIZE;
2027                 int i = offset / 64;
2028                 int j = offset % 64;
2029
2030                 page->dbr_bitmap[i] &= ~(1 << j);
2031         }
2032         return ret;
2033 }
2034
2035 int
2036 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
2037 {
2038         static const char *const dynf_names[] = {
2039                 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
2040                 RTE_MBUF_DYNFLAG_METADATA_NAME
2041         };
2042         unsigned int i;
2043
2044         if (n < RTE_DIM(dynf_names))
2045                 return -ENOMEM;
2046         for (i = 0; i < RTE_DIM(dynf_names); i++) {
2047                 if (names[i] == NULL)
2048                         return -EINVAL;
2049                 strcpy(names[i], dynf_names[i]);
2050         }
2051         return RTE_DIM(dynf_names);
2052 }
2053
2054 /**
2055  * Check sibling device configurations.
2056  *
2057  * Sibling devices sharing the Infiniband device context
2058  * should have compatible configurations. This regards
2059  * representors and bonding slaves.
2060  *
2061  * @param priv
2062  *   Private device descriptor.
2063  * @param config
2064  *   Configuration of the device is going to be created.
2065  *
2066  * @return
2067  *   0 on success, EINVAL otherwise
2068  */
2069 static int
2070 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
2071                               struct mlx5_dev_config *config)
2072 {
2073         struct mlx5_ibv_shared *sh = priv->sh;
2074         struct mlx5_dev_config *sh_conf = NULL;
2075         uint16_t port_id;
2076
2077         MLX5_ASSERT(sh);
2078         /* Nothing to compare for the single/first device. */
2079         if (sh->refcnt == 1)
2080                 return 0;
2081         /* Find the device with shared context. */
2082         MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
2083                 struct mlx5_priv *opriv =
2084                         rte_eth_devices[port_id].data->dev_private;
2085
2086                 if (opriv && opriv != priv && opriv->sh == sh) {
2087                         sh_conf = &opriv->config;
2088                         break;
2089                 }
2090         }
2091         if (!sh_conf)
2092                 return 0;
2093         if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
2094                 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
2095                              " for shared %s context", sh->ibdev_name);
2096                 rte_errno = EINVAL;
2097                 return rte_errno;
2098         }
2099         if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
2100                 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
2101                              " for shared %s context", sh->ibdev_name);
2102                 rte_errno = EINVAL;
2103                 return rte_errno;
2104         }
2105         return 0;
2106 }
2107 /**
2108  * Spawn an Ethernet device from Verbs information.
2109  *
2110  * @param dpdk_dev
2111  *   Backing DPDK device.
2112  * @param spawn
2113  *   Verbs device parameters (name, port, switch_info) to spawn.
2114  * @param config
2115  *   Device configuration parameters.
2116  *
2117  * @return
2118  *   A valid Ethernet device object on success, NULL otherwise and rte_errno
2119  *   is set. The following errors are defined:
2120  *
2121  *   EBUSY: device is not supposed to be spawned.
2122  *   EEXIST: device is already spawned
2123  */
2124 static struct rte_eth_dev *
2125 mlx5_dev_spawn(struct rte_device *dpdk_dev,
2126                struct mlx5_dev_spawn_data *spawn,
2127                struct mlx5_dev_config config)
2128 {
2129         const struct mlx5_switch_info *switch_info = &spawn->info;
2130         struct mlx5_ibv_shared *sh = NULL;
2131         struct ibv_port_attr port_attr;
2132         struct mlx5dv_context dv_attr = { .comp_mask = 0 };
2133         struct rte_eth_dev *eth_dev = NULL;
2134         struct mlx5_priv *priv = NULL;
2135         int err = 0;
2136         unsigned int hw_padding = 0;
2137         unsigned int mps;
2138         unsigned int cqe_comp;
2139         unsigned int cqe_pad = 0;
2140         unsigned int tunnel_en = 0;
2141         unsigned int mpls_en = 0;
2142         unsigned int swp = 0;
2143         unsigned int mprq = 0;
2144         unsigned int mprq_min_stride_size_n = 0;
2145         unsigned int mprq_max_stride_size_n = 0;
2146         unsigned int mprq_min_stride_num_n = 0;
2147         unsigned int mprq_max_stride_num_n = 0;
2148         struct rte_ether_addr mac;
2149         char name[RTE_ETH_NAME_MAX_LEN];
2150         int own_domain_id = 0;
2151         uint16_t port_id;
2152         unsigned int i;
2153 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
2154         struct mlx5dv_devx_port devx_port = { .comp_mask = 0 };
2155 #endif
2156
2157         /* Determine if this port representor is supposed to be spawned. */
2158         if (switch_info->representor && dpdk_dev->devargs) {
2159                 struct rte_eth_devargs eth_da;
2160
2161                 err = rte_eth_devargs_parse(dpdk_dev->devargs->args, &eth_da);
2162                 if (err) {
2163                         rte_errno = -err;
2164                         DRV_LOG(ERR, "failed to process device arguments: %s",
2165                                 strerror(rte_errno));
2166                         return NULL;
2167                 }
2168                 for (i = 0; i < eth_da.nb_representor_ports; ++i)
2169                         if (eth_da.representor_ports[i] ==
2170                             (uint16_t)switch_info->port_name)
2171                                 break;
2172                 if (i == eth_da.nb_representor_ports) {
2173                         rte_errno = EBUSY;
2174                         return NULL;
2175                 }
2176         }
2177         /* Build device name. */
2178         if (spawn->pf_bond <  0) {
2179                 /* Single device. */
2180                 if (!switch_info->representor)
2181                         strlcpy(name, dpdk_dev->name, sizeof(name));
2182                 else
2183                         snprintf(name, sizeof(name), "%s_representor_%u",
2184                                  dpdk_dev->name, switch_info->port_name);
2185         } else {
2186                 /* Bonding device. */
2187                 if (!switch_info->representor)
2188                         snprintf(name, sizeof(name), "%s_%s",
2189                                  dpdk_dev->name, spawn->ibv_dev->name);
2190                 else
2191                         snprintf(name, sizeof(name), "%s_%s_representor_%u",
2192                                  dpdk_dev->name, spawn->ibv_dev->name,
2193                                  switch_info->port_name);
2194         }
2195         /* check if the device is already spawned */
2196         if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) {
2197                 rte_errno = EEXIST;
2198                 return NULL;
2199         }
2200         DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name);
2201         if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
2202                 eth_dev = rte_eth_dev_attach_secondary(name);
2203                 if (eth_dev == NULL) {
2204                         DRV_LOG(ERR, "can not attach rte ethdev");
2205                         rte_errno = ENOMEM;
2206                         return NULL;
2207                 }
2208                 eth_dev->device = dpdk_dev;
2209                 eth_dev->dev_ops = &mlx5_dev_sec_ops;
2210                 err = mlx5_proc_priv_init(eth_dev);
2211                 if (err)
2212                         return NULL;
2213                 /* Receive command fd from primary process */
2214                 err = mlx5_mp_req_verbs_cmd_fd(eth_dev);
2215                 if (err < 0)
2216                         return NULL;
2217                 /* Remap UAR for Tx queues. */
2218                 err = mlx5_tx_uar_init_secondary(eth_dev, err);
2219                 if (err)
2220                         return NULL;
2221                 /*
2222                  * Ethdev pointer is still required as input since
2223                  * the primary device is not accessible from the
2224                  * secondary process.
2225                  */
2226                 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev);
2227                 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev);
2228                 return eth_dev;
2229         }
2230         /*
2231          * Some parameters ("tx_db_nc" in particularly) are needed in
2232          * advance to create dv/verbs device context. We proceed the
2233          * devargs here to get ones, and later proceed devargs again
2234          * to override some hardware settings.
2235          */
2236         err = mlx5_args(&config, dpdk_dev->devargs);
2237         if (err) {
2238                 err = rte_errno;
2239                 DRV_LOG(ERR, "failed to process device arguments: %s",
2240                         strerror(rte_errno));
2241                 goto error;
2242         }
2243         sh = mlx5_alloc_shared_ibctx(spawn, &config);
2244         if (!sh)
2245                 return NULL;
2246         config.devx = sh->devx;
2247 #ifdef HAVE_MLX5DV_DR_ACTION_DEST_DEVX_TIR
2248         config.dest_tir = 1;
2249 #endif
2250 #ifdef HAVE_IBV_MLX5_MOD_SWP
2251         dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP;
2252 #endif
2253         /*
2254          * Multi-packet send is supported by ConnectX-4 Lx PF as well
2255          * as all ConnectX-5 devices.
2256          */
2257 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
2258         dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS;
2259 #endif
2260 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
2261         dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ;
2262 #endif
2263         mlx5_glue->dv_query_device(sh->ctx, &dv_attr);
2264         if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
2265                 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) {
2266                         DRV_LOG(DEBUG, "enhanced MPW is supported");
2267                         mps = MLX5_MPW_ENHANCED;
2268                 } else {
2269                         DRV_LOG(DEBUG, "MPW is supported");
2270                         mps = MLX5_MPW;
2271                 }
2272         } else {
2273                 DRV_LOG(DEBUG, "MPW isn't supported");
2274                 mps = MLX5_MPW_DISABLED;
2275         }
2276 #ifdef HAVE_IBV_MLX5_MOD_SWP
2277         if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP)
2278                 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads;
2279         DRV_LOG(DEBUG, "SWP support: %u", swp);
2280 #endif
2281         config.swp = !!swp;
2282 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
2283         if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) {
2284                 struct mlx5dv_striding_rq_caps mprq_caps =
2285                         dv_attr.striding_rq_caps;
2286
2287                 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d",
2288                         mprq_caps.min_single_stride_log_num_of_bytes);
2289                 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d",
2290                         mprq_caps.max_single_stride_log_num_of_bytes);
2291                 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d",
2292                         mprq_caps.min_single_wqe_log_num_of_strides);
2293                 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d",
2294                         mprq_caps.max_single_wqe_log_num_of_strides);
2295                 DRV_LOG(DEBUG, "\tsupported_qpts: %d",
2296                         mprq_caps.supported_qpts);
2297                 DRV_LOG(DEBUG, "device supports Multi-Packet RQ");
2298                 mprq = 1;
2299                 mprq_min_stride_size_n =
2300                         mprq_caps.min_single_stride_log_num_of_bytes;
2301                 mprq_max_stride_size_n =
2302                         mprq_caps.max_single_stride_log_num_of_bytes;
2303                 mprq_min_stride_num_n =
2304                         mprq_caps.min_single_wqe_log_num_of_strides;
2305                 mprq_max_stride_num_n =
2306                         mprq_caps.max_single_wqe_log_num_of_strides;
2307                 config.mprq.stride_num_n = RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,
2308                                                    mprq_min_stride_num_n);
2309         }
2310 #endif
2311         if (RTE_CACHE_LINE_SIZE == 128 &&
2312             !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP))
2313                 cqe_comp = 0;
2314         else
2315                 cqe_comp = 1;
2316         config.cqe_comp = cqe_comp;
2317 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD
2318         /* Whether device supports 128B Rx CQE padding. */
2319         cqe_pad = RTE_CACHE_LINE_SIZE == 128 &&
2320                   (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_PAD);
2321 #endif
2322 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
2323         if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) {
2324                 tunnel_en = ((dv_attr.tunnel_offloads_caps &
2325                               MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) &&
2326                              (dv_attr.tunnel_offloads_caps &
2327                               MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE) &&
2328                              (dv_attr.tunnel_offloads_caps &
2329                               MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE));
2330         }
2331         DRV_LOG(DEBUG, "tunnel offloading is %ssupported",
2332                 tunnel_en ? "" : "not ");
2333 #else
2334         DRV_LOG(WARNING,
2335                 "tunnel offloading disabled due to old OFED/rdma-core version");
2336 #endif
2337         config.tunnel_en = tunnel_en;
2338 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
2339         mpls_en = ((dv_attr.tunnel_offloads_caps &
2340                     MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) &&
2341                    (dv_attr.tunnel_offloads_caps &
2342                     MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP));
2343         DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported",
2344                 mpls_en ? "" : "not ");
2345 #else
2346         DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to"
2347                 " old OFED/rdma-core version or firmware configuration");
2348 #endif
2349         config.mpls_en = mpls_en;
2350         /* Check port status. */
2351         err = mlx5_glue->query_port(sh->ctx, spawn->ibv_port, &port_attr);
2352         if (err) {
2353                 DRV_LOG(ERR, "port query failed: %s", strerror(err));
2354                 goto error;
2355         }
2356         if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
2357                 DRV_LOG(ERR, "port is not configured in Ethernet mode");
2358                 err = EINVAL;
2359                 goto error;
2360         }
2361         if (port_attr.state != IBV_PORT_ACTIVE)
2362                 DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)",
2363                         mlx5_glue->port_state_str(port_attr.state),
2364                         port_attr.state);
2365         /* Allocate private eth device data. */
2366         priv = rte_zmalloc("ethdev private structure",
2367                            sizeof(*priv),
2368                            RTE_CACHE_LINE_SIZE);
2369         if (priv == NULL) {
2370                 DRV_LOG(ERR, "priv allocation failure");
2371                 err = ENOMEM;
2372                 goto error;
2373         }
2374         priv->sh = sh;
2375         priv->ibv_port = spawn->ibv_port;
2376         priv->pci_dev = spawn->pci_dev;
2377         priv->mtu = RTE_ETHER_MTU;
2378 #ifndef RTE_ARCH_64
2379         /* Initialize UAR access locks for 32bit implementations. */
2380         rte_spinlock_init(&priv->uar_lock_cq);
2381         for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
2382                 rte_spinlock_init(&priv->uar_lock[i]);
2383 #endif
2384         /* Some internal functions rely on Netlink sockets, open them now. */
2385         priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA);
2386         priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE);
2387         priv->representor = !!switch_info->representor;
2388         priv->master = !!switch_info->master;
2389         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
2390         priv->vport_meta_tag = 0;
2391         priv->vport_meta_mask = 0;
2392         priv->pf_bond = spawn->pf_bond;
2393 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
2394         /*
2395          * The DevX port query API is implemented. E-Switch may use
2396          * either vport or reg_c[0] metadata register to match on
2397          * vport index. The engaged part of metadata register is
2398          * defined by mask.
2399          */
2400         if (switch_info->representor || switch_info->master) {
2401                 devx_port.comp_mask = MLX5DV_DEVX_PORT_VPORT |
2402                                       MLX5DV_DEVX_PORT_MATCH_REG_C_0;
2403                 err = mlx5_glue->devx_port_query(sh->ctx, spawn->ibv_port,
2404                                                  &devx_port);
2405                 if (err) {
2406                         DRV_LOG(WARNING,
2407                                 "can't query devx port %d on device %s",
2408                                 spawn->ibv_port, spawn->ibv_dev->name);
2409                         devx_port.comp_mask = 0;
2410                 }
2411         }
2412         if (devx_port.comp_mask & MLX5DV_DEVX_PORT_MATCH_REG_C_0) {
2413                 priv->vport_meta_tag = devx_port.reg_c_0.value;
2414                 priv->vport_meta_mask = devx_port.reg_c_0.mask;
2415                 if (!priv->vport_meta_mask) {
2416                         DRV_LOG(ERR, "vport zero mask for port %d"
2417                                      " on bonding device %s",
2418                                      spawn->ibv_port, spawn->ibv_dev->name);
2419                         err = ENOTSUP;
2420                         goto error;
2421                 }
2422                 if (priv->vport_meta_tag & ~priv->vport_meta_mask) {
2423                         DRV_LOG(ERR, "invalid vport tag for port %d"
2424                                      " on bonding device %s",
2425                                      spawn->ibv_port, spawn->ibv_dev->name);
2426                         err = ENOTSUP;
2427                         goto error;
2428                 }
2429         }
2430         if (devx_port.comp_mask & MLX5DV_DEVX_PORT_VPORT) {
2431                 priv->vport_id = devx_port.vport_num;
2432         } else if (spawn->pf_bond >= 0) {
2433                 DRV_LOG(ERR, "can't deduce vport index for port %d"
2434                              " on bonding device %s",
2435                              spawn->ibv_port, spawn->ibv_dev->name);
2436                 err = ENOTSUP;
2437                 goto error;
2438         } else {
2439                 /* Suppose vport index in compatible way. */
2440                 priv->vport_id = switch_info->representor ?
2441                                  switch_info->port_name + 1 : -1;
2442         }
2443 #else
2444         /*
2445          * Kernel/rdma_core support single E-Switch per PF configurations
2446          * only and vport_id field contains the vport index for
2447          * associated VF, which is deduced from representor port name.
2448          * For example, let's have the IB device port 10, it has
2449          * attached network device eth0, which has port name attribute
2450          * pf0vf2, we can deduce the VF number as 2, and set vport index
2451          * as 3 (2+1). This assigning schema should be changed if the
2452          * multiple E-Switch instances per PF configurations or/and PCI
2453          * subfunctions are added.
2454          */
2455         priv->vport_id = switch_info->representor ?
2456                          switch_info->port_name + 1 : -1;
2457 #endif
2458         /* representor_id field keeps the unmodified VF index. */
2459         priv->representor_id = switch_info->representor ?
2460                                switch_info->port_name : -1;
2461         /*
2462          * Look for sibling devices in order to reuse their switch domain
2463          * if any, otherwise allocate one.
2464          */
2465         MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
2466                 const struct mlx5_priv *opriv =
2467                         rte_eth_devices[port_id].data->dev_private;
2468
2469                 if (!opriv ||
2470                     opriv->sh != priv->sh ||
2471                         opriv->domain_id ==
2472                         RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID)
2473                         continue;
2474                 priv->domain_id = opriv->domain_id;
2475                 break;
2476         }
2477         if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
2478                 err = rte_eth_switch_domain_alloc(&priv->domain_id);
2479                 if (err) {
2480                         err = rte_errno;
2481                         DRV_LOG(ERR, "unable to allocate switch domain: %s",
2482                                 strerror(rte_errno));
2483                         goto error;
2484                 }
2485                 own_domain_id = 1;
2486         }
2487         /* Override some values set by hardware configuration. */
2488         mlx5_args(&config, dpdk_dev->devargs);
2489         err = mlx5_dev_check_sibling_config(priv, &config);
2490         if (err)
2491                 goto error;
2492         config.hw_csum = !!(sh->device_attr.device_cap_flags_ex &
2493                             IBV_DEVICE_RAW_IP_CSUM);
2494         DRV_LOG(DEBUG, "checksum offloading is %ssupported",
2495                 (config.hw_csum ? "" : "not "));
2496 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \
2497         !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
2498         DRV_LOG(DEBUG, "counters are not supported");
2499 #endif
2500 #if !defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_MLX5DV_DR)
2501         if (config.dv_flow_en) {
2502                 DRV_LOG(WARNING, "DV flow is not supported");
2503                 config.dv_flow_en = 0;
2504         }
2505 #endif
2506         config.ind_table_max_size =
2507                 sh->device_attr.rss_caps.max_rwq_indirection_table_size;
2508         /*
2509          * Remove this check once DPDK supports larger/variable
2510          * indirection tables.
2511          */
2512         if (config.ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512)
2513                 config.ind_table_max_size = ETH_RSS_RETA_SIZE_512;
2514         DRV_LOG(DEBUG, "maximum Rx indirection table size is %u",
2515                 config.ind_table_max_size);
2516         config.hw_vlan_strip = !!(sh->device_attr.raw_packet_caps &
2517                                   IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
2518         DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
2519                 (config.hw_vlan_strip ? "" : "not "));
2520         config.hw_fcs_strip = !!(sh->device_attr.raw_packet_caps &
2521                                  IBV_RAW_PACKET_CAP_SCATTER_FCS);
2522         DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported",
2523                 (config.hw_fcs_strip ? "" : "not "));
2524 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING)
2525         hw_padding = !!sh->device_attr.rx_pad_end_addr_align;
2526 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING)
2527         hw_padding = !!(sh->device_attr.device_cap_flags_ex &
2528                         IBV_DEVICE_PCI_WRITE_END_PADDING);
2529 #endif
2530         if (config.hw_padding && !hw_padding) {
2531                 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported");
2532                 config.hw_padding = 0;
2533         } else if (config.hw_padding) {
2534                 DRV_LOG(DEBUG, "Rx end alignment padding is enabled");
2535         }
2536         config.tso = (sh->device_attr.tso_caps.max_tso > 0 &&
2537                       (sh->device_attr.tso_caps.supported_qpts &
2538                        (1 << IBV_QPT_RAW_PACKET)));
2539         if (config.tso)
2540                 config.tso_max_payload_sz = sh->device_attr.tso_caps.max_tso;
2541         /*
2542          * MPW is disabled by default, while the Enhanced MPW is enabled
2543          * by default.
2544          */
2545         if (config.mps == MLX5_ARG_UNSET)
2546                 config.mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED :
2547                                                           MLX5_MPW_DISABLED;
2548         else
2549                 config.mps = config.mps ? mps : MLX5_MPW_DISABLED;
2550         DRV_LOG(INFO, "%sMPS is %s",
2551                 config.mps == MLX5_MPW_ENHANCED ? "enhanced " :
2552                 config.mps == MLX5_MPW ? "legacy " : "",
2553                 config.mps != MLX5_MPW_DISABLED ? "enabled" : "disabled");
2554         if (config.cqe_comp && !cqe_comp) {
2555                 DRV_LOG(WARNING, "Rx CQE compression isn't supported");
2556                 config.cqe_comp = 0;
2557         }
2558         if (config.cqe_pad && !cqe_pad) {
2559                 DRV_LOG(WARNING, "Rx CQE padding isn't supported");
2560                 config.cqe_pad = 0;
2561         } else if (config.cqe_pad) {
2562                 DRV_LOG(INFO, "Rx CQE padding is enabled");
2563         }
2564         if (config.devx) {
2565                 priv->counter_fallback = 0;
2566                 err = mlx5_devx_cmd_query_hca_attr(sh->ctx, &config.hca_attr);
2567                 if (err) {
2568                         err = -err;
2569                         goto error;
2570                 }
2571                 if (!config.hca_attr.flow_counters_dump)
2572                         priv->counter_fallback = 1;
2573 #ifndef HAVE_IBV_DEVX_ASYNC
2574                 priv->counter_fallback = 1;
2575 #endif
2576                 if (priv->counter_fallback)
2577                         DRV_LOG(INFO, "Use fall-back DV counter management");
2578                 /* Check for LRO support. */
2579                 if (config.dest_tir && config.hca_attr.lro_cap &&
2580                     config.dv_flow_en) {
2581                         /* TBD check tunnel lro caps. */
2582                         config.lro.supported = config.hca_attr.lro_cap;
2583                         DRV_LOG(DEBUG, "Device supports LRO");
2584                         /*
2585                          * If LRO timeout is not configured by application,
2586                          * use the minimal supported value.
2587                          */
2588                         if (!config.lro.timeout)
2589                                 config.lro.timeout =
2590                                 config.hca_attr.lro_timer_supported_periods[0];
2591                         DRV_LOG(DEBUG, "LRO session timeout set to %d usec",
2592                                 config.lro.timeout);
2593                 }
2594 #if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_METER)
2595                 if (config.hca_attr.qos.sup && config.hca_attr.qos.srtcm_sup &&
2596                     config.dv_flow_en) {
2597                         uint8_t reg_c_mask =
2598                                 config.hca_attr.qos.flow_meter_reg_c_ids;
2599                         /*
2600                          * Meter needs two REG_C's for color match and pre-sfx
2601                          * flow match. Here get the REG_C for color match.
2602                          * REG_C_0 and REG_C_1 is reserved for metadata feature.
2603                          */
2604                         reg_c_mask &= 0xfc;
2605                         if (__builtin_popcount(reg_c_mask) < 1) {
2606                                 priv->mtr_en = 0;
2607                                 DRV_LOG(WARNING, "No available register for"
2608                                         " meter.");
2609                         } else {
2610                                 priv->mtr_color_reg = ffs(reg_c_mask) - 1 +
2611                                                       REG_C_0;
2612                                 priv->mtr_en = 1;
2613                                 priv->mtr_reg_share =
2614                                       config.hca_attr.qos.flow_meter_reg_share;
2615                                 DRV_LOG(DEBUG, "The REG_C meter uses is %d",
2616                                         priv->mtr_color_reg);
2617                         }
2618                 }
2619 #endif
2620         }
2621         if (config.mprq.enabled && mprq) {
2622                 if (config.mprq.stride_num_n > mprq_max_stride_num_n ||
2623                     config.mprq.stride_num_n < mprq_min_stride_num_n) {
2624                         config.mprq.stride_num_n =
2625                                 RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,
2626                                         mprq_min_stride_num_n);
2627                         DRV_LOG(WARNING,
2628                                 "the number of strides"
2629                                 " for Multi-Packet RQ is out of range,"
2630                                 " setting default value (%u)",
2631                                 1 << config.mprq.stride_num_n);
2632                 }
2633                 config.mprq.min_stride_size_n = mprq_min_stride_size_n;
2634                 config.mprq.max_stride_size_n = mprq_max_stride_size_n;
2635         } else if (config.mprq.enabled && !mprq) {
2636                 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported");
2637                 config.mprq.enabled = 0;
2638         }
2639         if (config.max_dump_files_num == 0)
2640                 config.max_dump_files_num = 128;
2641         eth_dev = rte_eth_dev_allocate(name);
2642         if (eth_dev == NULL) {
2643                 DRV_LOG(ERR, "can not allocate rte ethdev");
2644                 err = ENOMEM;
2645                 goto error;
2646         }
2647         /* Flag to call rte_eth_dev_release_port() in rte_eth_dev_close(). */
2648         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2649         if (priv->representor) {
2650                 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR;
2651                 eth_dev->data->representor_id = priv->representor_id;
2652         }
2653         /*
2654          * Store associated network device interface index. This index
2655          * is permanent throughout the lifetime of device. So, we may store
2656          * the ifindex here and use the cached value further.
2657          */
2658         MLX5_ASSERT(spawn->ifindex);
2659         priv->if_index = spawn->ifindex;
2660         eth_dev->data->dev_private = priv;
2661         priv->dev_data = eth_dev->data;
2662         eth_dev->data->mac_addrs = priv->mac;
2663         eth_dev->device = dpdk_dev;
2664         /* Configure the first MAC address by default. */
2665         if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) {
2666                 DRV_LOG(ERR,
2667                         "port %u cannot get MAC address, is mlx5_en"
2668                         " loaded? (errno: %s)",
2669                         eth_dev->data->port_id, strerror(rte_errno));
2670                 err = ENODEV;
2671                 goto error;
2672         }
2673         DRV_LOG(INFO,
2674                 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x",
2675                 eth_dev->data->port_id,
2676                 mac.addr_bytes[0], mac.addr_bytes[1],
2677                 mac.addr_bytes[2], mac.addr_bytes[3],
2678                 mac.addr_bytes[4], mac.addr_bytes[5]);
2679 #ifdef RTE_LIBRTE_MLX5_DEBUG
2680         {
2681                 char ifname[IF_NAMESIZE];
2682
2683                 if (mlx5_get_ifname(eth_dev, &ifname) == 0)
2684                         DRV_LOG(DEBUG, "port %u ifname is \"%s\"",
2685                                 eth_dev->data->port_id, ifname);
2686                 else
2687                         DRV_LOG(DEBUG, "port %u ifname is unknown",
2688                                 eth_dev->data->port_id);
2689         }
2690 #endif
2691         /* Get actual MTU if possible. */
2692         err = mlx5_get_mtu(eth_dev, &priv->mtu);
2693         if (err) {
2694                 err = rte_errno;
2695                 goto error;
2696         }
2697         DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id,
2698                 priv->mtu);
2699         /* Initialize burst functions to prevent crashes before link-up. */
2700         eth_dev->rx_pkt_burst = removed_rx_burst;
2701         eth_dev->tx_pkt_burst = removed_tx_burst;
2702         eth_dev->dev_ops = &mlx5_dev_ops;
2703         /* Register MAC address. */
2704         claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
2705         if (config.vf && config.vf_nl_en)
2706                 mlx5_nl_mac_addr_sync(priv->nl_socket_route,
2707                                       mlx5_ifindex(eth_dev),
2708                                       eth_dev->data->mac_addrs,
2709                                       MLX5_MAX_MAC_ADDRESSES);
2710         TAILQ_INIT(&priv->flows);
2711         TAILQ_INIT(&priv->ctrl_flows);
2712         TAILQ_INIT(&priv->flow_meters);
2713         TAILQ_INIT(&priv->flow_meter_profiles);
2714         /* Hint libmlx5 to use PMD allocator for data plane resources */
2715         struct mlx5dv_ctx_allocators alctr = {
2716                 .alloc = &mlx5_alloc_verbs_buf,
2717                 .free = &mlx5_free_verbs_buf,
2718                 .data = priv,
2719         };
2720         mlx5_glue->dv_set_context_attr(sh->ctx,
2721                                        MLX5DV_CTX_ATTR_BUF_ALLOCATORS,
2722                                        (void *)((uintptr_t)&alctr));
2723         /* Bring Ethernet device up. */
2724         DRV_LOG(DEBUG, "port %u forcing Ethernet interface up",
2725                 eth_dev->data->port_id);
2726         mlx5_set_link_up(eth_dev);
2727         /*
2728          * Even though the interrupt handler is not installed yet,
2729          * interrupts will still trigger on the async_fd from
2730          * Verbs context returned by ibv_open_device().
2731          */
2732         mlx5_link_update(eth_dev, 0);
2733 #ifdef HAVE_MLX5DV_DR_ESWITCH
2734         if (!(config.hca_attr.eswitch_manager && config.dv_flow_en &&
2735               (switch_info->representor || switch_info->master)))
2736                 config.dv_esw_en = 0;
2737 #else
2738         config.dv_esw_en = 0;
2739 #endif
2740         /* Detect minimal data bytes to inline. */
2741         mlx5_set_min_inline(spawn, &config);
2742         /* Store device configuration on private structure. */
2743         priv->config = config;
2744         /* Create context for virtual machine VLAN workaround. */
2745         priv->vmwa_context = mlx5_vlan_vmwa_init(eth_dev, spawn->ifindex);
2746         if (config.dv_flow_en) {
2747                 err = mlx5_alloc_shared_dr(priv);
2748                 if (err)
2749                         goto error;
2750                 /*
2751                  * RSS id is shared with meter flow id. Meter flow id can only
2752                  * use the 24 MSB of the register.
2753                  */
2754                 priv->qrss_id_pool = mlx5_flow_id_pool_alloc(UINT32_MAX >>
2755                                      MLX5_MTR_COLOR_BITS);
2756                 if (!priv->qrss_id_pool) {
2757                         DRV_LOG(ERR, "can't create flow id pool");
2758                         err = ENOMEM;
2759                         goto error;
2760                 }
2761         }
2762         /* Supported Verbs flow priority number detection. */
2763         err = mlx5_flow_discover_priorities(eth_dev);
2764         if (err < 0) {
2765                 err = -err;
2766                 goto error;
2767         }
2768         priv->config.flow_prio = err;
2769         if (!priv->config.dv_esw_en &&
2770             priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
2771                 DRV_LOG(WARNING, "metadata mode %u is not supported "
2772                                  "(no E-Switch)", priv->config.dv_xmeta_en);
2773                 priv->config.dv_xmeta_en = MLX5_XMETA_MODE_LEGACY;
2774         }
2775         mlx5_set_metadata_mask(eth_dev);
2776         if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
2777             !priv->sh->dv_regc0_mask) {
2778                 DRV_LOG(ERR, "metadata mode %u is not supported "
2779                              "(no metadata reg_c[0] is available)",
2780                              priv->config.dv_xmeta_en);
2781                         err = ENOTSUP;
2782                         goto error;
2783         }
2784         /*
2785          * Allocate the buffer for flow creating, just once.
2786          * The allocation must be done before any flow creating.
2787          */
2788         mlx5_flow_alloc_intermediate(eth_dev);
2789         /* Query availibility of metadata reg_c's. */
2790         err = mlx5_flow_discover_mreg_c(eth_dev);
2791         if (err < 0) {
2792                 err = -err;
2793                 goto error;
2794         }
2795         if (!mlx5_flow_ext_mreg_supported(eth_dev)) {
2796                 DRV_LOG(DEBUG,
2797                         "port %u extensive metadata register is not supported",
2798                         eth_dev->data->port_id);
2799                 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
2800                         DRV_LOG(ERR, "metadata mode %u is not supported "
2801                                      "(no metadata registers available)",
2802                                      priv->config.dv_xmeta_en);
2803                         err = ENOTSUP;
2804                         goto error;
2805                 }
2806         }
2807         if (priv->config.dv_flow_en &&
2808             priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
2809             mlx5_flow_ext_mreg_supported(eth_dev) &&
2810             priv->sh->dv_regc0_mask) {
2811                 priv->mreg_cp_tbl = mlx5_hlist_create(MLX5_FLOW_MREG_HNAME,
2812                                                       MLX5_FLOW_MREG_HTABLE_SZ);
2813                 if (!priv->mreg_cp_tbl) {
2814                         err = ENOMEM;
2815                         goto error;
2816                 }
2817         }
2818         return eth_dev;
2819 error:
2820         if (priv) {
2821                 if (priv->mreg_cp_tbl)
2822                         mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
2823                 if (priv->sh)
2824                         mlx5_free_shared_dr(priv);
2825                 if (priv->nl_socket_route >= 0)
2826                         close(priv->nl_socket_route);
2827                 if (priv->nl_socket_rdma >= 0)
2828                         close(priv->nl_socket_rdma);
2829                 if (priv->vmwa_context)
2830                         mlx5_vlan_vmwa_exit(priv->vmwa_context);
2831                 if (priv->qrss_id_pool)
2832                         mlx5_flow_id_pool_release(priv->qrss_id_pool);
2833                 if (own_domain_id)
2834                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
2835                 rte_free(priv);
2836                 if (eth_dev != NULL)
2837                         eth_dev->data->dev_private = NULL;
2838         }
2839         if (eth_dev != NULL) {
2840                 /* mac_addrs must not be freed alone because part of dev_private */
2841                 eth_dev->data->mac_addrs = NULL;
2842                 rte_eth_dev_release_port(eth_dev);
2843         }
2844         if (sh)
2845                 mlx5_free_shared_ibctx(sh);
2846         MLX5_ASSERT(err > 0);
2847         rte_errno = err;
2848         return NULL;
2849 }
2850
2851 /**
2852  * Comparison callback to sort device data.
2853  *
2854  * This is meant to be used with qsort().
2855  *
2856  * @param a[in]
2857  *   Pointer to pointer to first data object.
2858  * @param b[in]
2859  *   Pointer to pointer to second data object.
2860  *
2861  * @return
2862  *   0 if both objects are equal, less than 0 if the first argument is less
2863  *   than the second, greater than 0 otherwise.
2864  */
2865 static int
2866 mlx5_dev_spawn_data_cmp(const void *a, const void *b)
2867 {
2868         const struct mlx5_switch_info *si_a =
2869                 &((const struct mlx5_dev_spawn_data *)a)->info;
2870         const struct mlx5_switch_info *si_b =
2871                 &((const struct mlx5_dev_spawn_data *)b)->info;
2872         int ret;
2873
2874         /* Master device first. */
2875         ret = si_b->master - si_a->master;
2876         if (ret)
2877                 return ret;
2878         /* Then representor devices. */
2879         ret = si_b->representor - si_a->representor;
2880         if (ret)
2881                 return ret;
2882         /* Unidentified devices come last in no specific order. */
2883         if (!si_a->representor)
2884                 return 0;
2885         /* Order representors by name. */
2886         return si_a->port_name - si_b->port_name;
2887 }
2888
2889 /**
2890  * Match PCI information for possible slaves of bonding device.
2891  *
2892  * @param[in] ibv_dev
2893  *   Pointer to Infiniband device structure.
2894  * @param[in] pci_dev
2895  *   Pointer to PCI device structure to match PCI address.
2896  * @param[in] nl_rdma
2897  *   Netlink RDMA group socket handle.
2898  *
2899  * @return
2900  *   negative value if no bonding device found, otherwise
2901  *   positive index of slave PF in bonding.
2902  */
2903 static int
2904 mlx5_device_bond_pci_match(const struct ibv_device *ibv_dev,
2905                            const struct rte_pci_device *pci_dev,
2906                            int nl_rdma)
2907 {
2908         char ifname[IF_NAMESIZE + 1];
2909         unsigned int ifindex;
2910         unsigned int np, i;
2911         FILE *file = NULL;
2912         int pf = -1;
2913
2914         /*
2915          * Try to get master device name. If something goes
2916          * wrong suppose the lack of kernel support and no
2917          * bonding devices.
2918          */
2919         if (nl_rdma < 0)
2920                 return -1;
2921         if (!strstr(ibv_dev->name, "bond"))
2922                 return -1;
2923         np = mlx5_nl_portnum(nl_rdma, ibv_dev->name);
2924         if (!np)
2925                 return -1;
2926         /*
2927          * The Master device might not be on the predefined
2928          * port (not on port index 1, it is not garanted),
2929          * we have to scan all Infiniband device port and
2930          * find master.
2931          */
2932         for (i = 1; i <= np; ++i) {
2933                 /* Check whether Infiniband port is populated. */
2934                 ifindex = mlx5_nl_ifindex(nl_rdma, ibv_dev->name, i);
2935                 if (!ifindex)
2936                         continue;
2937                 if (!if_indextoname(ifindex, ifname))
2938                         continue;
2939                 /* Try to read bonding slave names from sysfs. */
2940                 MKSTR(slaves,
2941                       "/sys/class/net/%s/master/bonding/slaves", ifname);
2942                 file = fopen(slaves, "r");
2943                 if (file)
2944                         break;
2945         }
2946         if (!file)
2947                 return -1;
2948         /* Use safe format to check maximal buffer length. */
2949         MLX5_ASSERT(atol(RTE_STR(IF_NAMESIZE)) == IF_NAMESIZE);
2950         while (fscanf(file, "%" RTE_STR(IF_NAMESIZE) "s", ifname) == 1) {
2951                 char tmp_str[IF_NAMESIZE + 32];
2952                 struct rte_pci_addr pci_addr;
2953                 struct mlx5_switch_info info;
2954
2955                 /* Process slave interface names in the loop. */
2956                 snprintf(tmp_str, sizeof(tmp_str),
2957                          "/sys/class/net/%s", ifname);
2958                 if (mlx5_dev_to_pci_addr(tmp_str, &pci_addr)) {
2959                         DRV_LOG(WARNING, "can not get PCI address"
2960                                          " for netdev \"%s\"", ifname);
2961                         continue;
2962                 }
2963                 if (pci_dev->addr.domain != pci_addr.domain ||
2964                     pci_dev->addr.bus != pci_addr.bus ||
2965                     pci_dev->addr.devid != pci_addr.devid ||
2966                     pci_dev->addr.function != pci_addr.function)
2967                         continue;
2968                 /* Slave interface PCI address match found. */
2969                 fclose(file);
2970                 snprintf(tmp_str, sizeof(tmp_str),
2971                          "/sys/class/net/%s/phys_port_name", ifname);
2972                 file = fopen(tmp_str, "rb");
2973                 if (!file)
2974                         break;
2975                 info.name_type = MLX5_PHYS_PORT_NAME_TYPE_NOTSET;
2976                 if (fscanf(file, "%32s", tmp_str) == 1)
2977                         mlx5_translate_port_name(tmp_str, &info);
2978                 if (info.name_type == MLX5_PHYS_PORT_NAME_TYPE_LEGACY ||
2979                     info.name_type == MLX5_PHYS_PORT_NAME_TYPE_UPLINK)
2980                         pf = info.port_name;
2981                 break;
2982         }
2983         if (file)
2984                 fclose(file);
2985         return pf;
2986 }
2987
2988 /**
2989  * DPDK callback to register a PCI device.
2990  *
2991  * This function spawns Ethernet devices out of a given PCI device.
2992  *
2993  * @param[in] pci_drv
2994  *   PCI driver structure (mlx5_driver).
2995  * @param[in] pci_dev
2996  *   PCI device information.
2997  *
2998  * @return
2999  *   0 on success, a negative errno value otherwise and rte_errno is set.
3000  */
3001 static int
3002 mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3003                struct rte_pci_device *pci_dev)
3004 {
3005         struct ibv_device **ibv_list;
3006         /*
3007          * Number of found IB Devices matching with requested PCI BDF.
3008          * nd != 1 means there are multiple IB devices over the same
3009          * PCI device and we have representors and master.
3010          */
3011         unsigned int nd = 0;
3012         /*
3013          * Number of found IB device Ports. nd = 1 and np = 1..n means
3014          * we have the single multiport IB device, and there may be
3015          * representors attached to some of found ports.
3016          */
3017         unsigned int np = 0;
3018         /*
3019          * Number of DPDK ethernet devices to Spawn - either over
3020          * multiple IB devices or multiple ports of single IB device.
3021          * Actually this is the number of iterations to spawn.
3022          */
3023         unsigned int ns = 0;
3024         /*
3025          * Bonding device
3026          *   < 0 - no bonding device (single one)
3027          *  >= 0 - bonding device (value is slave PF index)
3028          */
3029         int bd = -1;
3030         struct mlx5_dev_spawn_data *list = NULL;
3031         struct mlx5_dev_config dev_config;
3032         int ret;
3033
3034         if (mlx5_class_get(pci_dev->device.devargs) != MLX5_CLASS_NET) {
3035                 DRV_LOG(DEBUG, "Skip probing - should be probed by other mlx5"
3036                         " driver.");
3037                 return 1;
3038         }
3039         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
3040                 mlx5_pmd_socket_init();
3041         ret = mlx5_init_once();
3042         if (ret) {
3043                 DRV_LOG(ERR, "unable to init PMD global data: %s",
3044                         strerror(rte_errno));
3045                 return -rte_errno;
3046         }
3047         MLX5_ASSERT(pci_drv == &mlx5_driver);
3048         errno = 0;
3049         ibv_list = mlx5_glue->get_device_list(&ret);
3050         if (!ibv_list) {
3051                 rte_errno = errno ? errno : ENOSYS;
3052                 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?");
3053                 return -rte_errno;
3054         }
3055         /*
3056          * First scan the list of all Infiniband devices to find
3057          * matching ones, gathering into the list.
3058          */
3059         struct ibv_device *ibv_match[ret + 1];
3060         int nl_route = mlx5_nl_init(NETLINK_ROUTE);
3061         int nl_rdma = mlx5_nl_init(NETLINK_RDMA);
3062         unsigned int i;
3063
3064         while (ret-- > 0) {
3065                 struct rte_pci_addr pci_addr;
3066
3067                 DRV_LOG(DEBUG, "checking device \"%s\"", ibv_list[ret]->name);
3068                 bd = mlx5_device_bond_pci_match
3069                                 (ibv_list[ret], pci_dev, nl_rdma);
3070                 if (bd >= 0) {
3071                         /*
3072                          * Bonding device detected. Only one match is allowed,
3073                          * the bonding is supported over multi-port IB device,
3074                          * there should be no matches on representor PCI
3075                          * functions or non VF LAG bonding devices with
3076                          * specified address.
3077                          */
3078                         if (nd) {
3079                                 DRV_LOG(ERR,
3080                                         "multiple PCI match on bonding device"
3081                                         "\"%s\" found", ibv_list[ret]->name);
3082                                 rte_errno = ENOENT;
3083                                 ret = -rte_errno;
3084                                 goto exit;
3085                         }
3086                         DRV_LOG(INFO, "PCI information matches for"
3087                                       " slave %d bonding device \"%s\"",
3088                                       bd, ibv_list[ret]->name);
3089                         ibv_match[nd++] = ibv_list[ret];
3090                         break;
3091                 }
3092                 if (mlx5_dev_to_pci_addr
3093                         (ibv_list[ret]->ibdev_path, &pci_addr))
3094                         continue;
3095                 if (pci_dev->addr.domain != pci_addr.domain ||
3096                     pci_dev->addr.bus != pci_addr.bus ||
3097                     pci_dev->addr.devid != pci_addr.devid ||
3098                     pci_dev->addr.function != pci_addr.function)
3099                         continue;
3100                 DRV_LOG(INFO, "PCI information matches for device \"%s\"",
3101                         ibv_list[ret]->name);
3102                 ibv_match[nd++] = ibv_list[ret];
3103         }
3104         ibv_match[nd] = NULL;
3105         if (!nd) {
3106                 /* No device matches, just complain and bail out. */
3107                 DRV_LOG(WARNING,
3108                         "no Verbs device matches PCI device " PCI_PRI_FMT ","
3109                         " are kernel drivers loaded?",
3110                         pci_dev->addr.domain, pci_dev->addr.bus,
3111                         pci_dev->addr.devid, pci_dev->addr.function);
3112                 rte_errno = ENOENT;
3113                 ret = -rte_errno;
3114                 goto exit;
3115         }
3116         if (nd == 1) {
3117                 /*
3118                  * Found single matching device may have multiple ports.
3119                  * Each port may be representor, we have to check the port
3120                  * number and check the representors existence.
3121                  */
3122                 if (nl_rdma >= 0)
3123                         np = mlx5_nl_portnum(nl_rdma, ibv_match[0]->name);
3124                 if (!np)
3125                         DRV_LOG(WARNING, "can not get IB device \"%s\""
3126                                          " ports number", ibv_match[0]->name);
3127                 if (bd >= 0 && !np) {
3128                         DRV_LOG(ERR, "can not get ports"
3129                                      " for bonding device");
3130                         rte_errno = ENOENT;
3131                         ret = -rte_errno;
3132                         goto exit;
3133                 }
3134         }
3135 #ifndef HAVE_MLX5DV_DR_DEVX_PORT
3136         if (bd >= 0) {
3137                 /*
3138                  * This may happen if there is VF LAG kernel support and
3139                  * application is compiled with older rdma_core library.
3140                  */
3141                 DRV_LOG(ERR,
3142                         "No kernel/verbs support for VF LAG bonding found.");
3143                 rte_errno = ENOTSUP;
3144                 ret = -rte_errno;
3145                 goto exit;
3146         }
3147 #endif
3148         /*
3149          * Now we can determine the maximal
3150          * amount of devices to be spawned.
3151          */
3152         list = rte_zmalloc("device spawn data",
3153                          sizeof(struct mlx5_dev_spawn_data) *
3154                          (np ? np : nd),
3155                          RTE_CACHE_LINE_SIZE);
3156         if (!list) {
3157                 DRV_LOG(ERR, "spawn data array allocation failure");
3158                 rte_errno = ENOMEM;
3159                 ret = -rte_errno;
3160                 goto exit;
3161         }
3162         if (bd >= 0 || np > 1) {
3163                 /*
3164                  * Single IB device with multiple ports found,
3165                  * it may be E-Switch master device and representors.
3166                  * We have to perform identification trough the ports.
3167                  */
3168                 MLX5_ASSERT(nl_rdma >= 0);
3169                 MLX5_ASSERT(ns == 0);
3170                 MLX5_ASSERT(nd == 1);
3171                 MLX5_ASSERT(np);
3172                 for (i = 1; i <= np; ++i) {
3173                         list[ns].max_port = np;
3174                         list[ns].ibv_port = i;
3175                         list[ns].ibv_dev = ibv_match[0];
3176                         list[ns].eth_dev = NULL;
3177                         list[ns].pci_dev = pci_dev;
3178                         list[ns].pf_bond = bd;
3179                         list[ns].ifindex = mlx5_nl_ifindex
3180                                         (nl_rdma, list[ns].ibv_dev->name, i);
3181                         if (!list[ns].ifindex) {
3182                                 /*
3183                                  * No network interface index found for the
3184                                  * specified port, it means there is no
3185                                  * representor on this port. It's OK,
3186                                  * there can be disabled ports, for example
3187                                  * if sriov_numvfs < sriov_totalvfs.
3188                                  */
3189                                 continue;
3190                         }
3191                         ret = -1;
3192                         if (nl_route >= 0)
3193                                 ret = mlx5_nl_switch_info
3194                                                (nl_route,
3195                                                 list[ns].ifindex,
3196                                                 &list[ns].info);
3197                         if (ret || (!list[ns].info.representor &&
3198                                     !list[ns].info.master)) {
3199                                 /*
3200                                  * We failed to recognize representors with
3201                                  * Netlink, let's try to perform the task
3202                                  * with sysfs.
3203                                  */
3204                                 ret =  mlx5_sysfs_switch_info
3205                                                 (list[ns].ifindex,
3206                                                  &list[ns].info);
3207                         }
3208                         if (!ret && bd >= 0) {
3209                                 switch (list[ns].info.name_type) {
3210                                 case MLX5_PHYS_PORT_NAME_TYPE_UPLINK:
3211                                         if (list[ns].info.port_name == bd)
3212                                                 ns++;
3213                                         break;
3214                                 case MLX5_PHYS_PORT_NAME_TYPE_PFVF:
3215                                         if (list[ns].info.pf_num == bd)
3216                                                 ns++;
3217                                         break;
3218                                 default:
3219                                         break;
3220                                 }
3221                                 continue;
3222                         }
3223                         if (!ret && (list[ns].info.representor ^
3224                                      list[ns].info.master))
3225                                 ns++;
3226                 }
3227                 if (!ns) {
3228                         DRV_LOG(ERR,
3229                                 "unable to recognize master/representors"
3230                                 " on the IB device with multiple ports");
3231                         rte_errno = ENOENT;
3232                         ret = -rte_errno;
3233                         goto exit;
3234                 }
3235         } else {
3236                 /*
3237                  * The existence of several matching entries (nd > 1) means
3238                  * port representors have been instantiated. No existing Verbs
3239                  * call nor sysfs entries can tell them apart, this can only
3240                  * be done through Netlink calls assuming kernel drivers are
3241                  * recent enough to support them.
3242                  *
3243                  * In the event of identification failure through Netlink,
3244                  * try again through sysfs, then:
3245                  *
3246                  * 1. A single IB device matches (nd == 1) with single
3247                  *    port (np=0/1) and is not a representor, assume
3248                  *    no switch support.
3249                  *
3250                  * 2. Otherwise no safe assumptions can be made;
3251                  *    complain louder and bail out.
3252                  */
3253                 np = 1;
3254                 for (i = 0; i != nd; ++i) {
3255                         memset(&list[ns].info, 0, sizeof(list[ns].info));
3256                         list[ns].max_port = 1;
3257                         list[ns].ibv_port = 1;
3258                         list[ns].ibv_dev = ibv_match[i];
3259                         list[ns].eth_dev = NULL;
3260                         list[ns].pci_dev = pci_dev;
3261                         list[ns].pf_bond = -1;
3262                         list[ns].ifindex = 0;
3263                         if (nl_rdma >= 0)
3264                                 list[ns].ifindex = mlx5_nl_ifindex
3265                                         (nl_rdma, list[ns].ibv_dev->name, 1);
3266                         if (!list[ns].ifindex) {
3267                                 char ifname[IF_NAMESIZE];
3268
3269                                 /*
3270                                  * Netlink failed, it may happen with old
3271                                  * ib_core kernel driver (before 4.16).
3272                                  * We can assume there is old driver because
3273                                  * here we are processing single ports IB
3274                                  * devices. Let's try sysfs to retrieve
3275                                  * the ifindex. The method works for
3276                                  * master device only.
3277                                  */
3278                                 if (nd > 1) {
3279                                         /*
3280                                          * Multiple devices found, assume
3281                                          * representors, can not distinguish
3282                                          * master/representor and retrieve
3283                                          * ifindex via sysfs.
3284                                          */
3285                                         continue;
3286                                 }
3287                                 ret = mlx5_get_master_ifname
3288                                         (ibv_match[i]->ibdev_path, &ifname);
3289                                 if (!ret)
3290                                         list[ns].ifindex =
3291                                                 if_nametoindex(ifname);
3292                                 if (!list[ns].ifindex) {
3293                                         /*
3294                                          * No network interface index found
3295                                          * for the specified device, it means
3296                                          * there it is neither representor
3297                                          * nor master.
3298                                          */
3299                                         continue;
3300                                 }
3301                         }
3302                         ret = -1;
3303                         if (nl_route >= 0)
3304                                 ret = mlx5_nl_switch_info
3305                                                (nl_route,
3306                                                 list[ns].ifindex,
3307                                                 &list[ns].info);
3308                         if (ret || (!list[ns].info.representor &&
3309                                     !list[ns].info.master)) {
3310                                 /*
3311                                  * We failed to recognize representors with
3312                                  * Netlink, let's try to perform the task
3313                                  * with sysfs.
3314                                  */
3315                                 ret =  mlx5_sysfs_switch_info
3316                                                 (list[ns].ifindex,
3317                                                  &list[ns].info);
3318                         }
3319                         if (!ret && (list[ns].info.representor ^
3320                                      list[ns].info.master)) {
3321                                 ns++;
3322                         } else if ((nd == 1) &&
3323                                    !list[ns].info.representor &&
3324                                    !list[ns].info.master) {
3325                                 /*
3326                                  * Single IB device with
3327                                  * one physical port and
3328                                  * attached network device.
3329                                  * May be SRIOV is not enabled
3330                                  * or there is no representors.
3331                                  */
3332                                 DRV_LOG(INFO, "no E-Switch support detected");
3333                                 ns++;
3334                                 break;
3335                         }
3336                 }
3337                 if (!ns) {
3338                         DRV_LOG(ERR,
3339                                 "unable to recognize master/representors"
3340                                 " on the multiple IB devices");
3341                         rte_errno = ENOENT;
3342                         ret = -rte_errno;
3343                         goto exit;
3344                 }
3345         }
3346         MLX5_ASSERT(ns);
3347         /*
3348          * Sort list to probe devices in natural order for users convenience
3349          * (i.e. master first, then representors from lowest to highest ID).
3350          */
3351         qsort(list, ns, sizeof(*list), mlx5_dev_spawn_data_cmp);
3352         /* Default configuration. */
3353         dev_config = (struct mlx5_dev_config){
3354                 .hw_padding = 0,
3355                 .mps = MLX5_ARG_UNSET,
3356                 .dbnc = MLX5_ARG_UNSET,
3357                 .rx_vec_en = 1,
3358                 .txq_inline_max = MLX5_ARG_UNSET,
3359                 .txq_inline_min = MLX5_ARG_UNSET,
3360                 .txq_inline_mpw = MLX5_ARG_UNSET,
3361                 .txqs_inline = MLX5_ARG_UNSET,
3362                 .vf_nl_en = 1,
3363                 .mr_ext_memseg_en = 1,
3364                 .mprq = {
3365                         .enabled = 0, /* Disabled by default. */
3366                         .stride_num_n = MLX5_MPRQ_STRIDE_NUM_N,
3367                         .max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN,
3368                         .min_rxqs_num = MLX5_MPRQ_MIN_RXQS,
3369                 },
3370                 .dv_esw_en = 1,
3371                 .dv_flow_en = 1,
3372                 .log_hp_size = MLX5_ARG_UNSET,
3373         };
3374         /* Device specific configuration. */
3375         switch (pci_dev->id.device_id) {
3376         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
3377         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
3378         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
3379         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
3380         case PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF:
3381         case PCI_DEVICE_ID_MELLANOX_CONNECTX6VF:
3382         case PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF:
3383                 dev_config.vf = 1;
3384                 break;
3385         default:
3386                 break;
3387         }
3388         for (i = 0; i != ns; ++i) {
3389                 uint32_t restore;
3390
3391                 list[i].eth_dev = mlx5_dev_spawn(&pci_dev->device,
3392                                                  &list[i],
3393                                                  dev_config);
3394                 if (!list[i].eth_dev) {
3395                         if (rte_errno != EBUSY && rte_errno != EEXIST)
3396                                 break;
3397                         /* Device is disabled or already spawned. Ignore it. */
3398                         continue;
3399                 }
3400                 restore = list[i].eth_dev->data->dev_flags;
3401                 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev);
3402                 /* Restore non-PCI flags cleared by the above call. */
3403                 list[i].eth_dev->data->dev_flags |= restore;
3404                 mlx5_dev_interrupt_handler_devx_install(list[i].eth_dev);
3405                 rte_eth_dev_probing_finish(list[i].eth_dev);
3406         }
3407         if (i != ns) {
3408                 DRV_LOG(ERR,
3409                         "probe of PCI device " PCI_PRI_FMT " aborted after"
3410                         " encountering an error: %s",
3411                         pci_dev->addr.domain, pci_dev->addr.bus,
3412                         pci_dev->addr.devid, pci_dev->addr.function,
3413                         strerror(rte_errno));
3414                 ret = -rte_errno;
3415                 /* Roll back. */
3416                 while (i--) {
3417                         if (!list[i].eth_dev)
3418                                 continue;
3419                         mlx5_dev_close(list[i].eth_dev);
3420                         /* mac_addrs must not be freed because in dev_private */
3421                         list[i].eth_dev->data->mac_addrs = NULL;
3422                         claim_zero(rte_eth_dev_release_port(list[i].eth_dev));
3423                 }
3424                 /* Restore original error. */
3425                 rte_errno = -ret;
3426         } else {
3427                 ret = 0;
3428         }
3429 exit:
3430         /*
3431          * Do the routine cleanup:
3432          * - close opened Netlink sockets
3433          * - free allocated spawn data array
3434          * - free the Infiniband device list
3435          */
3436         if (nl_rdma >= 0)
3437                 close(nl_rdma);
3438         if (nl_route >= 0)
3439                 close(nl_route);
3440         if (list)
3441                 rte_free(list);
3442         MLX5_ASSERT(ibv_list);
3443         mlx5_glue->free_device_list(ibv_list);
3444         return ret;
3445 }
3446
3447 /**
3448  * Look for the ethernet device belonging to mlx5 driver.
3449  *
3450  * @param[in] port_id
3451  *   port_id to start looking for device.
3452  * @param[in] pci_dev
3453  *   Pointer to the hint PCI device. When device is being probed
3454  *   the its siblings (master and preceding representors might
3455  *   not have assigned driver yet (because the mlx5_pci_probe()
3456  *   is not completed yet, for this case match on hint PCI
3457  *   device may be used to detect sibling device.
3458  *
3459  * @return
3460  *   port_id of found device, RTE_MAX_ETHPORT if not found.
3461  */
3462 uint16_t
3463 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
3464 {
3465         while (port_id < RTE_MAX_ETHPORTS) {
3466                 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
3467
3468                 if (dev->state != RTE_ETH_DEV_UNUSED &&
3469                     dev->device &&
3470                     (dev->device == &pci_dev->device ||
3471                      (dev->device->driver &&
3472                      dev->device->driver->name &&
3473                      !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
3474                         break;
3475                 port_id++;
3476         }
3477         if (port_id >= RTE_MAX_ETHPORTS)
3478                 return RTE_MAX_ETHPORTS;
3479         return port_id;
3480 }
3481
3482 /**
3483  * DPDK callback to remove a PCI device.
3484  *
3485  * This function removes all Ethernet devices belong to a given PCI device.
3486  *
3487  * @param[in] pci_dev
3488  *   Pointer to the PCI device.
3489  *
3490  * @return
3491  *   0 on success, the function cannot fail.
3492  */
3493 static int
3494 mlx5_pci_remove(struct rte_pci_device *pci_dev)
3495 {
3496         uint16_t port_id;
3497
3498         RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device)
3499                 rte_eth_dev_close(port_id);
3500         return 0;
3501 }
3502
3503 static const struct rte_pci_id mlx5_pci_id_map[] = {
3504         {
3505                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3506                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
3507         },
3508         {
3509                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3510                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
3511         },
3512         {
3513                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3514                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
3515         },
3516         {
3517                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3518                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
3519         },
3520         {
3521                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3522                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
3523         },
3524         {
3525                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3526                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
3527         },
3528         {
3529                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3530                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
3531         },
3532         {
3533                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3534                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
3535         },
3536         {
3537                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3538                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
3539         },
3540         {
3541                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3542                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
3543         },
3544         {
3545                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3546                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
3547         },
3548         {
3549                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3550                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
3551         },
3552         {
3553                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3554                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
3555         },
3556         {
3557                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3558                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF)
3559         },
3560         {
3561                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3562                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
3563         },
3564         {
3565                 .vendor_id = 0
3566         }
3567 };
3568
3569 static struct rte_pci_driver mlx5_driver = {
3570         .driver = {
3571                 .name = MLX5_DRIVER_NAME
3572         },
3573         .id_table = mlx5_pci_id_map,
3574         .probe = mlx5_pci_probe,
3575         .remove = mlx5_pci_remove,
3576         .dma_map = mlx5_dma_map,
3577         .dma_unmap = mlx5_dma_unmap,
3578         .drv_flags = RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV |
3579                      RTE_PCI_DRV_PROBE_AGAIN,
3580 };
3581
3582 /**
3583  * Driver initialization routine.
3584  */
3585 RTE_INIT(rte_mlx5_pmd_init)
3586 {
3587         /* Initialize driver log type. */
3588         mlx5_logtype = rte_log_register("pmd.net.mlx5");
3589         if (mlx5_logtype >= 0)
3590                 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE);
3591
3592         /* Build the static tables for Verbs conversion. */
3593         mlx5_set_ptype_table();
3594         mlx5_set_cksum_table();
3595         mlx5_set_swp_types_table();
3596         if (mlx5_glue)
3597                 rte_pci_register(&mlx5_driver);
3598 }
3599
3600 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
3601 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
3602 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");