1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
13 #include <rte_malloc.h>
14 #include <ethdev_driver.h>
16 #include <rte_bus_pci.h>
17 #include <rte_common.h>
18 #include <rte_kvargs.h>
19 #include <rte_rwlock.h>
20 #include <rte_spinlock.h>
21 #include <rte_string_fns.h>
22 #include <rte_eal_paging.h>
23 #include <rte_alarm.h>
24 #include <rte_cycles.h>
26 #include <mlx5_glue.h>
27 #include <mlx5_devx_cmds.h>
28 #include <mlx5_common.h>
29 #include <mlx5_common_os.h>
30 #include <mlx5_common_mp.h>
31 #include <mlx5_malloc.h>
33 #include "mlx5_defs.h"
35 #include "mlx5_utils.h"
36 #include "mlx5_rxtx.h"
39 #include "mlx5_autoconf.h"
40 #include "mlx5_flow.h"
41 #include "mlx5_flow_os.h"
42 #include "rte_pmd_mlx5.h"
44 #define MLX5_ETH_DRIVER_NAME mlx5_eth
46 /* Device parameter to enable RX completion queue compression. */
47 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
49 /* Device parameter to enable padding Rx packet to cacheline size. */
50 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
52 /* Device parameter to enable Multi-Packet Rx queue. */
53 #define MLX5_RX_MPRQ_EN "mprq_en"
55 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
56 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
58 /* Device parameter to configure log 2 of the stride size for MPRQ. */
59 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
61 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
62 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
64 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
65 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
67 /* Device parameter to configure inline send. Deprecated, ignored.*/
68 #define MLX5_TXQ_INLINE "txq_inline"
70 /* Device parameter to limit packet size to inline with ordinary SEND. */
71 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
73 /* Device parameter to configure minimal data size to inline. */
74 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
76 /* Device parameter to limit packet size to inline with Enhanced MPW. */
77 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
80 * Device parameter to configure the number of TX queues threshold for
81 * enabling inline send.
83 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
86 * Device parameter to configure the number of TX queues threshold for
87 * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
89 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
91 /* Device parameter to enable multi-packet send WQEs. */
92 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
95 * Device parameter to include 2 dsegs in the title WQEBB.
96 * Deprecated, ignored.
98 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
101 * Device parameter to limit the size of inlining packet.
102 * Deprecated, ignored.
104 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
107 * Device parameter to enable Tx scheduling on timestamps
108 * and specify the packet pacing granularity in nanoseconds.
110 #define MLX5_TX_PP "tx_pp"
113 * Device parameter to specify skew in nanoseconds on Tx datapath,
114 * it represents the time between SQ start WQE processing and
115 * appearing actual packet data on the wire.
117 #define MLX5_TX_SKEW "tx_skew"
120 * Device parameter to enable hardware Tx vector.
121 * Deprecated, ignored (no vectorized Tx routines anymore).
123 #define MLX5_TX_VEC_EN "tx_vec_en"
125 /* Device parameter to enable hardware Rx vector. */
126 #define MLX5_RX_VEC_EN "rx_vec_en"
128 /* Allow L3 VXLAN flow creation. */
129 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
131 /* Activate DV E-Switch flow steering. */
132 #define MLX5_DV_ESW_EN "dv_esw_en"
134 /* Activate DV flow steering. */
135 #define MLX5_DV_FLOW_EN "dv_flow_en"
137 /* Enable extensive flow metadata support. */
138 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
140 /* Device parameter to let the user manage the lacp traffic of bonded device */
141 #define MLX5_LACP_BY_USER "lacp_by_user"
143 /* Activate Netlink support in VF mode. */
144 #define MLX5_VF_NL_EN "vf_nl_en"
146 /* Select port representors to instantiate. */
147 #define MLX5_REPRESENTOR "representor"
149 /* Device parameter to configure the maximum number of dump files per queue. */
150 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
152 /* Configure timeout of LRO session (in microseconds). */
153 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
156 * Device parameter to configure the total data buffer size for a single
157 * hairpin queue (logarithm value).
159 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
161 /* Flow memory reclaim mode. */
162 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
164 /* Decap will be used or not. */
165 #define MLX5_DECAP_EN "decap_en"
167 /* Device parameter to configure allow or prevent duplicate rules pattern. */
168 #define MLX5_ALLOW_DUPLICATE_PATTERN "allow_duplicate_pattern"
170 /* Device parameter to configure the delay drop when creating Rxqs. */
171 #define MLX5_DELAY_DROP "delay_drop"
173 /* Shared memory between primary and secondary processes. */
174 struct mlx5_shared_data *mlx5_shared_data;
176 /** Driver-specific log messages type. */
179 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
180 LIST_HEAD_INITIALIZER();
181 static pthread_mutex_t mlx5_dev_ctx_list_mutex;
182 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
183 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
184 [MLX5_IPOOL_DECAP_ENCAP] = {
185 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
191 .malloc = mlx5_malloc,
193 .type = "mlx5_encap_decap_ipool",
195 [MLX5_IPOOL_PUSH_VLAN] = {
196 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
202 .malloc = mlx5_malloc,
204 .type = "mlx5_push_vlan_ipool",
207 .size = sizeof(struct mlx5_flow_dv_tag_resource),
213 .per_core_cache = (1 << 16),
214 .malloc = mlx5_malloc,
216 .type = "mlx5_tag_ipool",
218 [MLX5_IPOOL_PORT_ID] = {
219 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
225 .malloc = mlx5_malloc,
227 .type = "mlx5_port_id_ipool",
229 [MLX5_IPOOL_JUMP] = {
230 .size = sizeof(struct mlx5_flow_tbl_data_entry),
236 .malloc = mlx5_malloc,
238 .type = "mlx5_jump_ipool",
240 [MLX5_IPOOL_SAMPLE] = {
241 .size = sizeof(struct mlx5_flow_dv_sample_resource),
247 .malloc = mlx5_malloc,
249 .type = "mlx5_sample_ipool",
251 [MLX5_IPOOL_DEST_ARRAY] = {
252 .size = sizeof(struct mlx5_flow_dv_dest_array_resource),
258 .malloc = mlx5_malloc,
260 .type = "mlx5_dest_array_ipool",
262 [MLX5_IPOOL_TUNNEL_ID] = {
263 .size = sizeof(struct mlx5_flow_tunnel),
264 .trunk_size = MLX5_MAX_TUNNELS,
267 .type = "mlx5_tunnel_offload",
269 [MLX5_IPOOL_TNL_TBL_ID] = {
272 .type = "mlx5_flow_tnl_tbl_ipool",
277 * The ipool index should grow continually from small to big,
278 * for meter idx, so not set grow_trunk to avoid meter index
279 * not jump continually.
281 .size = sizeof(struct mlx5_legacy_flow_meter),
285 .malloc = mlx5_malloc,
287 .type = "mlx5_meter_ipool",
290 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
296 .malloc = mlx5_malloc,
298 .type = "mlx5_mcp_ipool",
300 [MLX5_IPOOL_HRXQ] = {
301 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
307 .malloc = mlx5_malloc,
309 .type = "mlx5_hrxq_ipool",
311 [MLX5_IPOOL_MLX5_FLOW] = {
313 * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
314 * It set in run time according to PCI function configuration.
322 .per_core_cache = 1 << 19,
323 .malloc = mlx5_malloc,
325 .type = "mlx5_flow_handle_ipool",
327 [MLX5_IPOOL_RTE_FLOW] = {
328 .size = sizeof(struct rte_flow),
332 .malloc = mlx5_malloc,
334 .type = "rte_flow_ipool",
336 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID] = {
339 .type = "mlx5_flow_rss_id_ipool",
341 [MLX5_IPOOL_RSS_SHARED_ACTIONS] = {
342 .size = sizeof(struct mlx5_shared_action_rss),
348 .malloc = mlx5_malloc,
350 .type = "mlx5_shared_action_rss",
352 [MLX5_IPOOL_MTR_POLICY] = {
354 * The ipool index should grow continually from small to big,
355 * for policy idx, so not set grow_trunk to avoid policy index
356 * not jump continually.
358 .size = sizeof(struct mlx5_flow_meter_sub_policy),
362 .malloc = mlx5_malloc,
364 .type = "mlx5_meter_policy_ipool",
368 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
369 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
371 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 1024
374 * Decide whether representor ID is a HPF(host PF) port on BF2.
377 * Pointer to Ethernet device structure.
380 * Non-zero if HPF, otherwise 0.
383 mlx5_is_hpf(struct rte_eth_dev *dev)
385 struct mlx5_priv *priv = dev->data->dev_private;
386 uint16_t repr = MLX5_REPRESENTOR_REPR(priv->representor_id);
387 int type = MLX5_REPRESENTOR_TYPE(priv->representor_id);
389 return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_VF &&
390 MLX5_REPRESENTOR_REPR(-1) == repr;
394 * Decide whether representor ID is a SF port representor.
397 * Pointer to Ethernet device structure.
400 * Non-zero if HPF, otherwise 0.
403 mlx5_is_sf_repr(struct rte_eth_dev *dev)
405 struct mlx5_priv *priv = dev->data->dev_private;
406 int type = MLX5_REPRESENTOR_TYPE(priv->representor_id);
408 return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_SF;
412 * Initialize the ASO aging management structure.
415 * Pointer to mlx5_dev_ctx_shared object to free
418 * 0 on success, a negative errno value otherwise and rte_errno is set.
421 mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh)
427 sh->aso_age_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->aso_age_mng),
428 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
429 if (!sh->aso_age_mng) {
430 DRV_LOG(ERR, "aso_age_mng allocation was failed.");
434 err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_FLOW_HIT);
436 mlx5_free(sh->aso_age_mng);
439 rte_rwlock_init(&sh->aso_age_mng->resize_rwl);
440 rte_spinlock_init(&sh->aso_age_mng->free_sl);
441 LIST_INIT(&sh->aso_age_mng->free);
446 * Close and release all the resources of the ASO aging management structure.
449 * Pointer to mlx5_dev_ctx_shared object to free.
452 mlx5_flow_aso_age_mng_close(struct mlx5_dev_ctx_shared *sh)
456 mlx5_aso_flow_hit_queue_poll_stop(sh);
457 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_FLOW_HIT);
458 if (sh->aso_age_mng->pools) {
459 struct mlx5_aso_age_pool *pool;
461 for (i = 0; i < sh->aso_age_mng->next; ++i) {
462 pool = sh->aso_age_mng->pools[i];
463 claim_zero(mlx5_devx_cmd_destroy
464 (pool->flow_hit_aso_obj));
465 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j)
466 if (pool->actions[j].dr_action)
468 (mlx5_flow_os_destroy_flow_action
469 (pool->actions[j].dr_action));
472 mlx5_free(sh->aso_age_mng->pools);
474 mlx5_free(sh->aso_age_mng);
478 * Initialize the shared aging list information per port.
481 * Pointer to mlx5_dev_ctx_shared object.
484 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
487 struct mlx5_age_info *age_info;
489 for (i = 0; i < sh->max_port; i++) {
490 age_info = &sh->port[i].age_info;
492 TAILQ_INIT(&age_info->aged_counters);
493 LIST_INIT(&age_info->aged_aso);
494 rte_spinlock_init(&age_info->aged_sl);
495 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
500 * DV flow counter mode detect and config.
503 * Pointer to rte_eth_dev structure.
507 mlx5_flow_counter_mode_config(struct rte_eth_dev *dev __rte_unused)
509 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
510 struct mlx5_priv *priv = dev->data->dev_private;
511 struct mlx5_dev_ctx_shared *sh = priv->sh;
512 struct mlx5_hca_attr *hca_attr = &sh->cdev->config.hca_attr;
515 #ifndef HAVE_IBV_DEVX_ASYNC
519 if (!sh->cdev->config.devx || !sh->config.dv_flow_en ||
520 !hca_attr->flow_counters_dump ||
521 !(hca_attr->flow_counter_bulk_alloc_bitmap & 0x4) ||
522 (mlx5_flow_dv_discover_counter_offset_support(dev) == -ENOTSUP))
526 DRV_LOG(INFO, "Use fall-back DV counter management. Flow "
527 "counter dump:%d, bulk_alloc_bitmap:0x%hhx.",
528 hca_attr->flow_counters_dump,
529 hca_attr->flow_counter_bulk_alloc_bitmap);
530 /* Initialize fallback mode only on the port initializes sh. */
532 sh->cmng.counter_fallback = fallback;
533 else if (fallback != sh->cmng.counter_fallback)
534 DRV_LOG(WARNING, "Port %d in sh has different fallback mode "
535 "with others:%d.", PORT_ID(priv), fallback);
540 * Initialize the counters management structure.
543 * Pointer to mlx5_dev_ctx_shared object to free
546 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
550 memset(&sh->cmng, 0, sizeof(sh->cmng));
551 TAILQ_INIT(&sh->cmng.flow_counters);
552 sh->cmng.min_id = MLX5_CNT_BATCH_OFFSET;
553 sh->cmng.max_id = -1;
554 sh->cmng.last_pool_idx = POOL_IDX_INVALID;
555 rte_spinlock_init(&sh->cmng.pool_update_sl);
556 for (i = 0; i < MLX5_COUNTER_TYPE_MAX; i++) {
557 TAILQ_INIT(&sh->cmng.counters[i]);
558 rte_spinlock_init(&sh->cmng.csl[i]);
563 * Destroy all the resources allocated for a counter memory management.
566 * Pointer to the memory management structure.
569 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
571 uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
573 LIST_REMOVE(mng, next);
574 mlx5_os_wrapped_mkey_destroy(&mng->wm);
579 * Close and release all the resources of the counters management.
582 * Pointer to mlx5_dev_ctx_shared object to free.
585 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
587 struct mlx5_counter_stats_mem_mng *mng;
593 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
594 if (rte_errno != EINPROGRESS)
599 if (sh->cmng.pools) {
600 struct mlx5_flow_counter_pool *pool;
601 uint16_t n_valid = sh->cmng.n_valid;
602 bool fallback = sh->cmng.counter_fallback;
604 for (i = 0; i < n_valid; ++i) {
605 pool = sh->cmng.pools[i];
606 if (!fallback && pool->min_dcs)
607 claim_zero(mlx5_devx_cmd_destroy
609 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
610 struct mlx5_flow_counter *cnt =
611 MLX5_POOL_GET_CNT(pool, j);
615 (mlx5_flow_os_destroy_flow_action
617 if (fallback && MLX5_POOL_GET_CNT
618 (pool, j)->dcs_when_free)
619 claim_zero(mlx5_devx_cmd_destroy
620 (cnt->dcs_when_free));
624 mlx5_free(sh->cmng.pools);
626 mng = LIST_FIRST(&sh->cmng.mem_mngs);
628 mlx5_flow_destroy_counter_stat_mem_mng(mng);
629 mng = LIST_FIRST(&sh->cmng.mem_mngs);
631 memset(&sh->cmng, 0, sizeof(sh->cmng));
635 * Initialize the aso flow meters management structure.
638 * Pointer to mlx5_dev_ctx_shared object to free
641 mlx5_aso_flow_mtrs_mng_init(struct mlx5_dev_ctx_shared *sh)
644 sh->mtrmng = mlx5_malloc(MLX5_MEM_ZERO,
646 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
649 "meter management allocation was failed.");
653 if (sh->meter_aso_en) {
654 rte_spinlock_init(&sh->mtrmng->pools_mng.mtrsl);
655 rte_rwlock_init(&sh->mtrmng->pools_mng.resize_mtrwl);
656 LIST_INIT(&sh->mtrmng->pools_mng.meters);
658 sh->mtrmng->def_policy_id = MLX5_INVALID_POLICY_ID;
664 * Close and release all the resources of
665 * the ASO flow meter management structure.
668 * Pointer to mlx5_dev_ctx_shared object to free.
671 mlx5_aso_flow_mtrs_mng_close(struct mlx5_dev_ctx_shared *sh)
673 struct mlx5_aso_mtr_pool *mtr_pool;
674 struct mlx5_flow_mtr_mng *mtrmng = sh->mtrmng;
676 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
677 struct mlx5_aso_mtr *aso_mtr;
679 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
681 if (sh->meter_aso_en) {
682 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_POLICER);
683 idx = mtrmng->pools_mng.n_valid;
685 mtr_pool = mtrmng->pools_mng.pools[idx];
686 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
687 for (i = 0; i < MLX5_ASO_MTRS_PER_POOL; i++) {
688 aso_mtr = &mtr_pool->mtrs[i];
689 if (aso_mtr->fm.meter_action_g)
691 (mlx5_glue->destroy_flow_action
692 (aso_mtr->fm.meter_action_g));
693 if (aso_mtr->fm.meter_action_y)
695 (mlx5_glue->destroy_flow_action
696 (aso_mtr->fm.meter_action_y));
698 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
699 claim_zero(mlx5_devx_cmd_destroy
700 (mtr_pool->devx_obj));
701 mtrmng->pools_mng.n_valid--;
704 mlx5_free(sh->mtrmng->pools_mng.pools);
706 mlx5_free(sh->mtrmng);
710 /* Send FLOW_AGED event if needed. */
712 mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh)
714 struct mlx5_age_info *age_info;
717 for (i = 0; i < sh->max_port; i++) {
718 age_info = &sh->port[i].age_info;
719 if (!MLX5_AGE_GET(age_info, MLX5_AGE_EVENT_NEW))
721 MLX5_AGE_UNSET(age_info, MLX5_AGE_EVENT_NEW);
722 if (MLX5_AGE_GET(age_info, MLX5_AGE_TRIGGER)) {
723 MLX5_AGE_UNSET(age_info, MLX5_AGE_TRIGGER);
724 rte_eth_dev_callback_process
725 (&rte_eth_devices[sh->port[i].devx_ih_port_id],
726 RTE_ETH_EVENT_FLOW_AGED, NULL);
732 * Initialize the ASO connection tracking structure.
735 * Pointer to mlx5_dev_ctx_shared object.
738 * 0 on success, a negative errno value otherwise and rte_errno is set.
741 mlx5_flow_aso_ct_mng_init(struct mlx5_dev_ctx_shared *sh)
747 sh->ct_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->ct_mng),
748 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
750 DRV_LOG(ERR, "ASO CT management allocation failed.");
754 err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_CONNECTION_TRACKING);
756 mlx5_free(sh->ct_mng);
757 /* rte_errno should be extracted from the failure. */
761 rte_spinlock_init(&sh->ct_mng->ct_sl);
762 rte_rwlock_init(&sh->ct_mng->resize_rwl);
763 LIST_INIT(&sh->ct_mng->free_cts);
768 * Close and release all the resources of the
769 * ASO connection tracking management structure.
772 * Pointer to mlx5_dev_ctx_shared object to free.
775 mlx5_flow_aso_ct_mng_close(struct mlx5_dev_ctx_shared *sh)
777 struct mlx5_aso_ct_pools_mng *mng = sh->ct_mng;
778 struct mlx5_aso_ct_pool *ct_pool;
779 struct mlx5_aso_ct_action *ct;
785 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_CONNECTION_TRACKING);
789 ct_pool = mng->pools[idx];
790 for (i = 0; i < MLX5_ASO_CT_ACTIONS_PER_POOL; i++) {
791 ct = &ct_pool->actions[i];
792 val = __atomic_fetch_sub(&ct->refcnt, 1,
794 MLX5_ASSERT(val == 1);
797 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
798 if (ct->dr_action_orig)
799 claim_zero(mlx5_glue->destroy_flow_action
800 (ct->dr_action_orig));
801 if (ct->dr_action_rply)
802 claim_zero(mlx5_glue->destroy_flow_action
803 (ct->dr_action_rply));
806 claim_zero(mlx5_devx_cmd_destroy(ct_pool->devx_obj));
808 DRV_LOG(DEBUG, "%u ASO CT objects are being used in the pool %u",
812 /* in case of failure. */
815 mlx5_free(mng->pools);
817 /* Management structure must be cleared to 0s during allocation. */
822 * Initialize the flow resources' indexed mempool.
825 * Pointer to mlx5_dev_ctx_shared object.
828 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh)
831 struct mlx5_indexed_pool_config cfg;
833 for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
834 cfg = mlx5_ipool_cfg[i];
839 * Set MLX5_IPOOL_MLX5_FLOW ipool size
840 * according to PCI function flow configuration.
842 case MLX5_IPOOL_MLX5_FLOW:
843 cfg.size = sh->config.dv_flow_en ?
844 sizeof(struct mlx5_flow_handle) :
845 MLX5_FLOW_HANDLE_VERBS_SIZE;
848 if (sh->config.reclaim_mode) {
849 cfg.release_mem_en = 1;
850 cfg.per_core_cache = 0;
852 cfg.release_mem_en = 0;
854 sh->ipool[i] = mlx5_ipool_create(&cfg);
860 * Release the flow resources' indexed mempool.
863 * Pointer to mlx5_dev_ctx_shared object.
866 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
870 for (i = 0; i < MLX5_IPOOL_MAX; ++i)
871 mlx5_ipool_destroy(sh->ipool[i]);
872 for (i = 0; i < MLX5_MAX_MODIFY_NUM; ++i)
873 if (sh->mdh_ipools[i])
874 mlx5_ipool_destroy(sh->mdh_ipools[i]);
878 * Check if dynamic flex parser for eCPRI already exists.
881 * Pointer to Ethernet device structure.
884 * true on exists, false on not.
887 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
889 struct mlx5_priv *priv = dev->data->dev_private;
890 struct mlx5_ecpri_parser_profile *prf = &priv->sh->ecpri_parser;
896 * Allocation of a flex parser for eCPRI. Once created, this parser related
897 * resources will be held until the device is closed.
900 * Pointer to Ethernet device structure.
903 * 0 on success, a negative errno value otherwise and rte_errno is set.
906 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
908 struct mlx5_priv *priv = dev->data->dev_private;
909 struct mlx5_ecpri_parser_profile *prf = &priv->sh->ecpri_parser;
910 struct mlx5_devx_graph_node_attr node = {
911 .modify_field_select = 0,
916 if (!priv->sh->cdev->config.hca_attr.parse_graph_flex_node) {
917 DRV_LOG(ERR, "Dynamic flex parser is not supported "
918 "for device %s.", priv->dev_data->name);
921 node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED;
922 /* 8 bytes now: 4B common header + 4B message body header. */
923 node.header_length_base_value = 0x8;
924 /* After MAC layer: Ether / VLAN. */
925 node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC;
926 /* Type of compared condition should be 0xAEFE in the L2 layer. */
927 node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI;
928 /* Sample #0: type in common header. */
929 node.sample[0].flow_match_sample_en = 1;
931 node.sample[0].flow_match_sample_offset_mode = 0x0;
932 /* Only the 2nd byte will be used. */
933 node.sample[0].flow_match_sample_field_base_offset = 0x0;
934 /* Sample #1: message payload. */
935 node.sample[1].flow_match_sample_en = 1;
937 node.sample[1].flow_match_sample_offset_mode = 0x0;
939 * Only the first two bytes will be used right now, and its offset will
940 * start after the common header that with the length of a DW(u32).
942 node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);
943 prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->cdev->ctx, &node);
945 DRV_LOG(ERR, "Failed to create flex parser node object.");
946 return (rte_errno == 0) ? -ENODEV : -rte_errno;
949 ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num);
951 DRV_LOG(ERR, "Failed to query sample IDs.");
952 return (rte_errno == 0) ? -ENODEV : -rte_errno;
954 prf->offset[0] = 0x0;
955 prf->offset[1] = sizeof(uint32_t);
956 prf->ids[0] = ids[0];
957 prf->ids[1] = ids[1];
962 * Destroy the flex parser node, including the parser itself, input / output
963 * arcs and DW samples. Resources could be reused then.
966 * Pointer to Ethernet device structure.
969 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
971 struct mlx5_priv *priv = dev->data->dev_private;
972 struct mlx5_ecpri_parser_profile *prf = &priv->sh->ecpri_parser;
975 mlx5_devx_cmd_destroy(prf->obj);
980 mlx5_get_supported_sw_parsing_offloads(const struct mlx5_hca_attr *attr)
982 uint32_t sw_parsing_offloads = 0;
985 sw_parsing_offloads |= MLX5_SW_PARSING_CAP;
987 sw_parsing_offloads |= MLX5_SW_PARSING_CSUM_CAP;
990 sw_parsing_offloads |= MLX5_SW_PARSING_TSO_CAP;
992 return sw_parsing_offloads;
996 mlx5_get_supported_tunneling_offloads(const struct mlx5_hca_attr *attr)
998 uint32_t tn_offloads = 0;
1000 if (attr->tunnel_stateless_vxlan)
1001 tn_offloads |= MLX5_TUNNELED_OFFLOADS_VXLAN_CAP;
1002 if (attr->tunnel_stateless_gre)
1003 tn_offloads |= MLX5_TUNNELED_OFFLOADS_GRE_CAP;
1004 if (attr->tunnel_stateless_geneve_rx)
1005 tn_offloads |= MLX5_TUNNELED_OFFLOADS_GENEVE_CAP;
1009 /* Fill all fields of UAR structure. */
1011 mlx5_rxtx_uars_prepare(struct mlx5_dev_ctx_shared *sh)
1015 ret = mlx5_devx_uar_prepare(sh->cdev, &sh->tx_uar);
1017 DRV_LOG(ERR, "Failed to prepare Tx DevX UAR.");
1020 MLX5_ASSERT(sh->tx_uar.obj);
1021 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->tx_uar.obj));
1022 ret = mlx5_devx_uar_prepare(sh->cdev, &sh->rx_uar);
1024 DRV_LOG(ERR, "Failed to prepare Rx DevX UAR.");
1025 mlx5_devx_uar_release(&sh->tx_uar);
1028 MLX5_ASSERT(sh->rx_uar.obj);
1029 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->rx_uar.obj));
1034 mlx5_rxtx_uars_release(struct mlx5_dev_ctx_shared *sh)
1036 mlx5_devx_uar_release(&sh->rx_uar);
1037 mlx5_devx_uar_release(&sh->tx_uar);
1041 * rte_mempool_walk() callback to unregister Rx mempools.
1042 * It used when implicit mempool registration is disabled.
1045 * The mempool being walked.
1047 * Pointer to the device shared context.
1050 mlx5_dev_ctx_shared_rx_mempool_unregister_cb(struct rte_mempool *mp, void *arg)
1052 struct mlx5_dev_ctx_shared *sh = arg;
1054 mlx5_dev_mempool_unregister(sh->cdev, mp);
1058 * Callback used when implicit mempool registration is disabled
1059 * in order to track Rx mempool destruction.
1062 * Mempool life cycle event.
1064 * An Rx mempool registered explicitly when the port is started.
1066 * Pointer to a device shared context.
1069 mlx5_dev_ctx_shared_rx_mempool_event_cb(enum rte_mempool_event event,
1070 struct rte_mempool *mp, void *arg)
1072 struct mlx5_dev_ctx_shared *sh = arg;
1074 if (event == RTE_MEMPOOL_EVENT_DESTROY)
1075 mlx5_dev_mempool_unregister(sh->cdev, mp);
1079 mlx5_dev_ctx_shared_mempool_subscribe(struct rte_eth_dev *dev)
1081 struct mlx5_priv *priv = dev->data->dev_private;
1082 struct mlx5_dev_ctx_shared *sh = priv->sh;
1085 /* Check if we only need to track Rx mempool destruction. */
1086 if (!sh->cdev->config.mr_mempool_reg_en) {
1087 ret = rte_mempool_event_callback_register
1088 (mlx5_dev_ctx_shared_rx_mempool_event_cb, sh);
1089 return ret == 0 || rte_errno == EEXIST ? 0 : ret;
1091 return mlx5_dev_mempool_subscribe(sh->cdev);
1095 * Set up multiple TISs with different affinities according to
1096 * number of bonding ports
1099 * Pointer of shared context.
1102 * Zero on success, -1 otherwise.
1105 mlx5_setup_tis(struct mlx5_dev_ctx_shared *sh)
1108 struct mlx5_devx_lag_context lag_ctx = { 0 };
1109 struct mlx5_devx_tis_attr tis_attr = { 0 };
1111 tis_attr.transport_domain = sh->td->id;
1112 if (sh->bond.n_port) {
1113 if (!mlx5_devx_cmd_query_lag(sh->cdev->ctx, &lag_ctx)) {
1114 sh->lag.tx_remap_affinity[0] =
1115 lag_ctx.tx_remap_affinity_1;
1116 sh->lag.tx_remap_affinity[1] =
1117 lag_ctx.tx_remap_affinity_2;
1118 sh->lag.affinity_mode = lag_ctx.port_select_mode;
1120 DRV_LOG(ERR, "Failed to query lag affinity.");
1123 if (sh->lag.affinity_mode == MLX5_LAG_MODE_TIS) {
1124 for (i = 0; i < sh->bond.n_port; i++) {
1125 tis_attr.lag_tx_port_affinity =
1126 MLX5_IFC_LAG_MAP_TIS_AFFINITY(i,
1128 sh->tis[i] = mlx5_devx_cmd_create_tis(sh->cdev->ctx,
1131 DRV_LOG(ERR, "Failed to TIS %d/%d for bonding device"
1132 " %s.", i, sh->bond.n_port,
1137 DRV_LOG(DEBUG, "LAG number of ports : %d, affinity_1 & 2 : pf%d & %d.\n",
1138 sh->bond.n_port, lag_ctx.tx_remap_affinity_1,
1139 lag_ctx.tx_remap_affinity_2);
1142 if (sh->lag.affinity_mode == MLX5_LAG_MODE_HASH)
1143 DRV_LOG(INFO, "Device %s enabled HW hash based LAG.",
1146 tis_attr.lag_tx_port_affinity = 0;
1147 sh->tis[0] = mlx5_devx_cmd_create_tis(sh->cdev->ctx, &tis_attr);
1149 DRV_LOG(ERR, "Failed to TIS 0 for bonding device"
1150 " %s.", sh->ibdev_name);
1157 * Verify and store value for share device argument.
1160 * Key argument to verify.
1162 * Value associated with key.
1167 * 0 on success, a negative errno value otherwise and rte_errno is set.
1170 mlx5_dev_args_check_handler(const char *key, const char *val, void *opaque)
1172 struct mlx5_sh_config *config = opaque;
1176 tmp = strtol(val, NULL, 0);
1179 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1182 if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
1183 /* Negative values are acceptable for some keys only. */
1185 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
1188 if (strcmp(MLX5_TX_PP, key) == 0) {
1189 unsigned long mod = tmp >= 0 ? tmp : -tmp;
1192 DRV_LOG(ERR, "Zero Tx packet pacing parameter.");
1196 config->tx_pp = tmp;
1197 } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
1198 config->tx_skew = tmp;
1199 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1200 config->l3_vxlan_en = !!tmp;
1201 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1202 config->vf_nl_en = !!tmp;
1203 } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1204 config->dv_esw_en = !!tmp;
1205 } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1207 DRV_LOG(ERR, "Invalid %s parameter.", key);
1211 config->dv_flow_en = tmp;
1212 } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1213 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1214 tmp != MLX5_XMETA_MODE_META16 &&
1215 tmp != MLX5_XMETA_MODE_META32 &&
1216 tmp != MLX5_XMETA_MODE_MISS_INFO) {
1217 DRV_LOG(ERR, "Invalid extensive metadata parameter.");
1221 if (tmp != MLX5_XMETA_MODE_MISS_INFO)
1222 config->dv_xmeta_en = tmp;
1224 config->dv_miss_info = 1;
1225 } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
1226 config->lacp_by_user = !!tmp;
1227 } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1228 if (tmp != MLX5_RCM_NONE &&
1229 tmp != MLX5_RCM_LIGHT &&
1230 tmp != MLX5_RCM_AGGR) {
1231 DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1235 config->reclaim_mode = tmp;
1236 } else if (strcmp(MLX5_DECAP_EN, key) == 0) {
1237 config->decap_en = !!tmp;
1238 } else if (strcmp(MLX5_ALLOW_DUPLICATE_PATTERN, key) == 0) {
1239 config->allow_duplicate_pattern = !!tmp;
1245 * Parse user device parameters and adjust them according to device
1249 * Pointer to shared device context.
1251 * Pointer to mlx5 kvargs control, can be NULL if there is no devargs.
1253 * Pointer to shared device configuration structure.
1256 * 0 on success, a negative errno value otherwise and rte_errno is set.
1259 mlx5_shared_dev_ctx_args_config(struct mlx5_dev_ctx_shared *sh,
1260 struct mlx5_kvargs_ctrl *mkvlist,
1261 struct mlx5_sh_config *config)
1263 const char **params = (const char *[]){
1274 MLX5_ALLOW_DUPLICATE_PATTERN,
1279 /* Default configuration. */
1280 memset(config, 0, sizeof(*config));
1281 config->vf_nl_en = 1;
1282 config->dv_esw_en = 1;
1283 config->dv_flow_en = 1;
1284 config->decap_en = 1;
1285 config->allow_duplicate_pattern = 1;
1286 if (mkvlist != NULL) {
1287 /* Process parameters. */
1288 ret = mlx5_kvargs_process(mkvlist, params,
1289 mlx5_dev_args_check_handler, config);
1291 DRV_LOG(ERR, "Failed to process device arguments: %s",
1292 strerror(rte_errno));
1296 /* Adjust parameters according to device capabilities. */
1297 if (config->dv_flow_en && !sh->dev_cap.dv_flow_en) {
1298 DRV_LOG(WARNING, "DV flow is not supported.");
1299 config->dv_flow_en = 0;
1301 if (config->dv_esw_en && !sh->dev_cap.dv_esw_en) {
1302 DRV_LOG(DEBUG, "E-Switch DV flow is not supported.");
1303 config->dv_esw_en = 0;
1305 if (config->dv_esw_en && !config->dv_flow_en) {
1307 "E-Switch DV flow is supported only when DV flow is enabled.");
1308 config->dv_esw_en = 0;
1310 if (config->dv_miss_info && config->dv_esw_en)
1311 config->dv_xmeta_en = MLX5_XMETA_MODE_META16;
1312 if (!config->dv_esw_en &&
1313 config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1315 "Metadata mode %u is not supported (no E-Switch).",
1316 config->dv_xmeta_en);
1317 config->dv_xmeta_en = MLX5_XMETA_MODE_LEGACY;
1319 if (config->tx_pp && !sh->dev_cap.txpp_en) {
1320 DRV_LOG(ERR, "Packet pacing is not supported.");
1324 if (!config->tx_pp && config->tx_skew) {
1326 "\"tx_skew\" doesn't affect without \"tx_pp\".");
1329 * If HW has bug working with tunnel packet decapsulation and scatter
1330 * FCS, and decapsulation is needed, clear the hw_fcs_strip bit.
1331 * Then RTE_ETH_RX_OFFLOAD_KEEP_CRC bit will not be set anymore.
1333 if (sh->dev_cap.scatter_fcs_w_decap_disable && sh->config.decap_en)
1334 config->hw_fcs_strip = 0;
1336 config->hw_fcs_strip = sh->dev_cap.hw_fcs_strip;
1337 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported",
1338 (config->hw_fcs_strip ? "" : "not "));
1339 DRV_LOG(DEBUG, "\"tx_pp\" is %d.", config->tx_pp);
1340 DRV_LOG(DEBUG, "\"tx_skew\" is %d.", config->tx_skew);
1341 DRV_LOG(DEBUG, "\"reclaim_mode\" is %u.", config->reclaim_mode);
1342 DRV_LOG(DEBUG, "\"dv_esw_en\" is %u.", config->dv_esw_en);
1343 DRV_LOG(DEBUG, "\"dv_flow_en\" is %u.", config->dv_flow_en);
1344 DRV_LOG(DEBUG, "\"dv_xmeta_en\" is %u.", config->dv_xmeta_en);
1345 DRV_LOG(DEBUG, "\"dv_miss_info\" is %u.", config->dv_miss_info);
1346 DRV_LOG(DEBUG, "\"l3_vxlan_en\" is %u.", config->l3_vxlan_en);
1347 DRV_LOG(DEBUG, "\"vf_nl_en\" is %u.", config->vf_nl_en);
1348 DRV_LOG(DEBUG, "\"lacp_by_user\" is %u.", config->lacp_by_user);
1349 DRV_LOG(DEBUG, "\"decap_en\" is %u.", config->decap_en);
1350 DRV_LOG(DEBUG, "\"allow_duplicate_pattern\" is %u.",
1351 config->allow_duplicate_pattern);
1356 * Configure realtime timestamp format.
1359 * Pointer to mlx5_dev_ctx_shared object.
1361 * Pointer to DevX HCA capabilities structure.
1364 mlx5_rt_timestamp_config(struct mlx5_dev_ctx_shared *sh,
1365 struct mlx5_hca_attr *hca_attr)
1367 uint32_t dw_cnt = MLX5_ST_SZ_DW(register_mtutc);
1368 uint32_t reg[dw_cnt];
1371 if (hca_attr->access_register_user)
1372 ret = mlx5_devx_cmd_register_read(sh->cdev->ctx,
1373 MLX5_REGISTER_ID_MTUTC, 0,
1378 /* MTUTC register is read successfully. */
1379 ts_mode = MLX5_GET(register_mtutc, reg, time_stamp_mode);
1380 if (ts_mode == MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME)
1381 sh->dev_cap.rt_timestamp = 1;
1383 /* Kernel does not support register reading. */
1384 if (hca_attr->dev_freq_khz == (NS_PER_S / MS_PER_S))
1385 sh->dev_cap.rt_timestamp = 1;
1390 * Allocate shared device context. If there is multiport device the
1391 * master and representors will share this context, if there is single
1392 * port dedicated device, the context will be used by only given
1393 * port due to unification.
1395 * Routine first searches the context for the specified device name,
1396 * if found the shared context assumed and reference counter is incremented.
1397 * If no context found the new one is created and initialized with specified
1398 * device context and parameters.
1401 * Pointer to the device attributes (name, port, etc).
1403 * Pointer to mlx5 kvargs control, can be NULL if there is no devargs.
1406 * Pointer to mlx5_dev_ctx_shared object on success,
1407 * otherwise NULL and rte_errno is set.
1409 struct mlx5_dev_ctx_shared *
1410 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
1411 struct mlx5_kvargs_ctrl *mkvlist)
1413 struct mlx5_dev_ctx_shared *sh;
1418 /* Secondary process should not create the shared context. */
1419 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1420 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1421 /* Search for IB context by device name. */
1422 LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
1423 if (!strcmp(sh->ibdev_name, spawn->phys_dev_name)) {
1428 /* No device found, we have to create new shared context. */
1429 MLX5_ASSERT(spawn->max_port);
1430 sh = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
1431 sizeof(struct mlx5_dev_ctx_shared) +
1432 spawn->max_port * sizeof(struct mlx5_dev_shared_port),
1433 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
1435 DRV_LOG(ERR, "Shared context allocation failure.");
1439 pthread_mutex_init(&sh->txpp.mutex, NULL);
1440 sh->numa_node = spawn->cdev->dev->numa_node;
1441 sh->cdev = spawn->cdev;
1442 sh->esw_mode = !!(spawn->info.master || spawn->info.representor);
1443 if (spawn->bond_info)
1444 sh->bond = *spawn->bond_info;
1445 err = mlx5_os_capabilities_prepare(sh);
1447 DRV_LOG(ERR, "Fail to configure device capabilities.");
1450 err = mlx5_shared_dev_ctx_args_config(sh, mkvlist, &sh->config);
1452 DRV_LOG(ERR, "Failed to process device configure: %s",
1453 strerror(rte_errno));
1457 sh->max_port = spawn->max_port;
1458 strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->cdev->ctx),
1459 sizeof(sh->ibdev_name) - 1);
1460 strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->cdev->ctx),
1461 sizeof(sh->ibdev_path) - 1);
1463 * Setting port_id to max unallowed value means there is no interrupt
1464 * subhandler installed for the given port index i.
1466 for (i = 0; i < sh->max_port; i++) {
1467 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
1468 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
1469 sh->port[i].nl_ih_port_id = RTE_MAX_ETHPORTS;
1471 if (sh->cdev->config.devx) {
1472 sh->td = mlx5_devx_cmd_create_td(sh->cdev->ctx);
1474 DRV_LOG(ERR, "TD allocation failure");
1478 if (mlx5_setup_tis(sh)) {
1479 DRV_LOG(ERR, "TIS allocation failure");
1483 err = mlx5_rxtx_uars_prepare(sh);
1488 /* Initialize UAR access locks for 32bit implementations. */
1489 rte_spinlock_init(&sh->uar_lock_cq);
1490 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
1491 rte_spinlock_init(&sh->uar_lock[i]);
1494 mlx5_os_dev_shared_handler_install(sh);
1495 if (LIST_EMPTY(&mlx5_dev_ctx_list)) {
1496 err = mlx5_flow_os_init_workspace_once();
1500 mlx5_flow_aging_init(sh);
1501 mlx5_flow_counters_mng_init(sh);
1502 mlx5_flow_ipool_create(sh);
1503 /* Add context to the global device list. */
1504 LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
1505 rte_spinlock_init(&sh->geneve_tlv_opt_sl);
1507 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1511 pthread_mutex_destroy(&sh->txpp.mutex);
1512 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1514 mlx5_rxtx_uars_release(sh);
1518 claim_zero(mlx5_devx_cmd_destroy(sh->tis[i]));
1519 } while (++i < (uint32_t)sh->bond.n_port);
1521 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1528 * Free shared IB device context. Decrement counter and if zero free
1529 * all allocated resources and close handles.
1532 * Pointer to mlx5_dev_ctx_shared object to free
1535 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
1540 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1541 #ifdef RTE_LIBRTE_MLX5_DEBUG
1542 /* Check the object presence in the list. */
1543 struct mlx5_dev_ctx_shared *lctx;
1545 LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
1550 DRV_LOG(ERR, "Freeing non-existing shared IB context");
1555 MLX5_ASSERT(sh->refcnt);
1556 /* Secondary process should not free the shared context. */
1557 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1560 /* Stop watching for mempool events and unregister all mempools. */
1561 if (!sh->cdev->config.mr_mempool_reg_en) {
1562 ret = rte_mempool_event_callback_unregister
1563 (mlx5_dev_ctx_shared_rx_mempool_event_cb, sh);
1566 (mlx5_dev_ctx_shared_rx_mempool_unregister_cb, sh);
1568 /* Remove context from the global device list. */
1569 LIST_REMOVE(sh, next);
1570 /* Release resources on the last device removal. */
1571 if (LIST_EMPTY(&mlx5_dev_ctx_list)) {
1572 mlx5_os_net_cleanup();
1573 mlx5_flow_os_release_workspace();
1575 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1576 if (sh->flex_parsers_dv) {
1577 mlx5_list_destroy(sh->flex_parsers_dv);
1578 sh->flex_parsers_dv = NULL;
1581 * Ensure there is no async event handler installed.
1582 * Only primary process handles async device events.
1584 mlx5_flow_counters_mng_close(sh);
1586 mlx5_flow_aso_ct_mng_close(sh);
1587 if (sh->aso_age_mng) {
1588 mlx5_flow_aso_age_mng_close(sh);
1589 sh->aso_age_mng = NULL;
1592 mlx5_aso_flow_mtrs_mng_close(sh);
1593 mlx5_flow_ipool_destroy(sh);
1594 mlx5_os_dev_shared_handler_uninstall(sh);
1595 mlx5_rxtx_uars_release(sh);
1598 claim_zero(mlx5_devx_cmd_destroy(sh->tis[i]));
1599 } while (++i < sh->bond.n_port);
1601 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1602 MLX5_ASSERT(sh->geneve_tlv_option_resource == NULL);
1603 pthread_mutex_destroy(&sh->txpp.mutex);
1607 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1611 * Destroy table hash list.
1614 * Pointer to the private device data structure.
1617 mlx5_free_table_hash_list(struct mlx5_priv *priv)
1619 struct mlx5_dev_ctx_shared *sh = priv->sh;
1620 struct mlx5_hlist **tbls = (priv->sh->config.dv_flow_en == 2) ?
1621 &sh->groups : &sh->flow_tbls;
1624 mlx5_hlist_destroy(*tbls);
1628 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
1630 * Allocate HW steering group hash list.
1633 * Pointer to the private device data structure.
1636 mlx5_alloc_hw_group_hash_list(struct mlx5_priv *priv)
1639 struct mlx5_dev_ctx_shared *sh = priv->sh;
1640 char s[MLX5_NAME_SIZE];
1643 snprintf(s, sizeof(s), "%s_flow_groups", priv->sh->ibdev_name);
1644 sh->groups = mlx5_hlist_create
1645 (s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE,
1647 flow_hw_grp_create_cb,
1648 flow_hw_grp_match_cb,
1649 flow_hw_grp_remove_cb,
1650 flow_hw_grp_clone_cb,
1651 flow_hw_grp_clone_free_cb);
1653 DRV_LOG(ERR, "flow groups with hash creation failed.");
1662 * Initialize flow table hash list and create the root tables entry
1666 * Pointer to the private device data structure.
1669 * Zero on success, positive error code otherwise.
1672 mlx5_alloc_table_hash_list(struct mlx5_priv *priv __rte_unused)
1676 /* Tables are only used in DV and DR modes. */
1677 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
1678 struct mlx5_dev_ctx_shared *sh = priv->sh;
1679 char s[MLX5_NAME_SIZE];
1681 if (priv->sh->config.dv_flow_en == 2)
1682 return mlx5_alloc_hw_group_hash_list(priv);
1684 snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1685 sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE,
1687 flow_dv_tbl_create_cb,
1688 flow_dv_tbl_match_cb,
1689 flow_dv_tbl_remove_cb,
1690 flow_dv_tbl_clone_cb,
1691 flow_dv_tbl_clone_free_cb);
1692 if (!sh->flow_tbls) {
1693 DRV_LOG(ERR, "flow tables with hash creation failed.");
1697 #ifndef HAVE_MLX5DV_DR
1698 struct rte_flow_error error;
1699 struct rte_eth_dev *dev = &rte_eth_devices[priv->dev_data->port_id];
1702 * In case we have not DR support, the zero tables should be created
1703 * because DV expect to see them even if they cannot be created by
1706 if (!flow_dv_tbl_resource_get(dev, 0, 0, 0, 0,
1707 NULL, 0, 1, 0, &error) ||
1708 !flow_dv_tbl_resource_get(dev, 0, 1, 0, 0,
1709 NULL, 0, 1, 0, &error) ||
1710 !flow_dv_tbl_resource_get(dev, 0, 0, 1, 0,
1711 NULL, 0, 1, 0, &error)) {
1717 mlx5_free_table_hash_list(priv);
1718 #endif /* HAVE_MLX5DV_DR */
1724 * Retrieve integer value from environment variable.
1727 * Environment variable name.
1730 * Integer value, 0 if the variable is not set.
1733 mlx5_getenv_int(const char *name)
1735 const char *val = getenv(name);
1743 * DPDK callback to add udp tunnel port
1746 * A pointer to eth_dev
1747 * @param[in] udp_tunnel
1748 * A pointer to udp tunnel
1751 * 0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1754 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1755 struct rte_eth_udp_tunnel *udp_tunnel)
1757 MLX5_ASSERT(udp_tunnel != NULL);
1758 if (udp_tunnel->prot_type == RTE_ETH_TUNNEL_TYPE_VXLAN &&
1759 udp_tunnel->udp_port == 4789)
1761 if (udp_tunnel->prot_type == RTE_ETH_TUNNEL_TYPE_VXLAN_GPE &&
1762 udp_tunnel->udp_port == 4790)
1768 * Initialize process private data structure.
1771 * Pointer to Ethernet device structure.
1774 * 0 on success, a negative errno value otherwise and rte_errno is set.
1777 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1779 struct mlx5_priv *priv = dev->data->dev_private;
1780 struct mlx5_proc_priv *ppriv;
1783 mlx5_proc_priv_uninit(dev);
1785 * UAR register table follows the process private structure. BlueFlame
1786 * registers for Tx queues are stored in the table.
1788 ppriv_size = sizeof(struct mlx5_proc_priv) +
1789 priv->txqs_n * sizeof(struct mlx5_uar_data);
1790 ppriv = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, ppriv_size,
1791 RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1796 ppriv->uar_table_sz = priv->txqs_n;
1797 dev->process_private = ppriv;
1798 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
1799 priv->sh->pppriv = ppriv;
1804 * Un-initialize process private data structure.
1807 * Pointer to Ethernet device structure.
1810 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1812 if (!dev->process_private)
1814 mlx5_free(dev->process_private);
1815 dev->process_private = NULL;
1819 * DPDK callback to close the device.
1821 * Destroy all queues and objects, free memory.
1824 * Pointer to Ethernet device structure.
1827 mlx5_dev_close(struct rte_eth_dev *dev)
1829 struct mlx5_priv *priv = dev->data->dev_private;
1833 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1834 /* Check if process_private released. */
1835 if (!dev->process_private)
1837 mlx5_tx_uar_uninit_secondary(dev);
1838 mlx5_proc_priv_uninit(dev);
1839 rte_eth_dev_release_port(dev);
1844 DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1846 ((priv->sh->cdev->ctx != NULL) ?
1847 mlx5_os_get_ctx_device_name(priv->sh->cdev->ctx) : ""));
1849 * If default mreg copy action is removed at the stop stage,
1850 * the search will return none and nothing will be done anymore.
1852 mlx5_flow_stop_default(dev);
1853 mlx5_traffic_disable(dev);
1855 * If all the flows are already flushed in the device stop stage,
1856 * then this will return directly without any action.
1858 mlx5_flow_list_flush(dev, MLX5_FLOW_TYPE_GEN, true);
1859 mlx5_action_handle_flush(dev);
1860 mlx5_flow_meter_flush(dev, NULL);
1861 /* Prevent crashes when queues are still in use. */
1862 dev->rx_pkt_burst = rte_eth_pkt_burst_dummy;
1863 dev->tx_pkt_burst = rte_eth_pkt_burst_dummy;
1865 /* Disable datapath on secondary process. */
1866 mlx5_mp_os_req_stop_rxtx(dev);
1867 /* Free the eCPRI flex parser resource. */
1868 mlx5_flex_parser_ecpri_release(dev);
1869 mlx5_flex_item_port_cleanup(dev);
1870 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
1871 flow_hw_resource_release(dev);
1873 if (priv->rxq_privs != NULL) {
1874 /* XXX race condition if mlx5_rx_burst() is still running. */
1875 rte_delay_us_sleep(1000);
1876 for (i = 0; (i != priv->rxqs_n); ++i)
1877 mlx5_rxq_release(dev, i);
1879 mlx5_free(priv->rxq_privs);
1880 priv->rxq_privs = NULL;
1882 if (priv->txqs != NULL) {
1883 /* XXX race condition if mlx5_tx_burst() is still running. */
1884 rte_delay_us_sleep(1000);
1885 for (i = 0; (i != priv->txqs_n); ++i)
1886 mlx5_txq_release(dev, i);
1890 mlx5_proc_priv_uninit(dev);
1891 if (priv->q_counters) {
1892 mlx5_devx_cmd_destroy(priv->q_counters);
1893 priv->q_counters = NULL;
1895 if (priv->drop_queue.hrxq)
1896 mlx5_drop_action_destroy(dev);
1897 if (priv->mreg_cp_tbl)
1898 mlx5_hlist_destroy(priv->mreg_cp_tbl);
1899 mlx5_mprq_free_mp(dev);
1900 mlx5_os_free_shared_dr(priv);
1901 if (priv->rss_conf.rss_key != NULL)
1902 mlx5_free(priv->rss_conf.rss_key);
1903 if (priv->reta_idx != NULL)
1904 mlx5_free(priv->reta_idx);
1905 if (priv->sh->dev_cap.vf)
1906 mlx5_os_mac_addr_flush(dev);
1907 if (priv->nl_socket_route >= 0)
1908 close(priv->nl_socket_route);
1909 if (priv->nl_socket_rdma >= 0)
1910 close(priv->nl_socket_rdma);
1911 if (priv->vmwa_context)
1912 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1913 ret = mlx5_hrxq_verify(dev);
1915 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1916 dev->data->port_id);
1917 ret = mlx5_ind_table_obj_verify(dev);
1919 DRV_LOG(WARNING, "port %u some indirection table still remain",
1920 dev->data->port_id);
1921 ret = mlx5_rxq_obj_verify(dev);
1923 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1924 dev->data->port_id);
1925 ret = mlx5_ext_rxq_verify(dev);
1927 DRV_LOG(WARNING, "Port %u some external RxQ still remain.",
1928 dev->data->port_id);
1929 ret = mlx5_rxq_verify(dev);
1931 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1932 dev->data->port_id);
1933 ret = mlx5_txq_obj_verify(dev);
1935 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1936 dev->data->port_id);
1937 ret = mlx5_txq_verify(dev);
1939 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1940 dev->data->port_id);
1941 ret = mlx5_flow_verify(dev);
1943 DRV_LOG(WARNING, "port %u some flows still remain",
1944 dev->data->port_id);
1946 mlx5_list_destroy(priv->hrxqs);
1947 mlx5_free(priv->ext_rxqs);
1949 * Free the shared context in last turn, because the cleanup
1950 * routines above may use some shared fields, like
1951 * mlx5_os_mac_addr_flush() uses ibdev_path for retrieving
1952 * ifindex if Netlink fails.
1954 mlx5_free_shared_dev_ctx(priv->sh);
1955 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1959 MLX5_ETH_FOREACH_DEV(port_id, dev->device) {
1960 struct mlx5_priv *opriv =
1961 rte_eth_devices[port_id].data->dev_private;
1964 opriv->domain_id != priv->domain_id ||
1965 &rte_eth_devices[port_id] == dev)
1971 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1973 memset(priv, 0, sizeof(*priv));
1974 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1976 * Reset mac_addrs to NULL such that it is not freed as part of
1977 * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1978 * it is freed when dev_private is freed.
1980 dev->data->mac_addrs = NULL;
1984 const struct eth_dev_ops mlx5_dev_ops = {
1985 .dev_configure = mlx5_dev_configure,
1986 .dev_start = mlx5_dev_start,
1987 .dev_stop = mlx5_dev_stop,
1988 .dev_set_link_down = mlx5_set_link_down,
1989 .dev_set_link_up = mlx5_set_link_up,
1990 .dev_close = mlx5_dev_close,
1991 .promiscuous_enable = mlx5_promiscuous_enable,
1992 .promiscuous_disable = mlx5_promiscuous_disable,
1993 .allmulticast_enable = mlx5_allmulticast_enable,
1994 .allmulticast_disable = mlx5_allmulticast_disable,
1995 .link_update = mlx5_link_update,
1996 .stats_get = mlx5_stats_get,
1997 .stats_reset = mlx5_stats_reset,
1998 .xstats_get = mlx5_xstats_get,
1999 .xstats_reset = mlx5_xstats_reset,
2000 .xstats_get_names = mlx5_xstats_get_names,
2001 .fw_version_get = mlx5_fw_version_get,
2002 .dev_infos_get = mlx5_dev_infos_get,
2003 .representor_info_get = mlx5_representor_info_get,
2004 .read_clock = mlx5_txpp_read_clock,
2005 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
2006 .vlan_filter_set = mlx5_vlan_filter_set,
2007 .rx_queue_setup = mlx5_rx_queue_setup,
2008 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
2009 .tx_queue_setup = mlx5_tx_queue_setup,
2010 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
2011 .rx_queue_release = mlx5_rx_queue_release,
2012 .tx_queue_release = mlx5_tx_queue_release,
2013 .rx_queue_start = mlx5_rx_queue_start,
2014 .rx_queue_stop = mlx5_rx_queue_stop,
2015 .tx_queue_start = mlx5_tx_queue_start,
2016 .tx_queue_stop = mlx5_tx_queue_stop,
2017 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
2018 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
2019 .mac_addr_remove = mlx5_mac_addr_remove,
2020 .mac_addr_add = mlx5_mac_addr_add,
2021 .mac_addr_set = mlx5_mac_addr_set,
2022 .set_mc_addr_list = mlx5_set_mc_addr_list,
2023 .mtu_set = mlx5_dev_set_mtu,
2024 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
2025 .vlan_offload_set = mlx5_vlan_offload_set,
2026 .reta_update = mlx5_dev_rss_reta_update,
2027 .reta_query = mlx5_dev_rss_reta_query,
2028 .rss_hash_update = mlx5_rss_hash_update,
2029 .rss_hash_conf_get = mlx5_rss_hash_conf_get,
2030 .flow_ops_get = mlx5_flow_ops_get,
2031 .rxq_info_get = mlx5_rxq_info_get,
2032 .txq_info_get = mlx5_txq_info_get,
2033 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
2034 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
2035 .rx_queue_intr_enable = mlx5_rx_intr_enable,
2036 .rx_queue_intr_disable = mlx5_rx_intr_disable,
2037 .is_removed = mlx5_is_removed,
2038 .udp_tunnel_port_add = mlx5_udp_tunnel_port_add,
2039 .get_module_info = mlx5_get_module_info,
2040 .get_module_eeprom = mlx5_get_module_eeprom,
2041 .hairpin_cap_get = mlx5_hairpin_cap_get,
2042 .mtr_ops_get = mlx5_flow_meter_ops_get,
2043 .hairpin_bind = mlx5_hairpin_bind,
2044 .hairpin_unbind = mlx5_hairpin_unbind,
2045 .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
2046 .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
2047 .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
2048 .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
2049 .get_monitor_addr = mlx5_get_monitor_addr,
2052 /* Available operations from secondary process. */
2053 const struct eth_dev_ops mlx5_dev_sec_ops = {
2054 .stats_get = mlx5_stats_get,
2055 .stats_reset = mlx5_stats_reset,
2056 .xstats_get = mlx5_xstats_get,
2057 .xstats_reset = mlx5_xstats_reset,
2058 .xstats_get_names = mlx5_xstats_get_names,
2059 .fw_version_get = mlx5_fw_version_get,
2060 .dev_infos_get = mlx5_dev_infos_get,
2061 .representor_info_get = mlx5_representor_info_get,
2062 .read_clock = mlx5_txpp_read_clock,
2063 .rx_queue_start = mlx5_rx_queue_start,
2064 .rx_queue_stop = mlx5_rx_queue_stop,
2065 .tx_queue_start = mlx5_tx_queue_start,
2066 .tx_queue_stop = mlx5_tx_queue_stop,
2067 .rxq_info_get = mlx5_rxq_info_get,
2068 .txq_info_get = mlx5_txq_info_get,
2069 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
2070 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
2071 .get_module_info = mlx5_get_module_info,
2072 .get_module_eeprom = mlx5_get_module_eeprom,
2075 /* Available operations in flow isolated mode. */
2076 const struct eth_dev_ops mlx5_dev_ops_isolate = {
2077 .dev_configure = mlx5_dev_configure,
2078 .dev_start = mlx5_dev_start,
2079 .dev_stop = mlx5_dev_stop,
2080 .dev_set_link_down = mlx5_set_link_down,
2081 .dev_set_link_up = mlx5_set_link_up,
2082 .dev_close = mlx5_dev_close,
2083 .promiscuous_enable = mlx5_promiscuous_enable,
2084 .promiscuous_disable = mlx5_promiscuous_disable,
2085 .allmulticast_enable = mlx5_allmulticast_enable,
2086 .allmulticast_disable = mlx5_allmulticast_disable,
2087 .link_update = mlx5_link_update,
2088 .stats_get = mlx5_stats_get,
2089 .stats_reset = mlx5_stats_reset,
2090 .xstats_get = mlx5_xstats_get,
2091 .xstats_reset = mlx5_xstats_reset,
2092 .xstats_get_names = mlx5_xstats_get_names,
2093 .fw_version_get = mlx5_fw_version_get,
2094 .dev_infos_get = mlx5_dev_infos_get,
2095 .representor_info_get = mlx5_representor_info_get,
2096 .read_clock = mlx5_txpp_read_clock,
2097 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
2098 .vlan_filter_set = mlx5_vlan_filter_set,
2099 .rx_queue_setup = mlx5_rx_queue_setup,
2100 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
2101 .tx_queue_setup = mlx5_tx_queue_setup,
2102 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
2103 .rx_queue_release = mlx5_rx_queue_release,
2104 .tx_queue_release = mlx5_tx_queue_release,
2105 .rx_queue_start = mlx5_rx_queue_start,
2106 .rx_queue_stop = mlx5_rx_queue_stop,
2107 .tx_queue_start = mlx5_tx_queue_start,
2108 .tx_queue_stop = mlx5_tx_queue_stop,
2109 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
2110 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
2111 .mac_addr_remove = mlx5_mac_addr_remove,
2112 .mac_addr_add = mlx5_mac_addr_add,
2113 .mac_addr_set = mlx5_mac_addr_set,
2114 .set_mc_addr_list = mlx5_set_mc_addr_list,
2115 .mtu_set = mlx5_dev_set_mtu,
2116 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
2117 .vlan_offload_set = mlx5_vlan_offload_set,
2118 .flow_ops_get = mlx5_flow_ops_get,
2119 .rxq_info_get = mlx5_rxq_info_get,
2120 .txq_info_get = mlx5_txq_info_get,
2121 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
2122 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
2123 .rx_queue_intr_enable = mlx5_rx_intr_enable,
2124 .rx_queue_intr_disable = mlx5_rx_intr_disable,
2125 .is_removed = mlx5_is_removed,
2126 .get_module_info = mlx5_get_module_info,
2127 .get_module_eeprom = mlx5_get_module_eeprom,
2128 .hairpin_cap_get = mlx5_hairpin_cap_get,
2129 .mtr_ops_get = mlx5_flow_meter_ops_get,
2130 .hairpin_bind = mlx5_hairpin_bind,
2131 .hairpin_unbind = mlx5_hairpin_unbind,
2132 .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
2133 .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
2134 .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
2135 .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
2136 .get_monitor_addr = mlx5_get_monitor_addr,
2140 * Verify and store value for device argument.
2143 * Key argument to verify.
2145 * Value associated with key.
2150 * 0 on success, a negative errno value otherwise and rte_errno is set.
2153 mlx5_port_args_check_handler(const char *key, const char *val, void *opaque)
2155 struct mlx5_port_config *config = opaque;
2158 /* No-op, port representors are processed in mlx5_dev_spawn(). */
2159 if (!strcmp(MLX5_REPRESENTOR, key))
2162 tmp = strtol(val, NULL, 0);
2165 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
2169 /* Negative values are acceptable for some keys only. */
2171 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
2174 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
2175 if (tmp > MLX5_CQE_RESP_FORMAT_L34H_STRIDX) {
2176 DRV_LOG(ERR, "invalid CQE compression "
2177 "format parameter");
2181 config->cqe_comp = !!tmp;
2182 config->cqe_comp_fmt = tmp;
2183 } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
2184 config->hw_padding = !!tmp;
2185 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
2186 config->mprq.enabled = !!tmp;
2187 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
2188 config->mprq.log_stride_num = tmp;
2189 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
2190 config->mprq.log_stride_size = tmp;
2191 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
2192 config->mprq.max_memcpy_len = tmp;
2193 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
2194 config->mprq.min_rxqs_num = tmp;
2195 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
2196 DRV_LOG(WARNING, "%s: deprecated parameter,"
2197 " converted to txq_inline_max", key);
2198 config->txq_inline_max = tmp;
2199 } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
2200 config->txq_inline_max = tmp;
2201 } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
2202 config->txq_inline_min = tmp;
2203 } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
2204 config->txq_inline_mpw = tmp;
2205 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
2206 config->txqs_inline = tmp;
2207 } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
2208 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
2209 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
2210 config->mps = !!tmp;
2211 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
2212 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
2213 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
2214 DRV_LOG(WARNING, "%s: deprecated parameter,"
2215 " converted to txq_inline_mpw", key);
2216 config->txq_inline_mpw = tmp;
2217 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
2218 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
2219 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
2220 config->rx_vec_en = !!tmp;
2221 } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
2222 config->max_dump_files_num = tmp;
2223 } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
2224 config->lro_timeout = tmp;
2225 } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
2226 config->log_hp_size = tmp;
2227 } else if (strcmp(MLX5_DELAY_DROP, key) == 0) {
2228 config->std_delay_drop = !!(tmp & MLX5_DELAY_DROP_STANDARD);
2229 config->hp_delay_drop = !!(tmp & MLX5_DELAY_DROP_HAIRPIN);
2235 * Parse user port parameters and adjust them according to device capabilities.
2238 * Pointer to shared device context.
2240 * Pointer to mlx5 kvargs control, can be NULL if there is no devargs.
2242 * Pointer to port configuration structure.
2245 * 0 on success, a negative errno value otherwise and rte_errno is set.
2248 mlx5_port_args_config(struct mlx5_priv *priv, struct mlx5_kvargs_ctrl *mkvlist,
2249 struct mlx5_port_config *config)
2251 struct mlx5_hca_attr *hca_attr = &priv->sh->cdev->config.hca_attr;
2252 struct mlx5_dev_cap *dev_cap = &priv->sh->dev_cap;
2253 bool devx = priv->sh->cdev->config.devx;
2254 const char **params = (const char *[]){
2255 MLX5_RXQ_CQE_COMP_EN,
2256 MLX5_RXQ_PKT_PAD_EN,
2258 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
2259 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
2260 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
2263 MLX5_TXQ_INLINE_MIN,
2264 MLX5_TXQ_INLINE_MAX,
2265 MLX5_TXQ_INLINE_MPW,
2266 MLX5_TXQS_MIN_INLINE,
2269 MLX5_TXQ_MPW_HDR_DSEG_EN,
2270 MLX5_TXQ_MAX_INLINE_LEN,
2274 MLX5_MAX_DUMP_FILES_NUM,
2275 MLX5_LRO_TIMEOUT_USEC,
2282 /* Default configuration. */
2283 memset(config, 0, sizeof(*config));
2284 config->mps = MLX5_ARG_UNSET;
2285 config->cqe_comp = 1;
2286 config->rx_vec_en = 1;
2287 config->txq_inline_max = MLX5_ARG_UNSET;
2288 config->txq_inline_min = MLX5_ARG_UNSET;
2289 config->txq_inline_mpw = MLX5_ARG_UNSET;
2290 config->txqs_inline = MLX5_ARG_UNSET;
2291 config->mprq.max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN;
2292 config->mprq.min_rxqs_num = MLX5_MPRQ_MIN_RXQS;
2293 config->mprq.log_stride_num = MLX5_MPRQ_DEFAULT_LOG_STRIDE_NUM;
2294 config->log_hp_size = MLX5_ARG_UNSET;
2295 config->std_delay_drop = 0;
2296 config->hp_delay_drop = 0;
2297 if (mkvlist != NULL) {
2298 /* Process parameters. */
2299 ret = mlx5_kvargs_process(mkvlist, params,
2300 mlx5_port_args_check_handler, config);
2302 DRV_LOG(ERR, "Failed to process port arguments: %s",
2303 strerror(rte_errno));
2307 /* Adjust parameters according to device capabilities. */
2308 if (config->hw_padding && !dev_cap->hw_padding) {
2309 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported.");
2310 config->hw_padding = 0;
2311 } else if (config->hw_padding) {
2312 DRV_LOG(DEBUG, "Rx end alignment padding is enabled.");
2315 * MPW is disabled by default, while the Enhanced MPW is enabled
2318 if (config->mps == MLX5_ARG_UNSET)
2319 config->mps = (dev_cap->mps == MLX5_MPW_ENHANCED) ?
2320 MLX5_MPW_ENHANCED : MLX5_MPW_DISABLED;
2322 config->mps = config->mps ? dev_cap->mps : MLX5_MPW_DISABLED;
2323 DRV_LOG(INFO, "%sMPS is %s",
2324 config->mps == MLX5_MPW_ENHANCED ? "enhanced " :
2325 config->mps == MLX5_MPW ? "legacy " : "",
2326 config->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled");
2327 /* LRO is supported only when DV flow enabled. */
2328 if (dev_cap->lro_supported && !priv->sh->config.dv_flow_en)
2329 dev_cap->lro_supported = 0;
2330 if (dev_cap->lro_supported) {
2332 * If LRO timeout is not configured by application,
2333 * use the minimal supported value.
2335 if (!config->lro_timeout)
2336 config->lro_timeout =
2337 hca_attr->lro_timer_supported_periods[0];
2338 DRV_LOG(DEBUG, "LRO session timeout set to %d usec.",
2339 config->lro_timeout);
2341 if (config->cqe_comp && !dev_cap->cqe_comp) {
2342 DRV_LOG(WARNING, "Rx CQE 128B compression is not supported.");
2343 config->cqe_comp = 0;
2345 if (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_FTAG_STRIDX &&
2346 (!devx || !hca_attr->mini_cqe_resp_flow_tag)) {
2348 "Flow Tag CQE compression format isn't supported.");
2349 config->cqe_comp = 0;
2351 if (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_L34H_STRIDX &&
2352 (!devx || !hca_attr->mini_cqe_resp_l3_l4_tag)) {
2354 "L3/L4 Header CQE compression format isn't supported.");
2355 config->cqe_comp = 0;
2357 DRV_LOG(DEBUG, "Rx CQE compression is %ssupported.",
2358 config->cqe_comp ? "" : "not ");
2359 if ((config->std_delay_drop || config->hp_delay_drop) &&
2360 !dev_cap->rq_delay_drop_en) {
2361 config->std_delay_drop = 0;
2362 config->hp_delay_drop = 0;
2363 DRV_LOG(WARNING, "dev_port-%u: Rxq delay drop isn't supported.",
2366 if (config->mprq.enabled && !priv->sh->dev_cap.mprq.enabled) {
2367 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported.");
2368 config->mprq.enabled = 0;
2370 if (config->max_dump_files_num == 0)
2371 config->max_dump_files_num = 128;
2372 /* Detect minimal data bytes to inline. */
2373 mlx5_set_min_inline(priv);
2374 DRV_LOG(DEBUG, "VLAN insertion in WQE is %ssupported.",
2375 config->hw_vlan_insert ? "" : "not ");
2376 DRV_LOG(DEBUG, "\"rxq_pkt_pad_en\" is %u.", config->hw_padding);
2377 DRV_LOG(DEBUG, "\"rxq_cqe_comp_en\" is %u.", config->cqe_comp);
2378 DRV_LOG(DEBUG, "\"cqe_comp_fmt\" is %u.", config->cqe_comp_fmt);
2379 DRV_LOG(DEBUG, "\"rx_vec_en\" is %u.", config->rx_vec_en);
2380 DRV_LOG(DEBUG, "Standard \"delay_drop\" is %u.",
2381 config->std_delay_drop);
2382 DRV_LOG(DEBUG, "Hairpin \"delay_drop\" is %u.", config->hp_delay_drop);
2383 DRV_LOG(DEBUG, "\"max_dump_files_num\" is %u.",
2384 config->max_dump_files_num);
2385 DRV_LOG(DEBUG, "\"log_hp_size\" is %u.", config->log_hp_size);
2386 DRV_LOG(DEBUG, "\"mprq_en\" is %u.", config->mprq.enabled);
2387 DRV_LOG(DEBUG, "\"mprq_log_stride_num\" is %u.",
2388 config->mprq.log_stride_num);
2389 DRV_LOG(DEBUG, "\"mprq_log_stride_size\" is %u.",
2390 config->mprq.log_stride_size);
2391 DRV_LOG(DEBUG, "\"mprq_max_memcpy_len\" is %u.",
2392 config->mprq.max_memcpy_len);
2393 DRV_LOG(DEBUG, "\"rxqs_min_mprq\" is %u.", config->mprq.min_rxqs_num);
2394 DRV_LOG(DEBUG, "\"lro_timeout_usec\" is %u.", config->lro_timeout);
2395 DRV_LOG(DEBUG, "\"txq_mpw_en\" is %d.", config->mps);
2396 DRV_LOG(DEBUG, "\"txqs_min_inline\" is %d.", config->txqs_inline);
2397 DRV_LOG(DEBUG, "\"txq_inline_min\" is %d.", config->txq_inline_min);
2398 DRV_LOG(DEBUG, "\"txq_inline_max\" is %d.", config->txq_inline_max);
2399 DRV_LOG(DEBUG, "\"txq_inline_mpw\" is %d.", config->txq_inline_mpw);
2404 * Print the key for device argument.
2406 * It is "dummy" handler whose whole purpose is to enable using
2407 * mlx5_kvargs_process() function which set devargs as used.
2412 * Value associated with key, unused.
2414 * Unused, can be NULL.
2417 * 0 on success, function cannot fail.
2420 mlx5_dummy_handler(const char *key, const char *val, void *opaque)
2422 DRV_LOG(DEBUG, "\tKey: \"%s\" is set as used.", key);
2423 RTE_SET_USED(opaque);
2429 * Set requested devargs as used when device is already spawned.
2431 * It is necessary since it is valid to ask probe again for existing device,
2432 * if its devargs don't assign as used, mlx5_kvargs_validate() will fail.
2435 * Name of the existing device.
2437 * Port identifier of the device.
2439 * Pointer to mlx5 kvargs control to sign as used.
2442 mlx5_port_args_set_used(const char *name, uint16_t port_id,
2443 struct mlx5_kvargs_ctrl *mkvlist)
2445 const char **params = (const char *[]){
2446 MLX5_RXQ_CQE_COMP_EN,
2447 MLX5_RXQ_PKT_PAD_EN,
2449 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
2450 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
2451 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
2454 MLX5_TXQ_INLINE_MIN,
2455 MLX5_TXQ_INLINE_MAX,
2456 MLX5_TXQ_INLINE_MPW,
2457 MLX5_TXQS_MIN_INLINE,
2460 MLX5_TXQ_MPW_HDR_DSEG_EN,
2461 MLX5_TXQ_MAX_INLINE_LEN,
2465 MLX5_MAX_DUMP_FILES_NUM,
2466 MLX5_LRO_TIMEOUT_USEC,
2472 /* Secondary process should not handle devargs. */
2473 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2475 MLX5_ASSERT(mkvlist != NULL);
2476 DRV_LOG(DEBUG, "Ethernet device \"%s\" for port %u "
2477 "already exists, set devargs as used:", name, port_id);
2478 /* This function cannot fail with this handler. */
2479 mlx5_kvargs_process(mkvlist, params, mlx5_dummy_handler, NULL);
2483 * Check sibling device configurations when probing again.
2485 * Sibling devices sharing infiniband device context should have compatible
2486 * configurations. This regards representors and bonding device.
2489 * Pointer to mlx5 device structure.
2491 * Pointer to mlx5 kvargs control, can be NULL if there is no devargs.
2494 * 0 on success, a negative errno value otherwise and rte_errno is set.
2497 mlx5_probe_again_args_validate(struct mlx5_common_device *cdev,
2498 struct mlx5_kvargs_ctrl *mkvlist)
2500 struct mlx5_dev_ctx_shared *sh = NULL;
2501 struct mlx5_sh_config *config;
2504 /* Secondary process should not handle devargs. */
2505 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2507 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
2508 /* Search for IB context by common device pointer. */
2509 LIST_FOREACH(sh, &mlx5_dev_ctx_list, next)
2510 if (sh->cdev == cdev)
2512 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
2513 /* There is sh for this device -> it isn't probe again. */
2516 config = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
2517 sizeof(struct mlx5_sh_config),
2518 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
2519 if (config == NULL) {
2520 rte_errno = -ENOMEM;
2524 * Creates a temporary IB context configure structure according to new
2525 * devargs attached in probing again.
2527 ret = mlx5_shared_dev_ctx_args_config(sh, mkvlist, config);
2529 DRV_LOG(ERR, "Failed to process device configure: %s",
2530 strerror(rte_errno));
2535 * Checks the match between the temporary structure and the existing
2536 * IB context structure.
2538 if (sh->config.dv_flow_en ^ config->dv_flow_en) {
2539 DRV_LOG(ERR, "\"dv_flow_en\" "
2540 "configuration mismatch for shared %s context.",
2544 if ((sh->config.dv_xmeta_en ^ config->dv_xmeta_en) ||
2545 (sh->config.dv_miss_info ^ config->dv_miss_info)) {
2546 DRV_LOG(ERR, "\"dv_xmeta_en\" "
2547 "configuration mismatch for shared %s context.",
2551 if (sh->config.dv_esw_en ^ config->dv_esw_en) {
2552 DRV_LOG(ERR, "\"dv_esw_en\" "
2553 "configuration mismatch for shared %s context.",
2557 if (sh->config.reclaim_mode ^ config->reclaim_mode) {
2558 DRV_LOG(ERR, "\"reclaim_mode\" "
2559 "configuration mismatch for shared %s context.",
2563 if (sh->config.allow_duplicate_pattern ^
2564 config->allow_duplicate_pattern) {
2565 DRV_LOG(ERR, "\"allow_duplicate_pattern\" "
2566 "configuration mismatch for shared %s context.",
2570 if (sh->config.l3_vxlan_en ^ config->l3_vxlan_en) {
2571 DRV_LOG(ERR, "\"l3_vxlan_en\" "
2572 "configuration mismatch for shared %s context.",
2576 if (sh->config.decap_en ^ config->decap_en) {
2577 DRV_LOG(ERR, "\"decap_en\" "
2578 "configuration mismatch for shared %s context.",
2582 if (sh->config.lacp_by_user ^ config->lacp_by_user) {
2583 DRV_LOG(ERR, "\"lacp_by_user\" "
2584 "configuration mismatch for shared %s context.",
2588 if (sh->config.tx_pp ^ config->tx_pp) {
2589 DRV_LOG(ERR, "\"tx_pp\" "
2590 "configuration mismatch for shared %s context.",
2594 if (sh->config.tx_skew ^ config->tx_skew) {
2595 DRV_LOG(ERR, "\"tx_skew\" "
2596 "configuration mismatch for shared %s context.",
2609 * Configures the minimal amount of data to inline into WQE
2610 * while sending packets.
2612 * - the txq_inline_min has the maximal priority, if this
2613 * key is specified in devargs
2614 * - if DevX is enabled the inline mode is queried from the
2615 * device (HCA attributes and NIC vport context if needed).
2616 * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
2617 * and none (0 bytes) for other NICs
2620 * Pointer to the private device data structure.
2623 mlx5_set_min_inline(struct mlx5_priv *priv)
2625 struct mlx5_hca_attr *hca_attr = &priv->sh->cdev->config.hca_attr;
2626 struct mlx5_port_config *config = &priv->config;
2628 if (config->txq_inline_min != MLX5_ARG_UNSET) {
2629 /* Application defines size of inlined data explicitly. */
2630 if (priv->pci_dev != NULL) {
2631 switch (priv->pci_dev->id.device_id) {
2632 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2633 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2634 if (config->txq_inline_min <
2635 (int)MLX5_INLINE_HSIZE_L2) {
2637 "txq_inline_mix aligned to minimal ConnectX-4 required value %d",
2638 (int)MLX5_INLINE_HSIZE_L2);
2639 config->txq_inline_min =
2640 MLX5_INLINE_HSIZE_L2;
2647 if (hca_attr->eth_net_offloads) {
2648 /* We have DevX enabled, inline mode queried successfully. */
2649 switch (hca_attr->wqe_inline_mode) {
2650 case MLX5_CAP_INLINE_MODE_L2:
2651 /* outer L2 header must be inlined. */
2652 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2654 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
2655 /* No inline data are required by NIC. */
2656 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2657 config->hw_vlan_insert =
2658 hca_attr->wqe_vlan_insert;
2659 DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
2661 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
2662 /* inline mode is defined by NIC vport context. */
2663 if (!hca_attr->eth_virt)
2665 switch (hca_attr->vport_inline_mode) {
2666 case MLX5_INLINE_MODE_NONE:
2667 config->txq_inline_min =
2668 MLX5_INLINE_HSIZE_NONE;
2670 case MLX5_INLINE_MODE_L2:
2671 config->txq_inline_min =
2672 MLX5_INLINE_HSIZE_L2;
2674 case MLX5_INLINE_MODE_IP:
2675 config->txq_inline_min =
2676 MLX5_INLINE_HSIZE_L3;
2678 case MLX5_INLINE_MODE_TCP_UDP:
2679 config->txq_inline_min =
2680 MLX5_INLINE_HSIZE_L4;
2682 case MLX5_INLINE_MODE_INNER_L2:
2683 config->txq_inline_min =
2684 MLX5_INLINE_HSIZE_INNER_L2;
2686 case MLX5_INLINE_MODE_INNER_IP:
2687 config->txq_inline_min =
2688 MLX5_INLINE_HSIZE_INNER_L3;
2690 case MLX5_INLINE_MODE_INNER_TCP_UDP:
2691 config->txq_inline_min =
2692 MLX5_INLINE_HSIZE_INNER_L4;
2697 if (priv->pci_dev == NULL) {
2698 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2702 * We get here if we are unable to deduce
2703 * inline data size with DevX. Try PCI ID
2704 * to determine old NICs.
2706 switch (priv->pci_dev->id.device_id) {
2707 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2708 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2709 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
2710 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
2711 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2712 config->hw_vlan_insert = 0;
2714 case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
2715 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
2716 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
2717 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
2719 * These NICs support VLAN insertion from WQE and
2720 * report the wqe_vlan_insert flag. But there is the bug
2721 * and PFC control may be broken, so disable feature.
2723 config->hw_vlan_insert = 0;
2724 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2727 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2731 DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
2735 * Configures the metadata mask fields in the shared context.
2738 * Pointer to Ethernet device.
2741 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
2743 struct mlx5_priv *priv = dev->data->dev_private;
2744 struct mlx5_dev_ctx_shared *sh = priv->sh;
2745 uint32_t meta, mark, reg_c0;
2747 reg_c0 = ~priv->vport_meta_mask;
2748 switch (sh->config.dv_xmeta_en) {
2749 case MLX5_XMETA_MODE_LEGACY:
2751 mark = MLX5_FLOW_MARK_MASK;
2753 case MLX5_XMETA_MODE_META16:
2754 meta = reg_c0 >> rte_bsf32(reg_c0);
2755 mark = MLX5_FLOW_MARK_MASK;
2757 case MLX5_XMETA_MODE_META32:
2759 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
2767 if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
2768 DRV_LOG(WARNING, "metadata MARK mask mismatch %08X:%08X",
2769 sh->dv_mark_mask, mark);
2771 sh->dv_mark_mask = mark;
2772 if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
2773 DRV_LOG(WARNING, "metadata META mask mismatch %08X:%08X",
2774 sh->dv_meta_mask, meta);
2776 sh->dv_meta_mask = meta;
2777 if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
2778 DRV_LOG(WARNING, "metadata reg_c0 mask mismatch %08X:%08X",
2779 sh->dv_meta_mask, reg_c0);
2781 sh->dv_regc0_mask = reg_c0;
2782 DRV_LOG(DEBUG, "metadata mode %u", sh->config.dv_xmeta_en);
2783 DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
2784 DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
2785 DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
2789 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
2791 static const char *const dynf_names[] = {
2792 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
2793 RTE_MBUF_DYNFLAG_METADATA_NAME,
2794 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
2798 if (n < RTE_DIM(dynf_names))
2800 for (i = 0; i < RTE_DIM(dynf_names); i++) {
2801 if (names[i] == NULL)
2803 strcpy(names[i], dynf_names[i]);
2805 return RTE_DIM(dynf_names);
2809 * Look for the ethernet device belonging to mlx5 driver.
2811 * @param[in] port_id
2812 * port_id to start looking for device.
2814 * Pointer to the hint device. When device is being probed
2815 * the its siblings (master and preceding representors might
2816 * not have assigned driver yet (because the mlx5_os_pci_probe()
2817 * is not completed yet, for this case match on hint
2818 * device may be used to detect sibling device.
2821 * port_id of found device, RTE_MAX_ETHPORT if not found.
2824 mlx5_eth_find_next(uint16_t port_id, struct rte_device *odev)
2826 while (port_id < RTE_MAX_ETHPORTS) {
2827 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
2829 if (dev->state != RTE_ETH_DEV_UNUSED &&
2831 (dev->device == odev ||
2832 (dev->device->driver &&
2833 dev->device->driver->name &&
2834 ((strcmp(dev->device->driver->name,
2835 MLX5_PCI_DRIVER_NAME) == 0) ||
2836 (strcmp(dev->device->driver->name,
2837 MLX5_AUXILIARY_DRIVER_NAME) == 0)))))
2841 if (port_id >= RTE_MAX_ETHPORTS)
2842 return RTE_MAX_ETHPORTS;
2847 * Callback to remove a device.
2849 * This function removes all Ethernet devices belong to a given device.
2852 * Pointer to the generic device.
2855 * 0 on success, the function cannot fail.
2858 mlx5_net_remove(struct mlx5_common_device *cdev)
2863 RTE_ETH_FOREACH_DEV_OF(port_id, cdev->dev) {
2865 * mlx5_dev_close() is not registered to secondary process,
2866 * call the close function explicitly for secondary process.
2868 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
2869 ret |= mlx5_dev_close(&rte_eth_devices[port_id]);
2871 ret |= rte_eth_dev_close(port_id);
2873 return ret == 0 ? 0 : -EIO;
2876 static const struct rte_pci_id mlx5_pci_id_map[] = {
2878 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2879 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
2882 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2883 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
2886 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2887 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
2890 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2891 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
2894 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2895 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
2898 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2899 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
2902 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2903 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
2906 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2907 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
2910 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2911 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
2914 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2915 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
2918 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2919 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
2922 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2923 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
2926 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2927 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
2930 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2931 PCI_DEVICE_ID_MELLANOX_CONNECTXVF)
2934 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2935 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
2938 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2939 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
2942 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2943 PCI_DEVICE_ID_MELLANOX_CONNECTX7)
2946 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2947 PCI_DEVICE_ID_MELLANOX_CONNECTX7BF)
2954 static struct mlx5_class_driver mlx5_net_driver = {
2955 .drv_class = MLX5_CLASS_ETH,
2956 .name = RTE_STR(MLX5_ETH_DRIVER_NAME),
2957 .id_table = mlx5_pci_id_map,
2958 .probe = mlx5_os_net_probe,
2959 .remove = mlx5_net_remove,
2965 /* Initialize driver log type. */
2966 RTE_LOG_REGISTER_DEFAULT(mlx5_logtype, NOTICE)
2969 * Driver initialization routine.
2971 RTE_INIT(rte_mlx5_pmd_init)
2973 pthread_mutex_init(&mlx5_dev_ctx_list_mutex, NULL);
2975 /* Build the static tables for Verbs conversion. */
2976 mlx5_set_ptype_table();
2977 mlx5_set_cksum_table();
2978 mlx5_set_swp_types_table();
2980 mlx5_class_driver_register(&mlx5_net_driver);
2983 RTE_PMD_EXPORT_NAME(MLX5_ETH_DRIVER_NAME, __COUNTER__);
2984 RTE_PMD_REGISTER_PCI_TABLE(MLX5_ETH_DRIVER_NAME, mlx5_pci_id_map);
2985 RTE_PMD_REGISTER_KMOD_DEP(MLX5_ETH_DRIVER_NAME, "* ib_uverbs & mlx5_core & mlx5_ib");