4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
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8 * modification, are permitted provided that the following conditions
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44 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
46 #pragma GCC diagnostic ignored "-Wpedantic"
48 #include <infiniband/verbs.h>
50 #pragma GCC diagnostic error "-Wpedantic"
53 #include <rte_malloc.h>
54 #include <rte_ethdev.h>
55 #include <rte_ethdev_pci.h>
57 #include <rte_common.h>
58 #include <rte_kvargs.h>
61 #include "mlx5_utils.h"
62 #include "mlx5_rxtx.h"
63 #include "mlx5_autoconf.h"
64 #include "mlx5_defs.h"
66 /* Device parameter to enable RX completion queue compression. */
67 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
69 /* Device parameter to configure inline send. */
70 #define MLX5_TXQ_INLINE "txq_inline"
73 * Device parameter to configure the number of TX queues threshold for
74 * enabling inline send.
76 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
78 /* Device parameter to enable multi-packet send WQEs. */
79 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
81 /* Device parameter to include 2 dsegs in the title WQEBB. */
82 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
84 /* Device parameter to limit the size of inlining packet. */
85 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
87 /* Device parameter to enable hardware TSO offload. */
88 #define MLX5_TSO "tso"
90 /* Device parameter to enable hardware Tx vector. */
91 #define MLX5_TX_VEC_EN "tx_vec_en"
93 /* Device parameter to enable hardware Rx vector. */
94 #define MLX5_RX_VEC_EN "rx_vec_en"
96 /* Default PMD specific parameter value. */
97 #define MLX5_ARG_UNSET (-1)
99 #ifndef HAVE_IBV_MLX5_MOD_MPW
100 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2)
101 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3)
110 int inline_max_packet_sz;
116 * Retrieve integer value from environment variable.
119 * Environment variable name.
122 * Integer value, 0 if the variable is not set.
125 mlx5_getenv_int(const char *name)
127 const char *val = getenv(name);
135 * DPDK callback to close the device.
137 * Destroy all queues and objects, free memory.
140 * Pointer to Ethernet device structure.
143 mlx5_dev_close(struct rte_eth_dev *dev)
145 struct priv *priv = mlx5_get_priv(dev);
149 DEBUG("%p: closing device \"%s\"",
151 ((priv->ctx != NULL) ? priv->ctx->device->name : ""));
152 /* In case mlx5_dev_stop() has not been called. */
153 priv_dev_interrupt_handler_uninstall(priv, dev);
154 priv_special_flow_disable_all(priv);
155 priv_mac_addrs_disable(priv);
156 priv_destroy_hash_rxqs(priv);
158 /* Remove flow director elements. */
159 priv_fdir_disable(priv);
160 priv_fdir_delete_filters_list(priv);
162 /* Prevent crashes when queues are still in use. */
163 dev->rx_pkt_burst = removed_rx_burst;
164 dev->tx_pkt_burst = removed_tx_burst;
165 if (priv->rxqs != NULL) {
166 /* XXX race condition if mlx5_rx_burst() is still running. */
168 for (i = 0; (i != priv->rxqs_n); ++i) {
169 struct rxq *rxq = (*priv->rxqs)[i];
170 struct rxq_ctrl *rxq_ctrl;
174 rxq_ctrl = container_of(rxq, struct rxq_ctrl, rxq);
175 (*priv->rxqs)[i] = NULL;
176 rxq_cleanup(rxq_ctrl);
182 if (priv->txqs != NULL) {
183 /* XXX race condition if mlx5_tx_burst() is still running. */
185 for (i = 0; (i != priv->txqs_n); ++i) {
186 struct txq *txq = (*priv->txqs)[i];
187 struct txq_ctrl *txq_ctrl;
191 txq_ctrl = container_of(txq, struct txq_ctrl, txq);
192 (*priv->txqs)[i] = NULL;
193 txq_cleanup(txq_ctrl);
199 if (priv->pd != NULL) {
200 assert(priv->ctx != NULL);
201 claim_zero(ibv_dealloc_pd(priv->pd));
202 claim_zero(ibv_close_device(priv->ctx));
204 assert(priv->ctx == NULL);
205 if (priv->rss_conf != NULL) {
206 for (i = 0; (i != hash_rxq_init_n); ++i)
207 rte_free((*priv->rss_conf)[i]);
208 rte_free(priv->rss_conf);
210 if (priv->reta_idx != NULL)
211 rte_free(priv->reta_idx);
212 priv_socket_uninit(priv);
214 memset(priv, 0, sizeof(*priv));
217 static const struct eth_dev_ops mlx5_dev_ops = {
218 .dev_configure = mlx5_dev_configure,
219 .dev_start = mlx5_dev_start,
220 .dev_stop = mlx5_dev_stop,
221 .dev_set_link_down = mlx5_set_link_down,
222 .dev_set_link_up = mlx5_set_link_up,
223 .dev_close = mlx5_dev_close,
224 .promiscuous_enable = mlx5_promiscuous_enable,
225 .promiscuous_disable = mlx5_promiscuous_disable,
226 .allmulticast_enable = mlx5_allmulticast_enable,
227 .allmulticast_disable = mlx5_allmulticast_disable,
228 .link_update = mlx5_link_update,
229 .stats_get = mlx5_stats_get,
230 .stats_reset = mlx5_stats_reset,
231 .xstats_get = mlx5_xstats_get,
232 .xstats_reset = mlx5_xstats_reset,
233 .xstats_get_names = mlx5_xstats_get_names,
234 .dev_infos_get = mlx5_dev_infos_get,
235 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
236 .vlan_filter_set = mlx5_vlan_filter_set,
237 .rx_queue_setup = mlx5_rx_queue_setup,
238 .tx_queue_setup = mlx5_tx_queue_setup,
239 .rx_queue_release = mlx5_rx_queue_release,
240 .tx_queue_release = mlx5_tx_queue_release,
241 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
242 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
243 .mac_addr_remove = mlx5_mac_addr_remove,
244 .mac_addr_add = mlx5_mac_addr_add,
245 .mac_addr_set = mlx5_mac_addr_set,
246 .mtu_set = mlx5_dev_set_mtu,
247 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
248 .vlan_offload_set = mlx5_vlan_offload_set,
249 .reta_update = mlx5_dev_rss_reta_update,
250 .reta_query = mlx5_dev_rss_reta_query,
251 .rss_hash_update = mlx5_rss_hash_update,
252 .rss_hash_conf_get = mlx5_rss_hash_conf_get,
253 .filter_ctrl = mlx5_dev_filter_ctrl,
254 .rx_descriptor_status = mlx5_rx_descriptor_status,
255 .tx_descriptor_status = mlx5_tx_descriptor_status,
256 .rx_queue_intr_enable = mlx5_rx_intr_enable,
257 .rx_queue_intr_disable = mlx5_rx_intr_disable,
261 struct rte_pci_addr pci_addr; /* associated PCI address */
262 uint32_t ports; /* physical ports bitfield. */
266 * Get device index in mlx5_dev[] from PCI bus address.
268 * @param[in] pci_addr
269 * PCI bus address to look for.
272 * mlx5_dev[] index on success, -1 on failure.
275 mlx5_dev_idx(struct rte_pci_addr *pci_addr)
280 assert(pci_addr != NULL);
281 for (i = 0; (i != RTE_DIM(mlx5_dev)); ++i) {
282 if ((mlx5_dev[i].pci_addr.domain == pci_addr->domain) &&
283 (mlx5_dev[i].pci_addr.bus == pci_addr->bus) &&
284 (mlx5_dev[i].pci_addr.devid == pci_addr->devid) &&
285 (mlx5_dev[i].pci_addr.function == pci_addr->function))
287 if ((mlx5_dev[i].ports == 0) && (ret == -1))
294 * Verify and store value for device argument.
297 * Key argument to verify.
299 * Value associated with key.
304 * 0 on success, negative errno value on failure.
307 mlx5_args_check(const char *key, const char *val, void *opaque)
309 struct mlx5_args *args = opaque;
313 tmp = strtoul(val, NULL, 0);
315 WARN("%s: \"%s\" is not a valid integer", key, val);
318 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
319 args->cqe_comp = !!tmp;
320 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
321 args->txq_inline = tmp;
322 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
323 args->txqs_inline = tmp;
324 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
326 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
327 args->mpw_hdr_dseg = !!tmp;
328 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
329 args->inline_max_packet_sz = tmp;
330 } else if (strcmp(MLX5_TSO, key) == 0) {
332 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
333 args->tx_vec_en = !!tmp;
334 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
335 args->rx_vec_en = !!tmp;
337 WARN("%s: unknown parameter", key);
344 * Parse device parameters.
347 * Pointer to private structure.
349 * Device arguments structure.
352 * 0 on success, errno value on failure.
355 mlx5_args(struct mlx5_args *args, struct rte_devargs *devargs)
357 const char **params = (const char *[]){
358 MLX5_RXQ_CQE_COMP_EN,
360 MLX5_TXQS_MIN_INLINE,
362 MLX5_TXQ_MPW_HDR_DSEG_EN,
363 MLX5_TXQ_MAX_INLINE_LEN,
369 struct rte_kvargs *kvlist;
375 /* Following UGLY cast is done to pass checkpatch. */
376 kvlist = rte_kvargs_parse(devargs->args, params);
379 /* Process parameters. */
380 for (i = 0; (params[i] != NULL); ++i) {
381 if (rte_kvargs_count(kvlist, params[i])) {
382 ret = rte_kvargs_process(kvlist, params[i],
383 mlx5_args_check, args);
385 rte_kvargs_free(kvlist);
390 rte_kvargs_free(kvlist);
394 static struct rte_pci_driver mlx5_driver;
397 * Assign parameters from args into priv, only non default
398 * values are considered.
401 * Pointer to private structure.
403 * Pointer to args values.
406 mlx5_args_assign(struct priv *priv, struct mlx5_args *args)
408 if (args->cqe_comp != MLX5_ARG_UNSET)
409 priv->cqe_comp = args->cqe_comp;
410 if (args->txq_inline != MLX5_ARG_UNSET)
411 priv->txq_inline = args->txq_inline;
412 if (args->txqs_inline != MLX5_ARG_UNSET)
413 priv->txqs_inline = args->txqs_inline;
414 if (args->mps != MLX5_ARG_UNSET)
415 priv->mps = args->mps ? priv->mps : 0;
416 if (args->mpw_hdr_dseg != MLX5_ARG_UNSET)
417 priv->mpw_hdr_dseg = args->mpw_hdr_dseg;
418 if (args->inline_max_packet_sz != MLX5_ARG_UNSET)
419 priv->inline_max_packet_sz = args->inline_max_packet_sz;
420 if (args->tso != MLX5_ARG_UNSET)
421 priv->tso = args->tso;
422 if (args->tx_vec_en != MLX5_ARG_UNSET)
423 priv->tx_vec_en = args->tx_vec_en;
424 if (args->rx_vec_en != MLX5_ARG_UNSET)
425 priv->rx_vec_en = args->rx_vec_en;
429 * DPDK callback to register a PCI device.
431 * This function creates an Ethernet device for each port of a given
435 * PCI driver structure (mlx5_driver).
437 * PCI device information.
440 * 0 on success, negative errno value on failure.
443 mlx5_pci_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
445 struct ibv_device **list;
446 struct ibv_device *ibv_dev;
448 struct ibv_context *attr_ctx = NULL;
449 struct ibv_device_attr_ex device_attr;
452 unsigned int tunnel_en = 0;
455 struct mlx5dv_context attrs_out;
458 assert(pci_drv == &mlx5_driver);
459 /* Get mlx5_dev[] index. */
460 idx = mlx5_dev_idx(&pci_dev->addr);
462 ERROR("this driver cannot support any more adapters");
465 DEBUG("using driver device index %d", idx);
467 /* Save PCI address. */
468 mlx5_dev[idx].pci_addr = pci_dev->addr;
469 list = ibv_get_device_list(&i);
473 ERROR("cannot list devices, is ib_uverbs loaded?");
478 * For each listed device, check related sysfs entry against
479 * the provided PCI ID.
482 struct rte_pci_addr pci_addr;
485 DEBUG("checking device \"%s\"", list[i]->name);
486 if (mlx5_ibv_device_to_pci_addr(list[i], &pci_addr))
488 if ((pci_dev->addr.domain != pci_addr.domain) ||
489 (pci_dev->addr.bus != pci_addr.bus) ||
490 (pci_dev->addr.devid != pci_addr.devid) ||
491 (pci_dev->addr.function != pci_addr.function))
493 sriov = ((pci_dev->id.device_id ==
494 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF) ||
495 (pci_dev->id.device_id ==
496 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF) ||
497 (pci_dev->id.device_id ==
498 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF) ||
499 (pci_dev->id.device_id ==
500 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF));
501 switch (pci_dev->id.device_id) {
502 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
505 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
506 case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
507 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
508 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
509 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
515 INFO("PCI information matches, using device \"%s\""
518 sriov ? "true" : "false");
519 attr_ctx = ibv_open_device(list[i]);
523 if (attr_ctx == NULL) {
524 ibv_free_device_list(list);
527 ERROR("cannot access device, is mlx5_ib loaded?");
530 ERROR("cannot use device, are drivers up to date?");
538 DEBUG("device opened");
540 * Multi-packet send is supported by ConnectX-4 Lx PF as well
541 * as all ConnectX-5 devices.
543 mlx5dv_query_device(attr_ctx, &attrs_out);
544 if (attrs_out.flags & (MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW |
545 MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED)) {
546 INFO("Enhanced MPW is detected\n");
547 mps = MLX5_MPW_ENHANCED;
548 } else if (attrs_out.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
549 INFO("MPW is detected\n");
552 INFO("MPW is disabled\n");
553 mps = MLX5_MPW_DISABLED;
555 if (ibv_query_device_ex(attr_ctx, NULL, &device_attr))
557 INFO("%u port(s) detected", device_attr.orig_attr.phys_port_cnt);
559 for (i = 0; i < device_attr.orig_attr.phys_port_cnt; i++) {
560 uint32_t port = i + 1; /* ports are indexed from one */
561 uint32_t test = (1 << i);
562 struct ibv_context *ctx = NULL;
563 struct ibv_port_attr port_attr;
564 struct ibv_pd *pd = NULL;
565 struct priv *priv = NULL;
566 struct rte_eth_dev *eth_dev;
567 struct ibv_device_attr_ex device_attr_ex;
568 struct ether_addr mac;
569 uint16_t num_vfs = 0;
570 struct mlx5_args args = {
571 .cqe_comp = MLX5_ARG_UNSET,
572 .txq_inline = MLX5_ARG_UNSET,
573 .txqs_inline = MLX5_ARG_UNSET,
574 .mps = MLX5_ARG_UNSET,
575 .mpw_hdr_dseg = MLX5_ARG_UNSET,
576 .inline_max_packet_sz = MLX5_ARG_UNSET,
577 .tso = MLX5_ARG_UNSET,
578 .tx_vec_en = MLX5_ARG_UNSET,
579 .rx_vec_en = MLX5_ARG_UNSET,
582 mlx5_dev[idx].ports |= test;
584 if (mlx5_is_secondary()) {
585 /* from rte_ethdev.c */
586 char name[RTE_ETH_NAME_MAX_LEN];
588 snprintf(name, sizeof(name), "%s port %u",
589 ibv_get_device_name(ibv_dev), port);
590 eth_dev = rte_eth_dev_attach_secondary(name);
591 if (eth_dev == NULL) {
592 ERROR("can not attach rte ethdev");
596 eth_dev->device = &pci_dev->device;
597 eth_dev->dev_ops = NULL;
598 priv = eth_dev->data->dev_private;
599 /* Receive command fd from primary process */
600 err = priv_socket_connect(priv);
605 /* Remap UAR for Tx queues. */
606 err = priv_tx_uar_remap(priv, err);
611 priv_dev_select_rx_function(priv, eth_dev);
612 priv_dev_select_tx_function(priv, eth_dev);
616 DEBUG("using port %u (%08" PRIx32 ")", port, test);
618 ctx = ibv_open_device(ibv_dev);
624 /* Check port status. */
625 err = ibv_query_port(ctx, port, &port_attr);
627 ERROR("port query failed: %s", strerror(err));
631 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
632 ERROR("port %d is not configured in Ethernet mode",
638 if (port_attr.state != IBV_PORT_ACTIVE)
639 DEBUG("port %d is not active: \"%s\" (%d)",
640 port, ibv_port_state_str(port_attr.state),
643 /* Allocate protection domain. */
644 pd = ibv_alloc_pd(ctx);
646 ERROR("PD allocation failure");
651 mlx5_dev[idx].ports |= test;
653 /* from rte_ethdev.c */
654 priv = rte_zmalloc("ethdev private structure",
656 RTE_CACHE_LINE_SIZE);
658 ERROR("priv allocation failure");
664 priv->device_attr = device_attr;
667 priv->mtu = ETHER_MTU;
668 priv->mps = mps; /* Enable MPW by default if supported. */
669 priv->cqe_comp = 1; /* Enable compression by default. */
670 priv->tunnel_en = tunnel_en;
671 /* Enable vector by default if supported. */
674 err = mlx5_args(&args, pci_dev->device.devargs);
676 ERROR("failed to process device arguments: %s",
680 mlx5_args_assign(priv, &args);
681 if (ibv_query_device_ex(ctx, NULL, &device_attr_ex)) {
682 ERROR("ibv_query_device_ex() failed");
687 !!(device_attr_ex.device_cap_flags_ex &
688 IBV_DEVICE_RAW_IP_CSUM);
689 DEBUG("checksum offloading is %ssupported",
690 (priv->hw_csum ? "" : "not "));
692 #ifdef HAVE_IBV_DEVICE_VXLAN_SUPPORT
693 priv->hw_csum_l2tun = !!(exp_device_attr.exp_device_cap_flags &
694 IBV_DEVICE_VXLAN_SUPPORT);
696 DEBUG("L2 tunnel checksum offloads are %ssupported",
697 (priv->hw_csum_l2tun ? "" : "not "));
699 priv->ind_table_max_size =
700 device_attr_ex.rss_caps.max_rwq_indirection_table_size;
701 /* Remove this check once DPDK supports larger/variable
702 * indirection tables. */
703 if (priv->ind_table_max_size >
704 (unsigned int)ETH_RSS_RETA_SIZE_512)
705 priv->ind_table_max_size = ETH_RSS_RETA_SIZE_512;
706 DEBUG("maximum RX indirection table size is %u",
707 priv->ind_table_max_size);
708 priv->hw_vlan_strip = !!(device_attr_ex.raw_packet_caps &
709 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
710 DEBUG("VLAN stripping is %ssupported",
711 (priv->hw_vlan_strip ? "" : "not "));
714 !!(device_attr_ex.orig_attr.device_cap_flags &
715 IBV_WQ_FLAGS_SCATTER_FCS);
716 DEBUG("FCS stripping configuration is %ssupported",
717 (priv->hw_fcs_strip ? "" : "not "));
719 #ifdef HAVE_IBV_WQ_FLAG_RX_END_PADDING
720 priv->hw_padding = !!device_attr_ex.rx_pad_end_addr_align;
722 DEBUG("hardware RX end alignment padding is %ssupported",
723 (priv->hw_padding ? "" : "not "));
725 priv_get_num_vfs(priv, &num_vfs);
726 priv->sriov = (num_vfs || sriov);
727 priv->tso = ((priv->tso) &&
728 (device_attr_ex.tso_caps.max_tso > 0) &&
729 (device_attr_ex.tso_caps.supported_qpts &
730 (1 << IBV_QPT_RAW_PACKET)));
732 priv->max_tso_payload_sz =
733 device_attr_ex.tso_caps.max_tso;
734 if (priv->mps && !mps) {
735 ERROR("multi-packet send not supported on this device"
736 " (" MLX5_TXQ_MPW_EN ")");
739 } else if (priv->mps && priv->tso) {
740 WARN("multi-packet send not supported in conjunction "
741 "with TSO. MPS disabled");
745 priv->mps == MLX5_MPW_ENHANCED ? "Enhanced " : "",
746 priv->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled");
747 /* Set default values for Enhanced MPW, a.k.a MPWv2. */
748 if (priv->mps == MLX5_MPW_ENHANCED) {
749 if (args.txqs_inline == MLX5_ARG_UNSET)
750 priv->txqs_inline = MLX5_EMPW_MIN_TXQS;
751 if (args.inline_max_packet_sz == MLX5_ARG_UNSET)
752 priv->inline_max_packet_sz =
753 MLX5_EMPW_MAX_INLINE_LEN;
754 if (args.txq_inline == MLX5_ARG_UNSET)
755 priv->txq_inline = MLX5_WQE_SIZE_MAX -
758 /* Allocate and register default RSS hash keys. */
759 priv->rss_conf = rte_calloc(__func__, hash_rxq_init_n,
760 sizeof((*priv->rss_conf)[0]), 0);
761 if (priv->rss_conf == NULL) {
765 err = rss_hash_rss_conf_new_key(priv,
766 rss_hash_default_key,
767 rss_hash_default_key_len,
771 /* Configure the first MAC address by default. */
772 if (priv_get_mac(priv, &mac.addr_bytes)) {
773 ERROR("cannot get MAC address, is mlx5_en loaded?"
774 " (errno: %s)", strerror(errno));
778 INFO("port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x",
780 mac.addr_bytes[0], mac.addr_bytes[1],
781 mac.addr_bytes[2], mac.addr_bytes[3],
782 mac.addr_bytes[4], mac.addr_bytes[5]);
783 /* Register MAC address. */
784 claim_zero(priv_mac_addr_add(priv, 0,
785 (const uint8_t (*)[ETHER_ADDR_LEN])
787 /* Initialize FD filters list. */
788 err = fdir_init_filters_list(priv);
793 char ifname[IF_NAMESIZE];
795 if (priv_get_ifname(priv, &ifname) == 0)
796 DEBUG("port %u ifname is \"%s\"",
799 DEBUG("port %u ifname is unknown", priv->port);
802 /* Get actual MTU if possible. */
803 priv_get_mtu(priv, &priv->mtu);
804 DEBUG("port %u MTU is %u", priv->port, priv->mtu);
806 /* from rte_ethdev.c */
808 char name[RTE_ETH_NAME_MAX_LEN];
810 snprintf(name, sizeof(name), "%s port %u",
811 ibv_get_device_name(ibv_dev), port);
812 eth_dev = rte_eth_dev_allocate(name);
814 if (eth_dev == NULL) {
815 ERROR("can not allocate rte ethdev");
819 eth_dev->data->dev_private = priv;
820 eth_dev->data->mac_addrs = priv->mac;
821 eth_dev->device = &pci_dev->device;
822 rte_eth_copy_pci_info(eth_dev, pci_dev);
823 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
824 eth_dev->device->driver = &mlx5_driver.driver;
826 eth_dev->dev_ops = &mlx5_dev_ops;
827 TAILQ_INIT(&priv->flows);
829 /* Bring Ethernet device up. */
830 DEBUG("forcing Ethernet interface up");
831 priv_set_flags(priv, ~IFF_UP, IFF_UP);
832 mlx5_link_update(priv->dev, 1);
837 rte_free(priv->rss_conf);
841 claim_zero(ibv_dealloc_pd(pd));
843 claim_zero(ibv_close_device(ctx));
848 * XXX if something went wrong in the loop above, there is a resource
849 * leak (ctx, pd, priv, dpdk ethdev) but we can do nothing about it as
850 * long as the dpdk does not provide a way to deallocate a ethdev and a
851 * way to enumerate the registered ethdevs to free the previous ones.
854 /* no port found, complain */
855 if (!mlx5_dev[idx].ports) {
862 claim_zero(ibv_close_device(attr_ctx));
864 ibv_free_device_list(list);
869 static const struct rte_pci_id mlx5_pci_id_map[] = {
871 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
872 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
875 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
876 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
879 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
880 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
883 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
884 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
887 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
888 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
891 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
892 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
895 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
896 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
899 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
900 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
907 static struct rte_pci_driver mlx5_driver = {
909 .name = MLX5_DRIVER_NAME
911 .id_table = mlx5_pci_id_map,
912 .probe = mlx5_pci_probe,
913 .drv_flags = RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV,
917 * Driver initialization routine.
919 RTE_INIT(rte_mlx5_pmd_init);
921 rte_mlx5_pmd_init(void)
923 /* Build the static table for ptype conversion. */
924 mlx5_set_ptype_table();
926 * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use
927 * huge pages. Calling ibv_fork_init() during init allows
928 * applications to use fork() safely for purposes other than
929 * using this PMD, which is not supported in forked processes.
931 setenv("RDMAV_HUGEPAGES_SAFE", "1", 1);
932 /* Don't map UAR to WC if BlueFlame is not used.*/
933 setenv("MLX5_SHUT_UP_BF", "1", 1);
935 rte_pci_register(&mlx5_driver);
938 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
939 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
940 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");