drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <stdint.h>
  10 #include <stdlib.h>
  11 #include <errno.h>
  12
  13 #include <rte_malloc.h>
  14 #include <ethdev_driver.h>
  15 #include <ethdev_pci.h>
  16 #include <rte_pci.h>
  17 #include <rte_bus_pci.h>
  18 #include <rte_common.h>
  19 #include <rte_kvargs.h>
  20 #include <rte_rwlock.h>
  21 #include <rte_spinlock.h>
  22 #include <rte_string_fns.h>
  23 #include <rte_alarm.h>
  24 #include <rte_cycles.h>
  25
  26 #include <mlx5_glue.h>
  27 #include <mlx5_devx_cmds.h>
  28 #include <mlx5_common.h>
  29 #include <mlx5_common_os.h>
  30 #include <mlx5_common_mp.h>
  31 #include <mlx5_common_pci.h>
  32 #include <mlx5_malloc.h>
  33
  34 #include "mlx5_defs.h"
  35 #include "mlx5.h"
  36 #include "mlx5_utils.h"
  37 #include "mlx5_rxtx.h"
  38 #include "mlx5_rx.h"
  39 #include "mlx5_tx.h"
  40 #include "mlx5_autoconf.h"
  41 #include "mlx5_mr.h"
  42 #include "mlx5_flow.h"
  43 #include "mlx5_flow_os.h"
  44 #include "rte_pmd_mlx5.h"
  45
  46 /* Device parameter to enable RX completion queue compression. */
  47 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  48
  49 /* Device parameter to enable padding Rx packet to cacheline size. */
  50 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
  51
  52 /* Device parameter to enable Multi-Packet Rx queue. */
  53 #define MLX5_RX_MPRQ_EN "mprq_en"
  54
  55 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
  56 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
  57
  58 /* Device parameter to configure log 2 of the stride size for MPRQ. */
  59 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
  60
  61 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
  62 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
  63
  64 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
  65 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
  66
  67 /* Device parameter to configure inline send. Deprecated, ignored.*/
  68 #define MLX5_TXQ_INLINE "txq_inline"
  69
  70 /* Device parameter to limit packet size to inline with ordinary SEND. */
  71 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
  72
  73 /* Device parameter to configure minimal data size to inline. */
  74 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
  75
  76 /* Device parameter to limit packet size to inline with Enhanced MPW. */
  77 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
  78
  79 /*
  80  * Device parameter to configure the number of TX queues threshold for
  81  * enabling inline send.
  82  */
  83 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  84
  85 /*
  86  * Device parameter to configure the number of TX queues threshold for
  87  * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
  88  */
  89 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
  90
  91 /* Device parameter to enable multi-packet send WQEs. */
  92 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
  93
  94 /*
  95  * Device parameter to force doorbell register mapping
  96  * to non-cahed region eliminating the extra write memory barrier.
  97  */
  98 #define MLX5_TX_DB_NC "tx_db_nc"
  99
 100 /*
 101  * Device parameter to include 2 dsegs in the title WQEBB.
 102  * Deprecated, ignored.
 103  */
 104 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
 105
 106 /*
 107  * Device parameter to limit the size of inlining packet.
 108  * Deprecated, ignored.
 109  */
 110 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
 111
 112 /*
 113  * Device parameter to enable Tx scheduling on timestamps
 114  * and specify the packet pacing granularity in nanoseconds.
 115  */
 116 #define MLX5_TX_PP "tx_pp"
 117
 118 /*
 119  * Device parameter to specify skew in nanoseconds on Tx datapath,
 120  * it represents the time between SQ start WQE processing and
 121  * appearing actual packet data on the wire.
 122  */
 123 #define MLX5_TX_SKEW "tx_skew"
 124
 125 /*
 126  * Device parameter to enable hardware Tx vector.
 127  * Deprecated, ignored (no vectorized Tx routines anymore).
 128  */
 129 #define MLX5_TX_VEC_EN "tx_vec_en"
 130
 131 /* Device parameter to enable hardware Rx vector. */
 132 #define MLX5_RX_VEC_EN "rx_vec_en"
 133
 134 /* Allow L3 VXLAN flow creation. */
 135 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
 136
 137 /* Activate DV E-Switch flow steering. */
 138 #define MLX5_DV_ESW_EN "dv_esw_en"
 139
 140 /* Activate DV flow steering. */
 141 #define MLX5_DV_FLOW_EN "dv_flow_en"
 142
 143 /* Enable extensive flow metadata support. */
 144 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
 145
 146 /* Device parameter to let the user manage the lacp traffic of bonded device */
 147 #define MLX5_LACP_BY_USER "lacp_by_user"
 148
 149 /* Activate Netlink support in VF mode. */
 150 #define MLX5_VF_NL_EN "vf_nl_en"
 151
 152 /* Enable extending memsegs when creating a MR. */
 153 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
 154
 155 /* Select port representors to instantiate. */
 156 #define MLX5_REPRESENTOR "representor"
 157
 158 /* Device parameter to configure the maximum number of dump files per queue. */
 159 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
 160
 161 /* Configure timeout of LRO session (in microseconds). */
 162 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
 163
 164 /*
 165  * Device parameter to configure the total data buffer size for a single
 166  * hairpin queue (logarithm value).
 167  */
 168 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
 169
 170 /* Flow memory reclaim mode. */
 171 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
 172
 173 /* The default memory allocator used in PMD. */
 174 #define MLX5_SYS_MEM_EN "sys_mem_en"
 175 /* Decap will be used or not. */
 176 #define MLX5_DECAP_EN "decap_en"
 177
 178 /* Device parameter to configure allow or prevent duplicate rules pattern. */
 179 #define MLX5_ALLOW_DUPLICATE_PATTERN "allow_duplicate_pattern"
 180
 181 /* Shared memory between primary and secondary processes. */
 182 struct mlx5_shared_data *mlx5_shared_data;
 183
 184 /** Driver-specific log messages type. */
 185 int mlx5_logtype;
 186
 187 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
 188                                                 LIST_HEAD_INITIALIZER();
 189 static pthread_mutex_t mlx5_dev_ctx_list_mutex;
 190 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
 191 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
 192         [MLX5_IPOOL_DECAP_ENCAP] = {
 193                 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
 194                 .trunk_size = 64,
 195                 .grow_trunk = 3,
 196                 .grow_shift = 2,
 197                 .need_lock = 1,
 198                 .release_mem_en = 1,
 199                 .malloc = mlx5_malloc,
 200                 .free = mlx5_free,
 201                 .type = "mlx5_encap_decap_ipool",
 202         },
 203         [MLX5_IPOOL_PUSH_VLAN] = {
 204                 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
 205                 .trunk_size = 64,
 206                 .grow_trunk = 3,
 207                 .grow_shift = 2,
 208                 .need_lock = 1,
 209                 .release_mem_en = 1,
 210                 .malloc = mlx5_malloc,
 211                 .free = mlx5_free,
 212                 .type = "mlx5_push_vlan_ipool",
 213         },
 214         [MLX5_IPOOL_TAG] = {
 215                 .size = sizeof(struct mlx5_flow_dv_tag_resource),
 216                 .trunk_size = 64,
 217                 .grow_trunk = 3,
 218                 .grow_shift = 2,
 219                 .need_lock = 1,
 220                 .release_mem_en = 0,
 221                 .per_core_cache = (1 << 16),
 222                 .malloc = mlx5_malloc,
 223                 .free = mlx5_free,
 224                 .type = "mlx5_tag_ipool",
 225         },
 226         [MLX5_IPOOL_PORT_ID] = {
 227                 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
 228                 .trunk_size = 64,
 229                 .grow_trunk = 3,
 230                 .grow_shift = 2,
 231                 .need_lock = 1,
 232                 .release_mem_en = 1,
 233                 .malloc = mlx5_malloc,
 234                 .free = mlx5_free,
 235                 .type = "mlx5_port_id_ipool",
 236         },
 237         [MLX5_IPOOL_JUMP] = {
 238                 .size = sizeof(struct mlx5_flow_tbl_data_entry),
 239                 .trunk_size = 64,
 240                 .grow_trunk = 3,
 241                 .grow_shift = 2,
 242                 .need_lock = 1,
 243                 .release_mem_en = 1,
 244                 .malloc = mlx5_malloc,
 245                 .free = mlx5_free,
 246                 .type = "mlx5_jump_ipool",
 247         },
 248         [MLX5_IPOOL_SAMPLE] = {
 249                 .size = sizeof(struct mlx5_flow_dv_sample_resource),
 250                 .trunk_size = 64,
 251                 .grow_trunk = 3,
 252                 .grow_shift = 2,
 253                 .need_lock = 1,
 254                 .release_mem_en = 1,
 255                 .malloc = mlx5_malloc,
 256                 .free = mlx5_free,
 257                 .type = "mlx5_sample_ipool",
 258         },
 259         [MLX5_IPOOL_DEST_ARRAY] = {
 260                 .size = sizeof(struct mlx5_flow_dv_dest_array_resource),
 261                 .trunk_size = 64,
 262                 .grow_trunk = 3,
 263                 .grow_shift = 2,
 264                 .need_lock = 1,
 265                 .release_mem_en = 1,
 266                 .malloc = mlx5_malloc,
 267                 .free = mlx5_free,
 268                 .type = "mlx5_dest_array_ipool",
 269         },
 270         [MLX5_IPOOL_TUNNEL_ID] = {
 271                 .size = sizeof(struct mlx5_flow_tunnel),
 272                 .trunk_size = MLX5_MAX_TUNNELS,
 273                 .need_lock = 1,
 274                 .release_mem_en = 1,
 275                 .type = "mlx5_tunnel_offload",
 276         },
 277         [MLX5_IPOOL_TNL_TBL_ID] = {
 278                 .size = 0,
 279                 .need_lock = 1,
 280                 .type = "mlx5_flow_tnl_tbl_ipool",
 281         },
 282 #endif
 283         [MLX5_IPOOL_MTR] = {
 284                 /**
 285                  * The ipool index should grow continually from small to big,
 286                  * for meter idx, so not set grow_trunk to avoid meter index
 287                  * not jump continually.
 288                  */
 289                 .size = sizeof(struct mlx5_legacy_flow_meter),
 290                 .trunk_size = 64,
 291                 .need_lock = 1,
 292                 .release_mem_en = 1,
 293                 .malloc = mlx5_malloc,
 294                 .free = mlx5_free,
 295                 .type = "mlx5_meter_ipool",
 296         },
 297         [MLX5_IPOOL_MCP] = {
 298                 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
 299                 .trunk_size = 64,
 300                 .grow_trunk = 3,
 301                 .grow_shift = 2,
 302                 .need_lock = 1,
 303                 .release_mem_en = 1,
 304                 .malloc = mlx5_malloc,
 305                 .free = mlx5_free,
 306                 .type = "mlx5_mcp_ipool",
 307         },
 308         [MLX5_IPOOL_HRXQ] = {
 309                 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
 310                 .trunk_size = 64,
 311                 .grow_trunk = 3,
 312                 .grow_shift = 2,
 313                 .need_lock = 1,
 314                 .release_mem_en = 1,
 315                 .malloc = mlx5_malloc,
 316                 .free = mlx5_free,
 317                 .type = "mlx5_hrxq_ipool",
 318         },
 319         [MLX5_IPOOL_MLX5_FLOW] = {
 320                 /*
 321                  * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
 322                  * It set in run time according to PCI function configuration.
 323                  */
 324                 .size = 0,
 325                 .trunk_size = 64,
 326                 .grow_trunk = 3,
 327                 .grow_shift = 2,
 328                 .need_lock = 1,
 329                 .release_mem_en = 0,
 330                 .per_core_cache = 1 << 19,
 331                 .malloc = mlx5_malloc,
 332                 .free = mlx5_free,
 333                 .type = "mlx5_flow_handle_ipool",
 334         },
 335         [MLX5_IPOOL_RTE_FLOW] = {
 336                 .size = sizeof(struct rte_flow),
 337                 .trunk_size = 4096,
 338                 .need_lock = 1,
 339                 .release_mem_en = 1,
 340                 .malloc = mlx5_malloc,
 341                 .free = mlx5_free,
 342                 .type = "rte_flow_ipool",
 343         },
 344         [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID] = {
 345                 .size = 0,
 346                 .need_lock = 1,
 347                 .type = "mlx5_flow_rss_id_ipool",
 348         },
 349         [MLX5_IPOOL_RSS_SHARED_ACTIONS] = {
 350                 .size = sizeof(struct mlx5_shared_action_rss),
 351                 .trunk_size = 64,
 352                 .grow_trunk = 3,
 353                 .grow_shift = 2,
 354                 .need_lock = 1,
 355                 .release_mem_en = 1,
 356                 .malloc = mlx5_malloc,
 357                 .free = mlx5_free,
 358                 .type = "mlx5_shared_action_rss",
 359         },
 360         [MLX5_IPOOL_MTR_POLICY] = {
 361                 /**
 362                  * The ipool index should grow continually from small to big,
 363                  * for policy idx, so not set grow_trunk to avoid policy index
 364                  * not jump continually.
 365                  */
 366                 .size = sizeof(struct mlx5_flow_meter_sub_policy),
 367                 .trunk_size = 64,
 368                 .need_lock = 1,
 369                 .release_mem_en = 1,
 370                 .malloc = mlx5_malloc,
 371                 .free = mlx5_free,
 372                 .type = "mlx5_meter_policy_ipool",
 373         },
 374 };
 375
 376
 377 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
 378 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
 379
 380 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 1024
 381
 382 /**
 383  * Decide whether representor ID is a HPF(host PF) port on BF2.
 384  *
 385  * @param dev
 386  *   Pointer to Ethernet device structure.
 387  *
 388  * @return
 389  *   Non-zero if HPF, otherwise 0.
 390  */
 391 bool
 392 mlx5_is_hpf(struct rte_eth_dev *dev)
 393 {
 394         struct mlx5_priv *priv = dev->data->dev_private;
 395         uint16_t repr = MLX5_REPRESENTOR_REPR(priv->representor_id);
 396         int type = MLX5_REPRESENTOR_TYPE(priv->representor_id);
 397
 398         return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_VF &&
 399                MLX5_REPRESENTOR_REPR(-1) == repr;
 400 }
 401
 402 /**
 403  * Initialize the ASO aging management structure.
 404  *
 405  * @param[in] sh
 406  *   Pointer to mlx5_dev_ctx_shared object to free
 407  *
 408  * @return
 409  *   0 on success, a negative errno value otherwise and rte_errno is set.
 410  */
 411 int
 412 mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh)
 413 {
 414         int err;
 415
 416         if (sh->aso_age_mng)
 417                 return 0;
 418         sh->aso_age_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->aso_age_mng),
 419                                       RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 420         if (!sh->aso_age_mng) {
 421                 DRV_LOG(ERR, "aso_age_mng allocation was failed.");
 422                 rte_errno = ENOMEM;
 423                 return -ENOMEM;
 424         }
 425         err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_FLOW_HIT);
 426         if (err) {
 427                 mlx5_free(sh->aso_age_mng);
 428                 return -1;
 429         }
 430         rte_spinlock_init(&sh->aso_age_mng->resize_sl);
 431         rte_spinlock_init(&sh->aso_age_mng->free_sl);
 432         LIST_INIT(&sh->aso_age_mng->free);
 433         return 0;
 434 }
 435
 436 /**
 437  * Close and release all the resources of the ASO aging management structure.
 438  *
 439  * @param[in] sh
 440  *   Pointer to mlx5_dev_ctx_shared object to free.
 441  */
 442 static void
 443 mlx5_flow_aso_age_mng_close(struct mlx5_dev_ctx_shared *sh)
 444 {
 445         int i, j;
 446
 447         mlx5_aso_flow_hit_queue_poll_stop(sh);
 448         mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_FLOW_HIT);
 449         if (sh->aso_age_mng->pools) {
 450                 struct mlx5_aso_age_pool *pool;
 451
 452                 for (i = 0; i < sh->aso_age_mng->next; ++i) {
 453                         pool = sh->aso_age_mng->pools[i];
 454                         claim_zero(mlx5_devx_cmd_destroy
 455                                                 (pool->flow_hit_aso_obj));
 456                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j)
 457                                 if (pool->actions[j].dr_action)
 458                                         claim_zero
 459                                             (mlx5_flow_os_destroy_flow_action
 460                                               (pool->actions[j].dr_action));
 461                         mlx5_free(pool);
 462                 }
 463                 mlx5_free(sh->aso_age_mng->pools);
 464         }
 465         mlx5_free(sh->aso_age_mng);
 466 }
 467
 468 /**
 469  * Initialize the shared aging list information per port.
 470  *
 471  * @param[in] sh
 472  *   Pointer to mlx5_dev_ctx_shared object.
 473  */
 474 static void
 475 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
 476 {
 477         uint32_t i;
 478         struct mlx5_age_info *age_info;
 479
 480         for (i = 0; i < sh->max_port; i++) {
 481                 age_info = &sh->port[i].age_info;
 482                 age_info->flags = 0;
 483                 TAILQ_INIT(&age_info->aged_counters);
 484                 LIST_INIT(&age_info->aged_aso);
 485                 rte_spinlock_init(&age_info->aged_sl);
 486                 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
 487         }
 488 }
 489
 490 /**
 491  * Initialize the counters management structure.
 492  *
 493  * @param[in] sh
 494  *   Pointer to mlx5_dev_ctx_shared object to free
 495  */
 496 static void
 497 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
 498 {
 499         int i;
 500
 501         memset(&sh->cmng, 0, sizeof(sh->cmng));
 502         TAILQ_INIT(&sh->cmng.flow_counters);
 503         sh->cmng.min_id = MLX5_CNT_BATCH_OFFSET;
 504         sh->cmng.max_id = -1;
 505         sh->cmng.last_pool_idx = POOL_IDX_INVALID;
 506         rte_spinlock_init(&sh->cmng.pool_update_sl);
 507         for (i = 0; i < MLX5_COUNTER_TYPE_MAX; i++) {
 508                 TAILQ_INIT(&sh->cmng.counters[i]);
 509                 rte_spinlock_init(&sh->cmng.csl[i]);
 510         }
 511 }
 512
 513 /**
 514  * Destroy all the resources allocated for a counter memory management.
 515  *
 516  * @param[in] mng
 517  *   Pointer to the memory management structure.
 518  */
 519 static void
 520 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
 521 {
 522         uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
 523
 524         LIST_REMOVE(mng, next);
 525         claim_zero(mlx5_devx_cmd_destroy(mng->dm));
 526         claim_zero(mlx5_os_umem_dereg(mng->umem));
 527         mlx5_free(mem);
 528 }
 529
 530 /**
 531  * Close and release all the resources of the counters management.
 532  *
 533  * @param[in] sh
 534  *   Pointer to mlx5_dev_ctx_shared object to free.
 535  */
 536 static void
 537 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
 538 {
 539         struct mlx5_counter_stats_mem_mng *mng;
 540         int i, j;
 541         int retries = 1024;
 542
 543         rte_errno = 0;
 544         while (--retries) {
 545                 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
 546                 if (rte_errno != EINPROGRESS)
 547                         break;
 548                 rte_pause();
 549         }
 550
 551         if (sh->cmng.pools) {
 552                 struct mlx5_flow_counter_pool *pool;
 553                 uint16_t n_valid = sh->cmng.n_valid;
 554                 bool fallback = sh->cmng.counter_fallback;
 555
 556                 for (i = 0; i < n_valid; ++i) {
 557                         pool = sh->cmng.pools[i];
 558                         if (!fallback && pool->min_dcs)
 559                                 claim_zero(mlx5_devx_cmd_destroy
 560                                                                (pool->min_dcs));
 561                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
 562                                 struct mlx5_flow_counter *cnt =
 563                                                 MLX5_POOL_GET_CNT(pool, j);
 564
 565                                 if (cnt->action)
 566                                         claim_zero
 567                                          (mlx5_flow_os_destroy_flow_action
 568                                           (cnt->action));
 569                                 if (fallback && MLX5_POOL_GET_CNT
 570                                     (pool, j)->dcs_when_free)
 571                                         claim_zero(mlx5_devx_cmd_destroy
 572                                                    (cnt->dcs_when_free));
 573                         }
 574                         mlx5_free(pool);
 575                 }
 576                 mlx5_free(sh->cmng.pools);
 577         }
 578         mng = LIST_FIRST(&sh->cmng.mem_mngs);
 579         while (mng) {
 580                 mlx5_flow_destroy_counter_stat_mem_mng(mng);
 581                 mng = LIST_FIRST(&sh->cmng.mem_mngs);
 582         }
 583         memset(&sh->cmng, 0, sizeof(sh->cmng));
 584 }
 585
 586 /**
 587  * Initialize the aso flow meters management structure.
 588  *
 589  * @param[in] sh
 590  *   Pointer to mlx5_dev_ctx_shared object to free
 591  */
 592 int
 593 mlx5_aso_flow_mtrs_mng_init(struct mlx5_dev_ctx_shared *sh)
 594 {
 595         if (!sh->mtrmng) {
 596                 sh->mtrmng = mlx5_malloc(MLX5_MEM_ZERO,
 597                         sizeof(*sh->mtrmng),
 598                         RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 599                 if (!sh->mtrmng) {
 600                         DRV_LOG(ERR,
 601                         "meter management allocation was failed.");
 602                         rte_errno = ENOMEM;
 603                         return -ENOMEM;
 604                 }
 605                 if (sh->meter_aso_en) {
 606                         rte_spinlock_init(&sh->mtrmng->pools_mng.mtrsl);
 607                         LIST_INIT(&sh->mtrmng->pools_mng.meters);
 608                 }
 609                 sh->mtrmng->def_policy_id = MLX5_INVALID_POLICY_ID;
 610         }
 611         return 0;
 612 }
 613
 614 /**
 615  * Close and release all the resources of
 616  * the ASO flow meter management structure.
 617  *
 618  * @param[in] sh
 619  *   Pointer to mlx5_dev_ctx_shared object to free.
 620  */
 621 static void
 622 mlx5_aso_flow_mtrs_mng_close(struct mlx5_dev_ctx_shared *sh)
 623 {
 624         struct mlx5_aso_mtr_pool *mtr_pool;
 625         struct mlx5_flow_mtr_mng *mtrmng = sh->mtrmng;
 626         uint32_t idx;
 627 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
 628         struct mlx5_aso_mtr *aso_mtr;
 629         int i;
 630 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
 631
 632         if (sh->meter_aso_en) {
 633                 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_POLICER);
 634                 idx = mtrmng->pools_mng.n_valid;
 635                 while (idx--) {
 636                         mtr_pool = mtrmng->pools_mng.pools[idx];
 637 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
 638                         for (i = 0; i < MLX5_ASO_MTRS_PER_POOL; i++) {
 639                                 aso_mtr = &mtr_pool->mtrs[i];
 640                                 if (aso_mtr->fm.meter_action)
 641                                         claim_zero
 642                                         (mlx5_glue->destroy_flow_action
 643                                         (aso_mtr->fm.meter_action));
 644                         }
 645 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
 646                         claim_zero(mlx5_devx_cmd_destroy
 647                                                 (mtr_pool->devx_obj));
 648                         mtrmng->pools_mng.n_valid--;
 649                         mlx5_free(mtr_pool);
 650                 }
 651                 mlx5_free(sh->mtrmng->pools_mng.pools);
 652         }
 653         mlx5_free(sh->mtrmng);
 654         sh->mtrmng = NULL;
 655 }
 656
 657 /* Send FLOW_AGED event if needed. */
 658 void
 659 mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh)
 660 {
 661         struct mlx5_age_info *age_info;
 662         uint32_t i;
 663
 664         for (i = 0; i < sh->max_port; i++) {
 665                 age_info = &sh->port[i].age_info;
 666                 if (!MLX5_AGE_GET(age_info, MLX5_AGE_EVENT_NEW))
 667                         continue;
 668                 MLX5_AGE_UNSET(age_info, MLX5_AGE_EVENT_NEW);
 669                 if (MLX5_AGE_GET(age_info, MLX5_AGE_TRIGGER)) {
 670                         MLX5_AGE_UNSET(age_info, MLX5_AGE_TRIGGER);
 671                         rte_eth_dev_callback_process
 672                                 (&rte_eth_devices[sh->port[i].devx_ih_port_id],
 673                                 RTE_ETH_EVENT_FLOW_AGED, NULL);
 674                 }
 675         }
 676 }
 677
 678 /*
 679  * Initialize the ASO connection tracking structure.
 680  *
 681  * @param[in] sh
 682  *   Pointer to mlx5_dev_ctx_shared object.
 683  *
 684  * @return
 685  *   0 on success, a negative errno value otherwise and rte_errno is set.
 686  */
 687 int
 688 mlx5_flow_aso_ct_mng_init(struct mlx5_dev_ctx_shared *sh)
 689 {
 690         int err;
 691
 692         if (sh->ct_mng)
 693                 return 0;
 694         sh->ct_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->ct_mng),
 695                                  RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 696         if (!sh->ct_mng) {
 697                 DRV_LOG(ERR, "ASO CT management allocation failed.");
 698                 rte_errno = ENOMEM;
 699                 return -rte_errno;
 700         }
 701         err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_CONNECTION_TRACKING);
 702         if (err) {
 703                 mlx5_free(sh->ct_mng);
 704                 /* rte_errno should be extracted from the failure. */
 705                 rte_errno = EINVAL;
 706                 return -rte_errno;
 707         }
 708         rte_spinlock_init(&sh->ct_mng->ct_sl);
 709         rte_rwlock_init(&sh->ct_mng->resize_rwl);
 710         LIST_INIT(&sh->ct_mng->free_cts);
 711         return 0;
 712 }
 713
 714 /*
 715  * Close and release all the resources of the
 716  * ASO connection tracking management structure.
 717  *
 718  * @param[in] sh
 719  *   Pointer to mlx5_dev_ctx_shared object to free.
 720  */
 721 static void
 722 mlx5_flow_aso_ct_mng_close(struct mlx5_dev_ctx_shared *sh)
 723 {
 724         struct mlx5_aso_ct_pools_mng *mng = sh->ct_mng;
 725         struct mlx5_aso_ct_pool *ct_pool;
 726         struct mlx5_aso_ct_action *ct;
 727         uint32_t idx;
 728         uint32_t val;
 729         uint32_t cnt;
 730         int i;
 731
 732         mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_CONNECTION_TRACKING);
 733         idx = mng->next;
 734         while (idx--) {
 735                 cnt = 0;
 736                 ct_pool = mng->pools[idx];
 737                 for (i = 0; i < MLX5_ASO_CT_ACTIONS_PER_POOL; i++) {
 738                         ct = &ct_pool->actions[i];
 739                         val = __atomic_fetch_sub(&ct->refcnt, 1,
 740                                                  __ATOMIC_RELAXED);
 741                         MLX5_ASSERT(val == 1);
 742                         if (val > 1)
 743                                 cnt++;
 744 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
 745                         if (ct->dr_action_orig)
 746                                 claim_zero(mlx5_glue->destroy_flow_action
 747                                                         (ct->dr_action_orig));
 748                         if (ct->dr_action_rply)
 749                                 claim_zero(mlx5_glue->destroy_flow_action
 750                                                         (ct->dr_action_rply));
 751 #endif
 752                 }
 753                 claim_zero(mlx5_devx_cmd_destroy(ct_pool->devx_obj));
 754                 if (cnt) {
 755                         DRV_LOG(DEBUG, "%u ASO CT objects are being used in the pool %u",
 756                                 cnt, i);
 757                 }
 758                 mlx5_free(ct_pool);
 759                 /* in case of failure. */
 760                 mng->next--;
 761         }
 762         mlx5_free(mng->pools);
 763         mlx5_free(mng);
 764         /* Management structure must be cleared to 0s during allocation. */
 765         sh->ct_mng = NULL;
 766 }
 767
 768 /**
 769  * Initialize the flow resources' indexed mempool.
 770  *
 771  * @param[in] sh
 772  *   Pointer to mlx5_dev_ctx_shared object.
 773  * @param[in] config
 774  *   Pointer to user dev config.
 775  */
 776 static void
 777 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
 778                        const struct mlx5_dev_config *config)
 779 {
 780         uint8_t i;
 781         struct mlx5_indexed_pool_config cfg;
 782
 783         for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
 784                 cfg = mlx5_ipool_cfg[i];
 785                 switch (i) {
 786                 default:
 787                         break;
 788                 /*
 789                  * Set MLX5_IPOOL_MLX5_FLOW ipool size
 790                  * according to PCI function flow configuration.
 791                  */
 792                 case MLX5_IPOOL_MLX5_FLOW:
 793                         cfg.size = config->dv_flow_en ?
 794                                 sizeof(struct mlx5_flow_handle) :
 795                                 MLX5_FLOW_HANDLE_VERBS_SIZE;
 796                         break;
 797                 }
 798                 if (config->reclaim_mode) {
 799                         cfg.release_mem_en = 1;
 800                         cfg.per_core_cache = 0;
 801                 }
 802                 sh->ipool[i] = mlx5_ipool_create(&cfg);
 803         }
 804 }
 805
 806
 807 /**
 808  * Release the flow resources' indexed mempool.
 809  *
 810  * @param[in] sh
 811  *   Pointer to mlx5_dev_ctx_shared object.
 812  */
 813 static void
 814 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
 815 {
 816         uint8_t i;
 817
 818         for (i = 0; i < MLX5_IPOOL_MAX; ++i)
 819                 mlx5_ipool_destroy(sh->ipool[i]);
 820         for (i = 0; i < MLX5_MAX_MODIFY_NUM; ++i)
 821                 if (sh->mdh_ipools[i])
 822                         mlx5_ipool_destroy(sh->mdh_ipools[i]);
 823 }
 824
 825 /*
 826  * Check if dynamic flex parser for eCPRI already exists.
 827  *
 828  * @param dev
 829  *   Pointer to Ethernet device structure.
 830  *
 831  * @return
 832  *   true on exists, false on not.
 833  */
 834 bool
 835 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
 836 {
 837         struct mlx5_priv *priv = dev->data->dev_private;
 838         struct mlx5_flex_parser_profiles *prf =
 839                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 840
 841         return !!prf->obj;
 842 }
 843
 844 /*
 845  * Allocation of a flex parser for eCPRI. Once created, this parser related
 846  * resources will be held until the device is closed.
 847  *
 848  * @param dev
 849  *   Pointer to Ethernet device structure.
 850  *
 851  * @return
 852  *   0 on success, a negative errno value otherwise and rte_errno is set.
 853  */
 854 int
 855 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
 856 {
 857         struct mlx5_priv *priv = dev->data->dev_private;
 858         struct mlx5_flex_parser_profiles *prf =
 859                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 860         struct mlx5_devx_graph_node_attr node = {
 861                 .modify_field_select = 0,
 862         };
 863         uint32_t ids[8];
 864         int ret;
 865
 866         if (!priv->config.hca_attr.parse_graph_flex_node) {
 867                 DRV_LOG(ERR, "Dynamic flex parser is not supported "
 868                         "for device %s.", priv->dev_data->name);
 869                 return -ENOTSUP;
 870         }
 871         node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED;
 872         /* 8 bytes now: 4B common header + 4B message body header. */
 873         node.header_length_base_value = 0x8;
 874         /* After MAC layer: Ether / VLAN. */
 875         node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC;
 876         /* Type of compared condition should be 0xAEFE in the L2 layer. */
 877         node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI;
 878         /* Sample #0: type in common header. */
 879         node.sample[0].flow_match_sample_en = 1;
 880         /* Fixed offset. */
 881         node.sample[0].flow_match_sample_offset_mode = 0x0;
 882         /* Only the 2nd byte will be used. */
 883         node.sample[0].flow_match_sample_field_base_offset = 0x0;
 884         /* Sample #1: message payload. */
 885         node.sample[1].flow_match_sample_en = 1;
 886         /* Fixed offset. */
 887         node.sample[1].flow_match_sample_offset_mode = 0x0;
 888         /*
 889          * Only the first two bytes will be used right now, and its offset will
 890          * start after the common header that with the length of a DW(u32).
 891          */
 892         node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);
 893         prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->ctx, &node);
 894         if (!prf->obj) {
 895                 DRV_LOG(ERR, "Failed to create flex parser node object.");
 896                 return (rte_errno == 0) ? -ENODEV : -rte_errno;
 897         }
 898         prf->num = 2;
 899         ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num);
 900         if (ret) {
 901                 DRV_LOG(ERR, "Failed to query sample IDs.");
 902                 return (rte_errno == 0) ? -ENODEV : -rte_errno;
 903         }
 904         prf->offset[0] = 0x0;
 905         prf->offset[1] = sizeof(uint32_t);
 906         prf->ids[0] = ids[0];
 907         prf->ids[1] = ids[1];
 908         return 0;
 909 }
 910
 911 /*
 912  * Destroy the flex parser node, including the parser itself, input / output
 913  * arcs and DW samples. Resources could be reused then.
 914  *
 915  * @param dev
 916  *   Pointer to Ethernet device structure.
 917  */
 918 static void
 919 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
 920 {
 921         struct mlx5_priv *priv = dev->data->dev_private;
 922         struct mlx5_flex_parser_profiles *prf =
 923                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 924
 925         if (prf->obj)
 926                 mlx5_devx_cmd_destroy(prf->obj);
 927         prf->obj = NULL;
 928 }
 929
 930 /*
 931  * Allocate Rx and Tx UARs in robust fashion.
 932  * This routine handles the following UAR allocation issues:
 933  *
 934  *  - tries to allocate the UAR with the most appropriate memory
 935  *    mapping type from the ones supported by the host
 936  *
 937  *  - tries to allocate the UAR with non-NULL base address
 938  *    OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as
 939  *    UAR base address if UAR was not the first object in the UAR page.
 940  *    It caused the PMD failure and we should try to get another UAR
 941  *    till we get the first one with non-NULL base address returned.
 942  */
 943 static int
 944 mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh,
 945                      const struct mlx5_dev_config *config)
 946 {
 947         uint32_t uar_mapping, retry;
 948         int err = 0;
 949         void *base_addr;
 950
 951         for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
 952 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
 953                 /* Control the mapping type according to the settings. */
 954                 uar_mapping = (config->dbnc == MLX5_TXDB_NCACHED) ?
 955                               MLX5DV_UAR_ALLOC_TYPE_NC :
 956                               MLX5DV_UAR_ALLOC_TYPE_BF;
 957 #else
 958                 RTE_SET_USED(config);
 959                 /*
 960                  * It seems we have no way to control the memory mapping type
 961                  * for the UAR, the default "Write-Combining" type is supposed.
 962                  * The UAR initialization on queue creation queries the
 963                  * actual mapping type done by Verbs/kernel and setups the
 964                  * PMD datapath accordingly.
 965                  */
 966                 uar_mapping = 0;
 967 #endif
 968                 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->ctx, uar_mapping);
 969 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
 970                 if (!sh->tx_uar &&
 971                     uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
 972                         if (config->dbnc == MLX5_TXDB_CACHED ||
 973                             config->dbnc == MLX5_TXDB_HEURISTIC)
 974                                 DRV_LOG(WARNING, "Devarg tx_db_nc setting "
 975                                                  "is not supported by DevX");
 976                         /*
 977                          * In some environments like virtual machine
 978                          * the Write Combining mapped might be not supported
 979                          * and UAR allocation fails. We try "Non-Cached"
 980                          * mapping for the case. The tx_burst routines take
 981                          * the UAR mapping type into account on UAR setup
 982                          * on queue creation.
 983                          */
 984                         DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (BF)");
 985                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
 986                         sh->tx_uar = mlx5_glue->devx_alloc_uar
 987                                                         (sh->ctx, uar_mapping);
 988                 } else if (!sh->tx_uar &&
 989                            uar_mapping == MLX5DV_UAR_ALLOC_TYPE_NC) {
 990                         if (config->dbnc == MLX5_TXDB_NCACHED)
 991                                 DRV_LOG(WARNING, "Devarg tx_db_nc settings "
 992                                                  "is not supported by DevX");
 993                         /*
 994                          * If Verbs/kernel does not support "Non-Cached"
 995                          * try the "Write-Combining".
 996                          */
 997                         DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (NC)");
 998                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_BF;
 999                         sh->tx_uar = mlx5_glue->devx_alloc_uar
1000                                                         (sh->ctx, uar_mapping);
1001                 }
1002 #endif
1003                 if (!sh->tx_uar) {
1004                         DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (BF/NC)");
1005                         err = ENOMEM;
1006                         goto exit;
1007                 }
1008                 base_addr = mlx5_os_get_devx_uar_base_addr(sh->tx_uar);
1009                 if (base_addr)
1010                         break;
1011                 /*
1012                  * The UARs are allocated by rdma_core within the
1013                  * IB device context, on context closure all UARs
1014                  * will be freed, should be no memory/object leakage.
1015                  */
1016                 DRV_LOG(DEBUG, "Retrying to allocate Tx DevX UAR");
1017                 sh->tx_uar = NULL;
1018         }
1019         /* Check whether we finally succeeded with valid UAR allocation. */
1020         if (!sh->tx_uar) {
1021                 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (NULL base)");
1022                 err = ENOMEM;
1023                 goto exit;
1024         }
1025         for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
1026                 uar_mapping = 0;
1027                 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
1028                                                         (sh->ctx, uar_mapping);
1029 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
1030                 if (!sh->devx_rx_uar &&
1031                     uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
1032                         /*
1033                          * Rx UAR is used to control interrupts only,
1034                          * should be no datapath noticeable impact,
1035                          * can try "Non-Cached" mapping safely.
1036                          */
1037                         DRV_LOG(DEBUG, "Failed to allocate Rx DevX UAR (BF)");
1038                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
1039                         sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
1040                                                         (sh->ctx, uar_mapping);
1041                 }
1042 #endif
1043                 if (!sh->devx_rx_uar) {
1044                         DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (BF/NC)");
1045                         err = ENOMEM;
1046                         goto exit;
1047                 }
1048                 base_addr = mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar);
1049                 if (base_addr)
1050                         break;
1051                 /*
1052                  * The UARs are allocated by rdma_core within the
1053                  * IB device context, on context closure all UARs
1054                  * will be freed, should be no memory/object leakage.
1055                  */
1056                 DRV_LOG(DEBUG, "Retrying to allocate Rx DevX UAR");
1057                 sh->devx_rx_uar = NULL;
1058         }
1059         /* Check whether we finally succeeded with valid UAR allocation. */
1060         if (!sh->devx_rx_uar) {
1061                 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (NULL base)");
1062                 err = ENOMEM;
1063         }
1064 exit:
1065         return err;
1066 }
1067
1068 /**
1069  * Allocate shared device context. If there is multiport device the
1070  * master and representors will share this context, if there is single
1071  * port dedicated device, the context will be used by only given
1072  * port due to unification.
1073  *
1074  * Routine first searches the context for the specified device name,
1075  * if found the shared context assumed and reference counter is incremented.
1076  * If no context found the new one is created and initialized with specified
1077  * device context and parameters.
1078  *
1079  * @param[in] spawn
1080  *   Pointer to the device attributes (name, port, etc).
1081  * @param[in] config
1082  *   Pointer to device configuration structure.
1083  *
1084  * @return
1085  *   Pointer to mlx5_dev_ctx_shared object on success,
1086  *   otherwise NULL and rte_errno is set.
1087  */
1088 struct mlx5_dev_ctx_shared *
1089 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
1090                            const struct mlx5_dev_config *config)
1091 {
1092         struct mlx5_dev_ctx_shared *sh;
1093         int err = 0;
1094         uint32_t i;
1095         struct mlx5_devx_tis_attr tis_attr = { 0 };
1096
1097         MLX5_ASSERT(spawn);
1098         /* Secondary process should not create the shared context. */
1099         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1100         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1101         /* Search for IB context by device name. */
1102         LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
1103                 if (!strcmp(sh->ibdev_name,
1104                         mlx5_os_get_dev_device_name(spawn->phys_dev))) {
1105                         sh->refcnt++;
1106                         goto exit;
1107                 }
1108         }
1109         /* No device found, we have to create new shared context. */
1110         MLX5_ASSERT(spawn->max_port);
1111         sh = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
1112                          sizeof(struct mlx5_dev_ctx_shared) +
1113                          spawn->max_port *
1114                          sizeof(struct mlx5_dev_shared_port),
1115                          RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
1116         if (!sh) {
1117                 DRV_LOG(ERR, "shared context allocation failure");
1118                 rte_errno  = ENOMEM;
1119                 goto exit;
1120         }
1121         if (spawn->bond_info)
1122                 sh->bond = *spawn->bond_info;
1123         err = mlx5_os_open_device(spawn, config, sh);
1124         if (!sh->ctx)
1125                 goto error;
1126         err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
1127         if (err) {
1128                 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
1129                 goto error;
1130         }
1131         sh->refcnt = 1;
1132         sh->max_port = spawn->max_port;
1133         sh->reclaim_mode = config->reclaim_mode;
1134         strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
1135                 sizeof(sh->ibdev_name) - 1);
1136         strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
1137                 sizeof(sh->ibdev_path) - 1);
1138         /*
1139          * Setting port_id to max unallowed value means
1140          * there is no interrupt subhandler installed for
1141          * the given port index i.
1142          */
1143         for (i = 0; i < sh->max_port; i++) {
1144                 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
1145                 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
1146         }
1147         sh->pd = mlx5_os_alloc_pd(sh->ctx);
1148         if (sh->pd == NULL) {
1149                 DRV_LOG(ERR, "PD allocation failure");
1150                 err = ENOMEM;
1151                 goto error;
1152         }
1153         if (sh->devx) {
1154                 err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
1155                 if (err) {
1156                         DRV_LOG(ERR, "Fail to extract pdn from PD");
1157                         goto error;
1158                 }
1159                 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
1160                 if (!sh->td) {
1161                         DRV_LOG(ERR, "TD allocation failure");
1162                         err = ENOMEM;
1163                         goto error;
1164                 }
1165                 tis_attr.transport_domain = sh->td->id;
1166                 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
1167                 if (!sh->tis) {
1168                         DRV_LOG(ERR, "TIS allocation failure");
1169                         err = ENOMEM;
1170                         goto error;
1171                 }
1172                 err = mlx5_alloc_rxtx_uars(sh, config);
1173                 if (err)
1174                         goto error;
1175                 MLX5_ASSERT(sh->tx_uar);
1176                 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->tx_uar));
1177
1178                 MLX5_ASSERT(sh->devx_rx_uar);
1179                 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar));
1180         }
1181 #ifndef RTE_ARCH_64
1182         /* Initialize UAR access locks for 32bit implementations. */
1183         rte_spinlock_init(&sh->uar_lock_cq);
1184         for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
1185                 rte_spinlock_init(&sh->uar_lock[i]);
1186 #endif
1187         /*
1188          * Once the device is added to the list of memory event
1189          * callback, its global MR cache table cannot be expanded
1190          * on the fly because of deadlock. If it overflows, lookup
1191          * should be done by searching MR list linearly, which is slow.
1192          *
1193          * At this point the device is not added to the memory
1194          * event list yet, context is just being created.
1195          */
1196         err = mlx5_mr_btree_init(&sh->share_cache.cache,
1197                                  MLX5_MR_BTREE_CACHE_N * 2,
1198                                  spawn->pci_dev->device.numa_node);
1199         if (err) {
1200                 err = rte_errno;
1201                 goto error;
1202         }
1203         mlx5_os_set_reg_mr_cb(&sh->share_cache.reg_mr_cb,
1204                               &sh->share_cache.dereg_mr_cb);
1205         mlx5_os_dev_shared_handler_install(sh);
1206         sh->cnt_id_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_DWORD);
1207         if (!sh->cnt_id_tbl) {
1208                 err = rte_errno;
1209                 goto error;
1210         }
1211         if (LIST_EMPTY(&mlx5_dev_ctx_list)) {
1212                 err = mlx5_flow_os_init_workspace_once();
1213                 if (err)
1214                         goto error;
1215         }
1216         mlx5_flow_aging_init(sh);
1217         mlx5_flow_counters_mng_init(sh);
1218         mlx5_flow_ipool_create(sh, config);
1219         /* Add device to memory callback list. */
1220         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1221         LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
1222                          sh, mem_event_cb);
1223         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1224         /* Add context to the global device list. */
1225         LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
1226         rte_spinlock_init(&sh->geneve_tlv_opt_sl);
1227 exit:
1228         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1229         return sh;
1230 error:
1231         pthread_mutex_destroy(&sh->txpp.mutex);
1232         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1233         MLX5_ASSERT(sh);
1234         if (sh->cnt_id_tbl)
1235                 mlx5_l3t_destroy(sh->cnt_id_tbl);
1236         if (sh->tis)
1237                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1238         if (sh->td)
1239                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1240         if (sh->devx_rx_uar)
1241                 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1242         if (sh->tx_uar)
1243                 mlx5_glue->devx_free_uar(sh->tx_uar);
1244         if (sh->pd)
1245                 claim_zero(mlx5_os_dealloc_pd(sh->pd));
1246         if (sh->ctx)
1247                 claim_zero(mlx5_glue->close_device(sh->ctx));
1248         mlx5_free(sh);
1249         MLX5_ASSERT(err > 0);
1250         rte_errno = err;
1251         return NULL;
1252 }
1253
1254 /**
1255  * Free shared IB device context. Decrement counter and if zero free
1256  * all allocated resources and close handles.
1257  *
1258  * @param[in] sh
1259  *   Pointer to mlx5_dev_ctx_shared object to free
1260  */
1261 void
1262 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
1263 {
1264         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1265 #ifdef RTE_LIBRTE_MLX5_DEBUG
1266         /* Check the object presence in the list. */
1267         struct mlx5_dev_ctx_shared *lctx;
1268
1269         LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
1270                 if (lctx == sh)
1271                         break;
1272         MLX5_ASSERT(lctx);
1273         if (lctx != sh) {
1274                 DRV_LOG(ERR, "Freeing non-existing shared IB context");
1275                 goto exit;
1276         }
1277 #endif
1278         MLX5_ASSERT(sh);
1279         MLX5_ASSERT(sh->refcnt);
1280         /* Secondary process should not free the shared context. */
1281         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1282         if (--sh->refcnt)
1283                 goto exit;
1284         /* Remove from memory callback device list. */
1285         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1286         LIST_REMOVE(sh, mem_event_cb);
1287         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1288         /* Release created Memory Regions. */
1289         mlx5_mr_release_cache(&sh->share_cache);
1290         /* Remove context from the global device list. */
1291         LIST_REMOVE(sh, next);
1292         /* Release flow workspaces objects on the last device. */
1293         if (LIST_EMPTY(&mlx5_dev_ctx_list))
1294                 mlx5_flow_os_release_workspace();
1295         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1296         /*
1297          *  Ensure there is no async event handler installed.
1298          *  Only primary process handles async device events.
1299          **/
1300         mlx5_flow_counters_mng_close(sh);
1301         if (sh->aso_age_mng) {
1302                 mlx5_flow_aso_age_mng_close(sh);
1303                 sh->aso_age_mng = NULL;
1304         }
1305         if (sh->mtrmng)
1306                 mlx5_aso_flow_mtrs_mng_close(sh);
1307         mlx5_flow_ipool_destroy(sh);
1308         mlx5_os_dev_shared_handler_uninstall(sh);
1309         if (sh->cnt_id_tbl) {
1310                 mlx5_l3t_destroy(sh->cnt_id_tbl);
1311                 sh->cnt_id_tbl = NULL;
1312         }
1313         if (sh->tx_uar) {
1314                 mlx5_glue->devx_free_uar(sh->tx_uar);
1315                 sh->tx_uar = NULL;
1316         }
1317         if (sh->pd)
1318                 claim_zero(mlx5_os_dealloc_pd(sh->pd));
1319         if (sh->tis)
1320                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1321         if (sh->td)
1322                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1323         if (sh->devx_rx_uar)
1324                 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1325         if (sh->ctx)
1326                 claim_zero(mlx5_glue->close_device(sh->ctx));
1327         MLX5_ASSERT(sh->geneve_tlv_option_resource == NULL);
1328         pthread_mutex_destroy(&sh->txpp.mutex);
1329         mlx5_free(sh);
1330         return;
1331 exit:
1332         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1333 }
1334
1335 /**
1336  * Destroy table hash list.
1337  *
1338  * @param[in] priv
1339  *   Pointer to the private device data structure.
1340  */
1341 void
1342 mlx5_free_table_hash_list(struct mlx5_priv *priv)
1343 {
1344         struct mlx5_dev_ctx_shared *sh = priv->sh;
1345
1346         if (!sh->flow_tbls)
1347                 return;
1348         mlx5_hlist_destroy(sh->flow_tbls);
1349 }
1350
1351 /**
1352  * Initialize flow table hash list and create the root tables entry
1353  * for each domain.
1354  *
1355  * @param[in] priv
1356  *   Pointer to the private device data structure.
1357  *
1358  * @return
1359  *   Zero on success, positive error code otherwise.
1360  */
1361 int
1362 mlx5_alloc_table_hash_list(struct mlx5_priv *priv __rte_unused)
1363 {
1364         int err = 0;
1365         /* Tables are only used in DV and DR modes. */
1366 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
1367         struct mlx5_dev_ctx_shared *sh = priv->sh;
1368         char s[MLX5_NAME_SIZE];
1369
1370         MLX5_ASSERT(sh);
1371         snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1372         sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE,
1373                                           false, true, sh,
1374                                           flow_dv_tbl_create_cb,
1375                                           flow_dv_tbl_match_cb,
1376                                           flow_dv_tbl_remove_cb,
1377                                           flow_dv_tbl_clone_cb,
1378                                           flow_dv_tbl_clone_free_cb);
1379         if (!sh->flow_tbls) {
1380                 DRV_LOG(ERR, "flow tables with hash creation failed.");
1381                 err = ENOMEM;
1382                 return err;
1383         }
1384 #ifndef HAVE_MLX5DV_DR
1385         struct rte_flow_error error;
1386         struct rte_eth_dev *dev = &rte_eth_devices[priv->dev_data->port_id];
1387
1388         /*
1389          * In case we have not DR support, the zero tables should be created
1390          * because DV expect to see them even if they cannot be created by
1391          * RDMA-CORE.
1392          */
1393         if (!flow_dv_tbl_resource_get(dev, 0, 0, 0, 0,
1394                 NULL, 0, 1, 0, &error) ||
1395             !flow_dv_tbl_resource_get(dev, 0, 1, 0, 0,
1396                 NULL, 0, 1, 0, &error) ||
1397             !flow_dv_tbl_resource_get(dev, 0, 0, 1, 0,
1398                 NULL, 0, 1, 0, &error)) {
1399                 err = ENOMEM;
1400                 goto error;
1401         }
1402         return err;
1403 error:
1404         mlx5_free_table_hash_list(priv);
1405 #endif /* HAVE_MLX5DV_DR */
1406 #endif
1407         return err;
1408 }
1409
1410 /**
1411  * Retrieve integer value from environment variable.
1412  *
1413  * @param[in] name
1414  *   Environment variable name.
1415  *
1416  * @return
1417  *   Integer value, 0 if the variable is not set.
1418  */
1419 int
1420 mlx5_getenv_int(const char *name)
1421 {
1422         const char *val = getenv(name);
1423
1424         if (val == NULL)
1425                 return 0;
1426         return atoi(val);
1427 }
1428
1429 /**
1430  * DPDK callback to add udp tunnel port
1431  *
1432  * @param[in] dev
1433  *   A pointer to eth_dev
1434  * @param[in] udp_tunnel
1435  *   A pointer to udp tunnel
1436  *
1437  * @return
1438  *   0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1439  */
1440 int
1441 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1442                          struct rte_eth_udp_tunnel *udp_tunnel)
1443 {
1444         MLX5_ASSERT(udp_tunnel != NULL);
1445         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1446             udp_tunnel->udp_port == 4789)
1447                 return 0;
1448         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1449             udp_tunnel->udp_port == 4790)
1450                 return 0;
1451         return -ENOTSUP;
1452 }
1453
1454 /**
1455  * Initialize process private data structure.
1456  *
1457  * @param dev
1458  *   Pointer to Ethernet device structure.
1459  *
1460  * @return
1461  *   0 on success, a negative errno value otherwise and rte_errno is set.
1462  */
1463 int
1464 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1465 {
1466         struct mlx5_priv *priv = dev->data->dev_private;
1467         struct mlx5_proc_priv *ppriv;
1468         size_t ppriv_size;
1469
1470         mlx5_proc_priv_uninit(dev);
1471         /*
1472          * UAR register table follows the process private structure. BlueFlame
1473          * registers for Tx queues are stored in the table.
1474          */
1475         ppriv_size =
1476                 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1477         ppriv = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, ppriv_size,
1478                             RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1479         if (!ppriv) {
1480                 rte_errno = ENOMEM;
1481                 return -rte_errno;
1482         }
1483         ppriv->uar_table_sz = priv->txqs_n;
1484         dev->process_private = ppriv;
1485         return 0;
1486 }
1487
1488 /**
1489  * Un-initialize process private data structure.
1490  *
1491  * @param dev
1492  *   Pointer to Ethernet device structure.
1493  */
1494 void
1495 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1496 {
1497         if (!dev->process_private)
1498                 return;
1499         mlx5_free(dev->process_private);
1500         dev->process_private = NULL;
1501 }
1502
1503 /**
1504  * DPDK callback to close the device.
1505  *
1506  * Destroy all queues and objects, free memory.
1507  *
1508  * @param dev
1509  *   Pointer to Ethernet device structure.
1510  */
1511 int
1512 mlx5_dev_close(struct rte_eth_dev *dev)
1513 {
1514         struct mlx5_priv *priv = dev->data->dev_private;
1515         unsigned int i;
1516         int ret;
1517
1518         if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1519                 /* Check if process_private released. */
1520                 if (!dev->process_private)
1521                         return 0;
1522                 mlx5_tx_uar_uninit_secondary(dev);
1523                 mlx5_proc_priv_uninit(dev);
1524                 rte_eth_dev_release_port(dev);
1525                 return 0;
1526         }
1527         if (!priv->sh)
1528                 return 0;
1529         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1530                 dev->data->port_id,
1531                 ((priv->sh->ctx != NULL) ?
1532                 mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
1533         /*
1534          * If default mreg copy action is removed at the stop stage,
1535          * the search will return none and nothing will be done anymore.
1536          */
1537         mlx5_flow_stop_default(dev);
1538         mlx5_traffic_disable(dev);
1539         /*
1540          * If all the flows are already flushed in the device stop stage,
1541          * then this will return directly without any action.
1542          */
1543         mlx5_flow_list_flush(dev, MLX5_FLOW_TYPE_GEN, true);
1544         mlx5_action_handle_flush(dev);
1545         mlx5_flow_meter_flush(dev, NULL);
1546         /* Prevent crashes when queues are still in use. */
1547         dev->rx_pkt_burst = removed_rx_burst;
1548         dev->tx_pkt_burst = removed_tx_burst;
1549         rte_wmb();
1550         /* Disable datapath on secondary process. */
1551         mlx5_mp_os_req_stop_rxtx(dev);
1552         /* Free the eCPRI flex parser resource. */
1553         mlx5_flex_parser_ecpri_release(dev);
1554         if (priv->rxqs != NULL) {
1555                 /* XXX race condition if mlx5_rx_burst() is still running. */
1556                 rte_delay_us_sleep(1000);
1557                 for (i = 0; (i != priv->rxqs_n); ++i)
1558                         mlx5_rxq_release(dev, i);
1559                 priv->rxqs_n = 0;
1560                 priv->rxqs = NULL;
1561         }
1562         if (priv->txqs != NULL) {
1563                 /* XXX race condition if mlx5_tx_burst() is still running. */
1564                 rte_delay_us_sleep(1000);
1565                 for (i = 0; (i != priv->txqs_n); ++i)
1566                         mlx5_txq_release(dev, i);
1567                 priv->txqs_n = 0;
1568                 priv->txqs = NULL;
1569         }
1570         mlx5_proc_priv_uninit(dev);
1571         if (priv->q_counters) {
1572                 mlx5_devx_cmd_destroy(priv->q_counters);
1573                 priv->q_counters = NULL;
1574         }
1575         if (priv->drop_queue.hrxq)
1576                 mlx5_drop_action_destroy(dev);
1577         if (priv->mreg_cp_tbl)
1578                 mlx5_hlist_destroy(priv->mreg_cp_tbl);
1579         mlx5_mprq_free_mp(dev);
1580         if (priv->sh->ct_mng)
1581                 mlx5_flow_aso_ct_mng_close(priv->sh);
1582         mlx5_os_free_shared_dr(priv);
1583         if (priv->rss_conf.rss_key != NULL)
1584                 mlx5_free(priv->rss_conf.rss_key);
1585         if (priv->reta_idx != NULL)
1586                 mlx5_free(priv->reta_idx);
1587         if (priv->config.vf)
1588                 mlx5_os_mac_addr_flush(dev);
1589         if (priv->nl_socket_route >= 0)
1590                 close(priv->nl_socket_route);
1591         if (priv->nl_socket_rdma >= 0)
1592                 close(priv->nl_socket_rdma);
1593         if (priv->vmwa_context)
1594                 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1595         ret = mlx5_hrxq_verify(dev);
1596         if (ret)
1597                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1598                         dev->data->port_id);
1599         ret = mlx5_ind_table_obj_verify(dev);
1600         if (ret)
1601                 DRV_LOG(WARNING, "port %u some indirection table still remain",
1602                         dev->data->port_id);
1603         ret = mlx5_rxq_obj_verify(dev);
1604         if (ret)
1605                 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1606                         dev->data->port_id);
1607         ret = mlx5_rxq_verify(dev);
1608         if (ret)
1609                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1610                         dev->data->port_id);
1611         ret = mlx5_txq_obj_verify(dev);
1612         if (ret)
1613                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1614                         dev->data->port_id);
1615         ret = mlx5_txq_verify(dev);
1616         if (ret)
1617                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1618                         dev->data->port_id);
1619         ret = mlx5_flow_verify(dev);
1620         if (ret)
1621                 DRV_LOG(WARNING, "port %u some flows still remain",
1622                         dev->data->port_id);
1623         if (priv->hrxqs)
1624                 mlx5_list_destroy(priv->hrxqs);
1625         /*
1626          * Free the shared context in last turn, because the cleanup
1627          * routines above may use some shared fields, like
1628          * mlx5_os_mac_addr_flush() uses ibdev_path for retrieveing
1629          * ifindex if Netlink fails.
1630          */
1631         mlx5_free_shared_dev_ctx(priv->sh);
1632         if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1633                 unsigned int c = 0;
1634                 uint16_t port_id;
1635
1636                 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1637                         struct mlx5_priv *opriv =
1638                                 rte_eth_devices[port_id].data->dev_private;
1639
1640                         if (!opriv ||
1641                             opriv->domain_id != priv->domain_id ||
1642                             &rte_eth_devices[port_id] == dev)
1643                                 continue;
1644                         ++c;
1645                         break;
1646                 }
1647                 if (!c)
1648                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1649         }
1650         memset(priv, 0, sizeof(*priv));
1651         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1652         /*
1653          * Reset mac_addrs to NULL such that it is not freed as part of
1654          * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1655          * it is freed when dev_private is freed.
1656          */
1657         dev->data->mac_addrs = NULL;
1658         return 0;
1659 }
1660
1661 const struct eth_dev_ops mlx5_dev_ops = {
1662         .dev_configure = mlx5_dev_configure,
1663         .dev_start = mlx5_dev_start,
1664         .dev_stop = mlx5_dev_stop,
1665         .dev_set_link_down = mlx5_set_link_down,
1666         .dev_set_link_up = mlx5_set_link_up,
1667         .dev_close = mlx5_dev_close,
1668         .promiscuous_enable = mlx5_promiscuous_enable,
1669         .promiscuous_disable = mlx5_promiscuous_disable,
1670         .allmulticast_enable = mlx5_allmulticast_enable,
1671         .allmulticast_disable = mlx5_allmulticast_disable,
1672         .link_update = mlx5_link_update,
1673         .stats_get = mlx5_stats_get,
1674         .stats_reset = mlx5_stats_reset,
1675         .xstats_get = mlx5_xstats_get,
1676         .xstats_reset = mlx5_xstats_reset,
1677         .xstats_get_names = mlx5_xstats_get_names,
1678         .fw_version_get = mlx5_fw_version_get,
1679         .dev_infos_get = mlx5_dev_infos_get,
1680         .representor_info_get = mlx5_representor_info_get,
1681         .read_clock = mlx5_txpp_read_clock,
1682         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1683         .vlan_filter_set = mlx5_vlan_filter_set,
1684         .rx_queue_setup = mlx5_rx_queue_setup,
1685         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1686         .tx_queue_setup = mlx5_tx_queue_setup,
1687         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1688         .rx_queue_release = mlx5_rx_queue_release,
1689         .tx_queue_release = mlx5_tx_queue_release,
1690         .rx_queue_start = mlx5_rx_queue_start,
1691         .rx_queue_stop = mlx5_rx_queue_stop,
1692         .tx_queue_start = mlx5_tx_queue_start,
1693         .tx_queue_stop = mlx5_tx_queue_stop,
1694         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1695         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1696         .mac_addr_remove = mlx5_mac_addr_remove,
1697         .mac_addr_add = mlx5_mac_addr_add,
1698         .mac_addr_set = mlx5_mac_addr_set,
1699         .set_mc_addr_list = mlx5_set_mc_addr_list,
1700         .mtu_set = mlx5_dev_set_mtu,
1701         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1702         .vlan_offload_set = mlx5_vlan_offload_set,
1703         .reta_update = mlx5_dev_rss_reta_update,
1704         .reta_query = mlx5_dev_rss_reta_query,
1705         .rss_hash_update = mlx5_rss_hash_update,
1706         .rss_hash_conf_get = mlx5_rss_hash_conf_get,
1707         .flow_ops_get = mlx5_flow_ops_get,
1708         .rxq_info_get = mlx5_rxq_info_get,
1709         .txq_info_get = mlx5_txq_info_get,
1710         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1711         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1712         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1713         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1714         .is_removed = mlx5_is_removed,
1715         .udp_tunnel_port_add  = mlx5_udp_tunnel_port_add,
1716         .get_module_info = mlx5_get_module_info,
1717         .get_module_eeprom = mlx5_get_module_eeprom,
1718         .hairpin_cap_get = mlx5_hairpin_cap_get,
1719         .mtr_ops_get = mlx5_flow_meter_ops_get,
1720         .hairpin_bind = mlx5_hairpin_bind,
1721         .hairpin_unbind = mlx5_hairpin_unbind,
1722         .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1723         .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1724         .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1725         .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1726         .get_monitor_addr = mlx5_get_monitor_addr,
1727 };
1728
1729 /* Available operations from secondary process. */
1730 const struct eth_dev_ops mlx5_dev_sec_ops = {
1731         .stats_get = mlx5_stats_get,
1732         .stats_reset = mlx5_stats_reset,
1733         .xstats_get = mlx5_xstats_get,
1734         .xstats_reset = mlx5_xstats_reset,
1735         .xstats_get_names = mlx5_xstats_get_names,
1736         .fw_version_get = mlx5_fw_version_get,
1737         .dev_infos_get = mlx5_dev_infos_get,
1738         .read_clock = mlx5_txpp_read_clock,
1739         .rx_queue_start = mlx5_rx_queue_start,
1740         .rx_queue_stop = mlx5_rx_queue_stop,
1741         .tx_queue_start = mlx5_tx_queue_start,
1742         .tx_queue_stop = mlx5_tx_queue_stop,
1743         .rxq_info_get = mlx5_rxq_info_get,
1744         .txq_info_get = mlx5_txq_info_get,
1745         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1746         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1747         .get_module_info = mlx5_get_module_info,
1748         .get_module_eeprom = mlx5_get_module_eeprom,
1749 };
1750
1751 /* Available operations in flow isolated mode. */
1752 const struct eth_dev_ops mlx5_dev_ops_isolate = {
1753         .dev_configure = mlx5_dev_configure,
1754         .dev_start = mlx5_dev_start,
1755         .dev_stop = mlx5_dev_stop,
1756         .dev_set_link_down = mlx5_set_link_down,
1757         .dev_set_link_up = mlx5_set_link_up,
1758         .dev_close = mlx5_dev_close,
1759         .promiscuous_enable = mlx5_promiscuous_enable,
1760         .promiscuous_disable = mlx5_promiscuous_disable,
1761         .allmulticast_enable = mlx5_allmulticast_enable,
1762         .allmulticast_disable = mlx5_allmulticast_disable,
1763         .link_update = mlx5_link_update,
1764         .stats_get = mlx5_stats_get,
1765         .stats_reset = mlx5_stats_reset,
1766         .xstats_get = mlx5_xstats_get,
1767         .xstats_reset = mlx5_xstats_reset,
1768         .xstats_get_names = mlx5_xstats_get_names,
1769         .fw_version_get = mlx5_fw_version_get,
1770         .dev_infos_get = mlx5_dev_infos_get,
1771         .read_clock = mlx5_txpp_read_clock,
1772         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1773         .vlan_filter_set = mlx5_vlan_filter_set,
1774         .rx_queue_setup = mlx5_rx_queue_setup,
1775         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1776         .tx_queue_setup = mlx5_tx_queue_setup,
1777         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1778         .rx_queue_release = mlx5_rx_queue_release,
1779         .tx_queue_release = mlx5_tx_queue_release,
1780         .rx_queue_start = mlx5_rx_queue_start,
1781         .rx_queue_stop = mlx5_rx_queue_stop,
1782         .tx_queue_start = mlx5_tx_queue_start,
1783         .tx_queue_stop = mlx5_tx_queue_stop,
1784         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1785         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1786         .mac_addr_remove = mlx5_mac_addr_remove,
1787         .mac_addr_add = mlx5_mac_addr_add,
1788         .mac_addr_set = mlx5_mac_addr_set,
1789         .set_mc_addr_list = mlx5_set_mc_addr_list,
1790         .mtu_set = mlx5_dev_set_mtu,
1791         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1792         .vlan_offload_set = mlx5_vlan_offload_set,
1793         .flow_ops_get = mlx5_flow_ops_get,
1794         .rxq_info_get = mlx5_rxq_info_get,
1795         .txq_info_get = mlx5_txq_info_get,
1796         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1797         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1798         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1799         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1800         .is_removed = mlx5_is_removed,
1801         .get_module_info = mlx5_get_module_info,
1802         .get_module_eeprom = mlx5_get_module_eeprom,
1803         .hairpin_cap_get = mlx5_hairpin_cap_get,
1804         .mtr_ops_get = mlx5_flow_meter_ops_get,
1805         .hairpin_bind = mlx5_hairpin_bind,
1806         .hairpin_unbind = mlx5_hairpin_unbind,
1807         .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1808         .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1809         .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1810         .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1811         .get_monitor_addr = mlx5_get_monitor_addr,
1812 };
1813
1814 /**
1815  * Verify and store value for device argument.
1816  *
1817  * @param[in] key
1818  *   Key argument to verify.
1819  * @param[in] val
1820  *   Value associated with key.
1821  * @param opaque
1822  *   User data.
1823  *
1824  * @return
1825  *   0 on success, a negative errno value otherwise and rte_errno is set.
1826  */
1827 static int
1828 mlx5_args_check(const char *key, const char *val, void *opaque)
1829 {
1830         struct mlx5_dev_config *config = opaque;
1831         unsigned long mod;
1832         signed long tmp;
1833
1834         /* No-op, port representors are processed in mlx5_dev_spawn(). */
1835         if (!strcmp(MLX5_REPRESENTOR, key))
1836                 return 0;
1837         errno = 0;
1838         tmp = strtol(val, NULL, 0);
1839         if (errno) {
1840                 rte_errno = errno;
1841                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1842                 return -rte_errno;
1843         }
1844         if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
1845                 /* Negative values are acceptable for some keys only. */
1846                 rte_errno = EINVAL;
1847                 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
1848                 return -rte_errno;
1849         }
1850         mod = tmp >= 0 ? tmp : -tmp;
1851         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1852                 if (tmp > MLX5_CQE_RESP_FORMAT_L34H_STRIDX) {
1853                         DRV_LOG(ERR, "invalid CQE compression "
1854                                      "format parameter");
1855                         rte_errno = EINVAL;
1856                         return -rte_errno;
1857                 }
1858                 config->cqe_comp = !!tmp;
1859                 config->cqe_comp_fmt = tmp;
1860         } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1861                 config->hw_padding = !!tmp;
1862         } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1863                 config->mprq.enabled = !!tmp;
1864         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1865                 config->mprq.stride_num_n = tmp;
1866         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1867                 config->mprq.stride_size_n = tmp;
1868         } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1869                 config->mprq.max_memcpy_len = tmp;
1870         } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1871                 config->mprq.min_rxqs_num = tmp;
1872         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1873                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1874                                  " converted to txq_inline_max", key);
1875                 config->txq_inline_max = tmp;
1876         } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1877                 config->txq_inline_max = tmp;
1878         } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1879                 config->txq_inline_min = tmp;
1880         } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1881                 config->txq_inline_mpw = tmp;
1882         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1883                 config->txqs_inline = tmp;
1884         } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1885                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1886         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1887                 config->mps = !!tmp;
1888         } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1889                 if (tmp != MLX5_TXDB_CACHED &&
1890                     tmp != MLX5_TXDB_NCACHED &&
1891                     tmp != MLX5_TXDB_HEURISTIC) {
1892                         DRV_LOG(ERR, "invalid Tx doorbell "
1893                                      "mapping parameter");
1894                         rte_errno = EINVAL;
1895                         return -rte_errno;
1896                 }
1897                 config->dbnc = tmp;
1898         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1899                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1900         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1901                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1902                                  " converted to txq_inline_mpw", key);
1903                 config->txq_inline_mpw = tmp;
1904         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1905                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1906         } else if (strcmp(MLX5_TX_PP, key) == 0) {
1907                 if (!mod) {
1908                         DRV_LOG(ERR, "Zero Tx packet pacing parameter");
1909                         rte_errno = EINVAL;
1910                         return -rte_errno;
1911                 }
1912                 config->tx_pp = tmp;
1913         } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
1914                 config->tx_skew = tmp;
1915         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1916                 config->rx_vec_en = !!tmp;
1917         } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1918                 config->l3_vxlan_en = !!tmp;
1919         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1920                 config->vf_nl_en = !!tmp;
1921         } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1922                 config->dv_esw_en = !!tmp;
1923         } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1924                 config->dv_flow_en = !!tmp;
1925         } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1926                 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1927                     tmp != MLX5_XMETA_MODE_META16 &&
1928                     tmp != MLX5_XMETA_MODE_META32 &&
1929                     tmp != MLX5_XMETA_MODE_MISS_INFO) {
1930                         DRV_LOG(ERR, "invalid extensive "
1931                                      "metadata parameter");
1932                         rte_errno = EINVAL;
1933                         return -rte_errno;
1934                 }
1935                 if (tmp != MLX5_XMETA_MODE_MISS_INFO)
1936                         config->dv_xmeta_en = tmp;
1937                 else
1938                         config->dv_miss_info = 1;
1939         } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
1940                 config->lacp_by_user = !!tmp;
1941         } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1942                 config->mr_ext_memseg_en = !!tmp;
1943         } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1944                 config->max_dump_files_num = tmp;
1945         } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1946                 config->lro.timeout = tmp;
1947         } else if (strcmp(RTE_DEVARGS_KEY_CLASS, key) == 0) {
1948                 DRV_LOG(DEBUG, "class argument is %s.", val);
1949         } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1950                 config->log_hp_size = tmp;
1951         } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1952                 if (tmp != MLX5_RCM_NONE &&
1953                     tmp != MLX5_RCM_LIGHT &&
1954                     tmp != MLX5_RCM_AGGR) {
1955                         DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1956                         rte_errno = EINVAL;
1957                         return -rte_errno;
1958                 }
1959                 config->reclaim_mode = tmp;
1960         } else if (strcmp(MLX5_SYS_MEM_EN, key) == 0) {
1961                 config->sys_mem_en = !!tmp;
1962         } else if (strcmp(MLX5_DECAP_EN, key) == 0) {
1963                 config->decap_en = !!tmp;
1964         } else if (strcmp(MLX5_ALLOW_DUPLICATE_PATTERN, key) == 0) {
1965                 config->allow_duplicate_pattern = !!tmp;
1966         } else {
1967                 DRV_LOG(WARNING, "%s: unknown parameter", key);
1968                 rte_errno = EINVAL;
1969                 return -rte_errno;
1970         }
1971         return 0;
1972 }
1973
1974 /**
1975  * Parse device parameters.
1976  *
1977  * @param config
1978  *   Pointer to device configuration structure.
1979  * @param devargs
1980  *   Device arguments structure.
1981  *
1982  * @return
1983  *   0 on success, a negative errno value otherwise and rte_errno is set.
1984  */
1985 int
1986 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1987 {
1988         const char **params = (const char *[]){
1989                 MLX5_RXQ_CQE_COMP_EN,
1990                 MLX5_RXQ_PKT_PAD_EN,
1991                 MLX5_RX_MPRQ_EN,
1992                 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1993                 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1994                 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1995                 MLX5_RXQS_MIN_MPRQ,
1996                 MLX5_TXQ_INLINE,
1997                 MLX5_TXQ_INLINE_MIN,
1998                 MLX5_TXQ_INLINE_MAX,
1999                 MLX5_TXQ_INLINE_MPW,
2000                 MLX5_TXQS_MIN_INLINE,
2001                 MLX5_TXQS_MAX_VEC,
2002                 MLX5_TXQ_MPW_EN,
2003                 MLX5_TXQ_MPW_HDR_DSEG_EN,
2004                 MLX5_TXQ_MAX_INLINE_LEN,
2005                 MLX5_TX_DB_NC,
2006                 MLX5_TX_PP,
2007                 MLX5_TX_SKEW,
2008                 MLX5_TX_VEC_EN,
2009                 MLX5_RX_VEC_EN,
2010                 MLX5_L3_VXLAN_EN,
2011                 MLX5_VF_NL_EN,
2012                 MLX5_DV_ESW_EN,
2013                 MLX5_DV_FLOW_EN,
2014                 MLX5_DV_XMETA_EN,
2015                 MLX5_LACP_BY_USER,
2016                 MLX5_MR_EXT_MEMSEG_EN,
2017                 MLX5_REPRESENTOR,
2018                 MLX5_MAX_DUMP_FILES_NUM,
2019                 MLX5_LRO_TIMEOUT_USEC,
2020                 RTE_DEVARGS_KEY_CLASS,
2021                 MLX5_HP_BUF_SIZE,
2022                 MLX5_RECLAIM_MEM,
2023                 MLX5_SYS_MEM_EN,
2024                 MLX5_DECAP_EN,
2025                 MLX5_ALLOW_DUPLICATE_PATTERN,
2026                 NULL,
2027         };
2028         struct rte_kvargs *kvlist;
2029         int ret = 0;
2030         int i;
2031
2032         if (devargs == NULL)
2033                 return 0;
2034         /* Following UGLY cast is done to pass checkpatch. */
2035         kvlist = rte_kvargs_parse(devargs->args, params);
2036         if (kvlist == NULL) {
2037                 rte_errno = EINVAL;
2038                 return -rte_errno;
2039         }
2040         /* Process parameters. */
2041         for (i = 0; (params[i] != NULL); ++i) {
2042                 if (rte_kvargs_count(kvlist, params[i])) {
2043                         ret = rte_kvargs_process(kvlist, params[i],
2044                                                  mlx5_args_check, config);
2045                         if (ret) {
2046                                 rte_errno = EINVAL;
2047                                 rte_kvargs_free(kvlist);
2048                                 return -rte_errno;
2049                         }
2050                 }
2051         }
2052         rte_kvargs_free(kvlist);
2053         return 0;
2054 }
2055
2056 /**
2057  * Configures the minimal amount of data to inline into WQE
2058  * while sending packets.
2059  *
2060  * - the txq_inline_min has the maximal priority, if this
2061  *   key is specified in devargs
2062  * - if DevX is enabled the inline mode is queried from the
2063  *   device (HCA attributes and NIC vport context if needed).
2064  * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
2065  *   and none (0 bytes) for other NICs
2066  *
2067  * @param spawn
2068  *   Verbs device parameters (name, port, switch_info) to spawn.
2069  * @param config
2070  *   Device configuration parameters.
2071  */
2072 void
2073 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
2074                     struct mlx5_dev_config *config)
2075 {
2076         if (config->txq_inline_min != MLX5_ARG_UNSET) {
2077                 /* Application defines size of inlined data explicitly. */
2078                 switch (spawn->pci_dev->id.device_id) {
2079                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2080                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2081                         if (config->txq_inline_min <
2082                                        (int)MLX5_INLINE_HSIZE_L2) {
2083                                 DRV_LOG(DEBUG,
2084                                         "txq_inline_mix aligned to minimal"
2085                                         " ConnectX-4 required value %d",
2086                                         (int)MLX5_INLINE_HSIZE_L2);
2087                                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2088                         }
2089                         break;
2090                 }
2091                 goto exit;
2092         }
2093         if (config->hca_attr.eth_net_offloads) {
2094                 /* We have DevX enabled, inline mode queried successfully. */
2095                 switch (config->hca_attr.wqe_inline_mode) {
2096                 case MLX5_CAP_INLINE_MODE_L2:
2097                         /* outer L2 header must be inlined. */
2098                         config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2099                         goto exit;
2100                 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
2101                         /* No inline data are required by NIC. */
2102                         config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2103                         config->hw_vlan_insert =
2104                                 config->hca_attr.wqe_vlan_insert;
2105                         DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
2106                         goto exit;
2107                 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
2108                         /* inline mode is defined by NIC vport context. */
2109                         if (!config->hca_attr.eth_virt)
2110                                 break;
2111                         switch (config->hca_attr.vport_inline_mode) {
2112                         case MLX5_INLINE_MODE_NONE:
2113                                 config->txq_inline_min =
2114                                         MLX5_INLINE_HSIZE_NONE;
2115                                 goto exit;
2116                         case MLX5_INLINE_MODE_L2:
2117                                 config->txq_inline_min =
2118                                         MLX5_INLINE_HSIZE_L2;
2119                                 goto exit;
2120                         case MLX5_INLINE_MODE_IP:
2121                                 config->txq_inline_min =
2122                                         MLX5_INLINE_HSIZE_L3;
2123                                 goto exit;
2124                         case MLX5_INLINE_MODE_TCP_UDP:
2125                                 config->txq_inline_min =
2126                                         MLX5_INLINE_HSIZE_L4;
2127                                 goto exit;
2128                         case MLX5_INLINE_MODE_INNER_L2:
2129                                 config->txq_inline_min =
2130                                         MLX5_INLINE_HSIZE_INNER_L2;
2131                                 goto exit;
2132                         case MLX5_INLINE_MODE_INNER_IP:
2133                                 config->txq_inline_min =
2134                                         MLX5_INLINE_HSIZE_INNER_L3;
2135                                 goto exit;
2136                         case MLX5_INLINE_MODE_INNER_TCP_UDP:
2137                                 config->txq_inline_min =
2138                                         MLX5_INLINE_HSIZE_INNER_L4;
2139                                 goto exit;
2140                         }
2141                 }
2142         }
2143         /*
2144          * We get here if we are unable to deduce
2145          * inline data size with DevX. Try PCI ID
2146          * to determine old NICs.
2147          */
2148         switch (spawn->pci_dev->id.device_id) {
2149         case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2150         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2151         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
2152         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
2153                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2154                 config->hw_vlan_insert = 0;
2155                 break;
2156         case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
2157         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
2158         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
2159         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
2160                 /*
2161                  * These NICs support VLAN insertion from WQE and
2162                  * report the wqe_vlan_insert flag. But there is the bug
2163                  * and PFC control may be broken, so disable feature.
2164                  */
2165                 config->hw_vlan_insert = 0;
2166                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2167                 break;
2168         default:
2169                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2170                 break;
2171         }
2172 exit:
2173         DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
2174 }
2175
2176 /**
2177  * Configures the metadata mask fields in the shared context.
2178  *
2179  * @param [in] dev
2180  *   Pointer to Ethernet device.
2181  */
2182 void
2183 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
2184 {
2185         struct mlx5_priv *priv = dev->data->dev_private;
2186         struct mlx5_dev_ctx_shared *sh = priv->sh;
2187         uint32_t meta, mark, reg_c0;
2188
2189         reg_c0 = ~priv->vport_meta_mask;
2190         switch (priv->config.dv_xmeta_en) {
2191         case MLX5_XMETA_MODE_LEGACY:
2192                 meta = UINT32_MAX;
2193                 mark = MLX5_FLOW_MARK_MASK;
2194                 break;
2195         case MLX5_XMETA_MODE_META16:
2196                 meta = reg_c0 >> rte_bsf32(reg_c0);
2197                 mark = MLX5_FLOW_MARK_MASK;
2198                 break;
2199         case MLX5_XMETA_MODE_META32:
2200                 meta = UINT32_MAX;
2201                 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
2202                 break;
2203         default:
2204                 meta = 0;
2205                 mark = 0;
2206                 MLX5_ASSERT(false);
2207                 break;
2208         }
2209         if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
2210                 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
2211                                  sh->dv_mark_mask, mark);
2212         else
2213                 sh->dv_mark_mask = mark;
2214         if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
2215                 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
2216                                  sh->dv_meta_mask, meta);
2217         else
2218                 sh->dv_meta_mask = meta;
2219         if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
2220                 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
2221                                  sh->dv_meta_mask, reg_c0);
2222         else
2223                 sh->dv_regc0_mask = reg_c0;
2224         DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
2225         DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
2226         DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
2227         DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
2228 }
2229
2230 int
2231 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
2232 {
2233         static const char *const dynf_names[] = {
2234                 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
2235                 RTE_MBUF_DYNFLAG_METADATA_NAME,
2236                 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
2237         };
2238         unsigned int i;
2239
2240         if (n < RTE_DIM(dynf_names))
2241                 return -ENOMEM;
2242         for (i = 0; i < RTE_DIM(dynf_names); i++) {
2243                 if (names[i] == NULL)
2244                         return -EINVAL;
2245                 strcpy(names[i], dynf_names[i]);
2246         }
2247         return RTE_DIM(dynf_names);
2248 }
2249
2250 /**
2251  * Comparison callback to sort device data.
2252  *
2253  * This is meant to be used with qsort().
2254  *
2255  * @param a[in]
2256  *   Pointer to pointer to first data object.
2257  * @param b[in]
2258  *   Pointer to pointer to second data object.
2259  *
2260  * @return
2261  *   0 if both objects are equal, less than 0 if the first argument is less
2262  *   than the second, greater than 0 otherwise.
2263  */
2264 int
2265 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
2266                               struct mlx5_dev_config *config)
2267 {
2268         struct mlx5_dev_ctx_shared *sh = priv->sh;
2269         struct mlx5_dev_config *sh_conf = NULL;
2270         uint16_t port_id;
2271
2272         MLX5_ASSERT(sh);
2273         /* Nothing to compare for the single/first device. */
2274         if (sh->refcnt == 1)
2275                 return 0;
2276         /* Find the device with shared context. */
2277         MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
2278                 struct mlx5_priv *opriv =
2279                         rte_eth_devices[port_id].data->dev_private;
2280
2281                 if (opriv && opriv != priv && opriv->sh == sh) {
2282                         sh_conf = &opriv->config;
2283                         break;
2284                 }
2285         }
2286         if (!sh_conf)
2287                 return 0;
2288         if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
2289                 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
2290                              " for shared %s context", sh->ibdev_name);
2291                 rte_errno = EINVAL;
2292                 return rte_errno;
2293         }
2294         if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
2295                 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
2296                              " for shared %s context", sh->ibdev_name);
2297                 rte_errno = EINVAL;
2298                 return rte_errno;
2299         }
2300         return 0;
2301 }
2302
2303 /**
2304  * Look for the ethernet device belonging to mlx5 driver.
2305  *
2306  * @param[in] port_id
2307  *   port_id to start looking for device.
2308  * @param[in] pci_dev
2309  *   Pointer to the hint PCI device. When device is being probed
2310  *   the its siblings (master and preceding representors might
2311  *   not have assigned driver yet (because the mlx5_os_pci_probe()
2312  *   is not completed yet, for this case match on hint PCI
2313  *   device may be used to detect sibling device.
2314  *
2315  * @return
2316  *   port_id of found device, RTE_MAX_ETHPORT if not found.
2317  */
2318 uint16_t
2319 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
2320 {
2321         while (port_id < RTE_MAX_ETHPORTS) {
2322                 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
2323
2324                 if (dev->state != RTE_ETH_DEV_UNUSED &&
2325                     dev->device &&
2326                     (dev->device == &pci_dev->device ||
2327                      (dev->device->driver &&
2328                      dev->device->driver->name &&
2329                      !strcmp(dev->device->driver->name, MLX5_PCI_DRIVER_NAME))))
2330                         break;
2331                 port_id++;
2332         }
2333         if (port_id >= RTE_MAX_ETHPORTS)
2334                 return RTE_MAX_ETHPORTS;
2335         return port_id;
2336 }
2337
2338 /**
2339  * DPDK callback to remove a PCI device.
2340  *
2341  * This function removes all Ethernet devices belong to a given PCI device.
2342  *
2343  * @param[in] pci_dev
2344  *   Pointer to the PCI device.
2345  *
2346  * @return
2347  *   0 on success, the function cannot fail.
2348  */
2349 static int
2350 mlx5_pci_remove(struct rte_pci_device *pci_dev)
2351 {
2352         uint16_t port_id;
2353         int ret = 0;
2354
2355         RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
2356                 /*
2357                  * mlx5_dev_close() is not registered to secondary process,
2358                  * call the close function explicitly for secondary process.
2359                  */
2360                 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
2361                         ret |= mlx5_dev_close(&rte_eth_devices[port_id]);
2362                 else
2363                         ret |= rte_eth_dev_close(port_id);
2364         }
2365         return ret == 0 ? 0 : -EIO;
2366 }
2367
2368 static const struct rte_pci_id mlx5_pci_id_map[] = {
2369         {
2370                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2371                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
2372         },
2373         {
2374                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2375                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
2376         },
2377         {
2378                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2379                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
2380         },
2381         {
2382                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2383                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
2384         },
2385         {
2386                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2387                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
2388         },
2389         {
2390                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2391                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
2392         },
2393         {
2394                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2395                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
2396         },
2397         {
2398                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2399                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
2400         },
2401         {
2402                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2403                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
2404         },
2405         {
2406                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2407                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
2408         },
2409         {
2410                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2411                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
2412         },
2413         {
2414                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2415                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
2416         },
2417         {
2418                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2419                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
2420         },
2421         {
2422                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2423                                 PCI_DEVICE_ID_MELLANOX_CONNECTXVF)
2424         },
2425         {
2426                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2427                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
2428         },
2429         {
2430                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2431                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
2432         },
2433         {
2434                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2435                                 PCI_DEVICE_ID_MELLANOX_CONNECTX7)
2436         },
2437         {
2438                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2439                                 PCI_DEVICE_ID_MELLANOX_CONNECTX7BF)
2440         },
2441         {
2442                 .vendor_id = 0
2443         }
2444 };
2445
2446 static struct mlx5_pci_driver mlx5_driver = {
2447         .driver_class = MLX5_CLASS_NET,
2448         .pci_driver = {
2449                 .driver = {
2450                         .name = MLX5_PCI_DRIVER_NAME,
2451                 },
2452                 .id_table = mlx5_pci_id_map,
2453                 .probe = mlx5_os_pci_probe,
2454                 .remove = mlx5_pci_remove,
2455                 .dma_map = mlx5_dma_map,
2456                 .dma_unmap = mlx5_dma_unmap,
2457                 .drv_flags = PCI_DRV_FLAGS,
2458         },
2459 };
2460
2461 /* Initialize driver log type. */
2462 RTE_LOG_REGISTER_DEFAULT(mlx5_logtype, NOTICE)
2463
2464 /**
2465  * Driver initialization routine.
2466  */
2467 RTE_INIT(rte_mlx5_pmd_init)
2468 {
2469         pthread_mutex_init(&mlx5_dev_ctx_list_mutex, NULL);
2470         mlx5_common_init();
2471         /* Build the static tables for Verbs conversion. */
2472         mlx5_set_ptype_table();
2473         mlx5_set_cksum_table();
2474         mlx5_set_swp_types_table();
2475         if (mlx5_glue)
2476                 mlx5_pci_driver_register(&mlx5_driver);
2477 }
2478
2479 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
2480 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
2481 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");