1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
13 #include <rte_malloc.h>
14 #include <ethdev_driver.h>
15 #include <ethdev_pci.h>
17 #include <rte_bus_pci.h>
18 #include <rte_common.h>
19 #include <rte_kvargs.h>
20 #include <rte_rwlock.h>
21 #include <rte_spinlock.h>
22 #include <rte_string_fns.h>
23 #include <rte_alarm.h>
24 #include <rte_cycles.h>
26 #include <mlx5_glue.h>
27 #include <mlx5_devx_cmds.h>
28 #include <mlx5_common.h>
29 #include <mlx5_common_os.h>
30 #include <mlx5_common_mp.h>
31 #include <mlx5_common_pci.h>
32 #include <mlx5_malloc.h>
34 #include "mlx5_defs.h"
36 #include "mlx5_utils.h"
37 #include "mlx5_rxtx.h"
40 #include "mlx5_autoconf.h"
42 #include "mlx5_flow.h"
43 #include "mlx5_flow_os.h"
44 #include "rte_pmd_mlx5.h"
46 /* Device parameter to enable RX completion queue compression. */
47 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
49 /* Device parameter to enable padding Rx packet to cacheline size. */
50 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
52 /* Device parameter to enable Multi-Packet Rx queue. */
53 #define MLX5_RX_MPRQ_EN "mprq_en"
55 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
56 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
58 /* Device parameter to configure log 2 of the stride size for MPRQ. */
59 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
61 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
62 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
64 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
65 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
67 /* Device parameter to configure inline send. Deprecated, ignored.*/
68 #define MLX5_TXQ_INLINE "txq_inline"
70 /* Device parameter to limit packet size to inline with ordinary SEND. */
71 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
73 /* Device parameter to configure minimal data size to inline. */
74 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
76 /* Device parameter to limit packet size to inline with Enhanced MPW. */
77 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
80 * Device parameter to configure the number of TX queues threshold for
81 * enabling inline send.
83 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
86 * Device parameter to configure the number of TX queues threshold for
87 * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
89 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
91 /* Device parameter to enable multi-packet send WQEs. */
92 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
95 * Device parameter to force doorbell register mapping
96 * to non-cahed region eliminating the extra write memory barrier.
98 #define MLX5_TX_DB_NC "tx_db_nc"
101 * Device parameter to include 2 dsegs in the title WQEBB.
102 * Deprecated, ignored.
104 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
107 * Device parameter to limit the size of inlining packet.
108 * Deprecated, ignored.
110 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
113 * Device parameter to enable Tx scheduling on timestamps
114 * and specify the packet pacing granularity in nanoseconds.
116 #define MLX5_TX_PP "tx_pp"
119 * Device parameter to specify skew in nanoseconds on Tx datapath,
120 * it represents the time between SQ start WQE processing and
121 * appearing actual packet data on the wire.
123 #define MLX5_TX_SKEW "tx_skew"
126 * Device parameter to enable hardware Tx vector.
127 * Deprecated, ignored (no vectorized Tx routines anymore).
129 #define MLX5_TX_VEC_EN "tx_vec_en"
131 /* Device parameter to enable hardware Rx vector. */
132 #define MLX5_RX_VEC_EN "rx_vec_en"
134 /* Allow L3 VXLAN flow creation. */
135 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
137 /* Activate DV E-Switch flow steering. */
138 #define MLX5_DV_ESW_EN "dv_esw_en"
140 /* Activate DV flow steering. */
141 #define MLX5_DV_FLOW_EN "dv_flow_en"
143 /* Enable extensive flow metadata support. */
144 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
146 /* Device parameter to let the user manage the lacp traffic of bonded device */
147 #define MLX5_LACP_BY_USER "lacp_by_user"
149 /* Activate Netlink support in VF mode. */
150 #define MLX5_VF_NL_EN "vf_nl_en"
152 /* Enable extending memsegs when creating a MR. */
153 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
155 /* Select port representors to instantiate. */
156 #define MLX5_REPRESENTOR "representor"
158 /* Device parameter to configure the maximum number of dump files per queue. */
159 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
161 /* Configure timeout of LRO session (in microseconds). */
162 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
165 * Device parameter to configure the total data buffer size for a single
166 * hairpin queue (logarithm value).
168 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
170 /* Flow memory reclaim mode. */
171 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
173 /* The default memory allocator used in PMD. */
174 #define MLX5_SYS_MEM_EN "sys_mem_en"
175 /* Decap will be used or not. */
176 #define MLX5_DECAP_EN "decap_en"
178 /* Device parameter to configure allow or prevent duplicate rules pattern. */
179 #define MLX5_ALLOW_DUPLICATE_PATTERN "allow_duplicate_pattern"
181 /* Shared memory between primary and secondary processes. */
182 struct mlx5_shared_data *mlx5_shared_data;
184 /** Driver-specific log messages type. */
187 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
188 LIST_HEAD_INITIALIZER();
189 static pthread_mutex_t mlx5_dev_ctx_list_mutex;
190 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
191 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
192 [MLX5_IPOOL_DECAP_ENCAP] = {
193 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
199 .malloc = mlx5_malloc,
201 .type = "mlx5_encap_decap_ipool",
203 [MLX5_IPOOL_PUSH_VLAN] = {
204 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
210 .malloc = mlx5_malloc,
212 .type = "mlx5_push_vlan_ipool",
215 .size = sizeof(struct mlx5_flow_dv_tag_resource),
221 .malloc = mlx5_malloc,
223 .type = "mlx5_tag_ipool",
225 [MLX5_IPOOL_PORT_ID] = {
226 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
232 .malloc = mlx5_malloc,
234 .type = "mlx5_port_id_ipool",
236 [MLX5_IPOOL_JUMP] = {
237 .size = sizeof(struct mlx5_flow_tbl_data_entry),
243 .malloc = mlx5_malloc,
245 .type = "mlx5_jump_ipool",
247 [MLX5_IPOOL_SAMPLE] = {
248 .size = sizeof(struct mlx5_flow_dv_sample_resource),
254 .malloc = mlx5_malloc,
256 .type = "mlx5_sample_ipool",
258 [MLX5_IPOOL_DEST_ARRAY] = {
259 .size = sizeof(struct mlx5_flow_dv_dest_array_resource),
265 .malloc = mlx5_malloc,
267 .type = "mlx5_dest_array_ipool",
269 [MLX5_IPOOL_TUNNEL_ID] = {
270 .size = sizeof(struct mlx5_flow_tunnel),
271 .trunk_size = MLX5_MAX_TUNNELS,
274 .type = "mlx5_tunnel_offload",
276 [MLX5_IPOOL_TNL_TBL_ID] = {
279 .type = "mlx5_flow_tnl_tbl_ipool",
284 * The ipool index should grow continually from small to big,
285 * for meter idx, so not set grow_trunk to avoid meter index
286 * not jump continually.
288 .size = sizeof(struct mlx5_legacy_flow_meter),
292 .malloc = mlx5_malloc,
294 .type = "mlx5_meter_ipool",
297 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
303 .malloc = mlx5_malloc,
305 .type = "mlx5_mcp_ipool",
307 [MLX5_IPOOL_HRXQ] = {
308 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
314 .malloc = mlx5_malloc,
316 .type = "mlx5_hrxq_ipool",
318 [MLX5_IPOOL_MLX5_FLOW] = {
320 * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
321 * It set in run time according to PCI function configuration.
329 .per_core_cache = 1 << 19,
330 .malloc = mlx5_malloc,
332 .type = "mlx5_flow_handle_ipool",
334 [MLX5_IPOOL_RTE_FLOW] = {
335 .size = sizeof(struct rte_flow),
339 .malloc = mlx5_malloc,
341 .type = "rte_flow_ipool",
343 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID] = {
346 .type = "mlx5_flow_rss_id_ipool",
348 [MLX5_IPOOL_RSS_SHARED_ACTIONS] = {
349 .size = sizeof(struct mlx5_shared_action_rss),
355 .malloc = mlx5_malloc,
357 .type = "mlx5_shared_action_rss",
359 [MLX5_IPOOL_MTR_POLICY] = {
361 * The ipool index should grow continually from small to big,
362 * for policy idx, so not set grow_trunk to avoid policy index
363 * not jump continually.
365 .size = sizeof(struct mlx5_flow_meter_sub_policy),
369 .malloc = mlx5_malloc,
371 .type = "mlx5_meter_policy_ipool",
376 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
377 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
379 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
382 * Decide whether representor ID is a HPF(host PF) port on BF2.
385 * Pointer to Ethernet device structure.
388 * Non-zero if HPF, otherwise 0.
391 mlx5_is_hpf(struct rte_eth_dev *dev)
393 struct mlx5_priv *priv = dev->data->dev_private;
394 uint16_t repr = MLX5_REPRESENTOR_REPR(priv->representor_id);
395 int type = MLX5_REPRESENTOR_TYPE(priv->representor_id);
397 return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_VF &&
398 MLX5_REPRESENTOR_REPR(-1) == repr;
402 * Initialize the ASO aging management structure.
405 * Pointer to mlx5_dev_ctx_shared object to free
408 * 0 on success, a negative errno value otherwise and rte_errno is set.
411 mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh)
417 sh->aso_age_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->aso_age_mng),
418 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
419 if (!sh->aso_age_mng) {
420 DRV_LOG(ERR, "aso_age_mng allocation was failed.");
424 err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_FLOW_HIT);
426 mlx5_free(sh->aso_age_mng);
429 rte_spinlock_init(&sh->aso_age_mng->resize_sl);
430 rte_spinlock_init(&sh->aso_age_mng->free_sl);
431 LIST_INIT(&sh->aso_age_mng->free);
436 * Close and release all the resources of the ASO aging management structure.
439 * Pointer to mlx5_dev_ctx_shared object to free.
442 mlx5_flow_aso_age_mng_close(struct mlx5_dev_ctx_shared *sh)
446 mlx5_aso_flow_hit_queue_poll_stop(sh);
447 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_FLOW_HIT);
448 if (sh->aso_age_mng->pools) {
449 struct mlx5_aso_age_pool *pool;
451 for (i = 0; i < sh->aso_age_mng->next; ++i) {
452 pool = sh->aso_age_mng->pools[i];
453 claim_zero(mlx5_devx_cmd_destroy
454 (pool->flow_hit_aso_obj));
455 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j)
456 if (pool->actions[j].dr_action)
458 (mlx5_flow_os_destroy_flow_action
459 (pool->actions[j].dr_action));
462 mlx5_free(sh->aso_age_mng->pools);
464 mlx5_free(sh->aso_age_mng);
468 * Initialize the shared aging list information per port.
471 * Pointer to mlx5_dev_ctx_shared object.
474 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
477 struct mlx5_age_info *age_info;
479 for (i = 0; i < sh->max_port; i++) {
480 age_info = &sh->port[i].age_info;
482 TAILQ_INIT(&age_info->aged_counters);
483 LIST_INIT(&age_info->aged_aso);
484 rte_spinlock_init(&age_info->aged_sl);
485 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
490 * Initialize the counters management structure.
493 * Pointer to mlx5_dev_ctx_shared object to free
496 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
500 memset(&sh->cmng, 0, sizeof(sh->cmng));
501 TAILQ_INIT(&sh->cmng.flow_counters);
502 sh->cmng.min_id = MLX5_CNT_BATCH_OFFSET;
503 sh->cmng.max_id = -1;
504 sh->cmng.last_pool_idx = POOL_IDX_INVALID;
505 rte_spinlock_init(&sh->cmng.pool_update_sl);
506 for (i = 0; i < MLX5_COUNTER_TYPE_MAX; i++) {
507 TAILQ_INIT(&sh->cmng.counters[i]);
508 rte_spinlock_init(&sh->cmng.csl[i]);
513 * Destroy all the resources allocated for a counter memory management.
516 * Pointer to the memory management structure.
519 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
521 uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
523 LIST_REMOVE(mng, next);
524 claim_zero(mlx5_devx_cmd_destroy(mng->dm));
525 claim_zero(mlx5_os_umem_dereg(mng->umem));
530 * Close and release all the resources of the counters management.
533 * Pointer to mlx5_dev_ctx_shared object to free.
536 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
538 struct mlx5_counter_stats_mem_mng *mng;
544 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
545 if (rte_errno != EINPROGRESS)
550 if (sh->cmng.pools) {
551 struct mlx5_flow_counter_pool *pool;
552 uint16_t n_valid = sh->cmng.n_valid;
553 bool fallback = sh->cmng.counter_fallback;
555 for (i = 0; i < n_valid; ++i) {
556 pool = sh->cmng.pools[i];
557 if (!fallback && pool->min_dcs)
558 claim_zero(mlx5_devx_cmd_destroy
560 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
561 struct mlx5_flow_counter *cnt =
562 MLX5_POOL_GET_CNT(pool, j);
566 (mlx5_flow_os_destroy_flow_action
568 if (fallback && MLX5_POOL_GET_CNT
569 (pool, j)->dcs_when_free)
570 claim_zero(mlx5_devx_cmd_destroy
571 (cnt->dcs_when_free));
575 mlx5_free(sh->cmng.pools);
577 mng = LIST_FIRST(&sh->cmng.mem_mngs);
579 mlx5_flow_destroy_counter_stat_mem_mng(mng);
580 mng = LIST_FIRST(&sh->cmng.mem_mngs);
582 memset(&sh->cmng, 0, sizeof(sh->cmng));
586 * Initialize the aso flow meters management structure.
589 * Pointer to mlx5_dev_ctx_shared object to free
592 mlx5_aso_flow_mtrs_mng_init(struct mlx5_dev_ctx_shared *sh)
595 sh->mtrmng = mlx5_malloc(MLX5_MEM_ZERO,
597 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
600 "meter management allocation was failed.");
604 if (sh->meter_aso_en) {
605 rte_spinlock_init(&sh->mtrmng->pools_mng.mtrsl);
606 LIST_INIT(&sh->mtrmng->pools_mng.meters);
608 sh->mtrmng->def_policy_id = MLX5_INVALID_POLICY_ID;
614 * Close and release all the resources of
615 * the ASO flow meter management structure.
618 * Pointer to mlx5_dev_ctx_shared object to free.
621 mlx5_aso_flow_mtrs_mng_close(struct mlx5_dev_ctx_shared *sh)
623 struct mlx5_aso_mtr_pool *mtr_pool;
624 struct mlx5_flow_mtr_mng *mtrmng = sh->mtrmng;
626 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
627 struct mlx5_aso_mtr *aso_mtr;
629 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
631 if (sh->meter_aso_en) {
632 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_POLICER);
633 idx = mtrmng->pools_mng.n_valid;
635 mtr_pool = mtrmng->pools_mng.pools[idx];
636 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
637 for (i = 0; i < MLX5_ASO_MTRS_PER_POOL; i++) {
638 aso_mtr = &mtr_pool->mtrs[i];
639 if (aso_mtr->fm.meter_action)
641 (mlx5_glue->destroy_flow_action
642 (aso_mtr->fm.meter_action));
644 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
645 claim_zero(mlx5_devx_cmd_destroy
646 (mtr_pool->devx_obj));
647 mtrmng->pools_mng.n_valid--;
650 mlx5_free(sh->mtrmng->pools_mng.pools);
652 mlx5_free(sh->mtrmng);
656 /* Send FLOW_AGED event if needed. */
658 mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh)
660 struct mlx5_age_info *age_info;
663 for (i = 0; i < sh->max_port; i++) {
664 age_info = &sh->port[i].age_info;
665 if (!MLX5_AGE_GET(age_info, MLX5_AGE_EVENT_NEW))
667 MLX5_AGE_UNSET(age_info, MLX5_AGE_EVENT_NEW);
668 if (MLX5_AGE_GET(age_info, MLX5_AGE_TRIGGER)) {
669 MLX5_AGE_UNSET(age_info, MLX5_AGE_TRIGGER);
670 rte_eth_dev_callback_process
671 (&rte_eth_devices[sh->port[i].devx_ih_port_id],
672 RTE_ETH_EVENT_FLOW_AGED, NULL);
678 * Initialize the ASO connection tracking structure.
681 * Pointer to mlx5_dev_ctx_shared object.
684 * 0 on success, a negative errno value otherwise and rte_errno is set.
687 mlx5_flow_aso_ct_mng_init(struct mlx5_dev_ctx_shared *sh)
693 sh->ct_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->ct_mng),
694 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
696 DRV_LOG(ERR, "ASO CT management allocation failed.");
700 err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_CONNECTION_TRACKING);
702 mlx5_free(sh->ct_mng);
703 /* rte_errno should be extracted from the failure. */
707 rte_spinlock_init(&sh->ct_mng->ct_sl);
708 rte_rwlock_init(&sh->ct_mng->resize_rwl);
709 LIST_INIT(&sh->ct_mng->free_cts);
714 * Close and release all the resources of the
715 * ASO connection tracking management structure.
718 * Pointer to mlx5_dev_ctx_shared object to free.
721 mlx5_flow_aso_ct_mng_close(struct mlx5_dev_ctx_shared *sh)
723 struct mlx5_aso_ct_pools_mng *mng = sh->ct_mng;
724 struct mlx5_aso_ct_pool *ct_pool;
725 struct mlx5_aso_ct_action *ct;
731 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_CONNECTION_TRACKING);
735 ct_pool = mng->pools[idx];
736 for (i = 0; i < MLX5_ASO_CT_ACTIONS_PER_POOL; i++) {
737 ct = &ct_pool->actions[i];
738 val = __atomic_fetch_sub(&ct->refcnt, 1,
740 MLX5_ASSERT(val == 1);
743 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
744 if (ct->dr_action_orig)
745 claim_zero(mlx5_glue->destroy_flow_action
746 (ct->dr_action_orig));
747 if (ct->dr_action_rply)
748 claim_zero(mlx5_glue->destroy_flow_action
749 (ct->dr_action_rply));
752 claim_zero(mlx5_devx_cmd_destroy(ct_pool->devx_obj));
754 DRV_LOG(DEBUG, "%u ASO CT objects are being used in the pool %u",
758 /* in case of failure. */
761 mlx5_free(mng->pools);
763 /* Management structure must be cleared to 0s during allocation. */
768 * Initialize the flow resources' indexed mempool.
771 * Pointer to mlx5_dev_ctx_shared object.
773 * Pointer to user dev config.
776 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
777 const struct mlx5_dev_config *config)
780 struct mlx5_indexed_pool_config cfg;
782 for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
783 cfg = mlx5_ipool_cfg[i];
788 * Set MLX5_IPOOL_MLX5_FLOW ipool size
789 * according to PCI function flow configuration.
791 case MLX5_IPOOL_MLX5_FLOW:
792 cfg.size = config->dv_flow_en ?
793 sizeof(struct mlx5_flow_handle) :
794 MLX5_FLOW_HANDLE_VERBS_SIZE;
797 if (config->reclaim_mode) {
798 cfg.release_mem_en = 1;
799 cfg.per_core_cache = 0;
801 sh->ipool[i] = mlx5_ipool_create(&cfg);
806 * Release the flow resources' indexed mempool.
809 * Pointer to mlx5_dev_ctx_shared object.
812 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
816 for (i = 0; i < MLX5_IPOOL_MAX; ++i)
817 mlx5_ipool_destroy(sh->ipool[i]);
821 * Check if dynamic flex parser for eCPRI already exists.
824 * Pointer to Ethernet device structure.
827 * true on exists, false on not.
830 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
832 struct mlx5_priv *priv = dev->data->dev_private;
833 struct mlx5_flex_parser_profiles *prf =
834 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
840 * Allocation of a flex parser for eCPRI. Once created, this parser related
841 * resources will be held until the device is closed.
844 * Pointer to Ethernet device structure.
847 * 0 on success, a negative errno value otherwise and rte_errno is set.
850 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
852 struct mlx5_priv *priv = dev->data->dev_private;
853 struct mlx5_flex_parser_profiles *prf =
854 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
855 struct mlx5_devx_graph_node_attr node = {
856 .modify_field_select = 0,
861 if (!priv->config.hca_attr.parse_graph_flex_node) {
862 DRV_LOG(ERR, "Dynamic flex parser is not supported "
863 "for device %s.", priv->dev_data->name);
866 node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED;
867 /* 8 bytes now: 4B common header + 4B message body header. */
868 node.header_length_base_value = 0x8;
869 /* After MAC layer: Ether / VLAN. */
870 node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC;
871 /* Type of compared condition should be 0xAEFE in the L2 layer. */
872 node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI;
873 /* Sample #0: type in common header. */
874 node.sample[0].flow_match_sample_en = 1;
876 node.sample[0].flow_match_sample_offset_mode = 0x0;
877 /* Only the 2nd byte will be used. */
878 node.sample[0].flow_match_sample_field_base_offset = 0x0;
879 /* Sample #1: message payload. */
880 node.sample[1].flow_match_sample_en = 1;
882 node.sample[1].flow_match_sample_offset_mode = 0x0;
884 * Only the first two bytes will be used right now, and its offset will
885 * start after the common header that with the length of a DW(u32).
887 node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);
888 prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->ctx, &node);
890 DRV_LOG(ERR, "Failed to create flex parser node object.");
891 return (rte_errno == 0) ? -ENODEV : -rte_errno;
894 ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num);
896 DRV_LOG(ERR, "Failed to query sample IDs.");
897 return (rte_errno == 0) ? -ENODEV : -rte_errno;
899 prf->offset[0] = 0x0;
900 prf->offset[1] = sizeof(uint32_t);
901 prf->ids[0] = ids[0];
902 prf->ids[1] = ids[1];
907 * Destroy the flex parser node, including the parser itself, input / output
908 * arcs and DW samples. Resources could be reused then.
911 * Pointer to Ethernet device structure.
914 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
916 struct mlx5_priv *priv = dev->data->dev_private;
917 struct mlx5_flex_parser_profiles *prf =
918 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
921 mlx5_devx_cmd_destroy(prf->obj);
926 * Allocate Rx and Tx UARs in robust fashion.
927 * This routine handles the following UAR allocation issues:
929 * - tries to allocate the UAR with the most appropriate memory
930 * mapping type from the ones supported by the host
932 * - tries to allocate the UAR with non-NULL base address
933 * OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as
934 * UAR base address if UAR was not the first object in the UAR page.
935 * It caused the PMD failure and we should try to get another UAR
936 * till we get the first one with non-NULL base address returned.
939 mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh,
940 const struct mlx5_dev_config *config)
942 uint32_t uar_mapping, retry;
946 for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
947 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
948 /* Control the mapping type according to the settings. */
949 uar_mapping = (config->dbnc == MLX5_TXDB_NCACHED) ?
950 MLX5DV_UAR_ALLOC_TYPE_NC :
951 MLX5DV_UAR_ALLOC_TYPE_BF;
953 RTE_SET_USED(config);
955 * It seems we have no way to control the memory mapping type
956 * for the UAR, the default "Write-Combining" type is supposed.
957 * The UAR initialization on queue creation queries the
958 * actual mapping type done by Verbs/kernel and setups the
959 * PMD datapath accordingly.
963 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->ctx, uar_mapping);
964 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
966 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
967 if (config->dbnc == MLX5_TXDB_CACHED ||
968 config->dbnc == MLX5_TXDB_HEURISTIC)
969 DRV_LOG(WARNING, "Devarg tx_db_nc setting "
970 "is not supported by DevX");
972 * In some environments like virtual machine
973 * the Write Combining mapped might be not supported
974 * and UAR allocation fails. We try "Non-Cached"
975 * mapping for the case. The tx_burst routines take
976 * the UAR mapping type into account on UAR setup
979 DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (BF)");
980 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
981 sh->tx_uar = mlx5_glue->devx_alloc_uar
982 (sh->ctx, uar_mapping);
983 } else if (!sh->tx_uar &&
984 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_NC) {
985 if (config->dbnc == MLX5_TXDB_NCACHED)
986 DRV_LOG(WARNING, "Devarg tx_db_nc settings "
987 "is not supported by DevX");
989 * If Verbs/kernel does not support "Non-Cached"
990 * try the "Write-Combining".
992 DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (NC)");
993 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_BF;
994 sh->tx_uar = mlx5_glue->devx_alloc_uar
995 (sh->ctx, uar_mapping);
999 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (BF/NC)");
1003 base_addr = mlx5_os_get_devx_uar_base_addr(sh->tx_uar);
1007 * The UARs are allocated by rdma_core within the
1008 * IB device context, on context closure all UARs
1009 * will be freed, should be no memory/object leakage.
1011 DRV_LOG(DEBUG, "Retrying to allocate Tx DevX UAR");
1014 /* Check whether we finally succeeded with valid UAR allocation. */
1016 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (NULL base)");
1020 for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
1022 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
1023 (sh->ctx, uar_mapping);
1024 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
1025 if (!sh->devx_rx_uar &&
1026 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
1028 * Rx UAR is used to control interrupts only,
1029 * should be no datapath noticeable impact,
1030 * can try "Non-Cached" mapping safely.
1032 DRV_LOG(DEBUG, "Failed to allocate Rx DevX UAR (BF)");
1033 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
1034 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
1035 (sh->ctx, uar_mapping);
1038 if (!sh->devx_rx_uar) {
1039 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (BF/NC)");
1043 base_addr = mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar);
1047 * The UARs are allocated by rdma_core within the
1048 * IB device context, on context closure all UARs
1049 * will be freed, should be no memory/object leakage.
1051 DRV_LOG(DEBUG, "Retrying to allocate Rx DevX UAR");
1052 sh->devx_rx_uar = NULL;
1054 /* Check whether we finally succeeded with valid UAR allocation. */
1055 if (!sh->devx_rx_uar) {
1056 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (NULL base)");
1064 * Allocate shared device context. If there is multiport device the
1065 * master and representors will share this context, if there is single
1066 * port dedicated device, the context will be used by only given
1067 * port due to unification.
1069 * Routine first searches the context for the specified device name,
1070 * if found the shared context assumed and reference counter is incremented.
1071 * If no context found the new one is created and initialized with specified
1072 * device context and parameters.
1075 * Pointer to the device attributes (name, port, etc).
1077 * Pointer to device configuration structure.
1080 * Pointer to mlx5_dev_ctx_shared object on success,
1081 * otherwise NULL and rte_errno is set.
1083 struct mlx5_dev_ctx_shared *
1084 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
1085 const struct mlx5_dev_config *config)
1087 struct mlx5_dev_ctx_shared *sh;
1090 struct mlx5_devx_tis_attr tis_attr = { 0 };
1093 /* Secondary process should not create the shared context. */
1094 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1095 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1096 /* Search for IB context by device name. */
1097 LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
1098 if (!strcmp(sh->ibdev_name,
1099 mlx5_os_get_dev_device_name(spawn->phys_dev))) {
1104 /* No device found, we have to create new shared context. */
1105 MLX5_ASSERT(spawn->max_port);
1106 sh = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
1107 sizeof(struct mlx5_dev_ctx_shared) +
1109 sizeof(struct mlx5_dev_shared_port),
1110 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
1112 DRV_LOG(ERR, "shared context allocation failure");
1116 if (spawn->bond_info)
1117 sh->bond = *spawn->bond_info;
1118 err = mlx5_os_open_device(spawn, config, sh);
1121 err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
1123 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
1127 sh->max_port = spawn->max_port;
1128 strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
1129 sizeof(sh->ibdev_name) - 1);
1130 strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
1131 sizeof(sh->ibdev_path) - 1);
1133 * Setting port_id to max unallowed value means
1134 * there is no interrupt subhandler installed for
1135 * the given port index i.
1137 for (i = 0; i < sh->max_port; i++) {
1138 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
1139 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
1141 sh->pd = mlx5_os_alloc_pd(sh->ctx);
1142 if (sh->pd == NULL) {
1143 DRV_LOG(ERR, "PD allocation failure");
1148 err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
1150 DRV_LOG(ERR, "Fail to extract pdn from PD");
1153 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
1155 DRV_LOG(ERR, "TD allocation failure");
1159 tis_attr.transport_domain = sh->td->id;
1160 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
1162 DRV_LOG(ERR, "TIS allocation failure");
1166 err = mlx5_alloc_rxtx_uars(sh, config);
1169 MLX5_ASSERT(sh->tx_uar);
1170 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->tx_uar));
1172 MLX5_ASSERT(sh->devx_rx_uar);
1173 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar));
1176 /* Initialize UAR access locks for 32bit implementations. */
1177 rte_spinlock_init(&sh->uar_lock_cq);
1178 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
1179 rte_spinlock_init(&sh->uar_lock[i]);
1182 * Once the device is added to the list of memory event
1183 * callback, its global MR cache table cannot be expanded
1184 * on the fly because of deadlock. If it overflows, lookup
1185 * should be done by searching MR list linearly, which is slow.
1187 * At this point the device is not added to the memory
1188 * event list yet, context is just being created.
1190 err = mlx5_mr_btree_init(&sh->share_cache.cache,
1191 MLX5_MR_BTREE_CACHE_N * 2,
1192 spawn->pci_dev->device.numa_node);
1197 mlx5_os_set_reg_mr_cb(&sh->share_cache.reg_mr_cb,
1198 &sh->share_cache.dereg_mr_cb);
1199 mlx5_os_dev_shared_handler_install(sh);
1200 sh->cnt_id_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_DWORD);
1201 if (!sh->cnt_id_tbl) {
1205 if (LIST_EMPTY(&mlx5_dev_ctx_list)) {
1206 err = mlx5_flow_os_init_workspace_once();
1210 mlx5_flow_aging_init(sh);
1211 mlx5_flow_counters_mng_init(sh);
1212 mlx5_flow_ipool_create(sh, config);
1213 /* Add device to memory callback list. */
1214 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1215 LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
1217 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1218 /* Add context to the global device list. */
1219 LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
1220 rte_spinlock_init(&sh->geneve_tlv_opt_sl);
1222 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1225 pthread_mutex_destroy(&sh->txpp.mutex);
1226 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1229 mlx5_l3t_destroy(sh->cnt_id_tbl);
1231 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1233 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1234 if (sh->devx_rx_uar)
1235 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1237 mlx5_glue->devx_free_uar(sh->tx_uar);
1239 claim_zero(mlx5_os_dealloc_pd(sh->pd));
1241 claim_zero(mlx5_glue->close_device(sh->ctx));
1243 MLX5_ASSERT(err > 0);
1249 * Free shared IB device context. Decrement counter and if zero free
1250 * all allocated resources and close handles.
1253 * Pointer to mlx5_dev_ctx_shared object to free
1256 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
1258 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1259 #ifdef RTE_LIBRTE_MLX5_DEBUG
1260 /* Check the object presence in the list. */
1261 struct mlx5_dev_ctx_shared *lctx;
1263 LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
1268 DRV_LOG(ERR, "Freeing non-existing shared IB context");
1273 MLX5_ASSERT(sh->refcnt);
1274 /* Secondary process should not free the shared context. */
1275 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1278 /* Remove from memory callback device list. */
1279 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1280 LIST_REMOVE(sh, mem_event_cb);
1281 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1282 /* Release created Memory Regions. */
1283 mlx5_mr_release_cache(&sh->share_cache);
1284 /* Remove context from the global device list. */
1285 LIST_REMOVE(sh, next);
1286 /* Release flow workspaces objects on the last device. */
1287 if (LIST_EMPTY(&mlx5_dev_ctx_list))
1288 mlx5_flow_os_release_workspace();
1289 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1291 * Ensure there is no async event handler installed.
1292 * Only primary process handles async device events.
1294 mlx5_flow_counters_mng_close(sh);
1295 if (sh->aso_age_mng) {
1296 mlx5_flow_aso_age_mng_close(sh);
1297 sh->aso_age_mng = NULL;
1300 mlx5_aso_flow_mtrs_mng_close(sh);
1301 mlx5_flow_ipool_destroy(sh);
1302 mlx5_os_dev_shared_handler_uninstall(sh);
1303 if (sh->cnt_id_tbl) {
1304 mlx5_l3t_destroy(sh->cnt_id_tbl);
1305 sh->cnt_id_tbl = NULL;
1308 mlx5_glue->devx_free_uar(sh->tx_uar);
1312 claim_zero(mlx5_os_dealloc_pd(sh->pd));
1314 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1316 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1317 if (sh->devx_rx_uar)
1318 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1320 claim_zero(mlx5_glue->close_device(sh->ctx));
1321 MLX5_ASSERT(sh->geneve_tlv_option_resource == NULL);
1322 pthread_mutex_destroy(&sh->txpp.mutex);
1326 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1330 * Destroy table hash list.
1333 * Pointer to the private device data structure.
1336 mlx5_free_table_hash_list(struct mlx5_priv *priv)
1338 struct mlx5_dev_ctx_shared *sh = priv->sh;
1342 mlx5_hlist_destroy(sh->flow_tbls);
1346 * Initialize flow table hash list and create the root tables entry
1350 * Pointer to the private device data structure.
1353 * Zero on success, positive error code otherwise.
1356 mlx5_alloc_table_hash_list(struct mlx5_priv *priv __rte_unused)
1359 /* Tables are only used in DV and DR modes. */
1360 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
1361 struct mlx5_dev_ctx_shared *sh = priv->sh;
1362 char s[MLX5_NAME_SIZE];
1365 snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1366 sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE,
1368 flow_dv_tbl_create_cb,
1369 flow_dv_tbl_match_cb,
1370 flow_dv_tbl_remove_cb,
1371 flow_dv_tbl_clone_cb,
1372 flow_dv_tbl_clone_free_cb);
1373 if (!sh->flow_tbls) {
1374 DRV_LOG(ERR, "flow tables with hash creation failed.");
1378 #ifndef HAVE_MLX5DV_DR
1379 struct rte_flow_error error;
1380 struct rte_eth_dev *dev = &rte_eth_devices[priv->dev_data->port_id];
1383 * In case we have not DR support, the zero tables should be created
1384 * because DV expect to see them even if they cannot be created by
1387 if (!flow_dv_tbl_resource_get(dev, 0, 0, 0, 0,
1388 NULL, 0, 1, 0, &error) ||
1389 !flow_dv_tbl_resource_get(dev, 0, 1, 0, 0,
1390 NULL, 0, 1, 0, &error) ||
1391 !flow_dv_tbl_resource_get(dev, 0, 0, 1, 0,
1392 NULL, 0, 1, 0, &error)) {
1398 mlx5_free_table_hash_list(priv);
1399 #endif /* HAVE_MLX5DV_DR */
1405 * Retrieve integer value from environment variable.
1408 * Environment variable name.
1411 * Integer value, 0 if the variable is not set.
1414 mlx5_getenv_int(const char *name)
1416 const char *val = getenv(name);
1424 * DPDK callback to add udp tunnel port
1427 * A pointer to eth_dev
1428 * @param[in] udp_tunnel
1429 * A pointer to udp tunnel
1432 * 0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1435 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1436 struct rte_eth_udp_tunnel *udp_tunnel)
1438 MLX5_ASSERT(udp_tunnel != NULL);
1439 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1440 udp_tunnel->udp_port == 4789)
1442 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1443 udp_tunnel->udp_port == 4790)
1449 * Initialize process private data structure.
1452 * Pointer to Ethernet device structure.
1455 * 0 on success, a negative errno value otherwise and rte_errno is set.
1458 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1460 struct mlx5_priv *priv = dev->data->dev_private;
1461 struct mlx5_proc_priv *ppriv;
1464 mlx5_proc_priv_uninit(dev);
1466 * UAR register table follows the process private structure. BlueFlame
1467 * registers for Tx queues are stored in the table.
1470 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1471 ppriv = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, ppriv_size,
1472 RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1477 ppriv->uar_table_sz = priv->txqs_n;
1478 dev->process_private = ppriv;
1483 * Un-initialize process private data structure.
1486 * Pointer to Ethernet device structure.
1489 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1491 if (!dev->process_private)
1493 mlx5_free(dev->process_private);
1494 dev->process_private = NULL;
1498 * DPDK callback to close the device.
1500 * Destroy all queues and objects, free memory.
1503 * Pointer to Ethernet device structure.
1506 mlx5_dev_close(struct rte_eth_dev *dev)
1508 struct mlx5_priv *priv = dev->data->dev_private;
1512 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1513 /* Check if process_private released. */
1514 if (!dev->process_private)
1516 mlx5_tx_uar_uninit_secondary(dev);
1517 mlx5_proc_priv_uninit(dev);
1518 rte_eth_dev_release_port(dev);
1523 DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1525 ((priv->sh->ctx != NULL) ?
1526 mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
1528 * If default mreg copy action is removed at the stop stage,
1529 * the search will return none and nothing will be done anymore.
1531 mlx5_flow_stop_default(dev);
1532 mlx5_traffic_disable(dev);
1534 * If all the flows are already flushed in the device stop stage,
1535 * then this will return directly without any action.
1537 mlx5_flow_list_flush(dev, MLX5_FLOW_TYPE_GEN, true);
1538 mlx5_action_handle_flush(dev);
1539 mlx5_flow_meter_flush(dev, NULL);
1540 /* Prevent crashes when queues are still in use. */
1541 dev->rx_pkt_burst = removed_rx_burst;
1542 dev->tx_pkt_burst = removed_tx_burst;
1544 /* Disable datapath on secondary process. */
1545 mlx5_mp_os_req_stop_rxtx(dev);
1546 /* Free the eCPRI flex parser resource. */
1547 mlx5_flex_parser_ecpri_release(dev);
1548 if (priv->rxqs != NULL) {
1549 /* XXX race condition if mlx5_rx_burst() is still running. */
1550 rte_delay_us_sleep(1000);
1551 for (i = 0; (i != priv->rxqs_n); ++i)
1552 mlx5_rxq_release(dev, i);
1556 if (priv->txqs != NULL) {
1557 /* XXX race condition if mlx5_tx_burst() is still running. */
1558 rte_delay_us_sleep(1000);
1559 for (i = 0; (i != priv->txqs_n); ++i)
1560 mlx5_txq_release(dev, i);
1564 mlx5_proc_priv_uninit(dev);
1565 if (priv->q_counters) {
1566 mlx5_devx_cmd_destroy(priv->q_counters);
1567 priv->q_counters = NULL;
1569 if (priv->drop_queue.hrxq)
1570 mlx5_drop_action_destroy(dev);
1571 if (priv->mreg_cp_tbl)
1572 mlx5_hlist_destroy(priv->mreg_cp_tbl);
1573 mlx5_mprq_free_mp(dev);
1574 if (priv->sh->ct_mng)
1575 mlx5_flow_aso_ct_mng_close(priv->sh);
1576 mlx5_os_free_shared_dr(priv);
1577 if (priv->rss_conf.rss_key != NULL)
1578 mlx5_free(priv->rss_conf.rss_key);
1579 if (priv->reta_idx != NULL)
1580 mlx5_free(priv->reta_idx);
1581 if (priv->config.vf)
1582 mlx5_os_mac_addr_flush(dev);
1583 if (priv->nl_socket_route >= 0)
1584 close(priv->nl_socket_route);
1585 if (priv->nl_socket_rdma >= 0)
1586 close(priv->nl_socket_rdma);
1587 if (priv->vmwa_context)
1588 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1589 ret = mlx5_hrxq_verify(dev);
1591 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1592 dev->data->port_id);
1593 ret = mlx5_ind_table_obj_verify(dev);
1595 DRV_LOG(WARNING, "port %u some indirection table still remain",
1596 dev->data->port_id);
1597 ret = mlx5_rxq_obj_verify(dev);
1599 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1600 dev->data->port_id);
1601 ret = mlx5_rxq_verify(dev);
1603 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1604 dev->data->port_id);
1605 ret = mlx5_txq_obj_verify(dev);
1607 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1608 dev->data->port_id);
1609 ret = mlx5_txq_verify(dev);
1611 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1612 dev->data->port_id);
1613 ret = mlx5_flow_verify(dev);
1615 DRV_LOG(WARNING, "port %u some flows still remain",
1616 dev->data->port_id);
1618 mlx5_list_destroy(priv->hrxqs);
1620 * Free the shared context in last turn, because the cleanup
1621 * routines above may use some shared fields, like
1622 * mlx5_os_mac_addr_flush() uses ibdev_path for retrieveing
1623 * ifindex if Netlink fails.
1625 mlx5_free_shared_dev_ctx(priv->sh);
1626 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1630 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1631 struct mlx5_priv *opriv =
1632 rte_eth_devices[port_id].data->dev_private;
1635 opriv->domain_id != priv->domain_id ||
1636 &rte_eth_devices[port_id] == dev)
1642 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1644 memset(priv, 0, sizeof(*priv));
1645 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1647 * Reset mac_addrs to NULL such that it is not freed as part of
1648 * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1649 * it is freed when dev_private is freed.
1651 dev->data->mac_addrs = NULL;
1655 const struct eth_dev_ops mlx5_dev_ops = {
1656 .dev_configure = mlx5_dev_configure,
1657 .dev_start = mlx5_dev_start,
1658 .dev_stop = mlx5_dev_stop,
1659 .dev_set_link_down = mlx5_set_link_down,
1660 .dev_set_link_up = mlx5_set_link_up,
1661 .dev_close = mlx5_dev_close,
1662 .promiscuous_enable = mlx5_promiscuous_enable,
1663 .promiscuous_disable = mlx5_promiscuous_disable,
1664 .allmulticast_enable = mlx5_allmulticast_enable,
1665 .allmulticast_disable = mlx5_allmulticast_disable,
1666 .link_update = mlx5_link_update,
1667 .stats_get = mlx5_stats_get,
1668 .stats_reset = mlx5_stats_reset,
1669 .xstats_get = mlx5_xstats_get,
1670 .xstats_reset = mlx5_xstats_reset,
1671 .xstats_get_names = mlx5_xstats_get_names,
1672 .fw_version_get = mlx5_fw_version_get,
1673 .dev_infos_get = mlx5_dev_infos_get,
1674 .representor_info_get = mlx5_representor_info_get,
1675 .read_clock = mlx5_txpp_read_clock,
1676 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1677 .vlan_filter_set = mlx5_vlan_filter_set,
1678 .rx_queue_setup = mlx5_rx_queue_setup,
1679 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1680 .tx_queue_setup = mlx5_tx_queue_setup,
1681 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1682 .rx_queue_release = mlx5_rx_queue_release,
1683 .tx_queue_release = mlx5_tx_queue_release,
1684 .rx_queue_start = mlx5_rx_queue_start,
1685 .rx_queue_stop = mlx5_rx_queue_stop,
1686 .tx_queue_start = mlx5_tx_queue_start,
1687 .tx_queue_stop = mlx5_tx_queue_stop,
1688 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1689 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1690 .mac_addr_remove = mlx5_mac_addr_remove,
1691 .mac_addr_add = mlx5_mac_addr_add,
1692 .mac_addr_set = mlx5_mac_addr_set,
1693 .set_mc_addr_list = mlx5_set_mc_addr_list,
1694 .mtu_set = mlx5_dev_set_mtu,
1695 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1696 .vlan_offload_set = mlx5_vlan_offload_set,
1697 .reta_update = mlx5_dev_rss_reta_update,
1698 .reta_query = mlx5_dev_rss_reta_query,
1699 .rss_hash_update = mlx5_rss_hash_update,
1700 .rss_hash_conf_get = mlx5_rss_hash_conf_get,
1701 .flow_ops_get = mlx5_flow_ops_get,
1702 .rxq_info_get = mlx5_rxq_info_get,
1703 .txq_info_get = mlx5_txq_info_get,
1704 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1705 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1706 .rx_queue_intr_enable = mlx5_rx_intr_enable,
1707 .rx_queue_intr_disable = mlx5_rx_intr_disable,
1708 .is_removed = mlx5_is_removed,
1709 .udp_tunnel_port_add = mlx5_udp_tunnel_port_add,
1710 .get_module_info = mlx5_get_module_info,
1711 .get_module_eeprom = mlx5_get_module_eeprom,
1712 .hairpin_cap_get = mlx5_hairpin_cap_get,
1713 .mtr_ops_get = mlx5_flow_meter_ops_get,
1714 .hairpin_bind = mlx5_hairpin_bind,
1715 .hairpin_unbind = mlx5_hairpin_unbind,
1716 .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1717 .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1718 .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1719 .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1720 .get_monitor_addr = mlx5_get_monitor_addr,
1723 /* Available operations from secondary process. */
1724 const struct eth_dev_ops mlx5_dev_sec_ops = {
1725 .stats_get = mlx5_stats_get,
1726 .stats_reset = mlx5_stats_reset,
1727 .xstats_get = mlx5_xstats_get,
1728 .xstats_reset = mlx5_xstats_reset,
1729 .xstats_get_names = mlx5_xstats_get_names,
1730 .fw_version_get = mlx5_fw_version_get,
1731 .dev_infos_get = mlx5_dev_infos_get,
1732 .read_clock = mlx5_txpp_read_clock,
1733 .rx_queue_start = mlx5_rx_queue_start,
1734 .rx_queue_stop = mlx5_rx_queue_stop,
1735 .tx_queue_start = mlx5_tx_queue_start,
1736 .tx_queue_stop = mlx5_tx_queue_stop,
1737 .rxq_info_get = mlx5_rxq_info_get,
1738 .txq_info_get = mlx5_txq_info_get,
1739 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1740 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1741 .get_module_info = mlx5_get_module_info,
1742 .get_module_eeprom = mlx5_get_module_eeprom,
1745 /* Available operations in flow isolated mode. */
1746 const struct eth_dev_ops mlx5_dev_ops_isolate = {
1747 .dev_configure = mlx5_dev_configure,
1748 .dev_start = mlx5_dev_start,
1749 .dev_stop = mlx5_dev_stop,
1750 .dev_set_link_down = mlx5_set_link_down,
1751 .dev_set_link_up = mlx5_set_link_up,
1752 .dev_close = mlx5_dev_close,
1753 .promiscuous_enable = mlx5_promiscuous_enable,
1754 .promiscuous_disable = mlx5_promiscuous_disable,
1755 .allmulticast_enable = mlx5_allmulticast_enable,
1756 .allmulticast_disable = mlx5_allmulticast_disable,
1757 .link_update = mlx5_link_update,
1758 .stats_get = mlx5_stats_get,
1759 .stats_reset = mlx5_stats_reset,
1760 .xstats_get = mlx5_xstats_get,
1761 .xstats_reset = mlx5_xstats_reset,
1762 .xstats_get_names = mlx5_xstats_get_names,
1763 .fw_version_get = mlx5_fw_version_get,
1764 .dev_infos_get = mlx5_dev_infos_get,
1765 .read_clock = mlx5_txpp_read_clock,
1766 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1767 .vlan_filter_set = mlx5_vlan_filter_set,
1768 .rx_queue_setup = mlx5_rx_queue_setup,
1769 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1770 .tx_queue_setup = mlx5_tx_queue_setup,
1771 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1772 .rx_queue_release = mlx5_rx_queue_release,
1773 .tx_queue_release = mlx5_tx_queue_release,
1774 .rx_queue_start = mlx5_rx_queue_start,
1775 .rx_queue_stop = mlx5_rx_queue_stop,
1776 .tx_queue_start = mlx5_tx_queue_start,
1777 .tx_queue_stop = mlx5_tx_queue_stop,
1778 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1779 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1780 .mac_addr_remove = mlx5_mac_addr_remove,
1781 .mac_addr_add = mlx5_mac_addr_add,
1782 .mac_addr_set = mlx5_mac_addr_set,
1783 .set_mc_addr_list = mlx5_set_mc_addr_list,
1784 .mtu_set = mlx5_dev_set_mtu,
1785 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1786 .vlan_offload_set = mlx5_vlan_offload_set,
1787 .flow_ops_get = mlx5_flow_ops_get,
1788 .rxq_info_get = mlx5_rxq_info_get,
1789 .txq_info_get = mlx5_txq_info_get,
1790 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1791 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1792 .rx_queue_intr_enable = mlx5_rx_intr_enable,
1793 .rx_queue_intr_disable = mlx5_rx_intr_disable,
1794 .is_removed = mlx5_is_removed,
1795 .get_module_info = mlx5_get_module_info,
1796 .get_module_eeprom = mlx5_get_module_eeprom,
1797 .hairpin_cap_get = mlx5_hairpin_cap_get,
1798 .mtr_ops_get = mlx5_flow_meter_ops_get,
1799 .hairpin_bind = mlx5_hairpin_bind,
1800 .hairpin_unbind = mlx5_hairpin_unbind,
1801 .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1802 .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1803 .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1804 .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1805 .get_monitor_addr = mlx5_get_monitor_addr,
1809 * Verify and store value for device argument.
1812 * Key argument to verify.
1814 * Value associated with key.
1819 * 0 on success, a negative errno value otherwise and rte_errno is set.
1822 mlx5_args_check(const char *key, const char *val, void *opaque)
1824 struct mlx5_dev_config *config = opaque;
1828 /* No-op, port representors are processed in mlx5_dev_spawn(). */
1829 if (!strcmp(MLX5_REPRESENTOR, key))
1832 tmp = strtol(val, NULL, 0);
1835 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1838 if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
1839 /* Negative values are acceptable for some keys only. */
1841 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
1844 mod = tmp >= 0 ? tmp : -tmp;
1845 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1846 if (tmp > MLX5_CQE_RESP_FORMAT_L34H_STRIDX) {
1847 DRV_LOG(ERR, "invalid CQE compression "
1848 "format parameter");
1852 config->cqe_comp = !!tmp;
1853 config->cqe_comp_fmt = tmp;
1854 } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1855 config->hw_padding = !!tmp;
1856 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1857 config->mprq.enabled = !!tmp;
1858 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1859 config->mprq.stride_num_n = tmp;
1860 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1861 config->mprq.stride_size_n = tmp;
1862 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1863 config->mprq.max_memcpy_len = tmp;
1864 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1865 config->mprq.min_rxqs_num = tmp;
1866 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1867 DRV_LOG(WARNING, "%s: deprecated parameter,"
1868 " converted to txq_inline_max", key);
1869 config->txq_inline_max = tmp;
1870 } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1871 config->txq_inline_max = tmp;
1872 } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1873 config->txq_inline_min = tmp;
1874 } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1875 config->txq_inline_mpw = tmp;
1876 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1877 config->txqs_inline = tmp;
1878 } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1879 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1880 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1881 config->mps = !!tmp;
1882 } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1883 if (tmp != MLX5_TXDB_CACHED &&
1884 tmp != MLX5_TXDB_NCACHED &&
1885 tmp != MLX5_TXDB_HEURISTIC) {
1886 DRV_LOG(ERR, "invalid Tx doorbell "
1887 "mapping parameter");
1892 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1893 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1894 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1895 DRV_LOG(WARNING, "%s: deprecated parameter,"
1896 " converted to txq_inline_mpw", key);
1897 config->txq_inline_mpw = tmp;
1898 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1899 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1900 } else if (strcmp(MLX5_TX_PP, key) == 0) {
1902 DRV_LOG(ERR, "Zero Tx packet pacing parameter");
1906 config->tx_pp = tmp;
1907 } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
1908 config->tx_skew = tmp;
1909 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1910 config->rx_vec_en = !!tmp;
1911 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1912 config->l3_vxlan_en = !!tmp;
1913 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1914 config->vf_nl_en = !!tmp;
1915 } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1916 config->dv_esw_en = !!tmp;
1917 } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1918 config->dv_flow_en = !!tmp;
1919 } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1920 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1921 tmp != MLX5_XMETA_MODE_META16 &&
1922 tmp != MLX5_XMETA_MODE_META32 &&
1923 tmp != MLX5_XMETA_MODE_MISS_INFO) {
1924 DRV_LOG(ERR, "invalid extensive "
1925 "metadata parameter");
1929 if (tmp != MLX5_XMETA_MODE_MISS_INFO)
1930 config->dv_xmeta_en = tmp;
1932 config->dv_miss_info = 1;
1933 } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
1934 config->lacp_by_user = !!tmp;
1935 } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1936 config->mr_ext_memseg_en = !!tmp;
1937 } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1938 config->max_dump_files_num = tmp;
1939 } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1940 config->lro.timeout = tmp;
1941 } else if (strcmp(RTE_DEVARGS_KEY_CLASS, key) == 0) {
1942 DRV_LOG(DEBUG, "class argument is %s.", val);
1943 } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1944 config->log_hp_size = tmp;
1945 } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1946 if (tmp != MLX5_RCM_NONE &&
1947 tmp != MLX5_RCM_LIGHT &&
1948 tmp != MLX5_RCM_AGGR) {
1949 DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1953 config->reclaim_mode = tmp;
1954 } else if (strcmp(MLX5_SYS_MEM_EN, key) == 0) {
1955 config->sys_mem_en = !!tmp;
1956 } else if (strcmp(MLX5_DECAP_EN, key) == 0) {
1957 config->decap_en = !!tmp;
1958 } else if (strcmp(MLX5_ALLOW_DUPLICATE_PATTERN, key) == 0) {
1959 config->allow_duplicate_pattern = !!tmp;
1961 DRV_LOG(WARNING, "%s: unknown parameter", key);
1969 * Parse device parameters.
1972 * Pointer to device configuration structure.
1974 * Device arguments structure.
1977 * 0 on success, a negative errno value otherwise and rte_errno is set.
1980 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1982 const char **params = (const char *[]){
1983 MLX5_RXQ_CQE_COMP_EN,
1984 MLX5_RXQ_PKT_PAD_EN,
1986 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1987 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1988 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1991 MLX5_TXQ_INLINE_MIN,
1992 MLX5_TXQ_INLINE_MAX,
1993 MLX5_TXQ_INLINE_MPW,
1994 MLX5_TXQS_MIN_INLINE,
1997 MLX5_TXQ_MPW_HDR_DSEG_EN,
1998 MLX5_TXQ_MAX_INLINE_LEN,
2010 MLX5_MR_EXT_MEMSEG_EN,
2012 MLX5_MAX_DUMP_FILES_NUM,
2013 MLX5_LRO_TIMEOUT_USEC,
2014 RTE_DEVARGS_KEY_CLASS,
2019 MLX5_ALLOW_DUPLICATE_PATTERN,
2022 struct rte_kvargs *kvlist;
2026 if (devargs == NULL)
2028 /* Following UGLY cast is done to pass checkpatch. */
2029 kvlist = rte_kvargs_parse(devargs->args, params);
2030 if (kvlist == NULL) {
2034 /* Process parameters. */
2035 for (i = 0; (params[i] != NULL); ++i) {
2036 if (rte_kvargs_count(kvlist, params[i])) {
2037 ret = rte_kvargs_process(kvlist, params[i],
2038 mlx5_args_check, config);
2041 rte_kvargs_free(kvlist);
2046 rte_kvargs_free(kvlist);
2051 * Configures the minimal amount of data to inline into WQE
2052 * while sending packets.
2054 * - the txq_inline_min has the maximal priority, if this
2055 * key is specified in devargs
2056 * - if DevX is enabled the inline mode is queried from the
2057 * device (HCA attributes and NIC vport context if needed).
2058 * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
2059 * and none (0 bytes) for other NICs
2062 * Verbs device parameters (name, port, switch_info) to spawn.
2064 * Device configuration parameters.
2067 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
2068 struct mlx5_dev_config *config)
2070 if (config->txq_inline_min != MLX5_ARG_UNSET) {
2071 /* Application defines size of inlined data explicitly. */
2072 switch (spawn->pci_dev->id.device_id) {
2073 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2074 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2075 if (config->txq_inline_min <
2076 (int)MLX5_INLINE_HSIZE_L2) {
2078 "txq_inline_mix aligned to minimal"
2079 " ConnectX-4 required value %d",
2080 (int)MLX5_INLINE_HSIZE_L2);
2081 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2087 if (config->hca_attr.eth_net_offloads) {
2088 /* We have DevX enabled, inline mode queried successfully. */
2089 switch (config->hca_attr.wqe_inline_mode) {
2090 case MLX5_CAP_INLINE_MODE_L2:
2091 /* outer L2 header must be inlined. */
2092 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2094 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
2095 /* No inline data are required by NIC. */
2096 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2097 config->hw_vlan_insert =
2098 config->hca_attr.wqe_vlan_insert;
2099 DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
2101 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
2102 /* inline mode is defined by NIC vport context. */
2103 if (!config->hca_attr.eth_virt)
2105 switch (config->hca_attr.vport_inline_mode) {
2106 case MLX5_INLINE_MODE_NONE:
2107 config->txq_inline_min =
2108 MLX5_INLINE_HSIZE_NONE;
2110 case MLX5_INLINE_MODE_L2:
2111 config->txq_inline_min =
2112 MLX5_INLINE_HSIZE_L2;
2114 case MLX5_INLINE_MODE_IP:
2115 config->txq_inline_min =
2116 MLX5_INLINE_HSIZE_L3;
2118 case MLX5_INLINE_MODE_TCP_UDP:
2119 config->txq_inline_min =
2120 MLX5_INLINE_HSIZE_L4;
2122 case MLX5_INLINE_MODE_INNER_L2:
2123 config->txq_inline_min =
2124 MLX5_INLINE_HSIZE_INNER_L2;
2126 case MLX5_INLINE_MODE_INNER_IP:
2127 config->txq_inline_min =
2128 MLX5_INLINE_HSIZE_INNER_L3;
2130 case MLX5_INLINE_MODE_INNER_TCP_UDP:
2131 config->txq_inline_min =
2132 MLX5_INLINE_HSIZE_INNER_L4;
2138 * We get here if we are unable to deduce
2139 * inline data size with DevX. Try PCI ID
2140 * to determine old NICs.
2142 switch (spawn->pci_dev->id.device_id) {
2143 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2144 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2145 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
2146 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
2147 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2148 config->hw_vlan_insert = 0;
2150 case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
2151 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
2152 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
2153 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
2155 * These NICs support VLAN insertion from WQE and
2156 * report the wqe_vlan_insert flag. But there is the bug
2157 * and PFC control may be broken, so disable feature.
2159 config->hw_vlan_insert = 0;
2160 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2163 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2167 DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
2171 * Configures the metadata mask fields in the shared context.
2174 * Pointer to Ethernet device.
2177 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
2179 struct mlx5_priv *priv = dev->data->dev_private;
2180 struct mlx5_dev_ctx_shared *sh = priv->sh;
2181 uint32_t meta, mark, reg_c0;
2183 reg_c0 = ~priv->vport_meta_mask;
2184 switch (priv->config.dv_xmeta_en) {
2185 case MLX5_XMETA_MODE_LEGACY:
2187 mark = MLX5_FLOW_MARK_MASK;
2189 case MLX5_XMETA_MODE_META16:
2190 meta = reg_c0 >> rte_bsf32(reg_c0);
2191 mark = MLX5_FLOW_MARK_MASK;
2193 case MLX5_XMETA_MODE_META32:
2195 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
2203 if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
2204 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
2205 sh->dv_mark_mask, mark);
2207 sh->dv_mark_mask = mark;
2208 if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
2209 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
2210 sh->dv_meta_mask, meta);
2212 sh->dv_meta_mask = meta;
2213 if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
2214 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
2215 sh->dv_meta_mask, reg_c0);
2217 sh->dv_regc0_mask = reg_c0;
2218 DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
2219 DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
2220 DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
2221 DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
2225 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
2227 static const char *const dynf_names[] = {
2228 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
2229 RTE_MBUF_DYNFLAG_METADATA_NAME,
2230 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
2234 if (n < RTE_DIM(dynf_names))
2236 for (i = 0; i < RTE_DIM(dynf_names); i++) {
2237 if (names[i] == NULL)
2239 strcpy(names[i], dynf_names[i]);
2241 return RTE_DIM(dynf_names);
2245 * Comparison callback to sort device data.
2247 * This is meant to be used with qsort().
2250 * Pointer to pointer to first data object.
2252 * Pointer to pointer to second data object.
2255 * 0 if both objects are equal, less than 0 if the first argument is less
2256 * than the second, greater than 0 otherwise.
2259 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
2260 struct mlx5_dev_config *config)
2262 struct mlx5_dev_ctx_shared *sh = priv->sh;
2263 struct mlx5_dev_config *sh_conf = NULL;
2267 /* Nothing to compare for the single/first device. */
2268 if (sh->refcnt == 1)
2270 /* Find the device with shared context. */
2271 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
2272 struct mlx5_priv *opriv =
2273 rte_eth_devices[port_id].data->dev_private;
2275 if (opriv && opriv != priv && opriv->sh == sh) {
2276 sh_conf = &opriv->config;
2282 if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
2283 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
2284 " for shared %s context", sh->ibdev_name);
2288 if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
2289 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
2290 " for shared %s context", sh->ibdev_name);
2298 * Look for the ethernet device belonging to mlx5 driver.
2300 * @param[in] port_id
2301 * port_id to start looking for device.
2302 * @param[in] pci_dev
2303 * Pointer to the hint PCI device. When device is being probed
2304 * the its siblings (master and preceding representors might
2305 * not have assigned driver yet (because the mlx5_os_pci_probe()
2306 * is not completed yet, for this case match on hint PCI
2307 * device may be used to detect sibling device.
2310 * port_id of found device, RTE_MAX_ETHPORT if not found.
2313 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
2315 while (port_id < RTE_MAX_ETHPORTS) {
2316 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
2318 if (dev->state != RTE_ETH_DEV_UNUSED &&
2320 (dev->device == &pci_dev->device ||
2321 (dev->device->driver &&
2322 dev->device->driver->name &&
2323 !strcmp(dev->device->driver->name, MLX5_PCI_DRIVER_NAME))))
2327 if (port_id >= RTE_MAX_ETHPORTS)
2328 return RTE_MAX_ETHPORTS;
2333 * DPDK callback to remove a PCI device.
2335 * This function removes all Ethernet devices belong to a given PCI device.
2337 * @param[in] pci_dev
2338 * Pointer to the PCI device.
2341 * 0 on success, the function cannot fail.
2344 mlx5_pci_remove(struct rte_pci_device *pci_dev)
2349 RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
2351 * mlx5_dev_close() is not registered to secondary process,
2352 * call the close function explicitly for secondary process.
2354 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
2355 ret |= mlx5_dev_close(&rte_eth_devices[port_id]);
2357 ret |= rte_eth_dev_close(port_id);
2359 return ret == 0 ? 0 : -EIO;
2362 static const struct rte_pci_id mlx5_pci_id_map[] = {
2364 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2365 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
2368 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2369 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
2372 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2373 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
2376 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2377 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
2380 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2381 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
2384 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2385 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
2388 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2389 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
2392 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2393 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
2396 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2397 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
2400 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2401 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
2404 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2405 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
2408 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2409 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
2412 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2413 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
2416 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2417 PCI_DEVICE_ID_MELLANOX_CONNECTXVF)
2420 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2421 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
2424 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2425 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
2428 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2429 PCI_DEVICE_ID_MELLANOX_CONNECTX7)
2432 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2433 PCI_DEVICE_ID_MELLANOX_CONNECTX7BF)
2440 static struct mlx5_pci_driver mlx5_driver = {
2441 .driver_class = MLX5_CLASS_NET,
2444 .name = MLX5_PCI_DRIVER_NAME,
2446 .id_table = mlx5_pci_id_map,
2447 .probe = mlx5_os_pci_probe,
2448 .remove = mlx5_pci_remove,
2449 .dma_map = mlx5_dma_map,
2450 .dma_unmap = mlx5_dma_unmap,
2451 .drv_flags = PCI_DRV_FLAGS,
2455 /* Initialize driver log type. */
2456 RTE_LOG_REGISTER_DEFAULT(mlx5_logtype, NOTICE)
2459 * Driver initialization routine.
2461 RTE_INIT(rte_mlx5_pmd_init)
2463 pthread_mutex_init(&mlx5_dev_ctx_list_mutex, NULL);
2465 /* Build the static tables for Verbs conversion. */
2466 mlx5_set_ptype_table();
2467 mlx5_set_cksum_table();
2468 mlx5_set_swp_types_table();
2470 mlx5_pci_driver_register(&mlx5_driver);
2473 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
2474 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
2475 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");