1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
13 #include <rte_malloc.h>
14 #include <rte_ethdev_driver.h>
15 #include <rte_ethdev_pci.h>
17 #include <rte_bus_pci.h>
18 #include <rte_common.h>
19 #include <rte_kvargs.h>
20 #include <rte_rwlock.h>
21 #include <rte_spinlock.h>
22 #include <rte_string_fns.h>
23 #include <rte_alarm.h>
25 #include <mlx5_glue.h>
26 #include <mlx5_devx_cmds.h>
27 #include <mlx5_common.h>
28 #include <mlx5_common_os.h>
29 #include <mlx5_common_mp.h>
30 #include <mlx5_common_pci.h>
31 #include <mlx5_malloc.h>
33 #include "mlx5_defs.h"
35 #include "mlx5_utils.h"
36 #include "mlx5_rxtx.h"
37 #include "mlx5_autoconf.h"
39 #include "mlx5_flow.h"
40 #include "rte_pmd_mlx5.h"
42 /* Device parameter to enable RX completion queue compression. */
43 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
45 /* Device parameter to enable RX completion entry padding to 128B. */
46 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
48 /* Device parameter to enable padding Rx packet to cacheline size. */
49 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
51 /* Device parameter to enable Multi-Packet Rx queue. */
52 #define MLX5_RX_MPRQ_EN "mprq_en"
54 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
55 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
57 /* Device parameter to configure log 2 of the stride size for MPRQ. */
58 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
60 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
61 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
63 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
64 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
66 /* Device parameter to configure inline send. Deprecated, ignored.*/
67 #define MLX5_TXQ_INLINE "txq_inline"
69 /* Device parameter to limit packet size to inline with ordinary SEND. */
70 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
72 /* Device parameter to configure minimal data size to inline. */
73 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
75 /* Device parameter to limit packet size to inline with Enhanced MPW. */
76 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
79 * Device parameter to configure the number of TX queues threshold for
80 * enabling inline send.
82 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
85 * Device parameter to configure the number of TX queues threshold for
86 * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
88 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
90 /* Device parameter to enable multi-packet send WQEs. */
91 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
94 * Device parameter to force doorbell register mapping
95 * to non-cahed region eliminating the extra write memory barrier.
97 #define MLX5_TX_DB_NC "tx_db_nc"
100 * Device parameter to include 2 dsegs in the title WQEBB.
101 * Deprecated, ignored.
103 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
106 * Device parameter to limit the size of inlining packet.
107 * Deprecated, ignored.
109 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
112 * Device parameter to enable Tx scheduling on timestamps
113 * and specify the packet pacing granularity in nanoseconds.
115 #define MLX5_TX_PP "tx_pp"
118 * Device parameter to specify skew in nanoseconds on Tx datapath,
119 * it represents the time between SQ start WQE processing and
120 * appearing actual packet data on the wire.
122 #define MLX5_TX_SKEW "tx_skew"
125 * Device parameter to enable hardware Tx vector.
126 * Deprecated, ignored (no vectorized Tx routines anymore).
128 #define MLX5_TX_VEC_EN "tx_vec_en"
130 /* Device parameter to enable hardware Rx vector. */
131 #define MLX5_RX_VEC_EN "rx_vec_en"
133 /* Allow L3 VXLAN flow creation. */
134 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
136 /* Activate DV E-Switch flow steering. */
137 #define MLX5_DV_ESW_EN "dv_esw_en"
139 /* Activate DV flow steering. */
140 #define MLX5_DV_FLOW_EN "dv_flow_en"
142 /* Enable extensive flow metadata support. */
143 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
145 /* Device parameter to let the user manage the lacp traffic of bonded device */
146 #define MLX5_LACP_BY_USER "lacp_by_user"
148 /* Activate Netlink support in VF mode. */
149 #define MLX5_VF_NL_EN "vf_nl_en"
151 /* Enable extending memsegs when creating a MR. */
152 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
154 /* Select port representors to instantiate. */
155 #define MLX5_REPRESENTOR "representor"
157 /* Device parameter to configure the maximum number of dump files per queue. */
158 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
160 /* Configure timeout of LRO session (in microseconds). */
161 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
164 * Device parameter to configure the total data buffer size for a single
165 * hairpin queue (logarithm value).
167 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
169 /* Flow memory reclaim mode. */
170 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
172 /* The default memory allocator used in PMD. */
173 #define MLX5_SYS_MEM_EN "sys_mem_en"
174 /* Decap will be used or not. */
175 #define MLX5_DECAP_EN "decap_en"
177 /* Shared memory between primary and secondary processes. */
178 struct mlx5_shared_data *mlx5_shared_data;
180 /** Driver-specific log messages type. */
183 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
184 LIST_HEAD_INITIALIZER();
185 static pthread_mutex_t mlx5_dev_ctx_list_mutex = PTHREAD_MUTEX_INITIALIZER;
187 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
188 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
190 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
196 .malloc = mlx5_malloc,
198 .type = "mlx5_encap_decap_ipool",
201 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
207 .malloc = mlx5_malloc,
209 .type = "mlx5_push_vlan_ipool",
212 .size = sizeof(struct mlx5_flow_dv_tag_resource),
218 .malloc = mlx5_malloc,
220 .type = "mlx5_tag_ipool",
223 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
229 .malloc = mlx5_malloc,
231 .type = "mlx5_port_id_ipool",
234 .size = sizeof(struct mlx5_flow_tbl_data_entry),
240 .malloc = mlx5_malloc,
242 .type = "mlx5_jump_ipool",
246 .size = sizeof(struct mlx5_flow_meter),
252 .malloc = mlx5_malloc,
254 .type = "mlx5_meter_ipool",
257 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
263 .malloc = mlx5_malloc,
265 .type = "mlx5_mcp_ipool",
268 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
274 .malloc = mlx5_malloc,
276 .type = "mlx5_hrxq_ipool",
280 * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
281 * It set in run time according to PCI function configuration.
289 .malloc = mlx5_malloc,
291 .type = "mlx5_flow_handle_ipool",
294 .size = sizeof(struct rte_flow),
298 .malloc = mlx5_malloc,
300 .type = "rte_flow_ipool",
305 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
306 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
308 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
311 * Allocate ID pool structure.
314 * The maximum id can be allocated from the pool.
317 * Pointer to pool object, NULL value otherwise.
319 struct mlx5_flow_id_pool *
320 mlx5_flow_id_pool_alloc(uint32_t max_id)
322 struct mlx5_flow_id_pool *pool;
325 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool),
326 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
328 DRV_LOG(ERR, "can't allocate id pool");
332 mem = mlx5_malloc(MLX5_MEM_ZERO,
333 MLX5_FLOW_MIN_ID_POOL_SIZE * sizeof(uint32_t),
334 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
336 DRV_LOG(ERR, "can't allocate mem for id pool");
340 pool->free_arr = mem;
341 pool->curr = pool->free_arr;
342 pool->last = pool->free_arr + MLX5_FLOW_MIN_ID_POOL_SIZE;
343 pool->base_index = 0;
344 pool->max_id = max_id;
352 * Release ID pool structure.
355 * Pointer to flow id pool object to free.
358 mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool)
360 mlx5_free(pool->free_arr);
368 * Pointer to flow id pool.
373 * 0 on success, error value otherwise.
376 mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id)
378 if (pool->curr == pool->free_arr) {
379 if (pool->base_index == pool->max_id) {
381 DRV_LOG(ERR, "no free id");
384 *id = ++pool->base_index;
387 *id = *(--pool->curr);
395 * Pointer to flow id pool.
400 * 0 on success, error value otherwise.
403 mlx5_flow_id_release(struct mlx5_flow_id_pool *pool, uint32_t id)
409 if (pool->curr == pool->last) {
410 size = pool->curr - pool->free_arr;
411 size2 = size * MLX5_ID_GENERATION_ARRAY_FACTOR;
412 MLX5_ASSERT(size2 > size);
413 mem = mlx5_malloc(0, size2 * sizeof(uint32_t), 0,
416 DRV_LOG(ERR, "can't allocate mem for id pool");
420 memcpy(mem, pool->free_arr, size * sizeof(uint32_t));
421 mlx5_free(pool->free_arr);
422 pool->free_arr = mem;
423 pool->curr = pool->free_arr + size;
424 pool->last = pool->free_arr + size2;
432 * Initialize the shared aging list information per port.
435 * Pointer to mlx5_dev_ctx_shared object.
438 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
441 struct mlx5_age_info *age_info;
443 for (i = 0; i < sh->max_port; i++) {
444 age_info = &sh->port[i].age_info;
446 TAILQ_INIT(&age_info->aged_counters);
447 rte_spinlock_init(&age_info->aged_sl);
448 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
453 * Initialize the counters management structure.
456 * Pointer to mlx5_dev_ctx_shared object to free
459 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
463 memset(&sh->cmng, 0, sizeof(sh->cmng));
464 TAILQ_INIT(&sh->cmng.flow_counters);
465 for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
466 sh->cmng.ccont[i].min_id = MLX5_CNT_BATCH_OFFSET;
467 sh->cmng.ccont[i].max_id = -1;
468 sh->cmng.ccont[i].last_pool_idx = POOL_IDX_INVALID;
469 TAILQ_INIT(&sh->cmng.ccont[i].pool_list);
470 rte_spinlock_init(&sh->cmng.ccont[i].resize_sl);
471 TAILQ_INIT(&sh->cmng.ccont[i].counters);
472 rte_spinlock_init(&sh->cmng.ccont[i].csl);
477 * Destroy all the resources allocated for a counter memory management.
480 * Pointer to the memory management structure.
483 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
485 uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
487 LIST_REMOVE(mng, next);
488 claim_zero(mlx5_devx_cmd_destroy(mng->dm));
489 claim_zero(mlx5_glue->devx_umem_dereg(mng->umem));
494 * Close and release all the resources of the counters management.
497 * Pointer to mlx5_dev_ctx_shared object to free.
500 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
502 struct mlx5_counter_stats_mem_mng *mng;
509 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
510 if (rte_errno != EINPROGRESS)
514 for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
515 struct mlx5_flow_counter_pool *pool;
516 uint32_t batch = !!(i > 1);
518 if (!sh->cmng.ccont[i].pools)
520 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
522 if (batch && pool->min_dcs)
523 claim_zero(mlx5_devx_cmd_destroy
525 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
526 if (MLX5_POOL_GET_CNT(pool, j)->action)
528 (mlx5_glue->destroy_flow_action
531 if (!batch && MLX5_GET_POOL_CNT_EXT
533 claim_zero(mlx5_devx_cmd_destroy
534 (MLX5_GET_POOL_CNT_EXT
537 TAILQ_REMOVE(&sh->cmng.ccont[i].pool_list, pool, next);
539 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
541 mlx5_free(sh->cmng.ccont[i].pools);
543 mng = LIST_FIRST(&sh->cmng.mem_mngs);
545 mlx5_flow_destroy_counter_stat_mem_mng(mng);
546 mng = LIST_FIRST(&sh->cmng.mem_mngs);
548 memset(&sh->cmng, 0, sizeof(sh->cmng));
552 * Initialize the flow resources' indexed mempool.
555 * Pointer to mlx5_dev_ctx_shared object.
557 * Pointer to user dev config.
560 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
561 const struct mlx5_dev_config *config)
564 struct mlx5_indexed_pool_config cfg;
566 for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
567 cfg = mlx5_ipool_cfg[i];
572 * Set MLX5_IPOOL_MLX5_FLOW ipool size
573 * according to PCI function flow configuration.
575 case MLX5_IPOOL_MLX5_FLOW:
576 cfg.size = config->dv_flow_en ?
577 sizeof(struct mlx5_flow_handle) :
578 MLX5_FLOW_HANDLE_VERBS_SIZE;
581 if (config->reclaim_mode)
582 cfg.release_mem_en = 1;
583 sh->ipool[i] = mlx5_ipool_create(&cfg);
588 * Release the flow resources' indexed mempool.
591 * Pointer to mlx5_dev_ctx_shared object.
594 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
598 for (i = 0; i < MLX5_IPOOL_MAX; ++i)
599 mlx5_ipool_destroy(sh->ipool[i]);
603 * Check if dynamic flex parser for eCPRI already exists.
606 * Pointer to Ethernet device structure.
609 * true on exists, false on not.
612 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
614 struct mlx5_priv *priv = dev->data->dev_private;
615 struct mlx5_flex_parser_profiles *prf =
616 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
622 * Allocation of a flex parser for eCPRI. Once created, this parser related
623 * resources will be held until the device is closed.
626 * Pointer to Ethernet device structure.
629 * 0 on success, a negative errno value otherwise and rte_errno is set.
632 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
634 struct mlx5_priv *priv = dev->data->dev_private;
635 struct mlx5_flex_parser_profiles *prf =
636 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
637 struct mlx5_devx_graph_node_attr node = {
638 .modify_field_select = 0,
643 if (!priv->config.hca_attr.parse_graph_flex_node) {
644 DRV_LOG(ERR, "Dynamic flex parser is not supported "
645 "for device %s.", priv->dev_data->name);
648 node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED;
649 /* 8 bytes now: 4B common header + 4B message body header. */
650 node.header_length_base_value = 0x8;
651 /* After MAC layer: Ether / VLAN. */
652 node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC;
653 /* Type of compared condition should be 0xAEFE in the L2 layer. */
654 node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI;
655 /* Sample #0: type in common header. */
656 node.sample[0].flow_match_sample_en = 1;
658 node.sample[0].flow_match_sample_offset_mode = 0x0;
659 /* Only the 2nd byte will be used. */
660 node.sample[0].flow_match_sample_field_base_offset = 0x0;
661 /* Sample #1: message payload. */
662 node.sample[1].flow_match_sample_en = 1;
664 node.sample[1].flow_match_sample_offset_mode = 0x0;
666 * Only the first two bytes will be used right now, and its offset will
667 * start after the common header that with the length of a DW(u32).
669 node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);
670 prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->ctx, &node);
672 DRV_LOG(ERR, "Failed to create flex parser node object.");
673 return (rte_errno == 0) ? -ENODEV : -rte_errno;
676 ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num);
678 DRV_LOG(ERR, "Failed to query sample IDs.");
679 return (rte_errno == 0) ? -ENODEV : -rte_errno;
681 prf->offset[0] = 0x0;
682 prf->offset[1] = sizeof(uint32_t);
683 prf->ids[0] = ids[0];
684 prf->ids[1] = ids[1];
689 * Destroy the flex parser node, including the parser itself, input / output
690 * arcs and DW samples. Resources could be reused then.
693 * Pointer to Ethernet device structure.
696 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
698 struct mlx5_priv *priv = dev->data->dev_private;
699 struct mlx5_flex_parser_profiles *prf =
700 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
703 mlx5_devx_cmd_destroy(prf->obj);
708 * Allocate Rx and Tx UARs in robust fashion.
709 * This routine handles the following UAR allocation issues:
711 * - tries to allocate the UAR with the most appropriate memory
712 * mapping type from the ones supported by the host
714 * - tries to allocate the UAR with non-NULL base address
715 * OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as
716 * UAR base address if UAR was not the first object in the UAR page.
717 * It caused the PMD failure and we should try to get another UAR
718 * till we get the first one with non-NULL base address returned.
721 mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh,
722 const struct mlx5_dev_config *config)
724 uint32_t uar_mapping, retry;
727 for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
728 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
729 /* Control the mapping type according to the settings. */
730 uar_mapping = (config->dbnc == MLX5_TXDB_NCACHED) ?
731 MLX5DV_UAR_ALLOC_TYPE_NC :
732 MLX5DV_UAR_ALLOC_TYPE_BF;
734 RTE_SET_USED(config);
736 * It seems we have no way to control the memory mapping type
737 * for the UAR, the default "Write-Combining" type is supposed.
738 * The UAR initialization on queue creation queries the
739 * actual mapping type done by Verbs/kernel and setups the
740 * PMD datapath accordingly.
744 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->ctx, uar_mapping);
745 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
747 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
748 if (config->dbnc == MLX5_TXDB_CACHED ||
749 config->dbnc == MLX5_TXDB_HEURISTIC)
750 DRV_LOG(WARNING, "Devarg tx_db_nc setting "
751 "is not supported by DevX");
753 * In some environments like virtual machine
754 * the Write Combining mapped might be not supported
755 * and UAR allocation fails. We try "Non-Cached"
756 * mapping for the case. The tx_burst routines take
757 * the UAR mapping type into account on UAR setup
760 DRV_LOG(WARNING, "Failed to allocate Tx DevX UAR (BF)");
761 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
762 sh->tx_uar = mlx5_glue->devx_alloc_uar
763 (sh->ctx, uar_mapping);
764 } else if (!sh->tx_uar &&
765 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_NC) {
766 if (config->dbnc == MLX5_TXDB_NCACHED)
767 DRV_LOG(WARNING, "Devarg tx_db_nc settings "
768 "is not supported by DevX");
770 * If Verbs/kernel does not support "Non-Cached"
771 * try the "Write-Combining".
773 DRV_LOG(WARNING, "Failed to allocate Tx DevX UAR (NC)");
774 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_BF;
775 sh->tx_uar = mlx5_glue->devx_alloc_uar
776 (sh->ctx, uar_mapping);
780 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (BF/NC)");
784 if (sh->tx_uar->base_addr)
787 * The UARs are allocated by rdma_core within the
788 * IB device context, on context closure all UARs
789 * will be freed, should be no memory/object leakage.
791 DRV_LOG(WARNING, "Retrying to allocate Tx DevX UAR");
794 /* Check whether we finally succeeded with valid UAR allocation. */
796 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (NULL base)");
800 for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
802 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
803 (sh->ctx, uar_mapping);
804 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
805 if (!sh->devx_rx_uar &&
806 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
808 * Rx UAR is used to control interrupts only,
809 * should be no datapath noticeable impact,
810 * can try "Non-Cached" mapping safely.
812 DRV_LOG(WARNING, "Failed to allocate Rx DevX UAR (BF)");
813 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
814 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
815 (sh->ctx, uar_mapping);
818 if (!sh->devx_rx_uar) {
819 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (BF/NC)");
823 if (sh->devx_rx_uar->base_addr)
826 * The UARs are allocated by rdma_core within the
827 * IB device context, on context closure all UARs
828 * will be freed, should be no memory/object leakage.
830 DRV_LOG(WARNING, "Retrying to allocate Rx DevX UAR");
831 sh->devx_rx_uar = NULL;
833 /* Check whether we finally succeeded with valid UAR allocation. */
834 if (!sh->devx_rx_uar) {
835 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (NULL base)");
843 * Allocate shared device context. If there is multiport device the
844 * master and representors will share this context, if there is single
845 * port dedicated device, the context will be used by only given
846 * port due to unification.
848 * Routine first searches the context for the specified device name,
849 * if found the shared context assumed and reference counter is incremented.
850 * If no context found the new one is created and initialized with specified
851 * device context and parameters.
854 * Pointer to the device attributes (name, port, etc).
856 * Pointer to device configuration structure.
859 * Pointer to mlx5_dev_ctx_shared object on success,
860 * otherwise NULL and rte_errno is set.
862 struct mlx5_dev_ctx_shared *
863 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
864 const struct mlx5_dev_config *config)
866 struct mlx5_dev_ctx_shared *sh;
869 struct mlx5_devx_tis_attr tis_attr = { 0 };
872 /* Secondary process should not create the shared context. */
873 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
874 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
875 /* Search for IB context by device name. */
876 LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
877 if (!strcmp(sh->ibdev_name,
878 mlx5_os_get_dev_device_name(spawn->phys_dev))) {
883 /* No device found, we have to create new shared context. */
884 MLX5_ASSERT(spawn->max_port);
885 sh = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
886 sizeof(struct mlx5_dev_ctx_shared) +
888 sizeof(struct mlx5_dev_shared_port),
889 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
891 DRV_LOG(ERR, "shared context allocation failure");
895 err = mlx5_os_open_device(spawn, config, sh);
898 err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
900 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
904 sh->max_port = spawn->max_port;
905 strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
906 sizeof(sh->ibdev_name) - 1);
907 strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
908 sizeof(sh->ibdev_path) - 1);
910 * Setting port_id to max unallowed value means
911 * there is no interrupt subhandler installed for
912 * the given port index i.
914 for (i = 0; i < sh->max_port; i++) {
915 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
916 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
918 sh->pd = mlx5_glue->alloc_pd(sh->ctx);
919 if (sh->pd == NULL) {
920 DRV_LOG(ERR, "PD allocation failure");
925 err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
927 DRV_LOG(ERR, "Fail to extract pdn from PD");
930 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
932 DRV_LOG(ERR, "TD allocation failure");
936 tis_attr.transport_domain = sh->td->id;
937 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
939 DRV_LOG(ERR, "TIS allocation failure");
943 err = mlx5_alloc_rxtx_uars(sh, config);
946 MLX5_ASSERT(sh->tx_uar && sh->tx_uar->base_addr);
947 MLX5_ASSERT(sh->devx_rx_uar && sh->devx_rx_uar->base_addr);
949 sh->flow_id_pool = mlx5_flow_id_pool_alloc
950 ((1 << HAIRPIN_FLOW_ID_BITS) - 1);
951 if (!sh->flow_id_pool) {
952 DRV_LOG(ERR, "can't create flow id pool");
957 /* Initialize UAR access locks for 32bit implementations. */
958 rte_spinlock_init(&sh->uar_lock_cq);
959 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
960 rte_spinlock_init(&sh->uar_lock[i]);
963 * Once the device is added to the list of memory event
964 * callback, its global MR cache table cannot be expanded
965 * on the fly because of deadlock. If it overflows, lookup
966 * should be done by searching MR list linearly, which is slow.
968 * At this point the device is not added to the memory
969 * event list yet, context is just being created.
971 err = mlx5_mr_btree_init(&sh->share_cache.cache,
972 MLX5_MR_BTREE_CACHE_N * 2,
973 spawn->pci_dev->device.numa_node);
978 mlx5_os_set_reg_mr_cb(&sh->share_cache.reg_mr_cb,
979 &sh->share_cache.dereg_mr_cb);
980 mlx5_os_dev_shared_handler_install(sh);
981 sh->cnt_id_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_DWORD);
982 if (!sh->cnt_id_tbl) {
986 mlx5_flow_aging_init(sh);
987 mlx5_flow_counters_mng_init(sh);
988 mlx5_flow_ipool_create(sh, config);
989 /* Add device to memory callback list. */
990 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
991 LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
993 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
994 /* Add context to the global device list. */
995 LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
997 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1000 pthread_mutex_destroy(&sh->txpp.mutex);
1001 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1004 mlx5_l3t_destroy(sh->cnt_id_tbl);
1006 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1008 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1009 if (sh->devx_rx_uar)
1010 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1012 mlx5_glue->devx_free_uar(sh->tx_uar);
1014 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
1016 claim_zero(mlx5_glue->close_device(sh->ctx));
1017 if (sh->flow_id_pool)
1018 mlx5_flow_id_pool_release(sh->flow_id_pool);
1020 MLX5_ASSERT(err > 0);
1026 * Free shared IB device context. Decrement counter and if zero free
1027 * all allocated resources and close handles.
1030 * Pointer to mlx5_dev_ctx_shared object to free
1033 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
1035 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1036 #ifdef RTE_LIBRTE_MLX5_DEBUG
1037 /* Check the object presence in the list. */
1038 struct mlx5_dev_ctx_shared *lctx;
1040 LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
1045 DRV_LOG(ERR, "Freeing non-existing shared IB context");
1050 MLX5_ASSERT(sh->refcnt);
1051 /* Secondary process should not free the shared context. */
1052 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1055 /* Remove from memory callback device list. */
1056 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1057 LIST_REMOVE(sh, mem_event_cb);
1058 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1059 /* Release created Memory Regions. */
1060 mlx5_mr_release_cache(&sh->share_cache);
1061 /* Remove context from the global device list. */
1062 LIST_REMOVE(sh, next);
1063 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1065 * Ensure there is no async event handler installed.
1066 * Only primary process handles async device events.
1068 mlx5_flow_counters_mng_close(sh);
1069 mlx5_flow_ipool_destroy(sh);
1070 mlx5_os_dev_shared_handler_uninstall(sh);
1071 if (sh->cnt_id_tbl) {
1072 mlx5_l3t_destroy(sh->cnt_id_tbl);
1073 sh->cnt_id_tbl = NULL;
1076 mlx5_glue->devx_free_uar(sh->tx_uar);
1080 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
1082 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1084 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1085 if (sh->devx_rx_uar)
1086 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1088 claim_zero(mlx5_glue->close_device(sh->ctx));
1089 if (sh->flow_id_pool)
1090 mlx5_flow_id_pool_release(sh->flow_id_pool);
1091 pthread_mutex_destroy(&sh->txpp.mutex);
1095 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1099 * Destroy table hash list and all the root entries per domain.
1102 * Pointer to the private device data structure.
1105 mlx5_free_table_hash_list(struct mlx5_priv *priv)
1107 struct mlx5_dev_ctx_shared *sh = priv->sh;
1108 struct mlx5_flow_tbl_data_entry *tbl_data;
1109 union mlx5_flow_tbl_key table_key = {
1117 struct mlx5_hlist_entry *pos;
1121 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
1123 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
1125 MLX5_ASSERT(tbl_data);
1126 mlx5_hlist_remove(sh->flow_tbls, pos);
1127 mlx5_free(tbl_data);
1129 table_key.direction = 1;
1130 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
1132 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
1134 MLX5_ASSERT(tbl_data);
1135 mlx5_hlist_remove(sh->flow_tbls, pos);
1136 mlx5_free(tbl_data);
1138 table_key.direction = 0;
1139 table_key.domain = 1;
1140 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
1142 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
1144 MLX5_ASSERT(tbl_data);
1145 mlx5_hlist_remove(sh->flow_tbls, pos);
1146 mlx5_free(tbl_data);
1148 mlx5_hlist_destroy(sh->flow_tbls, NULL, NULL);
1152 * Initialize flow table hash list and create the root tables entry
1156 * Pointer to the private device data structure.
1159 * Zero on success, positive error code otherwise.
1162 mlx5_alloc_table_hash_list(struct mlx5_priv *priv)
1164 struct mlx5_dev_ctx_shared *sh = priv->sh;
1165 char s[MLX5_HLIST_NAMESIZE];
1169 snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1170 sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE);
1171 if (!sh->flow_tbls) {
1172 DRV_LOG(ERR, "flow tables with hash creation failed.");
1176 #ifndef HAVE_MLX5DV_DR
1178 * In case we have not DR support, the zero tables should be created
1179 * because DV expect to see them even if they cannot be created by
1182 union mlx5_flow_tbl_key table_key = {
1190 struct mlx5_flow_tbl_data_entry *tbl_data = mlx5_malloc(MLX5_MEM_ZERO,
1191 sizeof(*tbl_data), 0,
1198 tbl_data->entry.key = table_key.v64;
1199 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1202 rte_atomic32_init(&tbl_data->tbl.refcnt);
1203 rte_atomic32_inc(&tbl_data->tbl.refcnt);
1204 table_key.direction = 1;
1205 tbl_data = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tbl_data), 0,
1211 tbl_data->entry.key = table_key.v64;
1212 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1215 rte_atomic32_init(&tbl_data->tbl.refcnt);
1216 rte_atomic32_inc(&tbl_data->tbl.refcnt);
1217 table_key.direction = 0;
1218 table_key.domain = 1;
1219 tbl_data = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tbl_data), 0,
1225 tbl_data->entry.key = table_key.v64;
1226 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1229 rte_atomic32_init(&tbl_data->tbl.refcnt);
1230 rte_atomic32_inc(&tbl_data->tbl.refcnt);
1233 mlx5_free_table_hash_list(priv);
1234 #endif /* HAVE_MLX5DV_DR */
1239 * Retrieve integer value from environment variable.
1242 * Environment variable name.
1245 * Integer value, 0 if the variable is not set.
1248 mlx5_getenv_int(const char *name)
1250 const char *val = getenv(name);
1258 * DPDK callback to add udp tunnel port
1261 * A pointer to eth_dev
1262 * @param[in] udp_tunnel
1263 * A pointer to udp tunnel
1266 * 0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1269 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1270 struct rte_eth_udp_tunnel *udp_tunnel)
1272 MLX5_ASSERT(udp_tunnel != NULL);
1273 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1274 udp_tunnel->udp_port == 4789)
1276 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1277 udp_tunnel->udp_port == 4790)
1283 * Initialize process private data structure.
1286 * Pointer to Ethernet device structure.
1289 * 0 on success, a negative errno value otherwise and rte_errno is set.
1292 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1294 struct mlx5_priv *priv = dev->data->dev_private;
1295 struct mlx5_proc_priv *ppriv;
1299 * UAR register table follows the process private structure. BlueFlame
1300 * registers for Tx queues are stored in the table.
1303 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1304 ppriv = mlx5_malloc(MLX5_MEM_RTE, ppriv_size, RTE_CACHE_LINE_SIZE,
1305 dev->device->numa_node);
1310 ppriv->uar_table_sz = ppriv_size;
1311 dev->process_private = ppriv;
1316 * Un-initialize process private data structure.
1319 * Pointer to Ethernet device structure.
1322 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1324 if (!dev->process_private)
1326 mlx5_free(dev->process_private);
1327 dev->process_private = NULL;
1331 * DPDK callback to close the device.
1333 * Destroy all queues and objects, free memory.
1336 * Pointer to Ethernet device structure.
1339 mlx5_dev_close(struct rte_eth_dev *dev)
1341 struct mlx5_priv *priv = dev->data->dev_private;
1345 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1346 /* Check if process_private released. */
1347 if (!dev->process_private)
1349 mlx5_tx_uar_uninit_secondary(dev);
1350 mlx5_proc_priv_uninit(dev);
1351 rte_eth_dev_release_port(dev);
1356 DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1358 ((priv->sh->ctx != NULL) ?
1359 mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
1361 * If default mreg copy action is removed at the stop stage,
1362 * the search will return none and nothing will be done anymore.
1364 mlx5_flow_stop_default(dev);
1365 mlx5_traffic_disable(dev);
1367 * If all the flows are already flushed in the device stop stage,
1368 * then this will return directly without any action.
1370 mlx5_flow_list_flush(dev, &priv->flows, true);
1371 mlx5_flow_meter_flush(dev, NULL);
1372 /* Free the intermediate buffers for flow creation. */
1373 mlx5_flow_free_intermediate(dev);
1374 /* Prevent crashes when queues are still in use. */
1375 dev->rx_pkt_burst = removed_rx_burst;
1376 dev->tx_pkt_burst = removed_tx_burst;
1378 /* Disable datapath on secondary process. */
1379 mlx5_mp_os_req_stop_rxtx(dev);
1380 /* Free the eCPRI flex parser resource. */
1381 mlx5_flex_parser_ecpri_release(dev);
1382 if (priv->rxqs != NULL) {
1383 /* XXX race condition if mlx5_rx_burst() is still running. */
1385 for (i = 0; (i != priv->rxqs_n); ++i)
1386 mlx5_rxq_release(dev, i);
1390 if (priv->txqs != NULL) {
1391 /* XXX race condition if mlx5_tx_burst() is still running. */
1393 for (i = 0; (i != priv->txqs_n); ++i)
1394 mlx5_txq_release(dev, i);
1398 mlx5_proc_priv_uninit(dev);
1399 if (priv->mreg_cp_tbl)
1400 mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
1401 mlx5_mprq_free_mp(dev);
1402 mlx5_os_free_shared_dr(priv);
1403 if (priv->rss_conf.rss_key != NULL)
1404 mlx5_free(priv->rss_conf.rss_key);
1405 if (priv->reta_idx != NULL)
1406 mlx5_free(priv->reta_idx);
1407 if (priv->config.vf)
1408 mlx5_os_mac_addr_flush(dev);
1409 if (priv->nl_socket_route >= 0)
1410 close(priv->nl_socket_route);
1411 if (priv->nl_socket_rdma >= 0)
1412 close(priv->nl_socket_rdma);
1413 if (priv->vmwa_context)
1414 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1415 ret = mlx5_hrxq_verify(dev);
1417 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1418 dev->data->port_id);
1419 ret = mlx5_ind_table_obj_verify(dev);
1421 DRV_LOG(WARNING, "port %u some indirection table still remain",
1422 dev->data->port_id);
1423 ret = mlx5_rxq_obj_verify(dev);
1425 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1426 dev->data->port_id);
1427 ret = mlx5_rxq_verify(dev);
1429 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1430 dev->data->port_id);
1431 ret = mlx5_txq_obj_verify(dev);
1433 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1434 dev->data->port_id);
1435 ret = mlx5_txq_verify(dev);
1437 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1438 dev->data->port_id);
1439 ret = mlx5_flow_verify(dev);
1441 DRV_LOG(WARNING, "port %u some flows still remain",
1442 dev->data->port_id);
1444 * Free the shared context in last turn, because the cleanup
1445 * routines above may use some shared fields, like
1446 * mlx5_os_mac_addr_flush() uses ibdev_path for retrieveing
1447 * ifindex if Netlink fails.
1449 mlx5_free_shared_dev_ctx(priv->sh);
1450 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1454 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1455 struct mlx5_priv *opriv =
1456 rte_eth_devices[port_id].data->dev_private;
1459 opriv->domain_id != priv->domain_id ||
1460 &rte_eth_devices[port_id] == dev)
1466 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1468 memset(priv, 0, sizeof(*priv));
1469 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1471 * Reset mac_addrs to NULL such that it is not freed as part of
1472 * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1473 * it is freed when dev_private is freed.
1475 dev->data->mac_addrs = NULL;
1479 * Verify and store value for device argument.
1482 * Key argument to verify.
1484 * Value associated with key.
1489 * 0 on success, a negative errno value otherwise and rte_errno is set.
1492 mlx5_args_check(const char *key, const char *val, void *opaque)
1494 struct mlx5_dev_config *config = opaque;
1498 /* No-op, port representors are processed in mlx5_dev_spawn(). */
1499 if (!strcmp(MLX5_REPRESENTOR, key))
1502 tmp = strtol(val, NULL, 0);
1505 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1508 if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
1509 /* Negative values are acceptable for some keys only. */
1511 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
1514 mod = tmp >= 0 ? tmp : -tmp;
1515 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1516 config->cqe_comp = !!tmp;
1517 } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
1518 config->cqe_pad = !!tmp;
1519 } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1520 config->hw_padding = !!tmp;
1521 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1522 config->mprq.enabled = !!tmp;
1523 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1524 config->mprq.stride_num_n = tmp;
1525 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1526 config->mprq.stride_size_n = tmp;
1527 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1528 config->mprq.max_memcpy_len = tmp;
1529 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1530 config->mprq.min_rxqs_num = tmp;
1531 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1532 DRV_LOG(WARNING, "%s: deprecated parameter,"
1533 " converted to txq_inline_max", key);
1534 config->txq_inline_max = tmp;
1535 } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1536 config->txq_inline_max = tmp;
1537 } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1538 config->txq_inline_min = tmp;
1539 } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1540 config->txq_inline_mpw = tmp;
1541 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1542 config->txqs_inline = tmp;
1543 } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1544 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1545 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1546 config->mps = !!tmp;
1547 } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1548 if (tmp != MLX5_TXDB_CACHED &&
1549 tmp != MLX5_TXDB_NCACHED &&
1550 tmp != MLX5_TXDB_HEURISTIC) {
1551 DRV_LOG(ERR, "invalid Tx doorbell "
1552 "mapping parameter");
1557 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1558 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1559 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1560 DRV_LOG(WARNING, "%s: deprecated parameter,"
1561 " converted to txq_inline_mpw", key);
1562 config->txq_inline_mpw = tmp;
1563 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1564 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1565 } else if (strcmp(MLX5_TX_PP, key) == 0) {
1567 DRV_LOG(ERR, "Zero Tx packet pacing parameter");
1571 config->tx_pp = tmp;
1572 } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
1573 config->tx_skew = tmp;
1574 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1575 config->rx_vec_en = !!tmp;
1576 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1577 config->l3_vxlan_en = !!tmp;
1578 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1579 config->vf_nl_en = !!tmp;
1580 } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1581 config->dv_esw_en = !!tmp;
1582 } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1583 config->dv_flow_en = !!tmp;
1584 } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1585 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1586 tmp != MLX5_XMETA_MODE_META16 &&
1587 tmp != MLX5_XMETA_MODE_META32) {
1588 DRV_LOG(ERR, "invalid extensive "
1589 "metadata parameter");
1593 config->dv_xmeta_en = tmp;
1594 } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
1595 config->lacp_by_user = !!tmp;
1596 } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1597 config->mr_ext_memseg_en = !!tmp;
1598 } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1599 config->max_dump_files_num = tmp;
1600 } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1601 config->lro.timeout = tmp;
1602 } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1603 DRV_LOG(DEBUG, "class argument is %s.", val);
1604 } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1605 config->log_hp_size = tmp;
1606 } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1607 if (tmp != MLX5_RCM_NONE &&
1608 tmp != MLX5_RCM_LIGHT &&
1609 tmp != MLX5_RCM_AGGR) {
1610 DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1614 config->reclaim_mode = tmp;
1615 } else if (strcmp(MLX5_SYS_MEM_EN, key) == 0) {
1616 config->sys_mem_en = !!tmp;
1617 } else if (strcmp(MLX5_DECAP_EN, key) == 0) {
1618 config->decap_en = !!tmp;
1620 DRV_LOG(WARNING, "%s: unknown parameter", key);
1628 * Parse device parameters.
1631 * Pointer to device configuration structure.
1633 * Device arguments structure.
1636 * 0 on success, a negative errno value otherwise and rte_errno is set.
1639 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1641 const char **params = (const char *[]){
1642 MLX5_RXQ_CQE_COMP_EN,
1643 MLX5_RXQ_CQE_PAD_EN,
1644 MLX5_RXQ_PKT_PAD_EN,
1646 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1647 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1648 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1651 MLX5_TXQ_INLINE_MIN,
1652 MLX5_TXQ_INLINE_MAX,
1653 MLX5_TXQ_INLINE_MPW,
1654 MLX5_TXQS_MIN_INLINE,
1657 MLX5_TXQ_MPW_HDR_DSEG_EN,
1658 MLX5_TXQ_MAX_INLINE_LEN,
1670 MLX5_MR_EXT_MEMSEG_EN,
1672 MLX5_MAX_DUMP_FILES_NUM,
1673 MLX5_LRO_TIMEOUT_USEC,
1674 MLX5_CLASS_ARG_NAME,
1681 struct rte_kvargs *kvlist;
1685 if (devargs == NULL)
1687 /* Following UGLY cast is done to pass checkpatch. */
1688 kvlist = rte_kvargs_parse(devargs->args, params);
1689 if (kvlist == NULL) {
1693 /* Process parameters. */
1694 for (i = 0; (params[i] != NULL); ++i) {
1695 if (rte_kvargs_count(kvlist, params[i])) {
1696 ret = rte_kvargs_process(kvlist, params[i],
1697 mlx5_args_check, config);
1700 rte_kvargs_free(kvlist);
1705 rte_kvargs_free(kvlist);
1710 * Configures the minimal amount of data to inline into WQE
1711 * while sending packets.
1713 * - the txq_inline_min has the maximal priority, if this
1714 * key is specified in devargs
1715 * - if DevX is enabled the inline mode is queried from the
1716 * device (HCA attributes and NIC vport context if needed).
1717 * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1718 * and none (0 bytes) for other NICs
1721 * Verbs device parameters (name, port, switch_info) to spawn.
1723 * Device configuration parameters.
1726 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1727 struct mlx5_dev_config *config)
1729 if (config->txq_inline_min != MLX5_ARG_UNSET) {
1730 /* Application defines size of inlined data explicitly. */
1731 switch (spawn->pci_dev->id.device_id) {
1732 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1733 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1734 if (config->txq_inline_min <
1735 (int)MLX5_INLINE_HSIZE_L2) {
1737 "txq_inline_mix aligned to minimal"
1738 " ConnectX-4 required value %d",
1739 (int)MLX5_INLINE_HSIZE_L2);
1740 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1746 if (config->hca_attr.eth_net_offloads) {
1747 /* We have DevX enabled, inline mode queried successfully. */
1748 switch (config->hca_attr.wqe_inline_mode) {
1749 case MLX5_CAP_INLINE_MODE_L2:
1750 /* outer L2 header must be inlined. */
1751 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1753 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1754 /* No inline data are required by NIC. */
1755 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1756 config->hw_vlan_insert =
1757 config->hca_attr.wqe_vlan_insert;
1758 DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1760 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1761 /* inline mode is defined by NIC vport context. */
1762 if (!config->hca_attr.eth_virt)
1764 switch (config->hca_attr.vport_inline_mode) {
1765 case MLX5_INLINE_MODE_NONE:
1766 config->txq_inline_min =
1767 MLX5_INLINE_HSIZE_NONE;
1769 case MLX5_INLINE_MODE_L2:
1770 config->txq_inline_min =
1771 MLX5_INLINE_HSIZE_L2;
1773 case MLX5_INLINE_MODE_IP:
1774 config->txq_inline_min =
1775 MLX5_INLINE_HSIZE_L3;
1777 case MLX5_INLINE_MODE_TCP_UDP:
1778 config->txq_inline_min =
1779 MLX5_INLINE_HSIZE_L4;
1781 case MLX5_INLINE_MODE_INNER_L2:
1782 config->txq_inline_min =
1783 MLX5_INLINE_HSIZE_INNER_L2;
1785 case MLX5_INLINE_MODE_INNER_IP:
1786 config->txq_inline_min =
1787 MLX5_INLINE_HSIZE_INNER_L3;
1789 case MLX5_INLINE_MODE_INNER_TCP_UDP:
1790 config->txq_inline_min =
1791 MLX5_INLINE_HSIZE_INNER_L4;
1797 * We get here if we are unable to deduce
1798 * inline data size with DevX. Try PCI ID
1799 * to determine old NICs.
1801 switch (spawn->pci_dev->id.device_id) {
1802 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1803 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1804 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
1805 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1806 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1807 config->hw_vlan_insert = 0;
1809 case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
1810 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1811 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
1812 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1814 * These NICs support VLAN insertion from WQE and
1815 * report the wqe_vlan_insert flag. But there is the bug
1816 * and PFC control may be broken, so disable feature.
1818 config->hw_vlan_insert = 0;
1819 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1822 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1826 DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
1830 * Configures the metadata mask fields in the shared context.
1833 * Pointer to Ethernet device.
1836 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
1838 struct mlx5_priv *priv = dev->data->dev_private;
1839 struct mlx5_dev_ctx_shared *sh = priv->sh;
1840 uint32_t meta, mark, reg_c0;
1842 reg_c0 = ~priv->vport_meta_mask;
1843 switch (priv->config.dv_xmeta_en) {
1844 case MLX5_XMETA_MODE_LEGACY:
1846 mark = MLX5_FLOW_MARK_MASK;
1848 case MLX5_XMETA_MODE_META16:
1849 meta = reg_c0 >> rte_bsf32(reg_c0);
1850 mark = MLX5_FLOW_MARK_MASK;
1852 case MLX5_XMETA_MODE_META32:
1854 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
1862 if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
1863 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
1864 sh->dv_mark_mask, mark);
1866 sh->dv_mark_mask = mark;
1867 if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
1868 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
1869 sh->dv_meta_mask, meta);
1871 sh->dv_meta_mask = meta;
1872 if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
1873 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
1874 sh->dv_meta_mask, reg_c0);
1876 sh->dv_regc0_mask = reg_c0;
1877 DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
1878 DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
1879 DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
1880 DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
1884 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
1886 static const char *const dynf_names[] = {
1887 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
1888 RTE_MBUF_DYNFLAG_METADATA_NAME,
1889 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
1893 if (n < RTE_DIM(dynf_names))
1895 for (i = 0; i < RTE_DIM(dynf_names); i++) {
1896 if (names[i] == NULL)
1898 strcpy(names[i], dynf_names[i]);
1900 return RTE_DIM(dynf_names);
1904 * Comparison callback to sort device data.
1906 * This is meant to be used with qsort().
1909 * Pointer to pointer to first data object.
1911 * Pointer to pointer to second data object.
1914 * 0 if both objects are equal, less than 0 if the first argument is less
1915 * than the second, greater than 0 otherwise.
1918 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
1919 struct mlx5_dev_config *config)
1921 struct mlx5_dev_ctx_shared *sh = priv->sh;
1922 struct mlx5_dev_config *sh_conf = NULL;
1926 /* Nothing to compare for the single/first device. */
1927 if (sh->refcnt == 1)
1929 /* Find the device with shared context. */
1930 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1931 struct mlx5_priv *opriv =
1932 rte_eth_devices[port_id].data->dev_private;
1934 if (opriv && opriv != priv && opriv->sh == sh) {
1935 sh_conf = &opriv->config;
1941 if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
1942 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
1943 " for shared %s context", sh->ibdev_name);
1947 if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
1948 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
1949 " for shared %s context", sh->ibdev_name);
1957 * Look for the ethernet device belonging to mlx5 driver.
1959 * @param[in] port_id
1960 * port_id to start looking for device.
1961 * @param[in] pci_dev
1962 * Pointer to the hint PCI device. When device is being probed
1963 * the its siblings (master and preceding representors might
1964 * not have assigned driver yet (because the mlx5_os_pci_probe()
1965 * is not completed yet, for this case match on hint PCI
1966 * device may be used to detect sibling device.
1969 * port_id of found device, RTE_MAX_ETHPORT if not found.
1972 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
1974 while (port_id < RTE_MAX_ETHPORTS) {
1975 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
1977 if (dev->state != RTE_ETH_DEV_UNUSED &&
1979 (dev->device == &pci_dev->device ||
1980 (dev->device->driver &&
1981 dev->device->driver->name &&
1982 !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
1986 if (port_id >= RTE_MAX_ETHPORTS)
1987 return RTE_MAX_ETHPORTS;
1992 * DPDK callback to remove a PCI device.
1994 * This function removes all Ethernet devices belong to a given PCI device.
1996 * @param[in] pci_dev
1997 * Pointer to the PCI device.
2000 * 0 on success, the function cannot fail.
2003 mlx5_pci_remove(struct rte_pci_device *pci_dev)
2007 RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
2009 * mlx5_dev_close() is not registered to secondary process,
2010 * call the close function explicitly for secondary process.
2012 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
2013 mlx5_dev_close(&rte_eth_devices[port_id]);
2015 rte_eth_dev_close(port_id);
2020 static const struct rte_pci_id mlx5_pci_id_map[] = {
2022 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2023 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
2026 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2027 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
2030 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2031 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
2034 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2035 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
2038 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2039 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
2042 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2043 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
2046 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2047 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
2050 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2051 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
2054 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2055 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
2058 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2059 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
2062 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2063 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
2066 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2067 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
2070 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2071 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
2074 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2075 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF)
2078 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2079 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
2082 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2083 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
2090 static struct mlx5_pci_driver mlx5_driver = {
2091 .driver_class = MLX5_CLASS_NET,
2094 .name = MLX5_DRIVER_NAME,
2096 .id_table = mlx5_pci_id_map,
2097 .probe = mlx5_os_pci_probe,
2098 .remove = mlx5_pci_remove,
2099 .dma_map = mlx5_dma_map,
2100 .dma_unmap = mlx5_dma_unmap,
2101 .drv_flags = PCI_DRV_FLAGS,
2105 /* Initialize driver log type. */
2106 RTE_LOG_REGISTER(mlx5_logtype, pmd.net.mlx5, NOTICE)
2109 * Driver initialization routine.
2111 RTE_INIT(rte_mlx5_pmd_init)
2114 /* Build the static tables for Verbs conversion. */
2115 mlx5_set_ptype_table();
2116 mlx5_set_cksum_table();
2117 mlx5_set_swp_types_table();
2119 mlx5_pci_driver_register(&mlx5_driver);
2122 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
2123 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
2124 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");