1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
16 #include <linux/netlink.h>
17 #include <linux/rtnetlink.h>
20 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
22 #pragma GCC diagnostic ignored "-Wpedantic"
24 #include <infiniband/verbs.h>
26 #pragma GCC diagnostic error "-Wpedantic"
29 #include <rte_malloc.h>
30 #include <rte_ethdev_driver.h>
31 #include <rte_ethdev_pci.h>
33 #include <rte_bus_pci.h>
34 #include <rte_common.h>
35 #include <rte_config.h>
36 #include <rte_eal_memconfig.h>
37 #include <rte_kvargs.h>
38 #include <rte_rwlock.h>
39 #include <rte_spinlock.h>
40 #include <rte_string_fns.h>
43 #include "mlx5_utils.h"
44 #include "mlx5_rxtx.h"
45 #include "mlx5_autoconf.h"
46 #include "mlx5_defs.h"
47 #include "mlx5_glue.h"
49 #include "mlx5_flow.h"
51 /* Device parameter to enable RX completion queue compression. */
52 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
54 /* Device parameter to enable RX completion entry padding to 128B. */
55 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
57 /* Device parameter to enable Multi-Packet Rx queue. */
58 #define MLX5_RX_MPRQ_EN "mprq_en"
60 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
61 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
63 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
64 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
66 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
67 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
69 /* Device parameter to configure inline send. */
70 #define MLX5_TXQ_INLINE "txq_inline"
73 * Device parameter to configure the number of TX queues threshold for
74 * enabling inline send.
76 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
79 * Device parameter to configure the number of TX queues threshold for
80 * enabling vectorized Tx.
82 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
84 /* Device parameter to enable multi-packet send WQEs. */
85 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
87 /* Device parameter to include 2 dsegs in the title WQEBB. */
88 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
90 /* Device parameter to limit the size of inlining packet. */
91 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
93 /* Device parameter to enable hardware Tx vector. */
94 #define MLX5_TX_VEC_EN "tx_vec_en"
96 /* Device parameter to enable hardware Rx vector. */
97 #define MLX5_RX_VEC_EN "rx_vec_en"
99 /* Allow L3 VXLAN flow creation. */
100 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
102 /* Activate DV flow steering. */
103 #define MLX5_DV_FLOW_EN "dv_flow_en"
105 /* Activate Netlink support in VF mode. */
106 #define MLX5_VF_NL_EN "vf_nl_en"
108 /* Select port representors to instantiate. */
109 #define MLX5_REPRESENTOR "representor"
111 #ifndef HAVE_IBV_MLX5_MOD_MPW
112 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2)
113 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3)
116 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP
117 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4)
120 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
122 /* Shared memory between primary and secondary processes. */
123 struct mlx5_shared_data *mlx5_shared_data;
125 /* Spinlock for mlx5_shared_data allocation. */
126 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
128 /** Driver-specific log messages type. */
132 * Prepare shared data between primary and secondary process.
135 mlx5_prepare_shared_data(void)
137 const struct rte_memzone *mz;
139 rte_spinlock_lock(&mlx5_shared_data_lock);
140 if (mlx5_shared_data == NULL) {
141 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
142 /* Allocate shared memory. */
143 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
144 sizeof(*mlx5_shared_data),
147 /* Lookup allocated shared memory. */
148 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA);
151 rte_panic("Cannot allocate mlx5 shared data\n");
152 mlx5_shared_data = mz->addr;
153 /* Initialize shared data. */
154 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
155 LIST_INIT(&mlx5_shared_data->mem_event_cb_list);
156 rte_rwlock_init(&mlx5_shared_data->mem_event_rwlock);
158 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
159 mlx5_mr_mem_event_cb, NULL);
161 rte_spinlock_unlock(&mlx5_shared_data_lock);
165 * Retrieve integer value from environment variable.
168 * Environment variable name.
171 * Integer value, 0 if the variable is not set.
174 mlx5_getenv_int(const char *name)
176 const char *val = getenv(name);
184 * Verbs callback to allocate a memory. This function should allocate the space
185 * according to the size provided residing inside a huge page.
186 * Please note that all allocation must respect the alignment from libmlx5
187 * (i.e. currently sysconf(_SC_PAGESIZE)).
190 * The size in bytes of the memory to allocate.
192 * A pointer to the callback data.
195 * Allocated buffer, NULL otherwise and rte_errno is set.
198 mlx5_alloc_verbs_buf(size_t size, void *data)
200 struct priv *priv = data;
202 size_t alignment = sysconf(_SC_PAGESIZE);
203 unsigned int socket = SOCKET_ID_ANY;
205 if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) {
206 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
208 socket = ctrl->socket;
209 } else if (priv->verbs_alloc_ctx.type ==
210 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) {
211 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
213 socket = ctrl->socket;
215 assert(data != NULL);
216 ret = rte_malloc_socket(__func__, size, alignment, socket);
223 * Verbs callback to free a memory.
226 * A pointer to the memory to free.
228 * A pointer to the callback data.
231 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused)
233 assert(data != NULL);
238 * DPDK callback to close the device.
240 * Destroy all queues and objects, free memory.
243 * Pointer to Ethernet device structure.
246 mlx5_dev_close(struct rte_eth_dev *dev)
248 struct priv *priv = dev->data->dev_private;
252 DRV_LOG(DEBUG, "port %u closing device \"%s\"",
254 ((priv->ctx != NULL) ? priv->ctx->device->name : ""));
255 /* In case mlx5_dev_stop() has not been called. */
256 mlx5_dev_interrupt_handler_uninstall(dev);
257 mlx5_traffic_disable(dev);
258 mlx5_flow_flush(dev, NULL);
259 /* Prevent crashes when queues are still in use. */
260 dev->rx_pkt_burst = removed_rx_burst;
261 dev->tx_pkt_burst = removed_tx_burst;
262 if (priv->rxqs != NULL) {
263 /* XXX race condition if mlx5_rx_burst() is still running. */
265 for (i = 0; (i != priv->rxqs_n); ++i)
266 mlx5_rxq_release(dev, i);
270 if (priv->txqs != NULL) {
271 /* XXX race condition if mlx5_tx_burst() is still running. */
273 for (i = 0; (i != priv->txqs_n); ++i)
274 mlx5_txq_release(dev, i);
278 mlx5_mprq_free_mp(dev);
279 mlx5_mr_release(dev);
280 if (priv->pd != NULL) {
281 assert(priv->ctx != NULL);
282 claim_zero(mlx5_glue->dealloc_pd(priv->pd));
283 claim_zero(mlx5_glue->close_device(priv->ctx));
285 assert(priv->ctx == NULL);
286 if (priv->rss_conf.rss_key != NULL)
287 rte_free(priv->rss_conf.rss_key);
288 if (priv->reta_idx != NULL)
289 rte_free(priv->reta_idx);
290 if (priv->primary_socket)
291 mlx5_socket_uninit(dev);
293 mlx5_nl_mac_addr_flush(dev);
294 if (priv->nl_socket_route >= 0)
295 close(priv->nl_socket_route);
296 if (priv->nl_socket_rdma >= 0)
297 close(priv->nl_socket_rdma);
298 if (priv->tcf_context)
299 mlx5_flow_tcf_context_destroy(priv->tcf_context);
300 ret = mlx5_hrxq_ibv_verify(dev);
302 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
304 ret = mlx5_ind_table_ibv_verify(dev);
306 DRV_LOG(WARNING, "port %u some indirection table still remain",
308 ret = mlx5_rxq_ibv_verify(dev);
310 DRV_LOG(WARNING, "port %u some Verbs Rx queue still remain",
312 ret = mlx5_rxq_verify(dev);
314 DRV_LOG(WARNING, "port %u some Rx queues still remain",
316 ret = mlx5_txq_ibv_verify(dev);
318 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
320 ret = mlx5_txq_verify(dev);
322 DRV_LOG(WARNING, "port %u some Tx queues still remain",
324 ret = mlx5_flow_verify(dev);
326 DRV_LOG(WARNING, "port %u some flows still remain",
328 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
330 unsigned int i = mlx5_dev_to_port_id(dev->device, NULL, 0);
333 i = RTE_MIN(mlx5_dev_to_port_id(dev->device, port_id, i), i);
336 rte_eth_devices[port_id[i]].data->dev_private;
339 opriv->domain_id != priv->domain_id ||
340 &rte_eth_devices[port_id[i]] == dev)
345 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
347 memset(priv, 0, sizeof(*priv));
348 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
350 * flag to rte_eth_dev_close() that it should release the port resources
351 * (calling rte_eth_dev_release_port()) in addition to closing it.
353 dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
355 * Reset mac_addrs to NULL such that it is not freed as part of
356 * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
357 * it is freed when dev_private is freed.
359 dev->data->mac_addrs = NULL;
362 const struct eth_dev_ops mlx5_dev_ops = {
363 .dev_configure = mlx5_dev_configure,
364 .dev_start = mlx5_dev_start,
365 .dev_stop = mlx5_dev_stop,
366 .dev_set_link_down = mlx5_set_link_down,
367 .dev_set_link_up = mlx5_set_link_up,
368 .dev_close = mlx5_dev_close,
369 .promiscuous_enable = mlx5_promiscuous_enable,
370 .promiscuous_disable = mlx5_promiscuous_disable,
371 .allmulticast_enable = mlx5_allmulticast_enable,
372 .allmulticast_disable = mlx5_allmulticast_disable,
373 .link_update = mlx5_link_update,
374 .stats_get = mlx5_stats_get,
375 .stats_reset = mlx5_stats_reset,
376 .xstats_get = mlx5_xstats_get,
377 .xstats_reset = mlx5_xstats_reset,
378 .xstats_get_names = mlx5_xstats_get_names,
379 .dev_infos_get = mlx5_dev_infos_get,
380 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
381 .vlan_filter_set = mlx5_vlan_filter_set,
382 .rx_queue_setup = mlx5_rx_queue_setup,
383 .tx_queue_setup = mlx5_tx_queue_setup,
384 .rx_queue_release = mlx5_rx_queue_release,
385 .tx_queue_release = mlx5_tx_queue_release,
386 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
387 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
388 .mac_addr_remove = mlx5_mac_addr_remove,
389 .mac_addr_add = mlx5_mac_addr_add,
390 .mac_addr_set = mlx5_mac_addr_set,
391 .set_mc_addr_list = mlx5_set_mc_addr_list,
392 .mtu_set = mlx5_dev_set_mtu,
393 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
394 .vlan_offload_set = mlx5_vlan_offload_set,
395 .reta_update = mlx5_dev_rss_reta_update,
396 .reta_query = mlx5_dev_rss_reta_query,
397 .rss_hash_update = mlx5_rss_hash_update,
398 .rss_hash_conf_get = mlx5_rss_hash_conf_get,
399 .filter_ctrl = mlx5_dev_filter_ctrl,
400 .rx_descriptor_status = mlx5_rx_descriptor_status,
401 .tx_descriptor_status = mlx5_tx_descriptor_status,
402 .rx_queue_intr_enable = mlx5_rx_intr_enable,
403 .rx_queue_intr_disable = mlx5_rx_intr_disable,
404 .is_removed = mlx5_is_removed,
407 static const struct eth_dev_ops mlx5_dev_sec_ops = {
408 .stats_get = mlx5_stats_get,
409 .stats_reset = mlx5_stats_reset,
410 .xstats_get = mlx5_xstats_get,
411 .xstats_reset = mlx5_xstats_reset,
412 .xstats_get_names = mlx5_xstats_get_names,
413 .dev_infos_get = mlx5_dev_infos_get,
414 .rx_descriptor_status = mlx5_rx_descriptor_status,
415 .tx_descriptor_status = mlx5_tx_descriptor_status,
418 /* Available operators in flow isolated mode. */
419 const struct eth_dev_ops mlx5_dev_ops_isolate = {
420 .dev_configure = mlx5_dev_configure,
421 .dev_start = mlx5_dev_start,
422 .dev_stop = mlx5_dev_stop,
423 .dev_set_link_down = mlx5_set_link_down,
424 .dev_set_link_up = mlx5_set_link_up,
425 .dev_close = mlx5_dev_close,
426 .promiscuous_enable = mlx5_promiscuous_enable,
427 .promiscuous_disable = mlx5_promiscuous_disable,
428 .allmulticast_enable = mlx5_allmulticast_enable,
429 .allmulticast_disable = mlx5_allmulticast_disable,
430 .link_update = mlx5_link_update,
431 .stats_get = mlx5_stats_get,
432 .stats_reset = mlx5_stats_reset,
433 .xstats_get = mlx5_xstats_get,
434 .xstats_reset = mlx5_xstats_reset,
435 .xstats_get_names = mlx5_xstats_get_names,
436 .dev_infos_get = mlx5_dev_infos_get,
437 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
438 .vlan_filter_set = mlx5_vlan_filter_set,
439 .rx_queue_setup = mlx5_rx_queue_setup,
440 .tx_queue_setup = mlx5_tx_queue_setup,
441 .rx_queue_release = mlx5_rx_queue_release,
442 .tx_queue_release = mlx5_tx_queue_release,
443 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
444 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
445 .mac_addr_remove = mlx5_mac_addr_remove,
446 .mac_addr_add = mlx5_mac_addr_add,
447 .mac_addr_set = mlx5_mac_addr_set,
448 .set_mc_addr_list = mlx5_set_mc_addr_list,
449 .mtu_set = mlx5_dev_set_mtu,
450 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
451 .vlan_offload_set = mlx5_vlan_offload_set,
452 .filter_ctrl = mlx5_dev_filter_ctrl,
453 .rx_descriptor_status = mlx5_rx_descriptor_status,
454 .tx_descriptor_status = mlx5_tx_descriptor_status,
455 .rx_queue_intr_enable = mlx5_rx_intr_enable,
456 .rx_queue_intr_disable = mlx5_rx_intr_disable,
457 .is_removed = mlx5_is_removed,
461 * Verify and store value for device argument.
464 * Key argument to verify.
466 * Value associated with key.
471 * 0 on success, a negative errno value otherwise and rte_errno is set.
474 mlx5_args_check(const char *key, const char *val, void *opaque)
476 struct mlx5_dev_config *config = opaque;
479 /* No-op, port representors are processed in mlx5_dev_spawn(). */
480 if (!strcmp(MLX5_REPRESENTOR, key))
483 tmp = strtoul(val, NULL, 0);
486 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
489 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
490 config->cqe_comp = !!tmp;
491 } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
492 config->cqe_pad = !!tmp;
493 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
494 config->mprq.enabled = !!tmp;
495 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
496 config->mprq.stride_num_n = tmp;
497 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
498 config->mprq.max_memcpy_len = tmp;
499 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
500 config->mprq.min_rxqs_num = tmp;
501 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
502 config->txq_inline = tmp;
503 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
504 config->txqs_inline = tmp;
505 } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
506 config->txqs_vec = tmp;
507 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
509 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
510 config->mpw_hdr_dseg = !!tmp;
511 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
512 config->inline_max_packet_sz = tmp;
513 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
514 config->tx_vec_en = !!tmp;
515 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
516 config->rx_vec_en = !!tmp;
517 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
518 config->l3_vxlan_en = !!tmp;
519 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
520 config->vf_nl_en = !!tmp;
521 } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
522 config->dv_flow_en = !!tmp;
524 DRV_LOG(WARNING, "%s: unknown parameter", key);
532 * Parse device parameters.
535 * Pointer to device configuration structure.
537 * Device arguments structure.
540 * 0 on success, a negative errno value otherwise and rte_errno is set.
543 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
545 const char **params = (const char *[]){
546 MLX5_RXQ_CQE_COMP_EN,
549 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
550 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
553 MLX5_TXQS_MIN_INLINE,
556 MLX5_TXQ_MPW_HDR_DSEG_EN,
557 MLX5_TXQ_MAX_INLINE_LEN,
566 struct rte_kvargs *kvlist;
572 /* Following UGLY cast is done to pass checkpatch. */
573 kvlist = rte_kvargs_parse(devargs->args, params);
576 /* Process parameters. */
577 for (i = 0; (params[i] != NULL); ++i) {
578 if (rte_kvargs_count(kvlist, params[i])) {
579 ret = rte_kvargs_process(kvlist, params[i],
580 mlx5_args_check, config);
583 rte_kvargs_free(kvlist);
588 rte_kvargs_free(kvlist);
592 static struct rte_pci_driver mlx5_driver;
595 * Reserved UAR address space for TXQ UAR(hw doorbell) mapping, process
596 * local resource used by both primary and secondary to avoid duplicate
598 * The space has to be available on both primary and secondary process,
599 * TXQ UAR maps to this area using fixed mmap w/o double check.
601 static void *uar_base;
604 find_lower_va_bound(const struct rte_memseg_list *msl,
605 const struct rte_memseg *ms, void *arg)
614 *addr = RTE_MIN(*addr, ms->addr);
620 * Reserve UAR address space for primary process.
623 * Pointer to Ethernet device.
626 * 0 on success, a negative errno value otherwise and rte_errno is set.
629 mlx5_uar_init_primary(struct rte_eth_dev *dev)
631 struct priv *priv = dev->data->dev_private;
632 void *addr = (void *)0;
634 if (uar_base) { /* UAR address space mapped. */
635 priv->uar_base = uar_base;
638 /* find out lower bound of hugepage segments */
639 rte_memseg_walk(find_lower_va_bound, &addr);
641 /* keep distance to hugepages to minimize potential conflicts. */
642 addr = RTE_PTR_SUB(addr, (uintptr_t)(MLX5_UAR_OFFSET + MLX5_UAR_SIZE));
643 /* anonymous mmap, no real memory consumption. */
644 addr = mmap(addr, MLX5_UAR_SIZE,
645 PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
646 if (addr == MAP_FAILED) {
648 "port %u failed to reserve UAR address space, please"
649 " adjust MLX5_UAR_SIZE or try --base-virtaddr",
654 /* Accept either same addr or a new addr returned from mmap if target
657 DRV_LOG(INFO, "port %u reserved UAR address space: %p",
658 dev->data->port_id, addr);
659 priv->uar_base = addr; /* for primary and secondary UAR re-mmap. */
660 uar_base = addr; /* process local, don't reserve again. */
665 * Reserve UAR address space for secondary process, align with
669 * Pointer to Ethernet device.
672 * 0 on success, a negative errno value otherwise and rte_errno is set.
675 mlx5_uar_init_secondary(struct rte_eth_dev *dev)
677 struct priv *priv = dev->data->dev_private;
680 assert(priv->uar_base);
681 if (uar_base) { /* already reserved. */
682 assert(uar_base == priv->uar_base);
685 /* anonymous mmap, no real memory consumption. */
686 addr = mmap(priv->uar_base, MLX5_UAR_SIZE,
687 PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
688 if (addr == MAP_FAILED) {
689 DRV_LOG(ERR, "port %u UAR mmap failed: %p size: %llu",
690 dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE);
694 if (priv->uar_base != addr) {
696 "port %u UAR address %p size %llu occupied, please"
697 " adjust MLX5_UAR_OFFSET or try EAL parameter"
699 dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE);
703 uar_base = addr; /* process local, don't reserve again */
704 DRV_LOG(INFO, "port %u reserved UAR address space: %p",
705 dev->data->port_id, addr);
710 * Spawn an Ethernet device from Verbs information.
713 * Backing DPDK device.
717 * Device configuration parameters.
718 * @param[in] switch_info
719 * Switch properties of Ethernet device.
722 * A valid Ethernet device object on success, NULL otherwise and rte_errno
723 * is set. The following errors are defined:
725 * EBUSY: device is not supposed to be spawned.
726 * EEXIST: device is already spawned
728 static struct rte_eth_dev *
729 mlx5_dev_spawn(struct rte_device *dpdk_dev,
730 struct ibv_device *ibv_dev,
731 struct mlx5_dev_config config,
732 const struct mlx5_switch_info *switch_info)
734 struct ibv_context *ctx;
735 struct ibv_device_attr_ex attr;
736 struct ibv_port_attr port_attr;
737 struct ibv_pd *pd = NULL;
738 struct mlx5dv_context dv_attr = { .comp_mask = 0 };
739 struct rte_eth_dev *eth_dev = NULL;
740 struct priv *priv = NULL;
743 unsigned int cqe_comp;
744 unsigned int cqe_pad = 0;
745 unsigned int tunnel_en = 0;
746 unsigned int mpls_en = 0;
747 unsigned int swp = 0;
748 unsigned int mprq = 0;
749 unsigned int mprq_min_stride_size_n = 0;
750 unsigned int mprq_max_stride_size_n = 0;
751 unsigned int mprq_min_stride_num_n = 0;
752 unsigned int mprq_max_stride_num_n = 0;
753 struct ether_addr mac;
754 char name[RTE_ETH_NAME_MAX_LEN];
755 int own_domain_id = 0;
759 /* Determine if this port representor is supposed to be spawned. */
760 if (switch_info->representor && dpdk_dev->devargs) {
761 struct rte_eth_devargs eth_da;
763 err = rte_eth_devargs_parse(dpdk_dev->devargs->args, ð_da);
766 DRV_LOG(ERR, "failed to process device arguments: %s",
767 strerror(rte_errno));
770 for (i = 0; i < eth_da.nb_representor_ports; ++i)
771 if (eth_da.representor_ports[i] ==
772 (uint16_t)switch_info->port_name)
774 if (i == eth_da.nb_representor_ports) {
779 /* Build device name. */
780 if (!switch_info->representor)
781 rte_strlcpy(name, dpdk_dev->name, sizeof(name));
783 snprintf(name, sizeof(name), "%s_representor_%u",
784 dpdk_dev->name, switch_info->port_name);
785 /* check if the device is already spawned */
786 if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) {
790 /* Prepare shared data between primary and secondary process. */
791 mlx5_prepare_shared_data();
793 ctx = mlx5_glue->open_device(ibv_dev);
795 rte_errno = errno ? errno : ENODEV;
798 #ifdef HAVE_IBV_MLX5_MOD_SWP
799 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP;
802 * Multi-packet send is supported by ConnectX-4 Lx PF as well
803 * as all ConnectX-5 devices.
805 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
806 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS;
808 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
809 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ;
811 mlx5_glue->dv_query_device(ctx, &dv_attr);
812 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
813 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) {
814 DRV_LOG(DEBUG, "enhanced MPW is supported");
815 mps = MLX5_MPW_ENHANCED;
817 DRV_LOG(DEBUG, "MPW is supported");
821 DRV_LOG(DEBUG, "MPW isn't supported");
822 mps = MLX5_MPW_DISABLED;
824 #ifdef HAVE_IBV_MLX5_MOD_SWP
825 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP)
826 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads;
827 DRV_LOG(DEBUG, "SWP support: %u", swp);
830 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
831 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) {
832 struct mlx5dv_striding_rq_caps mprq_caps =
833 dv_attr.striding_rq_caps;
835 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d",
836 mprq_caps.min_single_stride_log_num_of_bytes);
837 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d",
838 mprq_caps.max_single_stride_log_num_of_bytes);
839 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d",
840 mprq_caps.min_single_wqe_log_num_of_strides);
841 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d",
842 mprq_caps.max_single_wqe_log_num_of_strides);
843 DRV_LOG(DEBUG, "\tsupported_qpts: %d",
844 mprq_caps.supported_qpts);
845 DRV_LOG(DEBUG, "device supports Multi-Packet RQ");
847 mprq_min_stride_size_n =
848 mprq_caps.min_single_stride_log_num_of_bytes;
849 mprq_max_stride_size_n =
850 mprq_caps.max_single_stride_log_num_of_bytes;
851 mprq_min_stride_num_n =
852 mprq_caps.min_single_wqe_log_num_of_strides;
853 mprq_max_stride_num_n =
854 mprq_caps.max_single_wqe_log_num_of_strides;
855 config.mprq.stride_num_n = RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,
856 mprq_min_stride_num_n);
859 if (RTE_CACHE_LINE_SIZE == 128 &&
860 !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP))
864 config.cqe_comp = cqe_comp;
865 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD
866 /* Whether device supports 128B Rx CQE padding. */
867 cqe_pad = RTE_CACHE_LINE_SIZE == 128 &&
868 (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_PAD);
870 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
871 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) {
872 tunnel_en = ((dv_attr.tunnel_offloads_caps &
873 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) &&
874 (dv_attr.tunnel_offloads_caps &
875 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE));
877 DRV_LOG(DEBUG, "tunnel offloading is %ssupported",
878 tunnel_en ? "" : "not ");
881 "tunnel offloading disabled due to old OFED/rdma-core version");
883 config.tunnel_en = tunnel_en;
884 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
885 mpls_en = ((dv_attr.tunnel_offloads_caps &
886 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) &&
887 (dv_attr.tunnel_offloads_caps &
888 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP));
889 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported",
890 mpls_en ? "" : "not ");
892 DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to"
893 " old OFED/rdma-core version or firmware configuration");
895 config.mpls_en = mpls_en;
896 err = mlx5_glue->query_device_ex(ctx, NULL, &attr);
898 DEBUG("ibv_query_device_ex() failed");
901 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name);
902 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
903 eth_dev = rte_eth_dev_attach_secondary(name);
904 if (eth_dev == NULL) {
905 DRV_LOG(ERR, "can not attach rte ethdev");
910 eth_dev->device = dpdk_dev;
911 eth_dev->dev_ops = &mlx5_dev_sec_ops;
912 err = mlx5_uar_init_secondary(eth_dev);
917 /* Receive command fd from primary process */
918 err = mlx5_socket_connect(eth_dev);
923 /* Remap UAR for Tx queues. */
924 err = mlx5_tx_uar_remap(eth_dev, err);
930 * Ethdev pointer is still required as input since
931 * the primary device is not accessible from the
934 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev);
935 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev);
936 claim_zero(mlx5_glue->close_device(ctx));
939 /* Check port status. */
940 err = mlx5_glue->query_port(ctx, 1, &port_attr);
942 DRV_LOG(ERR, "port query failed: %s", strerror(err));
945 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
946 DRV_LOG(ERR, "port is not configured in Ethernet mode");
950 if (port_attr.state != IBV_PORT_ACTIVE)
951 DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)",
952 mlx5_glue->port_state_str(port_attr.state),
954 /* Allocate protection domain. */
955 pd = mlx5_glue->alloc_pd(ctx);
957 DRV_LOG(ERR, "PD allocation failure");
961 priv = rte_zmalloc("ethdev private structure",
963 RTE_CACHE_LINE_SIZE);
965 DRV_LOG(ERR, "priv allocation failure");
970 strncpy(priv->ibdev_name, priv->ctx->device->name,
971 sizeof(priv->ibdev_name));
972 strncpy(priv->ibdev_path, priv->ctx->device->ibdev_path,
973 sizeof(priv->ibdev_path));
974 priv->device_attr = attr;
976 priv->mtu = ETHER_MTU;
978 /* Initialize UAR access locks for 32bit implementations. */
979 rte_spinlock_init(&priv->uar_lock_cq);
980 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
981 rte_spinlock_init(&priv->uar_lock[i]);
983 /* Some internal functions rely on Netlink sockets, open them now. */
984 priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA);
985 priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE);
987 priv->representor = !!switch_info->representor;
988 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
989 priv->representor_id =
990 switch_info->representor ? switch_info->port_name : -1;
992 * Look for sibling devices in order to reuse their switch domain
993 * if any, otherwise allocate one.
995 i = mlx5_dev_to_port_id(dpdk_dev, NULL, 0);
999 i = RTE_MIN(mlx5_dev_to_port_id(dpdk_dev, port_id, i), i);
1001 const struct priv *opriv =
1002 rte_eth_devices[port_id[i]].data->dev_private;
1006 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID)
1008 priv->domain_id = opriv->domain_id;
1012 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1013 err = rte_eth_switch_domain_alloc(&priv->domain_id);
1016 DRV_LOG(ERR, "unable to allocate switch domain: %s",
1017 strerror(rte_errno));
1022 err = mlx5_args(&config, dpdk_dev->devargs);
1025 DRV_LOG(ERR, "failed to process device arguments: %s",
1026 strerror(rte_errno));
1029 config.hw_csum = !!(attr.device_cap_flags_ex & IBV_DEVICE_RAW_IP_CSUM);
1030 DRV_LOG(DEBUG, "checksum offloading is %ssupported",
1031 (config.hw_csum ? "" : "not "));
1032 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \
1033 !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
1034 DRV_LOG(DEBUG, "counters are not supported");
1036 #ifndef HAVE_IBV_FLOW_DV_SUPPORT
1037 if (config.dv_flow_en) {
1038 DRV_LOG(WARNING, "DV flow is not supported");
1039 config.dv_flow_en = 0;
1042 config.ind_table_max_size =
1043 attr.rss_caps.max_rwq_indirection_table_size;
1045 * Remove this check once DPDK supports larger/variable
1046 * indirection tables.
1048 if (config.ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512)
1049 config.ind_table_max_size = ETH_RSS_RETA_SIZE_512;
1050 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u",
1051 config.ind_table_max_size);
1052 config.hw_vlan_strip = !!(attr.raw_packet_caps &
1053 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
1054 DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
1055 (config.hw_vlan_strip ? "" : "not "));
1056 config.hw_fcs_strip = !!(attr.raw_packet_caps &
1057 IBV_RAW_PACKET_CAP_SCATTER_FCS);
1058 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported",
1059 (config.hw_fcs_strip ? "" : "not "));
1060 #ifdef HAVE_IBV_WQ_FLAG_RX_END_PADDING
1061 config.hw_padding = !!attr.rx_pad_end_addr_align;
1063 DRV_LOG(DEBUG, "hardware Rx end alignment padding is %ssupported",
1064 (config.hw_padding ? "" : "not "));
1065 config.tso = (attr.tso_caps.max_tso > 0 &&
1066 (attr.tso_caps.supported_qpts &
1067 (1 << IBV_QPT_RAW_PACKET)));
1069 config.tso_max_payload_sz = attr.tso_caps.max_tso;
1071 * MPW is disabled by default, while the Enhanced MPW is enabled
1074 if (config.mps == MLX5_ARG_UNSET)
1075 config.mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED :
1078 config.mps = config.mps ? mps : MLX5_MPW_DISABLED;
1079 DRV_LOG(INFO, "%sMPS is %s",
1080 config.mps == MLX5_MPW_ENHANCED ? "enhanced " : "",
1081 config.mps != MLX5_MPW_DISABLED ? "enabled" : "disabled");
1082 if (config.cqe_comp && !cqe_comp) {
1083 DRV_LOG(WARNING, "Rx CQE compression isn't supported");
1084 config.cqe_comp = 0;
1086 if (config.cqe_pad && !cqe_pad) {
1087 DRV_LOG(WARNING, "Rx CQE padding isn't supported");
1089 } else if (config.cqe_pad) {
1090 DRV_LOG(INFO, "Rx CQE padding is enabled");
1092 if (config.mprq.enabled && mprq) {
1093 if (config.mprq.stride_num_n > mprq_max_stride_num_n ||
1094 config.mprq.stride_num_n < mprq_min_stride_num_n) {
1095 config.mprq.stride_num_n =
1096 RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,
1097 mprq_min_stride_num_n);
1099 "the number of strides"
1100 " for Multi-Packet RQ is out of range,"
1101 " setting default value (%u)",
1102 1 << config.mprq.stride_num_n);
1104 config.mprq.min_stride_size_n = mprq_min_stride_size_n;
1105 config.mprq.max_stride_size_n = mprq_max_stride_size_n;
1106 } else if (config.mprq.enabled && !mprq) {
1107 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported");
1108 config.mprq.enabled = 0;
1110 eth_dev = rte_eth_dev_allocate(name);
1111 if (eth_dev == NULL) {
1112 DRV_LOG(ERR, "can not allocate rte ethdev");
1116 if (priv->representor) {
1117 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR;
1118 eth_dev->data->representor_id = priv->representor_id;
1120 eth_dev->data->dev_private = priv;
1121 priv->dev_data = eth_dev->data;
1122 eth_dev->data->mac_addrs = priv->mac;
1123 eth_dev->device = dpdk_dev;
1124 err = mlx5_uar_init_primary(eth_dev);
1129 /* Configure the first MAC address by default. */
1130 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) {
1132 "port %u cannot get MAC address, is mlx5_en"
1133 " loaded? (errno: %s)",
1134 eth_dev->data->port_id, strerror(rte_errno));
1139 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x",
1140 eth_dev->data->port_id,
1141 mac.addr_bytes[0], mac.addr_bytes[1],
1142 mac.addr_bytes[2], mac.addr_bytes[3],
1143 mac.addr_bytes[4], mac.addr_bytes[5]);
1146 char ifname[IF_NAMESIZE];
1148 if (mlx5_get_ifname(eth_dev, &ifname) == 0)
1149 DRV_LOG(DEBUG, "port %u ifname is \"%s\"",
1150 eth_dev->data->port_id, ifname);
1152 DRV_LOG(DEBUG, "port %u ifname is unknown",
1153 eth_dev->data->port_id);
1156 /* Get actual MTU if possible. */
1157 err = mlx5_get_mtu(eth_dev, &priv->mtu);
1162 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id,
1164 /* Initialize burst functions to prevent crashes before link-up. */
1165 eth_dev->rx_pkt_burst = removed_rx_burst;
1166 eth_dev->tx_pkt_burst = removed_tx_burst;
1167 eth_dev->dev_ops = &mlx5_dev_ops;
1168 /* Register MAC address. */
1169 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
1170 if (config.vf && config.vf_nl_en)
1171 mlx5_nl_mac_addr_sync(eth_dev);
1172 priv->tcf_context = mlx5_flow_tcf_context_create();
1173 if (!priv->tcf_context) {
1176 "flow rules relying on switch offloads will not be"
1177 " supported: cannot open libmnl socket: %s",
1178 strerror(rte_errno));
1180 struct rte_flow_error error;
1181 unsigned int ifindex = mlx5_ifindex(eth_dev);
1186 "cannot retrieve network interface index";
1188 err = mlx5_flow_tcf_init(priv->tcf_context,
1193 "flow rules relying on switch offloads will"
1194 " not be supported: %s: %s",
1195 error.message, strerror(rte_errno));
1196 mlx5_flow_tcf_context_destroy(priv->tcf_context);
1197 priv->tcf_context = NULL;
1200 TAILQ_INIT(&priv->flows);
1201 TAILQ_INIT(&priv->ctrl_flows);
1202 /* Hint libmlx5 to use PMD allocator for data plane resources */
1203 struct mlx5dv_ctx_allocators alctr = {
1204 .alloc = &mlx5_alloc_verbs_buf,
1205 .free = &mlx5_free_verbs_buf,
1208 mlx5_glue->dv_set_context_attr(ctx, MLX5DV_CTX_ATTR_BUF_ALLOCATORS,
1209 (void *)((uintptr_t)&alctr));
1210 /* Bring Ethernet device up. */
1211 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up",
1212 eth_dev->data->port_id);
1213 mlx5_set_link_up(eth_dev);
1215 * Even though the interrupt handler is not installed yet,
1216 * interrupts will still trigger on the asyn_fd from
1217 * Verbs context returned by ibv_open_device().
1219 mlx5_link_update(eth_dev, 0);
1220 /* Store device configuration on private structure. */
1221 priv->config = config;
1222 /* Supported Verbs flow priority number detection. */
1223 err = mlx5_flow_discover_priorities(eth_dev);
1226 priv->config.flow_prio = err;
1228 * Once the device is added to the list of memory event
1229 * callback, its global MR cache table cannot be expanded
1230 * on the fly because of deadlock. If it overflows, lookup
1231 * should be done by searching MR list linearly, which is slow.
1233 err = mlx5_mr_btree_init(&priv->mr.cache,
1234 MLX5_MR_BTREE_CACHE_N * 2,
1235 eth_dev->device->numa_node);
1240 /* Add device to memory callback list. */
1241 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1242 LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
1243 priv, mem_event_cb);
1244 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1248 if (priv->nl_socket_route >= 0)
1249 close(priv->nl_socket_route);
1250 if (priv->nl_socket_rdma >= 0)
1251 close(priv->nl_socket_rdma);
1252 if (priv->tcf_context)
1253 mlx5_flow_tcf_context_destroy(priv->tcf_context);
1255 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1257 if (eth_dev != NULL)
1258 eth_dev->data->dev_private = NULL;
1261 claim_zero(mlx5_glue->dealloc_pd(pd));
1262 if (eth_dev != NULL) {
1263 /* mac_addrs must not be freed alone because part of dev_private */
1264 eth_dev->data->mac_addrs = NULL;
1265 rte_eth_dev_release_port(eth_dev);
1268 claim_zero(mlx5_glue->close_device(ctx));
1274 /** Data associated with devices to spawn. */
1275 struct mlx5_dev_spawn_data {
1276 unsigned int ifindex; /**< Network interface index. */
1277 struct mlx5_switch_info info; /**< Switch information. */
1278 struct ibv_device *ibv_dev; /**< Associated IB device. */
1279 struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */
1283 * Comparison callback to sort device data.
1285 * This is meant to be used with qsort().
1288 * Pointer to pointer to first data object.
1290 * Pointer to pointer to second data object.
1293 * 0 if both objects are equal, less than 0 if the first argument is less
1294 * than the second, greater than 0 otherwise.
1297 mlx5_dev_spawn_data_cmp(const void *a, const void *b)
1299 const struct mlx5_switch_info *si_a =
1300 &((const struct mlx5_dev_spawn_data *)a)->info;
1301 const struct mlx5_switch_info *si_b =
1302 &((const struct mlx5_dev_spawn_data *)b)->info;
1305 /* Master device first. */
1306 ret = si_b->master - si_a->master;
1309 /* Then representor devices. */
1310 ret = si_b->representor - si_a->representor;
1313 /* Unidentified devices come last in no specific order. */
1314 if (!si_a->representor)
1316 /* Order representors by name. */
1317 return si_a->port_name - si_b->port_name;
1321 * DPDK callback to register a PCI device.
1323 * This function spawns Ethernet devices out of a given PCI device.
1325 * @param[in] pci_drv
1326 * PCI driver structure (mlx5_driver).
1327 * @param[in] pci_dev
1328 * PCI device information.
1331 * 0 on success, a negative errno value otherwise and rte_errno is set.
1334 mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1335 struct rte_pci_device *pci_dev)
1337 struct ibv_device **ibv_list;
1339 struct mlx5_dev_config dev_config;
1342 assert(pci_drv == &mlx5_driver);
1344 ibv_list = mlx5_glue->get_device_list(&ret);
1346 rte_errno = errno ? errno : ENOSYS;
1347 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?");
1351 struct ibv_device *ibv_match[ret + 1];
1354 struct rte_pci_addr pci_addr;
1356 DRV_LOG(DEBUG, "checking device \"%s\"", ibv_list[ret]->name);
1357 if (mlx5_ibv_device_to_pci_addr(ibv_list[ret], &pci_addr))
1359 if (pci_dev->addr.domain != pci_addr.domain ||
1360 pci_dev->addr.bus != pci_addr.bus ||
1361 pci_dev->addr.devid != pci_addr.devid ||
1362 pci_dev->addr.function != pci_addr.function)
1364 DRV_LOG(INFO, "PCI information matches for device \"%s\"",
1365 ibv_list[ret]->name);
1366 ibv_match[n++] = ibv_list[ret];
1368 ibv_match[n] = NULL;
1370 struct mlx5_dev_spawn_data list[n];
1371 int nl_route = n ? mlx5_nl_init(NETLINK_ROUTE) : -1;
1372 int nl_rdma = n ? mlx5_nl_init(NETLINK_RDMA) : -1;
1377 * The existence of several matching entries (n > 1) means port
1378 * representors have been instantiated. No existing Verbs call nor
1379 * /sys entries can tell them apart, this can only be done through
1380 * Netlink calls assuming kernel drivers are recent enough to
1383 * In the event of identification failure through Netlink, try again
1384 * through sysfs, then either:
1386 * 1. No device matches (n == 0), complain and bail out.
1387 * 2. A single IB device matches (n == 1) and is not a representor,
1388 * assume no switch support.
1389 * 3. Otherwise no safe assumptions can be made; complain louder and
1392 for (i = 0; i != n; ++i) {
1393 list[i].ibv_dev = ibv_match[i];
1394 list[i].eth_dev = NULL;
1396 list[i].ifindex = 0;
1398 list[i].ifindex = mlx5_nl_ifindex
1399 (nl_rdma, list[i].ibv_dev->name);
1402 mlx5_nl_switch_info(nl_route, list[i].ifindex,
1404 ((!list[i].info.representor && !list[i].info.master) &&
1405 mlx5_sysfs_switch_info(list[i].ifindex, &list[i].info))) {
1406 list[i].ifindex = 0;
1407 memset(&list[i].info, 0, sizeof(list[i].info));
1415 /* Count unidentified devices. */
1416 for (u = 0, i = 0; i != n; ++i)
1417 if (!list[i].info.master && !list[i].info.representor)
1420 if (n == 1 && u == 1) {
1422 DRV_LOG(INFO, "no switch support detected");
1426 "unable to tell which of the matching devices"
1427 " is the master (lack of kernel support?)");
1432 * Sort list to probe devices in natural order for users convenience
1433 * (i.e. master first, then representors from lowest to highest ID).
1436 qsort(list, n, sizeof(*list), mlx5_dev_spawn_data_cmp);
1437 /* Default configuration. */
1438 dev_config = (struct mlx5_dev_config){
1439 .mps = MLX5_ARG_UNSET,
1442 .txq_inline = MLX5_ARG_UNSET,
1443 .txqs_inline = MLX5_ARG_UNSET,
1444 .txqs_vec = MLX5_ARG_UNSET,
1445 .inline_max_packet_sz = MLX5_ARG_UNSET,
1448 .enabled = 0, /* Disabled by default. */
1449 .stride_num_n = MLX5_MPRQ_STRIDE_NUM_N,
1450 .max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN,
1451 .min_rxqs_num = MLX5_MPRQ_MIN_RXQS,
1454 /* Device speicific configuration. */
1455 switch (pci_dev->id.device_id) {
1456 case PCI_DEVICE_ID_MELLANOX_CONNECTX5BF:
1457 dev_config.txqs_vec = MLX5_VPMD_MAX_TXQS_BLUEFIELD;
1459 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1460 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1461 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1462 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1468 /* Set architecture-dependent default value if unset. */
1469 if (dev_config.txqs_vec == MLX5_ARG_UNSET)
1470 dev_config.txqs_vec = MLX5_VPMD_MAX_TXQS;
1471 for (i = 0; i != n; ++i) {
1474 list[i].eth_dev = mlx5_dev_spawn(&pci_dev->device,
1475 list[i].ibv_dev, dev_config,
1477 if (!list[i].eth_dev) {
1478 if (rte_errno != EBUSY && rte_errno != EEXIST)
1480 /* Device is disabled or already spawned. Ignore it. */
1483 restore = list[i].eth_dev->data->dev_flags;
1484 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev);
1485 /* Restore non-PCI flags cleared by the above call. */
1486 list[i].eth_dev->data->dev_flags |= restore;
1487 rte_eth_dev_probing_finish(list[i].eth_dev);
1489 mlx5_glue->free_device_list(ibv_list);
1492 "no Verbs device matches PCI device " PCI_PRI_FMT ","
1493 " are kernel drivers loaded?",
1494 pci_dev->addr.domain, pci_dev->addr.bus,
1495 pci_dev->addr.devid, pci_dev->addr.function);
1498 } else if (i != n) {
1500 "probe of PCI device " PCI_PRI_FMT " aborted after"
1501 " encountering an error: %s",
1502 pci_dev->addr.domain, pci_dev->addr.bus,
1503 pci_dev->addr.devid, pci_dev->addr.function,
1504 strerror(rte_errno));
1508 if (!list[i].eth_dev)
1510 mlx5_dev_close(list[i].eth_dev);
1511 /* mac_addrs must not be freed because in dev_private */
1512 list[i].eth_dev->data->mac_addrs = NULL;
1513 claim_zero(rte_eth_dev_release_port(list[i].eth_dev));
1515 /* Restore original error. */
1524 * DPDK callback to remove a PCI device.
1526 * This function removes all Ethernet devices belong to a given PCI device.
1528 * @param[in] pci_dev
1529 * Pointer to the PCI device.
1532 * 0 on success, the function cannot fail.
1535 mlx5_pci_remove(struct rte_pci_device *pci_dev)
1538 struct rte_eth_dev *port;
1540 for (port_id = 0; port_id < RTE_MAX_ETHPORTS; port_id++) {
1541 port = &rte_eth_devices[port_id];
1542 if (port->state != RTE_ETH_DEV_UNUSED &&
1543 port->device == &pci_dev->device)
1544 rte_eth_dev_close(port_id);
1549 static const struct rte_pci_id mlx5_pci_id_map[] = {
1551 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1552 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
1555 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1556 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
1559 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1560 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
1563 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1564 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
1567 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1568 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
1571 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1572 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
1575 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1576 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
1579 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1580 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
1583 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1584 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
1587 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1588 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
1595 static struct rte_pci_driver mlx5_driver = {
1597 .name = MLX5_DRIVER_NAME
1599 .id_table = mlx5_pci_id_map,
1600 .probe = mlx5_pci_probe,
1601 .remove = mlx5_pci_remove,
1602 .drv_flags = (RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV |
1603 RTE_PCI_DRV_PROBE_AGAIN),
1606 #ifdef RTE_LIBRTE_MLX5_DLOPEN_DEPS
1609 * Suffix RTE_EAL_PMD_PATH with "-glue".
1611 * This function performs a sanity check on RTE_EAL_PMD_PATH before
1612 * suffixing its last component.
1615 * Output buffer, should be large enough otherwise NULL is returned.
1620 * Pointer to @p buf or @p NULL in case suffix cannot be appended.
1623 mlx5_glue_path(char *buf, size_t size)
1625 static const char *const bad[] = { "/", ".", "..", NULL };
1626 const char *path = RTE_EAL_PMD_PATH;
1627 size_t len = strlen(path);
1631 while (len && path[len - 1] == '/')
1633 for (off = len; off && path[off - 1] != '/'; --off)
1635 for (i = 0; bad[i]; ++i)
1636 if (!strncmp(path + off, bad[i], (int)(len - off)))
1638 i = snprintf(buf, size, "%.*s-glue", (int)len, path);
1639 if (i == -1 || (size_t)i >= size)
1644 "unable to append \"-glue\" to last component of"
1645 " RTE_EAL_PMD_PATH (\"" RTE_EAL_PMD_PATH "\"),"
1646 " please re-configure DPDK");
1651 * Initialization routine for run-time dependency on rdma-core.
1654 mlx5_glue_init(void)
1656 char glue_path[sizeof(RTE_EAL_PMD_PATH) - 1 + sizeof("-glue")];
1657 const char *path[] = {
1659 * A basic security check is necessary before trusting
1660 * MLX5_GLUE_PATH, which may override RTE_EAL_PMD_PATH.
1662 (geteuid() == getuid() && getegid() == getgid() ?
1663 getenv("MLX5_GLUE_PATH") : NULL),
1665 * When RTE_EAL_PMD_PATH is set, use its glue-suffixed
1666 * variant, otherwise let dlopen() look up libraries on its
1669 (*RTE_EAL_PMD_PATH ?
1670 mlx5_glue_path(glue_path, sizeof(glue_path)) : ""),
1673 void *handle = NULL;
1677 while (!handle && i != RTE_DIM(path)) {
1686 end = strpbrk(path[i], ":;");
1688 end = path[i] + strlen(path[i]);
1689 len = end - path[i];
1694 ret = snprintf(name, sizeof(name), "%.*s%s" MLX5_GLUE,
1696 (!len || *(end - 1) == '/') ? "" : "/");
1699 if (sizeof(name) != (size_t)ret + 1)
1701 DRV_LOG(DEBUG, "looking for rdma-core glue as \"%s\"",
1703 handle = dlopen(name, RTLD_LAZY);
1714 DRV_LOG(WARNING, "cannot load glue library: %s", dlmsg);
1717 sym = dlsym(handle, "mlx5_glue");
1718 if (!sym || !*sym) {
1722 DRV_LOG(ERR, "cannot resolve glue symbol: %s", dlmsg);
1731 "cannot initialize PMD due to missing run-time dependency on"
1732 " rdma-core libraries (libibverbs, libmlx5)");
1739 * Driver initialization routine.
1741 RTE_INIT(rte_mlx5_pmd_init)
1743 /* Initialize driver log type. */
1744 mlx5_logtype = rte_log_register("pmd.net.mlx5");
1745 if (mlx5_logtype >= 0)
1746 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE);
1748 /* Build the static tables for Verbs conversion. */
1749 mlx5_set_ptype_table();
1750 mlx5_set_cksum_table();
1751 mlx5_set_swp_types_table();
1753 * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use
1754 * huge pages. Calling ibv_fork_init() during init allows
1755 * applications to use fork() safely for purposes other than
1756 * using this PMD, which is not supported in forked processes.
1758 setenv("RDMAV_HUGEPAGES_SAFE", "1", 1);
1759 /* Match the size of Rx completion entry to the size of a cacheline. */
1760 if (RTE_CACHE_LINE_SIZE == 128)
1761 setenv("MLX5_CQE_SIZE", "128", 0);
1763 * MLX5_DEVICE_FATAL_CLEANUP tells ibv_destroy functions to
1764 * cleanup all the Verbs resources even when the device was removed.
1766 setenv("MLX5_DEVICE_FATAL_CLEANUP", "1", 1);
1767 #ifdef RTE_LIBRTE_MLX5_DLOPEN_DEPS
1768 if (mlx5_glue_init())
1773 /* Glue structure must not contain any NULL pointers. */
1777 for (i = 0; i != sizeof(*mlx5_glue) / sizeof(void *); ++i)
1778 assert(((const void *const *)mlx5_glue)[i]);
1781 if (strcmp(mlx5_glue->version, MLX5_GLUE_VERSION)) {
1783 "rdma-core glue \"%s\" mismatch: \"%s\" is required",
1784 mlx5_glue->version, MLX5_GLUE_VERSION);
1787 mlx5_glue->fork_init();
1788 rte_pci_register(&mlx5_driver);
1791 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
1792 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
1793 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");