drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <stdint.h>
  10 #include <stdlib.h>
  11 #include <errno.h>
  12
  13 #include <rte_malloc.h>
  14 #include <ethdev_driver.h>
  15 #include <ethdev_pci.h>
  16 #include <rte_pci.h>
  17 #include <rte_bus_pci.h>
  18 #include <rte_common.h>
  19 #include <rte_kvargs.h>
  20 #include <rte_rwlock.h>
  21 #include <rte_spinlock.h>
  22 #include <rte_string_fns.h>
  23 #include <rte_alarm.h>
  24 #include <rte_cycles.h>
  25
  26 #include <mlx5_glue.h>
  27 #include <mlx5_devx_cmds.h>
  28 #include <mlx5_common.h>
  29 #include <mlx5_common_os.h>
  30 #include <mlx5_common_mp.h>
  31 #include <mlx5_common_pci.h>
  32 #include <mlx5_malloc.h>
  33
  34 #include "mlx5_defs.h"
  35 #include "mlx5.h"
  36 #include "mlx5_utils.h"
  37 #include "mlx5_rxtx.h"
  38 #include "mlx5_rx.h"
  39 #include "mlx5_tx.h"
  40 #include "mlx5_autoconf.h"
  41 #include "mlx5_mr.h"
  42 #include "mlx5_flow.h"
  43 #include "mlx5_flow_os.h"
  44 #include "rte_pmd_mlx5.h"
  45
  46 /* Device parameter to enable RX completion queue compression. */
  47 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  48
  49 /* Device parameter to enable padding Rx packet to cacheline size. */
  50 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
  51
  52 /* Device parameter to enable Multi-Packet Rx queue. */
  53 #define MLX5_RX_MPRQ_EN "mprq_en"
  54
  55 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
  56 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
  57
  58 /* Device parameter to configure log 2 of the stride size for MPRQ. */
  59 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
  60
  61 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
  62 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
  63
  64 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
  65 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
  66
  67 /* Device parameter to configure inline send. Deprecated, ignored.*/
  68 #define MLX5_TXQ_INLINE "txq_inline"
  69
  70 /* Device parameter to limit packet size to inline with ordinary SEND. */
  71 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
  72
  73 /* Device parameter to configure minimal data size to inline. */
  74 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
  75
  76 /* Device parameter to limit packet size to inline with Enhanced MPW. */
  77 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
  78
  79 /*
  80  * Device parameter to configure the number of TX queues threshold for
  81  * enabling inline send.
  82  */
  83 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  84
  85 /*
  86  * Device parameter to configure the number of TX queues threshold for
  87  * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
  88  */
  89 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
  90
  91 /* Device parameter to enable multi-packet send WQEs. */
  92 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
  93
  94 /*
  95  * Device parameter to force doorbell register mapping
  96  * to non-cahed region eliminating the extra write memory barrier.
  97  */
  98 #define MLX5_TX_DB_NC "tx_db_nc"
  99
 100 /*
 101  * Device parameter to include 2 dsegs in the title WQEBB.
 102  * Deprecated, ignored.
 103  */
 104 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
 105
 106 /*
 107  * Device parameter to limit the size of inlining packet.
 108  * Deprecated, ignored.
 109  */
 110 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
 111
 112 /*
 113  * Device parameter to enable Tx scheduling on timestamps
 114  * and specify the packet pacing granularity in nanoseconds.
 115  */
 116 #define MLX5_TX_PP "tx_pp"
 117
 118 /*
 119  * Device parameter to specify skew in nanoseconds on Tx datapath,
 120  * it represents the time between SQ start WQE processing and
 121  * appearing actual packet data on the wire.
 122  */
 123 #define MLX5_TX_SKEW "tx_skew"
 124
 125 /*
 126  * Device parameter to enable hardware Tx vector.
 127  * Deprecated, ignored (no vectorized Tx routines anymore).
 128  */
 129 #define MLX5_TX_VEC_EN "tx_vec_en"
 130
 131 /* Device parameter to enable hardware Rx vector. */
 132 #define MLX5_RX_VEC_EN "rx_vec_en"
 133
 134 /* Allow L3 VXLAN flow creation. */
 135 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
 136
 137 /* Activate DV E-Switch flow steering. */
 138 #define MLX5_DV_ESW_EN "dv_esw_en"
 139
 140 /* Activate DV flow steering. */
 141 #define MLX5_DV_FLOW_EN "dv_flow_en"
 142
 143 /* Enable extensive flow metadata support. */
 144 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
 145
 146 /* Device parameter to let the user manage the lacp traffic of bonded device */
 147 #define MLX5_LACP_BY_USER "lacp_by_user"
 148
 149 /* Activate Netlink support in VF mode. */
 150 #define MLX5_VF_NL_EN "vf_nl_en"
 151
 152 /* Enable extending memsegs when creating a MR. */
 153 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
 154
 155 /* Select port representors to instantiate. */
 156 #define MLX5_REPRESENTOR "representor"
 157
 158 /* Device parameter to configure the maximum number of dump files per queue. */
 159 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
 160
 161 /* Configure timeout of LRO session (in microseconds). */
 162 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
 163
 164 /*
 165  * Device parameter to configure the total data buffer size for a single
 166  * hairpin queue (logarithm value).
 167  */
 168 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
 169
 170 /* Flow memory reclaim mode. */
 171 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
 172
 173 /* The default memory allocator used in PMD. */
 174 #define MLX5_SYS_MEM_EN "sys_mem_en"
 175 /* Decap will be used or not. */
 176 #define MLX5_DECAP_EN "decap_en"
 177
 178 /* Shared memory between primary and secondary processes. */
 179 struct mlx5_shared_data *mlx5_shared_data;
 180
 181 /** Driver-specific log messages type. */
 182 int mlx5_logtype;
 183
 184 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
 185                                                 LIST_HEAD_INITIALIZER();
 186 static pthread_mutex_t mlx5_dev_ctx_list_mutex;
 187 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
 188 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
 189         [MLX5_IPOOL_DECAP_ENCAP] = {
 190                 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
 191                 .trunk_size = 64,
 192                 .grow_trunk = 3,
 193                 .grow_shift = 2,
 194                 .need_lock = 1,
 195                 .release_mem_en = 1,
 196                 .malloc = mlx5_malloc,
 197                 .free = mlx5_free,
 198                 .type = "mlx5_encap_decap_ipool",
 199         },
 200         [MLX5_IPOOL_PUSH_VLAN] = {
 201                 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
 202                 .trunk_size = 64,
 203                 .grow_trunk = 3,
 204                 .grow_shift = 2,
 205                 .need_lock = 1,
 206                 .release_mem_en = 1,
 207                 .malloc = mlx5_malloc,
 208                 .free = mlx5_free,
 209                 .type = "mlx5_push_vlan_ipool",
 210         },
 211         [MLX5_IPOOL_TAG] = {
 212                 .size = sizeof(struct mlx5_flow_dv_tag_resource),
 213                 .trunk_size = 64,
 214                 .grow_trunk = 3,
 215                 .grow_shift = 2,
 216                 .need_lock = 1,
 217                 .release_mem_en = 1,
 218                 .malloc = mlx5_malloc,
 219                 .free = mlx5_free,
 220                 .type = "mlx5_tag_ipool",
 221         },
 222         [MLX5_IPOOL_PORT_ID] = {
 223                 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
 224                 .trunk_size = 64,
 225                 .grow_trunk = 3,
 226                 .grow_shift = 2,
 227                 .need_lock = 1,
 228                 .release_mem_en = 1,
 229                 .malloc = mlx5_malloc,
 230                 .free = mlx5_free,
 231                 .type = "mlx5_port_id_ipool",
 232         },
 233         [MLX5_IPOOL_JUMP] = {
 234                 .size = sizeof(struct mlx5_flow_tbl_data_entry),
 235                 .trunk_size = 64,
 236                 .grow_trunk = 3,
 237                 .grow_shift = 2,
 238                 .need_lock = 1,
 239                 .release_mem_en = 1,
 240                 .malloc = mlx5_malloc,
 241                 .free = mlx5_free,
 242                 .type = "mlx5_jump_ipool",
 243         },
 244         [MLX5_IPOOL_SAMPLE] = {
 245                 .size = sizeof(struct mlx5_flow_dv_sample_resource),
 246                 .trunk_size = 64,
 247                 .grow_trunk = 3,
 248                 .grow_shift = 2,
 249                 .need_lock = 1,
 250                 .release_mem_en = 1,
 251                 .malloc = mlx5_malloc,
 252                 .free = mlx5_free,
 253                 .type = "mlx5_sample_ipool",
 254         },
 255         [MLX5_IPOOL_DEST_ARRAY] = {
 256                 .size = sizeof(struct mlx5_flow_dv_dest_array_resource),
 257                 .trunk_size = 64,
 258                 .grow_trunk = 3,
 259                 .grow_shift = 2,
 260                 .need_lock = 1,
 261                 .release_mem_en = 1,
 262                 .malloc = mlx5_malloc,
 263                 .free = mlx5_free,
 264                 .type = "mlx5_dest_array_ipool",
 265         },
 266         [MLX5_IPOOL_TUNNEL_ID] = {
 267                 .size = sizeof(struct mlx5_flow_tunnel),
 268                 .trunk_size = MLX5_MAX_TUNNELS,
 269                 .need_lock = 1,
 270                 .release_mem_en = 1,
 271                 .type = "mlx5_tunnel_offload",
 272         },
 273         [MLX5_IPOOL_TNL_TBL_ID] = {
 274                 .size = 0,
 275                 .need_lock = 1,
 276                 .type = "mlx5_flow_tnl_tbl_ipool",
 277         },
 278 #endif
 279         [MLX5_IPOOL_MTR] = {
 280                 /**
 281                  * The ipool index should grow continually from small to big,
 282                  * for meter idx, so not set grow_trunk to avoid meter index
 283                  * not jump continually.
 284                  */
 285                 .size = sizeof(struct mlx5_legacy_flow_meter),
 286                 .trunk_size = 64,
 287                 .need_lock = 1,
 288                 .release_mem_en = 1,
 289                 .malloc = mlx5_malloc,
 290                 .free = mlx5_free,
 291                 .type = "mlx5_meter_ipool",
 292         },
 293         [MLX5_IPOOL_MCP] = {
 294                 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
 295                 .trunk_size = 64,
 296                 .grow_trunk = 3,
 297                 .grow_shift = 2,
 298                 .need_lock = 1,
 299                 .release_mem_en = 1,
 300                 .malloc = mlx5_malloc,
 301                 .free = mlx5_free,
 302                 .type = "mlx5_mcp_ipool",
 303         },
 304         [MLX5_IPOOL_HRXQ] = {
 305                 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
 306                 .trunk_size = 64,
 307                 .grow_trunk = 3,
 308                 .grow_shift = 2,
 309                 .need_lock = 1,
 310                 .release_mem_en = 1,
 311                 .malloc = mlx5_malloc,
 312                 .free = mlx5_free,
 313                 .type = "mlx5_hrxq_ipool",
 314         },
 315         [MLX5_IPOOL_MLX5_FLOW] = {
 316                 /*
 317                  * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
 318                  * It set in run time according to PCI function configuration.
 319                  */
 320                 .size = 0,
 321                 .trunk_size = 64,
 322                 .grow_trunk = 3,
 323                 .grow_shift = 2,
 324                 .need_lock = 1,
 325                 .release_mem_en = 1,
 326                 .malloc = mlx5_malloc,
 327                 .free = mlx5_free,
 328                 .type = "mlx5_flow_handle_ipool",
 329         },
 330         [MLX5_IPOOL_RTE_FLOW] = {
 331                 .size = sizeof(struct rte_flow),
 332                 .trunk_size = 4096,
 333                 .need_lock = 1,
 334                 .release_mem_en = 1,
 335                 .malloc = mlx5_malloc,
 336                 .free = mlx5_free,
 337                 .type = "rte_flow_ipool",
 338         },
 339         [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID] = {
 340                 .size = 0,
 341                 .need_lock = 1,
 342                 .type = "mlx5_flow_rss_id_ipool",
 343         },
 344         [MLX5_IPOOL_RSS_SHARED_ACTIONS] = {
 345                 .size = sizeof(struct mlx5_shared_action_rss),
 346                 .trunk_size = 64,
 347                 .grow_trunk = 3,
 348                 .grow_shift = 2,
 349                 .need_lock = 1,
 350                 .release_mem_en = 1,
 351                 .malloc = mlx5_malloc,
 352                 .free = mlx5_free,
 353                 .type = "mlx5_shared_action_rss",
 354         },
 355 };
 356
 357
 358 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
 359 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
 360
 361 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
 362
 363 /**
 364  * Decide whether representor ID is a HPF(host PF) port on BF2.
 365  *
 366  * @param dev
 367  *   Pointer to Ethernet device structure.
 368  *
 369  * @return
 370  *   Non-zero if HPF, otherwise 0.
 371  */
 372 bool
 373 mlx5_is_hpf(struct rte_eth_dev *dev)
 374 {
 375         struct mlx5_priv *priv = dev->data->dev_private;
 376         uint16_t repr = MLX5_REPRESENTOR_REPR(priv->representor_id);
 377         int type = MLX5_REPRESENTOR_TYPE(priv->representor_id);
 378
 379         return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_VF &&
 380                MLX5_REPRESENTOR_REPR(-1) == repr;
 381 }
 382
 383 /**
 384  * Initialize the ASO aging management structure.
 385  *
 386  * @param[in] sh
 387  *   Pointer to mlx5_dev_ctx_shared object to free
 388  *
 389  * @return
 390  *   0 on success, a negative errno value otherwise and rte_errno is set.
 391  */
 392 int
 393 mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh)
 394 {
 395         int err;
 396
 397         if (sh->aso_age_mng)
 398                 return 0;
 399         sh->aso_age_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->aso_age_mng),
 400                                       RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 401         if (!sh->aso_age_mng) {
 402                 DRV_LOG(ERR, "aso_age_mng allocation was failed.");
 403                 rte_errno = ENOMEM;
 404                 return -ENOMEM;
 405         }
 406         err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_FLOW_HIT);
 407         if (err) {
 408                 mlx5_free(sh->aso_age_mng);
 409                 return -1;
 410         }
 411         rte_spinlock_init(&sh->aso_age_mng->resize_sl);
 412         rte_spinlock_init(&sh->aso_age_mng->free_sl);
 413         LIST_INIT(&sh->aso_age_mng->free);
 414         return 0;
 415 }
 416
 417 /**
 418  * Close and release all the resources of the ASO aging management structure.
 419  *
 420  * @param[in] sh
 421  *   Pointer to mlx5_dev_ctx_shared object to free.
 422  */
 423 static void
 424 mlx5_flow_aso_age_mng_close(struct mlx5_dev_ctx_shared *sh)
 425 {
 426         int i, j;
 427
 428         mlx5_aso_flow_hit_queue_poll_stop(sh);
 429         mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_FLOW_HIT);
 430         if (sh->aso_age_mng->pools) {
 431                 struct mlx5_aso_age_pool *pool;
 432
 433                 for (i = 0; i < sh->aso_age_mng->next; ++i) {
 434                         pool = sh->aso_age_mng->pools[i];
 435                         claim_zero(mlx5_devx_cmd_destroy
 436                                                 (pool->flow_hit_aso_obj));
 437                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j)
 438                                 if (pool->actions[j].dr_action)
 439                                         claim_zero
 440                                             (mlx5_flow_os_destroy_flow_action
 441                                               (pool->actions[j].dr_action));
 442                         mlx5_free(pool);
 443                 }
 444                 mlx5_free(sh->aso_age_mng->pools);
 445         }
 446         mlx5_free(sh->aso_age_mng);
 447 }
 448
 449 /**
 450  * Initialize the shared aging list information per port.
 451  *
 452  * @param[in] sh
 453  *   Pointer to mlx5_dev_ctx_shared object.
 454  */
 455 static void
 456 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
 457 {
 458         uint32_t i;
 459         struct mlx5_age_info *age_info;
 460
 461         for (i = 0; i < sh->max_port; i++) {
 462                 age_info = &sh->port[i].age_info;
 463                 age_info->flags = 0;
 464                 TAILQ_INIT(&age_info->aged_counters);
 465                 LIST_INIT(&age_info->aged_aso);
 466                 rte_spinlock_init(&age_info->aged_sl);
 467                 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
 468         }
 469 }
 470
 471 /**
 472  * Initialize the counters management structure.
 473  *
 474  * @param[in] sh
 475  *   Pointer to mlx5_dev_ctx_shared object to free
 476  */
 477 static void
 478 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
 479 {
 480         int i;
 481
 482         memset(&sh->cmng, 0, sizeof(sh->cmng));
 483         TAILQ_INIT(&sh->cmng.flow_counters);
 484         sh->cmng.min_id = MLX5_CNT_BATCH_OFFSET;
 485         sh->cmng.max_id = -1;
 486         sh->cmng.last_pool_idx = POOL_IDX_INVALID;
 487         rte_spinlock_init(&sh->cmng.pool_update_sl);
 488         for (i = 0; i < MLX5_COUNTER_TYPE_MAX; i++) {
 489                 TAILQ_INIT(&sh->cmng.counters[i]);
 490                 rte_spinlock_init(&sh->cmng.csl[i]);
 491         }
 492 }
 493
 494 /**
 495  * Destroy all the resources allocated for a counter memory management.
 496  *
 497  * @param[in] mng
 498  *   Pointer to the memory management structure.
 499  */
 500 static void
 501 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
 502 {
 503         uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
 504
 505         LIST_REMOVE(mng, next);
 506         claim_zero(mlx5_devx_cmd_destroy(mng->dm));
 507         claim_zero(mlx5_os_umem_dereg(mng->umem));
 508         mlx5_free(mem);
 509 }
 510
 511 /**
 512  * Close and release all the resources of the counters management.
 513  *
 514  * @param[in] sh
 515  *   Pointer to mlx5_dev_ctx_shared object to free.
 516  */
 517 static void
 518 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
 519 {
 520         struct mlx5_counter_stats_mem_mng *mng;
 521         int i, j;
 522         int retries = 1024;
 523
 524         rte_errno = 0;
 525         while (--retries) {
 526                 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
 527                 if (rte_errno != EINPROGRESS)
 528                         break;
 529                 rte_pause();
 530         }
 531
 532         if (sh->cmng.pools) {
 533                 struct mlx5_flow_counter_pool *pool;
 534                 uint16_t n_valid = sh->cmng.n_valid;
 535                 bool fallback = sh->cmng.counter_fallback;
 536
 537                 for (i = 0; i < n_valid; ++i) {
 538                         pool = sh->cmng.pools[i];
 539                         if (!fallback && pool->min_dcs)
 540                                 claim_zero(mlx5_devx_cmd_destroy
 541                                                                (pool->min_dcs));
 542                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
 543                                 struct mlx5_flow_counter *cnt =
 544                                                 MLX5_POOL_GET_CNT(pool, j);
 545
 546                                 if (cnt->action)
 547                                         claim_zero
 548                                          (mlx5_flow_os_destroy_flow_action
 549                                           (cnt->action));
 550                                 if (fallback && MLX5_POOL_GET_CNT
 551                                     (pool, j)->dcs_when_free)
 552                                         claim_zero(mlx5_devx_cmd_destroy
 553                                                    (cnt->dcs_when_free));
 554                         }
 555                         mlx5_free(pool);
 556                 }
 557                 mlx5_free(sh->cmng.pools);
 558         }
 559         mng = LIST_FIRST(&sh->cmng.mem_mngs);
 560         while (mng) {
 561                 mlx5_flow_destroy_counter_stat_mem_mng(mng);
 562                 mng = LIST_FIRST(&sh->cmng.mem_mngs);
 563         }
 564         memset(&sh->cmng, 0, sizeof(sh->cmng));
 565 }
 566
 567 /**
 568  * Initialize the aso flow meters management structure.
 569  *
 570  * @param[in] sh
 571  *   Pointer to mlx5_dev_ctx_shared object to free
 572  */
 573 int
 574 mlx5_aso_flow_mtrs_mng_init(struct mlx5_priv *priv)
 575 {
 576         if (!priv->mtr_idx_tbl) {
 577                 priv->mtr_idx_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_DWORD);
 578                 if (!priv->mtr_idx_tbl) {
 579                         DRV_LOG(ERR, "fail to create meter lookup table.");
 580                         rte_errno = ENOMEM;
 581                         return -ENOMEM;
 582                 }
 583         }
 584         if (!priv->sh->mtrmng) {
 585                 priv->sh->mtrmng = mlx5_malloc(MLX5_MEM_ZERO,
 586                         sizeof(*priv->sh->mtrmng),
 587                         RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 588                 if (!priv->sh->mtrmng) {
 589                         DRV_LOG(ERR, "mlx5_aso_mtr_pools_mng allocation was failed.");
 590                         rte_errno = ENOMEM;
 591                         return -ENOMEM;
 592                 }
 593                 rte_spinlock_init(&priv->sh->mtrmng->mtrsl);
 594                 LIST_INIT(&priv->sh->mtrmng->meters);
 595         }
 596         return 0;
 597 }
 598
 599 /**
 600  * Close and release all the resources of
 601  * the ASO flow meter management structure.
 602  *
 603  * @param[in] sh
 604  *   Pointer to mlx5_dev_ctx_shared object to free.
 605  */
 606 static void
 607 mlx5_aso_flow_mtrs_mng_close(struct mlx5_dev_ctx_shared *sh)
 608 {
 609         struct mlx5_aso_mtr_pool *mtr_pool;
 610         struct mlx5_aso_mtr_pools_mng *mtrmng = sh->mtrmng;
 611         uint32_t idx;
 612
 613         mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_POLICER);
 614         idx = mtrmng->n_valid;
 615         while (idx--) {
 616                 mtr_pool = mtrmng->pools[idx];
 617                 claim_zero(mlx5_devx_cmd_destroy
 618                                                 (mtr_pool->devx_obj));
 619                 mtrmng->n_valid--;
 620                 mlx5_free(mtr_pool);
 621         }
 622         mlx5_free(sh->mtrmng->pools);
 623         mlx5_free(sh->mtrmng);
 624         sh->mtrmng = NULL;
 625 }
 626
 627 /* Send FLOW_AGED event if needed. */
 628 void
 629 mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh)
 630 {
 631         struct mlx5_age_info *age_info;
 632         uint32_t i;
 633
 634         for (i = 0; i < sh->max_port; i++) {
 635                 age_info = &sh->port[i].age_info;
 636                 if (!MLX5_AGE_GET(age_info, MLX5_AGE_EVENT_NEW))
 637                         continue;
 638                 if (MLX5_AGE_GET(age_info, MLX5_AGE_TRIGGER))
 639                         rte_eth_dev_callback_process
 640                                 (&rte_eth_devices[sh->port[i].devx_ih_port_id],
 641                                 RTE_ETH_EVENT_FLOW_AGED, NULL);
 642                 age_info->flags = 0;
 643         }
 644 }
 645
 646 /**
 647  * Initialize the flow resources' indexed mempool.
 648  *
 649  * @param[in] sh
 650  *   Pointer to mlx5_dev_ctx_shared object.
 651  * @param[in] sh
 652  *   Pointer to user dev config.
 653  */
 654 static void
 655 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
 656                        const struct mlx5_dev_config *config)
 657 {
 658         uint8_t i;
 659         struct mlx5_indexed_pool_config cfg;
 660
 661         for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
 662                 cfg = mlx5_ipool_cfg[i];
 663                 switch (i) {
 664                 default:
 665                         break;
 666                 /*
 667                  * Set MLX5_IPOOL_MLX5_FLOW ipool size
 668                  * according to PCI function flow configuration.
 669                  */
 670                 case MLX5_IPOOL_MLX5_FLOW:
 671                         cfg.size = config->dv_flow_en ?
 672                                 sizeof(struct mlx5_flow_handle) :
 673                                 MLX5_FLOW_HANDLE_VERBS_SIZE;
 674                         break;
 675                 }
 676                 if (config->reclaim_mode)
 677                         cfg.release_mem_en = 1;
 678                 sh->ipool[i] = mlx5_ipool_create(&cfg);
 679         }
 680 }
 681
 682 /**
 683  * Release the flow resources' indexed mempool.
 684  *
 685  * @param[in] sh
 686  *   Pointer to mlx5_dev_ctx_shared object.
 687  */
 688 static void
 689 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
 690 {
 691         uint8_t i;
 692
 693         for (i = 0; i < MLX5_IPOOL_MAX; ++i)
 694                 mlx5_ipool_destroy(sh->ipool[i]);
 695 }
 696
 697 /*
 698  * Check if dynamic flex parser for eCPRI already exists.
 699  *
 700  * @param dev
 701  *   Pointer to Ethernet device structure.
 702  *
 703  * @return
 704  *   true on exists, false on not.
 705  */
 706 bool
 707 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
 708 {
 709         struct mlx5_priv *priv = dev->data->dev_private;
 710         struct mlx5_flex_parser_profiles *prf =
 711                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 712
 713         return !!prf->obj;
 714 }
 715
 716 /*
 717  * Allocation of a flex parser for eCPRI. Once created, this parser related
 718  * resources will be held until the device is closed.
 719  *
 720  * @param dev
 721  *   Pointer to Ethernet device structure.
 722  *
 723  * @return
 724  *   0 on success, a negative errno value otherwise and rte_errno is set.
 725  */
 726 int
 727 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
 728 {
 729         struct mlx5_priv *priv = dev->data->dev_private;
 730         struct mlx5_flex_parser_profiles *prf =
 731                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 732         struct mlx5_devx_graph_node_attr node = {
 733                 .modify_field_select = 0,
 734         };
 735         uint32_t ids[8];
 736         int ret;
 737
 738         if (!priv->config.hca_attr.parse_graph_flex_node) {
 739                 DRV_LOG(ERR, "Dynamic flex parser is not supported "
 740                         "for device %s.", priv->dev_data->name);
 741                 return -ENOTSUP;
 742         }
 743         node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED;
 744         /* 8 bytes now: 4B common header + 4B message body header. */
 745         node.header_length_base_value = 0x8;
 746         /* After MAC layer: Ether / VLAN. */
 747         node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC;
 748         /* Type of compared condition should be 0xAEFE in the L2 layer. */
 749         node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI;
 750         /* Sample #0: type in common header. */
 751         node.sample[0].flow_match_sample_en = 1;
 752         /* Fixed offset. */
 753         node.sample[0].flow_match_sample_offset_mode = 0x0;
 754         /* Only the 2nd byte will be used. */
 755         node.sample[0].flow_match_sample_field_base_offset = 0x0;
 756         /* Sample #1: message payload. */
 757         node.sample[1].flow_match_sample_en = 1;
 758         /* Fixed offset. */
 759         node.sample[1].flow_match_sample_offset_mode = 0x0;
 760         /*
 761          * Only the first two bytes will be used right now, and its offset will
 762          * start after the common header that with the length of a DW(u32).
 763          */
 764         node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);
 765         prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->ctx, &node);
 766         if (!prf->obj) {
 767                 DRV_LOG(ERR, "Failed to create flex parser node object.");
 768                 return (rte_errno == 0) ? -ENODEV : -rte_errno;
 769         }
 770         prf->num = 2;
 771         ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num);
 772         if (ret) {
 773                 DRV_LOG(ERR, "Failed to query sample IDs.");
 774                 return (rte_errno == 0) ? -ENODEV : -rte_errno;
 775         }
 776         prf->offset[0] = 0x0;
 777         prf->offset[1] = sizeof(uint32_t);
 778         prf->ids[0] = ids[0];
 779         prf->ids[1] = ids[1];
 780         return 0;
 781 }
 782
 783 /*
 784  * Destroy the flex parser node, including the parser itself, input / output
 785  * arcs and DW samples. Resources could be reused then.
 786  *
 787  * @param dev
 788  *   Pointer to Ethernet device structure.
 789  */
 790 static void
 791 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
 792 {
 793         struct mlx5_priv *priv = dev->data->dev_private;
 794         struct mlx5_flex_parser_profiles *prf =
 795                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 796
 797         if (prf->obj)
 798                 mlx5_devx_cmd_destroy(prf->obj);
 799         prf->obj = NULL;
 800 }
 801
 802 /*
 803  * Allocate Rx and Tx UARs in robust fashion.
 804  * This routine handles the following UAR allocation issues:
 805  *
 806  *  - tries to allocate the UAR with the most appropriate memory
 807  *    mapping type from the ones supported by the host
 808  *
 809  *  - tries to allocate the UAR with non-NULL base address
 810  *    OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as
 811  *    UAR base address if UAR was not the first object in the UAR page.
 812  *    It caused the PMD failure and we should try to get another UAR
 813  *    till we get the first one with non-NULL base address returned.
 814  */
 815 static int
 816 mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh,
 817                      const struct mlx5_dev_config *config)
 818 {
 819         uint32_t uar_mapping, retry;
 820         int err = 0;
 821         void *base_addr;
 822
 823         for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
 824 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
 825                 /* Control the mapping type according to the settings. */
 826                 uar_mapping = (config->dbnc == MLX5_TXDB_NCACHED) ?
 827                               MLX5DV_UAR_ALLOC_TYPE_NC :
 828                               MLX5DV_UAR_ALLOC_TYPE_BF;
 829 #else
 830                 RTE_SET_USED(config);
 831                 /*
 832                  * It seems we have no way to control the memory mapping type
 833                  * for the UAR, the default "Write-Combining" type is supposed.
 834                  * The UAR initialization on queue creation queries the
 835                  * actual mapping type done by Verbs/kernel and setups the
 836                  * PMD datapath accordingly.
 837                  */
 838                 uar_mapping = 0;
 839 #endif
 840                 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->ctx, uar_mapping);
 841 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
 842                 if (!sh->tx_uar &&
 843                     uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
 844                         if (config->dbnc == MLX5_TXDB_CACHED ||
 845                             config->dbnc == MLX5_TXDB_HEURISTIC)
 846                                 DRV_LOG(WARNING, "Devarg tx_db_nc setting "
 847                                                  "is not supported by DevX");
 848                         /*
 849                          * In some environments like virtual machine
 850                          * the Write Combining mapped might be not supported
 851                          * and UAR allocation fails. We try "Non-Cached"
 852                          * mapping for the case. The tx_burst routines take
 853                          * the UAR mapping type into account on UAR setup
 854                          * on queue creation.
 855                          */
 856                         DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (BF)");
 857                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
 858                         sh->tx_uar = mlx5_glue->devx_alloc_uar
 859                                                         (sh->ctx, uar_mapping);
 860                 } else if (!sh->tx_uar &&
 861                            uar_mapping == MLX5DV_UAR_ALLOC_TYPE_NC) {
 862                         if (config->dbnc == MLX5_TXDB_NCACHED)
 863                                 DRV_LOG(WARNING, "Devarg tx_db_nc settings "
 864                                                  "is not supported by DevX");
 865                         /*
 866                          * If Verbs/kernel does not support "Non-Cached"
 867                          * try the "Write-Combining".
 868                          */
 869                         DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (NC)");
 870                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_BF;
 871                         sh->tx_uar = mlx5_glue->devx_alloc_uar
 872                                                         (sh->ctx, uar_mapping);
 873                 }
 874 #endif
 875                 if (!sh->tx_uar) {
 876                         DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (BF/NC)");
 877                         err = ENOMEM;
 878                         goto exit;
 879                 }
 880                 base_addr = mlx5_os_get_devx_uar_base_addr(sh->tx_uar);
 881                 if (base_addr)
 882                         break;
 883                 /*
 884                  * The UARs are allocated by rdma_core within the
 885                  * IB device context, on context closure all UARs
 886                  * will be freed, should be no memory/object leakage.
 887                  */
 888                 DRV_LOG(DEBUG, "Retrying to allocate Tx DevX UAR");
 889                 sh->tx_uar = NULL;
 890         }
 891         /* Check whether we finally succeeded with valid UAR allocation. */
 892         if (!sh->tx_uar) {
 893                 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (NULL base)");
 894                 err = ENOMEM;
 895                 goto exit;
 896         }
 897         for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
 898                 uar_mapping = 0;
 899                 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
 900                                                         (sh->ctx, uar_mapping);
 901 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
 902                 if (!sh->devx_rx_uar &&
 903                     uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
 904                         /*
 905                          * Rx UAR is used to control interrupts only,
 906                          * should be no datapath noticeable impact,
 907                          * can try "Non-Cached" mapping safely.
 908                          */
 909                         DRV_LOG(DEBUG, "Failed to allocate Rx DevX UAR (BF)");
 910                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
 911                         sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
 912                                                         (sh->ctx, uar_mapping);
 913                 }
 914 #endif
 915                 if (!sh->devx_rx_uar) {
 916                         DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (BF/NC)");
 917                         err = ENOMEM;
 918                         goto exit;
 919                 }
 920                 base_addr = mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar);
 921                 if (base_addr)
 922                         break;
 923                 /*
 924                  * The UARs are allocated by rdma_core within the
 925                  * IB device context, on context closure all UARs
 926                  * will be freed, should be no memory/object leakage.
 927                  */
 928                 DRV_LOG(DEBUG, "Retrying to allocate Rx DevX UAR");
 929                 sh->devx_rx_uar = NULL;
 930         }
 931         /* Check whether we finally succeeded with valid UAR allocation. */
 932         if (!sh->devx_rx_uar) {
 933                 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (NULL base)");
 934                 err = ENOMEM;
 935         }
 936 exit:
 937         return err;
 938 }
 939
 940 /**
 941  * Allocate shared device context. If there is multiport device the
 942  * master and representors will share this context, if there is single
 943  * port dedicated device, the context will be used by only given
 944  * port due to unification.
 945  *
 946  * Routine first searches the context for the specified device name,
 947  * if found the shared context assumed and reference counter is incremented.
 948  * If no context found the new one is created and initialized with specified
 949  * device context and parameters.
 950  *
 951  * @param[in] spawn
 952  *   Pointer to the device attributes (name, port, etc).
 953  * @param[in] config
 954  *   Pointer to device configuration structure.
 955  *
 956  * @return
 957  *   Pointer to mlx5_dev_ctx_shared object on success,
 958  *   otherwise NULL and rte_errno is set.
 959  */
 960 struct mlx5_dev_ctx_shared *
 961 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
 962                            const struct mlx5_dev_config *config)
 963 {
 964         struct mlx5_dev_ctx_shared *sh;
 965         int err = 0;
 966         uint32_t i;
 967         struct mlx5_devx_tis_attr tis_attr = { 0 };
 968
 969         MLX5_ASSERT(spawn);
 970         /* Secondary process should not create the shared context. */
 971         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 972         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
 973         /* Search for IB context by device name. */
 974         LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
 975                 if (!strcmp(sh->ibdev_name,
 976                         mlx5_os_get_dev_device_name(spawn->phys_dev))) {
 977                         sh->refcnt++;
 978                         goto exit;
 979                 }
 980         }
 981         /* No device found, we have to create new shared context. */
 982         MLX5_ASSERT(spawn->max_port);
 983         sh = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
 984                          sizeof(struct mlx5_dev_ctx_shared) +
 985                          spawn->max_port *
 986                          sizeof(struct mlx5_dev_shared_port),
 987                          RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 988         if (!sh) {
 989                 DRV_LOG(ERR, "shared context allocation failure");
 990                 rte_errno  = ENOMEM;
 991                 goto exit;
 992         }
 993         if (spawn->bond_info)
 994                 sh->bond = *spawn->bond_info;
 995         err = mlx5_os_open_device(spawn, config, sh);
 996         if (!sh->ctx)
 997                 goto error;
 998         err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
 999         if (err) {
1000                 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
1001                 goto error;
1002         }
1003         sh->refcnt = 1;
1004         sh->max_port = spawn->max_port;
1005         strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
1006                 sizeof(sh->ibdev_name) - 1);
1007         strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
1008                 sizeof(sh->ibdev_path) - 1);
1009         /*
1010          * Setting port_id to max unallowed value means
1011          * there is no interrupt subhandler installed for
1012          * the given port index i.
1013          */
1014         for (i = 0; i < sh->max_port; i++) {
1015                 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
1016                 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
1017         }
1018         sh->pd = mlx5_os_alloc_pd(sh->ctx);
1019         if (sh->pd == NULL) {
1020                 DRV_LOG(ERR, "PD allocation failure");
1021                 err = ENOMEM;
1022                 goto error;
1023         }
1024         if (sh->devx) {
1025                 err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
1026                 if (err) {
1027                         DRV_LOG(ERR, "Fail to extract pdn from PD");
1028                         goto error;
1029                 }
1030                 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
1031                 if (!sh->td) {
1032                         DRV_LOG(ERR, "TD allocation failure");
1033                         err = ENOMEM;
1034                         goto error;
1035                 }
1036                 tis_attr.transport_domain = sh->td->id;
1037                 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
1038                 if (!sh->tis) {
1039                         DRV_LOG(ERR, "TIS allocation failure");
1040                         err = ENOMEM;
1041                         goto error;
1042                 }
1043                 err = mlx5_alloc_rxtx_uars(sh, config);
1044                 if (err)
1045                         goto error;
1046                 MLX5_ASSERT(sh->tx_uar);
1047                 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->tx_uar));
1048
1049                 MLX5_ASSERT(sh->devx_rx_uar);
1050                 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar));
1051         }
1052 #ifndef RTE_ARCH_64
1053         /* Initialize UAR access locks for 32bit implementations. */
1054         rte_spinlock_init(&sh->uar_lock_cq);
1055         for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
1056                 rte_spinlock_init(&sh->uar_lock[i]);
1057 #endif
1058         /*
1059          * Once the device is added to the list of memory event
1060          * callback, its global MR cache table cannot be expanded
1061          * on the fly because of deadlock. If it overflows, lookup
1062          * should be done by searching MR list linearly, which is slow.
1063          *
1064          * At this point the device is not added to the memory
1065          * event list yet, context is just being created.
1066          */
1067         err = mlx5_mr_btree_init(&sh->share_cache.cache,
1068                                  MLX5_MR_BTREE_CACHE_N * 2,
1069                                  spawn->pci_dev->device.numa_node);
1070         if (err) {
1071                 err = rte_errno;
1072                 goto error;
1073         }
1074         mlx5_os_set_reg_mr_cb(&sh->share_cache.reg_mr_cb,
1075                               &sh->share_cache.dereg_mr_cb);
1076         mlx5_os_dev_shared_handler_install(sh);
1077         sh->cnt_id_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_DWORD);
1078         if (!sh->cnt_id_tbl) {
1079                 err = rte_errno;
1080                 goto error;
1081         }
1082         if (LIST_EMPTY(&mlx5_dev_ctx_list)) {
1083                 err = mlx5_flow_os_init_workspace_once();
1084                 if (err)
1085                         goto error;
1086         }
1087         mlx5_flow_aging_init(sh);
1088         mlx5_flow_counters_mng_init(sh);
1089         mlx5_flow_ipool_create(sh, config);
1090         /* Add device to memory callback list. */
1091         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1092         LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
1093                          sh, mem_event_cb);
1094         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1095         /* Add context to the global device list. */
1096         LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
1097         rte_spinlock_init(&sh->geneve_tlv_opt_sl);
1098 exit:
1099         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1100         return sh;
1101 error:
1102         pthread_mutex_destroy(&sh->txpp.mutex);
1103         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1104         MLX5_ASSERT(sh);
1105         if (sh->cnt_id_tbl)
1106                 mlx5_l3t_destroy(sh->cnt_id_tbl);
1107         if (sh->tis)
1108                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1109         if (sh->td)
1110                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1111         if (sh->devx_rx_uar)
1112                 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1113         if (sh->tx_uar)
1114                 mlx5_glue->devx_free_uar(sh->tx_uar);
1115         if (sh->pd)
1116                 claim_zero(mlx5_os_dealloc_pd(sh->pd));
1117         if (sh->ctx)
1118                 claim_zero(mlx5_glue->close_device(sh->ctx));
1119         mlx5_free(sh);
1120         MLX5_ASSERT(err > 0);
1121         rte_errno = err;
1122         return NULL;
1123 }
1124
1125 /**
1126  * Free shared IB device context. Decrement counter and if zero free
1127  * all allocated resources and close handles.
1128  *
1129  * @param[in] sh
1130  *   Pointer to mlx5_dev_ctx_shared object to free
1131  */
1132 void
1133 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
1134 {
1135         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1136 #ifdef RTE_LIBRTE_MLX5_DEBUG
1137         /* Check the object presence in the list. */
1138         struct mlx5_dev_ctx_shared *lctx;
1139
1140         LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
1141                 if (lctx == sh)
1142                         break;
1143         MLX5_ASSERT(lctx);
1144         if (lctx != sh) {
1145                 DRV_LOG(ERR, "Freeing non-existing shared IB context");
1146                 goto exit;
1147         }
1148 #endif
1149         MLX5_ASSERT(sh);
1150         MLX5_ASSERT(sh->refcnt);
1151         /* Secondary process should not free the shared context. */
1152         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1153         if (--sh->refcnt)
1154                 goto exit;
1155         /* Remove from memory callback device list. */
1156         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1157         LIST_REMOVE(sh, mem_event_cb);
1158         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1159         /* Release created Memory Regions. */
1160         mlx5_mr_release_cache(&sh->share_cache);
1161         /* Remove context from the global device list. */
1162         LIST_REMOVE(sh, next);
1163         /* Release flow workspaces objects on the last device. */
1164         if (LIST_EMPTY(&mlx5_dev_ctx_list))
1165                 mlx5_flow_os_release_workspace();
1166         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1167         /*
1168          *  Ensure there is no async event handler installed.
1169          *  Only primary process handles async device events.
1170          **/
1171         mlx5_flow_counters_mng_close(sh);
1172         if (sh->aso_age_mng) {
1173                 mlx5_flow_aso_age_mng_close(sh);
1174                 sh->aso_age_mng = NULL;
1175         }
1176         if (sh->mtrmng)
1177                 mlx5_aso_flow_mtrs_mng_close(sh);
1178         mlx5_flow_ipool_destroy(sh);
1179         mlx5_os_dev_shared_handler_uninstall(sh);
1180         if (sh->cnt_id_tbl) {
1181                 mlx5_l3t_destroy(sh->cnt_id_tbl);
1182                 sh->cnt_id_tbl = NULL;
1183         }
1184         if (sh->tx_uar) {
1185                 mlx5_glue->devx_free_uar(sh->tx_uar);
1186                 sh->tx_uar = NULL;
1187         }
1188         if (sh->pd)
1189                 claim_zero(mlx5_os_dealloc_pd(sh->pd));
1190         if (sh->tis)
1191                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1192         if (sh->td)
1193                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1194         if (sh->devx_rx_uar)
1195                 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1196         if (sh->ctx)
1197                 claim_zero(mlx5_glue->close_device(sh->ctx));
1198         MLX5_ASSERT(sh->geneve_tlv_option_resource == NULL);
1199         pthread_mutex_destroy(&sh->txpp.mutex);
1200         mlx5_free(sh);
1201         return;
1202 exit:
1203         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1204 }
1205
1206 /**
1207  * Destroy table hash list.
1208  *
1209  * @param[in] priv
1210  *   Pointer to the private device data structure.
1211  */
1212 void
1213 mlx5_free_table_hash_list(struct mlx5_priv *priv)
1214 {
1215         struct mlx5_dev_ctx_shared *sh = priv->sh;
1216
1217         if (!sh->flow_tbls)
1218                 return;
1219         mlx5_hlist_destroy(sh->flow_tbls);
1220 }
1221
1222 /**
1223  * Initialize flow table hash list and create the root tables entry
1224  * for each domain.
1225  *
1226  * @param[in] priv
1227  *   Pointer to the private device data structure.
1228  *
1229  * @return
1230  *   Zero on success, positive error code otherwise.
1231  */
1232 int
1233 mlx5_alloc_table_hash_list(struct mlx5_priv *priv __rte_unused)
1234 {
1235         int err = 0;
1236         /* Tables are only used in DV and DR modes. */
1237 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
1238         struct mlx5_dev_ctx_shared *sh = priv->sh;
1239         char s[MLX5_HLIST_NAMESIZE];
1240
1241         MLX5_ASSERT(sh);
1242         snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1243         sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE,
1244                                           0, 0, flow_dv_tbl_create_cb,
1245                                           flow_dv_tbl_match_cb,
1246                                           flow_dv_tbl_remove_cb);
1247         if (!sh->flow_tbls) {
1248                 DRV_LOG(ERR, "flow tables with hash creation failed.");
1249                 err = ENOMEM;
1250                 return err;
1251         }
1252         sh->flow_tbls->ctx = sh;
1253 #ifndef HAVE_MLX5DV_DR
1254         struct rte_flow_error error;
1255         struct rte_eth_dev *dev = &rte_eth_devices[priv->dev_data->port_id];
1256
1257         /*
1258          * In case we have not DR support, the zero tables should be created
1259          * because DV expect to see them even if they cannot be created by
1260          * RDMA-CORE.
1261          */
1262         if (!flow_dv_tbl_resource_get(dev, 0, 0, 0, 0, NULL, 0, 1, &error) ||
1263             !flow_dv_tbl_resource_get(dev, 0, 1, 0, 0, NULL, 0, 1, &error) ||
1264             !flow_dv_tbl_resource_get(dev, 0, 0, 1, 0, NULL, 0, 1, &error)) {
1265                 err = ENOMEM;
1266                 goto error;
1267         }
1268         return err;
1269 error:
1270         mlx5_free_table_hash_list(priv);
1271 #endif /* HAVE_MLX5DV_DR */
1272 #endif
1273         return err;
1274 }
1275
1276 /**
1277  * Retrieve integer value from environment variable.
1278  *
1279  * @param[in] name
1280  *   Environment variable name.
1281  *
1282  * @return
1283  *   Integer value, 0 if the variable is not set.
1284  */
1285 int
1286 mlx5_getenv_int(const char *name)
1287 {
1288         const char *val = getenv(name);
1289
1290         if (val == NULL)
1291                 return 0;
1292         return atoi(val);
1293 }
1294
1295 /**
1296  * DPDK callback to add udp tunnel port
1297  *
1298  * @param[in] dev
1299  *   A pointer to eth_dev
1300  * @param[in] udp_tunnel
1301  *   A pointer to udp tunnel
1302  *
1303  * @return
1304  *   0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1305  */
1306 int
1307 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1308                          struct rte_eth_udp_tunnel *udp_tunnel)
1309 {
1310         MLX5_ASSERT(udp_tunnel != NULL);
1311         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1312             udp_tunnel->udp_port == 4789)
1313                 return 0;
1314         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1315             udp_tunnel->udp_port == 4790)
1316                 return 0;
1317         return -ENOTSUP;
1318 }
1319
1320 /**
1321  * Initialize process private data structure.
1322  *
1323  * @param dev
1324  *   Pointer to Ethernet device structure.
1325  *
1326  * @return
1327  *   0 on success, a negative errno value otherwise and rte_errno is set.
1328  */
1329 int
1330 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1331 {
1332         struct mlx5_priv *priv = dev->data->dev_private;
1333         struct mlx5_proc_priv *ppriv;
1334         size_t ppriv_size;
1335
1336         /*
1337          * UAR register table follows the process private structure. BlueFlame
1338          * registers for Tx queues are stored in the table.
1339          */
1340         ppriv_size =
1341                 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1342         ppriv = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, ppriv_size,
1343                             RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1344         if (!ppriv) {
1345                 rte_errno = ENOMEM;
1346                 return -rte_errno;
1347         }
1348         ppriv->uar_table_sz = priv->txqs_n;
1349         dev->process_private = ppriv;
1350         return 0;
1351 }
1352
1353 /**
1354  * Un-initialize process private data structure.
1355  *
1356  * @param dev
1357  *   Pointer to Ethernet device structure.
1358  */
1359 void
1360 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1361 {
1362         if (!dev->process_private)
1363                 return;
1364         mlx5_free(dev->process_private);
1365         dev->process_private = NULL;
1366 }
1367
1368 /**
1369  * DPDK callback to close the device.
1370  *
1371  * Destroy all queues and objects, free memory.
1372  *
1373  * @param dev
1374  *   Pointer to Ethernet device structure.
1375  */
1376 int
1377 mlx5_dev_close(struct rte_eth_dev *dev)
1378 {
1379         struct mlx5_priv *priv = dev->data->dev_private;
1380         unsigned int i;
1381         int ret;
1382
1383         if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1384                 /* Check if process_private released. */
1385                 if (!dev->process_private)
1386                         return 0;
1387                 mlx5_tx_uar_uninit_secondary(dev);
1388                 mlx5_proc_priv_uninit(dev);
1389                 rte_eth_dev_release_port(dev);
1390                 return 0;
1391         }
1392         if (!priv->sh)
1393                 return 0;
1394         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1395                 dev->data->port_id,
1396                 ((priv->sh->ctx != NULL) ?
1397                 mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
1398         /*
1399          * If default mreg copy action is removed at the stop stage,
1400          * the search will return none and nothing will be done anymore.
1401          */
1402         mlx5_flow_stop_default(dev);
1403         mlx5_traffic_disable(dev);
1404         /*
1405          * If all the flows are already flushed in the device stop stage,
1406          * then this will return directly without any action.
1407          */
1408         mlx5_flow_list_flush(dev, &priv->flows, true);
1409         mlx5_action_handle_flush(dev);
1410         mlx5_flow_meter_flush(dev, NULL);
1411         /* Prevent crashes when queues are still in use. */
1412         dev->rx_pkt_burst = removed_rx_burst;
1413         dev->tx_pkt_burst = removed_tx_burst;
1414         rte_wmb();
1415         /* Disable datapath on secondary process. */
1416         mlx5_mp_os_req_stop_rxtx(dev);
1417         /* Free the eCPRI flex parser resource. */
1418         mlx5_flex_parser_ecpri_release(dev);
1419         if (priv->rxqs != NULL) {
1420                 /* XXX race condition if mlx5_rx_burst() is still running. */
1421                 rte_delay_us_sleep(1000);
1422                 for (i = 0; (i != priv->rxqs_n); ++i)
1423                         mlx5_rxq_release(dev, i);
1424                 priv->rxqs_n = 0;
1425                 priv->rxqs = NULL;
1426         }
1427         if (priv->txqs != NULL) {
1428                 /* XXX race condition if mlx5_tx_burst() is still running. */
1429                 rte_delay_us_sleep(1000);
1430                 for (i = 0; (i != priv->txqs_n); ++i)
1431                         mlx5_txq_release(dev, i);
1432                 priv->txqs_n = 0;
1433                 priv->txqs = NULL;
1434         }
1435         mlx5_proc_priv_uninit(dev);
1436         if (priv->q_counters) {
1437                 mlx5_devx_cmd_destroy(priv->q_counters);
1438                 priv->q_counters = NULL;
1439         }
1440         if (priv->drop_queue.hrxq)
1441                 mlx5_drop_action_destroy(dev);
1442         if (priv->mreg_cp_tbl)
1443                 mlx5_hlist_destroy(priv->mreg_cp_tbl);
1444         mlx5_mprq_free_mp(dev);
1445         mlx5_os_free_shared_dr(priv);
1446         if (priv->rss_conf.rss_key != NULL)
1447                 mlx5_free(priv->rss_conf.rss_key);
1448         if (priv->reta_idx != NULL)
1449                 mlx5_free(priv->reta_idx);
1450         if (priv->config.vf)
1451                 mlx5_os_mac_addr_flush(dev);
1452         if (priv->nl_socket_route >= 0)
1453                 close(priv->nl_socket_route);
1454         if (priv->nl_socket_rdma >= 0)
1455                 close(priv->nl_socket_rdma);
1456         if (priv->vmwa_context)
1457                 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1458         ret = mlx5_hrxq_verify(dev);
1459         if (ret)
1460                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1461                         dev->data->port_id);
1462         ret = mlx5_ind_table_obj_verify(dev);
1463         if (ret)
1464                 DRV_LOG(WARNING, "port %u some indirection table still remain",
1465                         dev->data->port_id);
1466         ret = mlx5_rxq_obj_verify(dev);
1467         if (ret)
1468                 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1469                         dev->data->port_id);
1470         ret = mlx5_rxq_verify(dev);
1471         if (ret)
1472                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1473                         dev->data->port_id);
1474         ret = mlx5_txq_obj_verify(dev);
1475         if (ret)
1476                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1477                         dev->data->port_id);
1478         ret = mlx5_txq_verify(dev);
1479         if (ret)
1480                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1481                         dev->data->port_id);
1482         ret = mlx5_flow_verify(dev);
1483         if (ret)
1484                 DRV_LOG(WARNING, "port %u some flows still remain",
1485                         dev->data->port_id);
1486         mlx5_cache_list_destroy(&priv->hrxqs);
1487         /*
1488          * Free the shared context in last turn, because the cleanup
1489          * routines above may use some shared fields, like
1490          * mlx5_os_mac_addr_flush() uses ibdev_path for retrieveing
1491          * ifindex if Netlink fails.
1492          */
1493         mlx5_free_shared_dev_ctx(priv->sh);
1494         if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1495                 unsigned int c = 0;
1496                 uint16_t port_id;
1497
1498                 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1499                         struct mlx5_priv *opriv =
1500                                 rte_eth_devices[port_id].data->dev_private;
1501
1502                         if (!opriv ||
1503                             opriv->domain_id != priv->domain_id ||
1504                             &rte_eth_devices[port_id] == dev)
1505                                 continue;
1506                         ++c;
1507                         break;
1508                 }
1509                 if (!c)
1510                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1511         }
1512         memset(priv, 0, sizeof(*priv));
1513         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1514         /*
1515          * Reset mac_addrs to NULL such that it is not freed as part of
1516          * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1517          * it is freed when dev_private is freed.
1518          */
1519         dev->data->mac_addrs = NULL;
1520         return 0;
1521 }
1522
1523 const struct eth_dev_ops mlx5_dev_ops = {
1524         .dev_configure = mlx5_dev_configure,
1525         .dev_start = mlx5_dev_start,
1526         .dev_stop = mlx5_dev_stop,
1527         .dev_set_link_down = mlx5_set_link_down,
1528         .dev_set_link_up = mlx5_set_link_up,
1529         .dev_close = mlx5_dev_close,
1530         .promiscuous_enable = mlx5_promiscuous_enable,
1531         .promiscuous_disable = mlx5_promiscuous_disable,
1532         .allmulticast_enable = mlx5_allmulticast_enable,
1533         .allmulticast_disable = mlx5_allmulticast_disable,
1534         .link_update = mlx5_link_update,
1535         .stats_get = mlx5_stats_get,
1536         .stats_reset = mlx5_stats_reset,
1537         .xstats_get = mlx5_xstats_get,
1538         .xstats_reset = mlx5_xstats_reset,
1539         .xstats_get_names = mlx5_xstats_get_names,
1540         .fw_version_get = mlx5_fw_version_get,
1541         .dev_infos_get = mlx5_dev_infos_get,
1542         .representor_info_get = mlx5_representor_info_get,
1543         .read_clock = mlx5_txpp_read_clock,
1544         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1545         .vlan_filter_set = mlx5_vlan_filter_set,
1546         .rx_queue_setup = mlx5_rx_queue_setup,
1547         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1548         .tx_queue_setup = mlx5_tx_queue_setup,
1549         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1550         .rx_queue_release = mlx5_rx_queue_release,
1551         .tx_queue_release = mlx5_tx_queue_release,
1552         .rx_queue_start = mlx5_rx_queue_start,
1553         .rx_queue_stop = mlx5_rx_queue_stop,
1554         .tx_queue_start = mlx5_tx_queue_start,
1555         .tx_queue_stop = mlx5_tx_queue_stop,
1556         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1557         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1558         .mac_addr_remove = mlx5_mac_addr_remove,
1559         .mac_addr_add = mlx5_mac_addr_add,
1560         .mac_addr_set = mlx5_mac_addr_set,
1561         .set_mc_addr_list = mlx5_set_mc_addr_list,
1562         .mtu_set = mlx5_dev_set_mtu,
1563         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1564         .vlan_offload_set = mlx5_vlan_offload_set,
1565         .reta_update = mlx5_dev_rss_reta_update,
1566         .reta_query = mlx5_dev_rss_reta_query,
1567         .rss_hash_update = mlx5_rss_hash_update,
1568         .rss_hash_conf_get = mlx5_rss_hash_conf_get,
1569         .flow_ops_get = mlx5_flow_ops_get,
1570         .rxq_info_get = mlx5_rxq_info_get,
1571         .txq_info_get = mlx5_txq_info_get,
1572         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1573         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1574         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1575         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1576         .is_removed = mlx5_is_removed,
1577         .udp_tunnel_port_add  = mlx5_udp_tunnel_port_add,
1578         .get_module_info = mlx5_get_module_info,
1579         .get_module_eeprom = mlx5_get_module_eeprom,
1580         .hairpin_cap_get = mlx5_hairpin_cap_get,
1581         .mtr_ops_get = mlx5_flow_meter_ops_get,
1582         .hairpin_bind = mlx5_hairpin_bind,
1583         .hairpin_unbind = mlx5_hairpin_unbind,
1584         .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1585         .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1586         .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1587         .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1588 };
1589
1590 /* Available operations from secondary process. */
1591 const struct eth_dev_ops mlx5_dev_sec_ops = {
1592         .stats_get = mlx5_stats_get,
1593         .stats_reset = mlx5_stats_reset,
1594         .xstats_get = mlx5_xstats_get,
1595         .xstats_reset = mlx5_xstats_reset,
1596         .xstats_get_names = mlx5_xstats_get_names,
1597         .fw_version_get = mlx5_fw_version_get,
1598         .dev_infos_get = mlx5_dev_infos_get,
1599         .read_clock = mlx5_txpp_read_clock,
1600         .rx_queue_start = mlx5_rx_queue_start,
1601         .rx_queue_stop = mlx5_rx_queue_stop,
1602         .tx_queue_start = mlx5_tx_queue_start,
1603         .tx_queue_stop = mlx5_tx_queue_stop,
1604         .rxq_info_get = mlx5_rxq_info_get,
1605         .txq_info_get = mlx5_txq_info_get,
1606         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1607         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1608         .get_module_info = mlx5_get_module_info,
1609         .get_module_eeprom = mlx5_get_module_eeprom,
1610 };
1611
1612 /* Available operations in flow isolated mode. */
1613 const struct eth_dev_ops mlx5_dev_ops_isolate = {
1614         .dev_configure = mlx5_dev_configure,
1615         .dev_start = mlx5_dev_start,
1616         .dev_stop = mlx5_dev_stop,
1617         .dev_set_link_down = mlx5_set_link_down,
1618         .dev_set_link_up = mlx5_set_link_up,
1619         .dev_close = mlx5_dev_close,
1620         .promiscuous_enable = mlx5_promiscuous_enable,
1621         .promiscuous_disable = mlx5_promiscuous_disable,
1622         .allmulticast_enable = mlx5_allmulticast_enable,
1623         .allmulticast_disable = mlx5_allmulticast_disable,
1624         .link_update = mlx5_link_update,
1625         .stats_get = mlx5_stats_get,
1626         .stats_reset = mlx5_stats_reset,
1627         .xstats_get = mlx5_xstats_get,
1628         .xstats_reset = mlx5_xstats_reset,
1629         .xstats_get_names = mlx5_xstats_get_names,
1630         .fw_version_get = mlx5_fw_version_get,
1631         .dev_infos_get = mlx5_dev_infos_get,
1632         .read_clock = mlx5_txpp_read_clock,
1633         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1634         .vlan_filter_set = mlx5_vlan_filter_set,
1635         .rx_queue_setup = mlx5_rx_queue_setup,
1636         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1637         .tx_queue_setup = mlx5_tx_queue_setup,
1638         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1639         .rx_queue_release = mlx5_rx_queue_release,
1640         .tx_queue_release = mlx5_tx_queue_release,
1641         .rx_queue_start = mlx5_rx_queue_start,
1642         .rx_queue_stop = mlx5_rx_queue_stop,
1643         .tx_queue_start = mlx5_tx_queue_start,
1644         .tx_queue_stop = mlx5_tx_queue_stop,
1645         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1646         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1647         .mac_addr_remove = mlx5_mac_addr_remove,
1648         .mac_addr_add = mlx5_mac_addr_add,
1649         .mac_addr_set = mlx5_mac_addr_set,
1650         .set_mc_addr_list = mlx5_set_mc_addr_list,
1651         .mtu_set = mlx5_dev_set_mtu,
1652         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1653         .vlan_offload_set = mlx5_vlan_offload_set,
1654         .flow_ops_get = mlx5_flow_ops_get,
1655         .rxq_info_get = mlx5_rxq_info_get,
1656         .txq_info_get = mlx5_txq_info_get,
1657         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1658         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1659         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1660         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1661         .is_removed = mlx5_is_removed,
1662         .get_module_info = mlx5_get_module_info,
1663         .get_module_eeprom = mlx5_get_module_eeprom,
1664         .hairpin_cap_get = mlx5_hairpin_cap_get,
1665         .mtr_ops_get = mlx5_flow_meter_ops_get,
1666         .hairpin_bind = mlx5_hairpin_bind,
1667         .hairpin_unbind = mlx5_hairpin_unbind,
1668         .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1669         .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1670         .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1671         .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1672 };
1673
1674 /**
1675  * Verify and store value for device argument.
1676  *
1677  * @param[in] key
1678  *   Key argument to verify.
1679  * @param[in] val
1680  *   Value associated with key.
1681  * @param opaque
1682  *   User data.
1683  *
1684  * @return
1685  *   0 on success, a negative errno value otherwise and rte_errno is set.
1686  */
1687 static int
1688 mlx5_args_check(const char *key, const char *val, void *opaque)
1689 {
1690         struct mlx5_dev_config *config = opaque;
1691         unsigned long mod;
1692         signed long tmp;
1693
1694         /* No-op, port representors are processed in mlx5_dev_spawn(). */
1695         if (!strcmp(MLX5_REPRESENTOR, key))
1696                 return 0;
1697         errno = 0;
1698         tmp = strtol(val, NULL, 0);
1699         if (errno) {
1700                 rte_errno = errno;
1701                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1702                 return -rte_errno;
1703         }
1704         if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
1705                 /* Negative values are acceptable for some keys only. */
1706                 rte_errno = EINVAL;
1707                 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
1708                 return -rte_errno;
1709         }
1710         mod = tmp >= 0 ? tmp : -tmp;
1711         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1712                 if (tmp > MLX5_CQE_RESP_FORMAT_L34H_STRIDX) {
1713                         DRV_LOG(ERR, "invalid CQE compression "
1714                                      "format parameter");
1715                         rte_errno = EINVAL;
1716                         return -rte_errno;
1717                 }
1718                 config->cqe_comp = !!tmp;
1719                 config->cqe_comp_fmt = tmp;
1720         } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1721                 config->hw_padding = !!tmp;
1722         } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1723                 config->mprq.enabled = !!tmp;
1724         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1725                 config->mprq.stride_num_n = tmp;
1726         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1727                 config->mprq.stride_size_n = tmp;
1728         } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1729                 config->mprq.max_memcpy_len = tmp;
1730         } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1731                 config->mprq.min_rxqs_num = tmp;
1732         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1733                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1734                                  " converted to txq_inline_max", key);
1735                 config->txq_inline_max = tmp;
1736         } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1737                 config->txq_inline_max = tmp;
1738         } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1739                 config->txq_inline_min = tmp;
1740         } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1741                 config->txq_inline_mpw = tmp;
1742         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1743                 config->txqs_inline = tmp;
1744         } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1745                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1746         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1747                 config->mps = !!tmp;
1748         } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1749                 if (tmp != MLX5_TXDB_CACHED &&
1750                     tmp != MLX5_TXDB_NCACHED &&
1751                     tmp != MLX5_TXDB_HEURISTIC) {
1752                         DRV_LOG(ERR, "invalid Tx doorbell "
1753                                      "mapping parameter");
1754                         rte_errno = EINVAL;
1755                         return -rte_errno;
1756                 }
1757                 config->dbnc = tmp;
1758         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1759                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1760         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1761                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1762                                  " converted to txq_inline_mpw", key);
1763                 config->txq_inline_mpw = tmp;
1764         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1765                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1766         } else if (strcmp(MLX5_TX_PP, key) == 0) {
1767                 if (!mod) {
1768                         DRV_LOG(ERR, "Zero Tx packet pacing parameter");
1769                         rte_errno = EINVAL;
1770                         return -rte_errno;
1771                 }
1772                 config->tx_pp = tmp;
1773         } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
1774                 config->tx_skew = tmp;
1775         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1776                 config->rx_vec_en = !!tmp;
1777         } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1778                 config->l3_vxlan_en = !!tmp;
1779         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1780                 config->vf_nl_en = !!tmp;
1781         } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1782                 config->dv_esw_en = !!tmp;
1783         } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1784                 config->dv_flow_en = !!tmp;
1785         } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1786                 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1787                     tmp != MLX5_XMETA_MODE_META16 &&
1788                     tmp != MLX5_XMETA_MODE_META32 &&
1789                     tmp != MLX5_XMETA_MODE_MISS_INFO) {
1790                         DRV_LOG(ERR, "invalid extensive "
1791                                      "metadata parameter");
1792                         rte_errno = EINVAL;
1793                         return -rte_errno;
1794                 }
1795                 if (tmp != MLX5_XMETA_MODE_MISS_INFO)
1796                         config->dv_xmeta_en = tmp;
1797                 else
1798                         config->dv_miss_info = 1;
1799         } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
1800                 config->lacp_by_user = !!tmp;
1801         } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1802                 config->mr_ext_memseg_en = !!tmp;
1803         } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1804                 config->max_dump_files_num = tmp;
1805         } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1806                 config->lro.timeout = tmp;
1807         } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1808                 DRV_LOG(DEBUG, "class argument is %s.", val);
1809         } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1810                 config->log_hp_size = tmp;
1811         } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1812                 if (tmp != MLX5_RCM_NONE &&
1813                     tmp != MLX5_RCM_LIGHT &&
1814                     tmp != MLX5_RCM_AGGR) {
1815                         DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1816                         rte_errno = EINVAL;
1817                         return -rte_errno;
1818                 }
1819                 config->reclaim_mode = tmp;
1820         } else if (strcmp(MLX5_SYS_MEM_EN, key) == 0) {
1821                 config->sys_mem_en = !!tmp;
1822         } else if (strcmp(MLX5_DECAP_EN, key) == 0) {
1823                 config->decap_en = !!tmp;
1824         } else {
1825                 DRV_LOG(WARNING, "%s: unknown parameter", key);
1826                 rte_errno = EINVAL;
1827                 return -rte_errno;
1828         }
1829         return 0;
1830 }
1831
1832 /**
1833  * Parse device parameters.
1834  *
1835  * @param config
1836  *   Pointer to device configuration structure.
1837  * @param devargs
1838  *   Device arguments structure.
1839  *
1840  * @return
1841  *   0 on success, a negative errno value otherwise and rte_errno is set.
1842  */
1843 int
1844 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1845 {
1846         const char **params = (const char *[]){
1847                 MLX5_RXQ_CQE_COMP_EN,
1848                 MLX5_RXQ_PKT_PAD_EN,
1849                 MLX5_RX_MPRQ_EN,
1850                 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1851                 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1852                 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1853                 MLX5_RXQS_MIN_MPRQ,
1854                 MLX5_TXQ_INLINE,
1855                 MLX5_TXQ_INLINE_MIN,
1856                 MLX5_TXQ_INLINE_MAX,
1857                 MLX5_TXQ_INLINE_MPW,
1858                 MLX5_TXQS_MIN_INLINE,
1859                 MLX5_TXQS_MAX_VEC,
1860                 MLX5_TXQ_MPW_EN,
1861                 MLX5_TXQ_MPW_HDR_DSEG_EN,
1862                 MLX5_TXQ_MAX_INLINE_LEN,
1863                 MLX5_TX_DB_NC,
1864                 MLX5_TX_PP,
1865                 MLX5_TX_SKEW,
1866                 MLX5_TX_VEC_EN,
1867                 MLX5_RX_VEC_EN,
1868                 MLX5_L3_VXLAN_EN,
1869                 MLX5_VF_NL_EN,
1870                 MLX5_DV_ESW_EN,
1871                 MLX5_DV_FLOW_EN,
1872                 MLX5_DV_XMETA_EN,
1873                 MLX5_LACP_BY_USER,
1874                 MLX5_MR_EXT_MEMSEG_EN,
1875                 MLX5_REPRESENTOR,
1876                 MLX5_MAX_DUMP_FILES_NUM,
1877                 MLX5_LRO_TIMEOUT_USEC,
1878                 MLX5_CLASS_ARG_NAME,
1879                 MLX5_HP_BUF_SIZE,
1880                 MLX5_RECLAIM_MEM,
1881                 MLX5_SYS_MEM_EN,
1882                 MLX5_DECAP_EN,
1883                 NULL,
1884         };
1885         struct rte_kvargs *kvlist;
1886         int ret = 0;
1887         int i;
1888
1889         if (devargs == NULL)
1890                 return 0;
1891         /* Following UGLY cast is done to pass checkpatch. */
1892         kvlist = rte_kvargs_parse(devargs->args, params);
1893         if (kvlist == NULL) {
1894                 rte_errno = EINVAL;
1895                 return -rte_errno;
1896         }
1897         /* Process parameters. */
1898         for (i = 0; (params[i] != NULL); ++i) {
1899                 if (rte_kvargs_count(kvlist, params[i])) {
1900                         ret = rte_kvargs_process(kvlist, params[i],
1901                                                  mlx5_args_check, config);
1902                         if (ret) {
1903                                 rte_errno = EINVAL;
1904                                 rte_kvargs_free(kvlist);
1905                                 return -rte_errno;
1906                         }
1907                 }
1908         }
1909         rte_kvargs_free(kvlist);
1910         return 0;
1911 }
1912
1913 /**
1914  * Configures the minimal amount of data to inline into WQE
1915  * while sending packets.
1916  *
1917  * - the txq_inline_min has the maximal priority, if this
1918  *   key is specified in devargs
1919  * - if DevX is enabled the inline mode is queried from the
1920  *   device (HCA attributes and NIC vport context if needed).
1921  * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1922  *   and none (0 bytes) for other NICs
1923  *
1924  * @param spawn
1925  *   Verbs device parameters (name, port, switch_info) to spawn.
1926  * @param config
1927  *   Device configuration parameters.
1928  */
1929 void
1930 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1931                     struct mlx5_dev_config *config)
1932 {
1933         if (config->txq_inline_min != MLX5_ARG_UNSET) {
1934                 /* Application defines size of inlined data explicitly. */
1935                 switch (spawn->pci_dev->id.device_id) {
1936                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1937                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1938                         if (config->txq_inline_min <
1939                                        (int)MLX5_INLINE_HSIZE_L2) {
1940                                 DRV_LOG(DEBUG,
1941                                         "txq_inline_mix aligned to minimal"
1942                                         " ConnectX-4 required value %d",
1943                                         (int)MLX5_INLINE_HSIZE_L2);
1944                                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1945                         }
1946                         break;
1947                 }
1948                 goto exit;
1949         }
1950         if (config->hca_attr.eth_net_offloads) {
1951                 /* We have DevX enabled, inline mode queried successfully. */
1952                 switch (config->hca_attr.wqe_inline_mode) {
1953                 case MLX5_CAP_INLINE_MODE_L2:
1954                         /* outer L2 header must be inlined. */
1955                         config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1956                         goto exit;
1957                 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1958                         /* No inline data are required by NIC. */
1959                         config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1960                         config->hw_vlan_insert =
1961                                 config->hca_attr.wqe_vlan_insert;
1962                         DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1963                         goto exit;
1964                 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1965                         /* inline mode is defined by NIC vport context. */
1966                         if (!config->hca_attr.eth_virt)
1967                                 break;
1968                         switch (config->hca_attr.vport_inline_mode) {
1969                         case MLX5_INLINE_MODE_NONE:
1970                                 config->txq_inline_min =
1971                                         MLX5_INLINE_HSIZE_NONE;
1972                                 goto exit;
1973                         case MLX5_INLINE_MODE_L2:
1974                                 config->txq_inline_min =
1975                                         MLX5_INLINE_HSIZE_L2;
1976                                 goto exit;
1977                         case MLX5_INLINE_MODE_IP:
1978                                 config->txq_inline_min =
1979                                         MLX5_INLINE_HSIZE_L3;
1980                                 goto exit;
1981                         case MLX5_INLINE_MODE_TCP_UDP:
1982                                 config->txq_inline_min =
1983                                         MLX5_INLINE_HSIZE_L4;
1984                                 goto exit;
1985                         case MLX5_INLINE_MODE_INNER_L2:
1986                                 config->txq_inline_min =
1987                                         MLX5_INLINE_HSIZE_INNER_L2;
1988                                 goto exit;
1989                         case MLX5_INLINE_MODE_INNER_IP:
1990                                 config->txq_inline_min =
1991                                         MLX5_INLINE_HSIZE_INNER_L3;
1992                                 goto exit;
1993                         case MLX5_INLINE_MODE_INNER_TCP_UDP:
1994                                 config->txq_inline_min =
1995                                         MLX5_INLINE_HSIZE_INNER_L4;
1996                                 goto exit;
1997                         }
1998                 }
1999         }
2000         /*
2001          * We get here if we are unable to deduce
2002          * inline data size with DevX. Try PCI ID
2003          * to determine old NICs.
2004          */
2005         switch (spawn->pci_dev->id.device_id) {
2006         case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2007         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2008         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
2009         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
2010                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2011                 config->hw_vlan_insert = 0;
2012                 break;
2013         case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
2014         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
2015         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
2016         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
2017                 /*
2018                  * These NICs support VLAN insertion from WQE and
2019                  * report the wqe_vlan_insert flag. But there is the bug
2020                  * and PFC control may be broken, so disable feature.
2021                  */
2022                 config->hw_vlan_insert = 0;
2023                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2024                 break;
2025         default:
2026                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2027                 break;
2028         }
2029 exit:
2030         DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
2031 }
2032
2033 /**
2034  * Configures the metadata mask fields in the shared context.
2035  *
2036  * @param [in] dev
2037  *   Pointer to Ethernet device.
2038  */
2039 void
2040 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
2041 {
2042         struct mlx5_priv *priv = dev->data->dev_private;
2043         struct mlx5_dev_ctx_shared *sh = priv->sh;
2044         uint32_t meta, mark, reg_c0;
2045
2046         reg_c0 = ~priv->vport_meta_mask;
2047         switch (priv->config.dv_xmeta_en) {
2048         case MLX5_XMETA_MODE_LEGACY:
2049                 meta = UINT32_MAX;
2050                 mark = MLX5_FLOW_MARK_MASK;
2051                 break;
2052         case MLX5_XMETA_MODE_META16:
2053                 meta = reg_c0 >> rte_bsf32(reg_c0);
2054                 mark = MLX5_FLOW_MARK_MASK;
2055                 break;
2056         case MLX5_XMETA_MODE_META32:
2057                 meta = UINT32_MAX;
2058                 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
2059                 break;
2060         default:
2061                 meta = 0;
2062                 mark = 0;
2063                 MLX5_ASSERT(false);
2064                 break;
2065         }
2066         if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
2067                 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
2068                                  sh->dv_mark_mask, mark);
2069         else
2070                 sh->dv_mark_mask = mark;
2071         if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
2072                 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
2073                                  sh->dv_meta_mask, meta);
2074         else
2075                 sh->dv_meta_mask = meta;
2076         if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
2077                 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
2078                                  sh->dv_meta_mask, reg_c0);
2079         else
2080                 sh->dv_regc0_mask = reg_c0;
2081         DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
2082         DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
2083         DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
2084         DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
2085 }
2086
2087 int
2088 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
2089 {
2090         static const char *const dynf_names[] = {
2091                 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
2092                 RTE_MBUF_DYNFLAG_METADATA_NAME,
2093                 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
2094         };
2095         unsigned int i;
2096
2097         if (n < RTE_DIM(dynf_names))
2098                 return -ENOMEM;
2099         for (i = 0; i < RTE_DIM(dynf_names); i++) {
2100                 if (names[i] == NULL)
2101                         return -EINVAL;
2102                 strcpy(names[i], dynf_names[i]);
2103         }
2104         return RTE_DIM(dynf_names);
2105 }
2106
2107 /**
2108  * Comparison callback to sort device data.
2109  *
2110  * This is meant to be used with qsort().
2111  *
2112  * @param a[in]
2113  *   Pointer to pointer to first data object.
2114  * @param b[in]
2115  *   Pointer to pointer to second data object.
2116  *
2117  * @return
2118  *   0 if both objects are equal, less than 0 if the first argument is less
2119  *   than the second, greater than 0 otherwise.
2120  */
2121 int
2122 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
2123                               struct mlx5_dev_config *config)
2124 {
2125         struct mlx5_dev_ctx_shared *sh = priv->sh;
2126         struct mlx5_dev_config *sh_conf = NULL;
2127         uint16_t port_id;
2128
2129         MLX5_ASSERT(sh);
2130         /* Nothing to compare for the single/first device. */
2131         if (sh->refcnt == 1)
2132                 return 0;
2133         /* Find the device with shared context. */
2134         MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
2135                 struct mlx5_priv *opriv =
2136                         rte_eth_devices[port_id].data->dev_private;
2137
2138                 if (opriv && opriv != priv && opriv->sh == sh) {
2139                         sh_conf = &opriv->config;
2140                         break;
2141                 }
2142         }
2143         if (!sh_conf)
2144                 return 0;
2145         if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
2146                 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
2147                              " for shared %s context", sh->ibdev_name);
2148                 rte_errno = EINVAL;
2149                 return rte_errno;
2150         }
2151         if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
2152                 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
2153                              " for shared %s context", sh->ibdev_name);
2154                 rte_errno = EINVAL;
2155                 return rte_errno;
2156         }
2157         return 0;
2158 }
2159
2160 /**
2161  * Look for the ethernet device belonging to mlx5 driver.
2162  *
2163  * @param[in] port_id
2164  *   port_id to start looking for device.
2165  * @param[in] pci_dev
2166  *   Pointer to the hint PCI device. When device is being probed
2167  *   the its siblings (master and preceding representors might
2168  *   not have assigned driver yet (because the mlx5_os_pci_probe()
2169  *   is not completed yet, for this case match on hint PCI
2170  *   device may be used to detect sibling device.
2171  *
2172  * @return
2173  *   port_id of found device, RTE_MAX_ETHPORT if not found.
2174  */
2175 uint16_t
2176 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
2177 {
2178         while (port_id < RTE_MAX_ETHPORTS) {
2179                 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
2180
2181                 if (dev->state != RTE_ETH_DEV_UNUSED &&
2182                     dev->device &&
2183                     (dev->device == &pci_dev->device ||
2184                      (dev->device->driver &&
2185                      dev->device->driver->name &&
2186                      !strcmp(dev->device->driver->name, MLX5_PCI_DRIVER_NAME))))
2187                         break;
2188                 port_id++;
2189         }
2190         if (port_id >= RTE_MAX_ETHPORTS)
2191                 return RTE_MAX_ETHPORTS;
2192         return port_id;
2193 }
2194
2195 /**
2196  * DPDK callback to remove a PCI device.
2197  *
2198  * This function removes all Ethernet devices belong to a given PCI device.
2199  *
2200  * @param[in] pci_dev
2201  *   Pointer to the PCI device.
2202  *
2203  * @return
2204  *   0 on success, the function cannot fail.
2205  */
2206 static int
2207 mlx5_pci_remove(struct rte_pci_device *pci_dev)
2208 {
2209         uint16_t port_id;
2210         int ret = 0;
2211
2212         RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
2213                 /*
2214                  * mlx5_dev_close() is not registered to secondary process,
2215                  * call the close function explicitly for secondary process.
2216                  */
2217                 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
2218                         ret |= mlx5_dev_close(&rte_eth_devices[port_id]);
2219                 else
2220                         ret |= rte_eth_dev_close(port_id);
2221         }
2222         return ret == 0 ? 0 : -EIO;
2223 }
2224
2225 static const struct rte_pci_id mlx5_pci_id_map[] = {
2226         {
2227                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2228                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
2229         },
2230         {
2231                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2232                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
2233         },
2234         {
2235                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2236                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
2237         },
2238         {
2239                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2240                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
2241         },
2242         {
2243                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2244                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
2245         },
2246         {
2247                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2248                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
2249         },
2250         {
2251                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2252                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
2253         },
2254         {
2255                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2256                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
2257         },
2258         {
2259                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2260                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
2261         },
2262         {
2263                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2264                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
2265         },
2266         {
2267                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2268                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
2269         },
2270         {
2271                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2272                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
2273         },
2274         {
2275                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2276                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
2277         },
2278         {
2279                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2280                                 PCI_DEVICE_ID_MELLANOX_CONNECTXVF)
2281         },
2282         {
2283                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2284                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
2285         },
2286         {
2287                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2288                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
2289         },
2290         {
2291                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2292                                 PCI_DEVICE_ID_MELLANOX_CONNECTX7)
2293         },
2294         {
2295                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2296                                 PCI_DEVICE_ID_MELLANOX_CONNECTX7BF)
2297         },
2298         {
2299                 .vendor_id = 0
2300         }
2301 };
2302
2303 static struct mlx5_pci_driver mlx5_driver = {
2304         .driver_class = MLX5_CLASS_NET,
2305         .pci_driver = {
2306                 .driver = {
2307                         .name = MLX5_PCI_DRIVER_NAME,
2308                 },
2309                 .id_table = mlx5_pci_id_map,
2310                 .probe = mlx5_os_pci_probe,
2311                 .remove = mlx5_pci_remove,
2312                 .dma_map = mlx5_dma_map,
2313                 .dma_unmap = mlx5_dma_unmap,
2314                 .drv_flags = PCI_DRV_FLAGS,
2315         },
2316 };
2317
2318 /* Initialize driver log type. */
2319 RTE_LOG_REGISTER(mlx5_logtype, pmd.net.mlx5, NOTICE)
2320
2321 /**
2322  * Driver initialization routine.
2323  */
2324 RTE_INIT(rte_mlx5_pmd_init)
2325 {
2326         pthread_mutex_init(&mlx5_dev_ctx_list_mutex, NULL);
2327         mlx5_common_init();
2328         /* Build the static tables for Verbs conversion. */
2329         mlx5_set_ptype_table();
2330         mlx5_set_cksum_table();
2331         mlx5_set_swp_types_table();
2332         if (mlx5_glue)
2333                 mlx5_pci_driver_register(&mlx5_driver);
2334 }
2335
2336 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
2337 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
2338 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");