1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
13 #include <rte_malloc.h>
14 #include <rte_ethdev_driver.h>
15 #include <rte_ethdev_pci.h>
17 #include <rte_bus_pci.h>
18 #include <rte_common.h>
19 #include <rte_kvargs.h>
20 #include <rte_rwlock.h>
21 #include <rte_spinlock.h>
22 #include <rte_string_fns.h>
23 #include <rte_alarm.h>
25 #include <mlx5_glue.h>
26 #include <mlx5_devx_cmds.h>
27 #include <mlx5_common.h>
28 #include <mlx5_common_os.h>
29 #include <mlx5_common_mp.h>
30 #include <mlx5_common_pci.h>
31 #include <mlx5_malloc.h>
33 #include "mlx5_defs.h"
35 #include "mlx5_utils.h"
36 #include "mlx5_rxtx.h"
37 #include "mlx5_autoconf.h"
39 #include "mlx5_flow.h"
40 #include "rte_pmd_mlx5.h"
42 /* Device parameter to enable RX completion queue compression. */
43 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
45 /* Device parameter to enable RX completion entry padding to 128B. */
46 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
48 /* Device parameter to enable padding Rx packet to cacheline size. */
49 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
51 /* Device parameter to enable Multi-Packet Rx queue. */
52 #define MLX5_RX_MPRQ_EN "mprq_en"
54 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
55 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
57 /* Device parameter to configure log 2 of the stride size for MPRQ. */
58 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
60 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
61 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
63 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
64 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
66 /* Device parameter to configure inline send. Deprecated, ignored.*/
67 #define MLX5_TXQ_INLINE "txq_inline"
69 /* Device parameter to limit packet size to inline with ordinary SEND. */
70 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
72 /* Device parameter to configure minimal data size to inline. */
73 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
75 /* Device parameter to limit packet size to inline with Enhanced MPW. */
76 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
79 * Device parameter to configure the number of TX queues threshold for
80 * enabling inline send.
82 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
85 * Device parameter to configure the number of TX queues threshold for
86 * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
88 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
90 /* Device parameter to enable multi-packet send WQEs. */
91 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
94 * Device parameter to force doorbell register mapping
95 * to non-cahed region eliminating the extra write memory barrier.
97 #define MLX5_TX_DB_NC "tx_db_nc"
100 * Device parameter to include 2 dsegs in the title WQEBB.
101 * Deprecated, ignored.
103 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
106 * Device parameter to limit the size of inlining packet.
107 * Deprecated, ignored.
109 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
112 * Device parameter to enable Tx scheduling on timestamps
113 * and specify the packet pacing granularity in nanoseconds.
115 #define MLX5_TX_PP "tx_pp"
118 * Device parameter to specify skew in nanoseconds on Tx datapath,
119 * it represents the time between SQ start WQE processing and
120 * appearing actual packet data on the wire.
122 #define MLX5_TX_SKEW "tx_skew"
125 * Device parameter to enable hardware Tx vector.
126 * Deprecated, ignored (no vectorized Tx routines anymore).
128 #define MLX5_TX_VEC_EN "tx_vec_en"
130 /* Device parameter to enable hardware Rx vector. */
131 #define MLX5_RX_VEC_EN "rx_vec_en"
133 /* Allow L3 VXLAN flow creation. */
134 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
136 /* Activate DV E-Switch flow steering. */
137 #define MLX5_DV_ESW_EN "dv_esw_en"
139 /* Activate DV flow steering. */
140 #define MLX5_DV_FLOW_EN "dv_flow_en"
142 /* Enable extensive flow metadata support. */
143 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
145 /* Device parameter to let the user manage the lacp traffic of bonded device */
146 #define MLX5_LACP_BY_USER "lacp_by_user"
148 /* Activate Netlink support in VF mode. */
149 #define MLX5_VF_NL_EN "vf_nl_en"
151 /* Enable extending memsegs when creating a MR. */
152 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
154 /* Select port representors to instantiate. */
155 #define MLX5_REPRESENTOR "representor"
157 /* Device parameter to configure the maximum number of dump files per queue. */
158 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
160 /* Configure timeout of LRO session (in microseconds). */
161 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
164 * Device parameter to configure the total data buffer size for a single
165 * hairpin queue (logarithm value).
167 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
169 /* Flow memory reclaim mode. */
170 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
172 /* The default memory allocator used in PMD. */
173 #define MLX5_SYS_MEM_EN "sys_mem_en"
174 /* Decap will be used or not. */
175 #define MLX5_DECAP_EN "decap_en"
177 /* Shared memory between primary and secondary processes. */
178 struct mlx5_shared_data *mlx5_shared_data;
180 /** Driver-specific log messages type. */
183 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
184 LIST_HEAD_INITIALIZER();
185 static pthread_mutex_t mlx5_dev_ctx_list_mutex = PTHREAD_MUTEX_INITIALIZER;
187 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
188 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
190 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
196 .malloc = mlx5_malloc,
198 .type = "mlx5_encap_decap_ipool",
201 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
207 .malloc = mlx5_malloc,
209 .type = "mlx5_push_vlan_ipool",
212 .size = sizeof(struct mlx5_flow_dv_tag_resource),
218 .malloc = mlx5_malloc,
220 .type = "mlx5_tag_ipool",
223 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
229 .malloc = mlx5_malloc,
231 .type = "mlx5_port_id_ipool",
234 .size = sizeof(struct mlx5_flow_tbl_data_entry),
240 .malloc = mlx5_malloc,
242 .type = "mlx5_jump_ipool",
245 .size = sizeof(struct mlx5_flow_dv_sample_resource),
251 .malloc = mlx5_malloc,
253 .type = "mlx5_sample_ipool",
256 .size = sizeof(struct mlx5_flow_dv_dest_array_resource),
262 .malloc = mlx5_malloc,
264 .type = "mlx5_dest_array_ipool",
268 .size = sizeof(struct mlx5_flow_meter),
274 .malloc = mlx5_malloc,
276 .type = "mlx5_meter_ipool",
279 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
285 .malloc = mlx5_malloc,
287 .type = "mlx5_mcp_ipool",
290 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
296 .malloc = mlx5_malloc,
298 .type = "mlx5_hrxq_ipool",
302 * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
303 * It set in run time according to PCI function configuration.
311 .malloc = mlx5_malloc,
313 .type = "mlx5_flow_handle_ipool",
316 .size = sizeof(struct rte_flow),
320 .malloc = mlx5_malloc,
322 .type = "rte_flow_ipool",
327 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
328 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
330 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
333 * Allocate ID pool structure.
336 * The maximum id can be allocated from the pool.
339 * Pointer to pool object, NULL value otherwise.
341 struct mlx5_flow_id_pool *
342 mlx5_flow_id_pool_alloc(uint32_t max_id)
344 struct mlx5_flow_id_pool *pool;
347 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool),
348 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
350 DRV_LOG(ERR, "can't allocate id pool");
354 mem = mlx5_malloc(MLX5_MEM_ZERO,
355 MLX5_FLOW_MIN_ID_POOL_SIZE * sizeof(uint32_t),
356 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
358 DRV_LOG(ERR, "can't allocate mem for id pool");
362 pool->free_arr = mem;
363 pool->curr = pool->free_arr;
364 pool->last = pool->free_arr + MLX5_FLOW_MIN_ID_POOL_SIZE;
365 pool->base_index = 0;
366 pool->max_id = max_id;
374 * Release ID pool structure.
377 * Pointer to flow id pool object to free.
380 mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool)
382 mlx5_free(pool->free_arr);
390 * Pointer to flow id pool.
395 * 0 on success, error value otherwise.
398 mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id)
400 if (pool->curr == pool->free_arr) {
401 if (pool->base_index == pool->max_id) {
403 DRV_LOG(ERR, "no free id");
406 *id = ++pool->base_index;
409 *id = *(--pool->curr);
417 * Pointer to flow id pool.
422 * 0 on success, error value otherwise.
425 mlx5_flow_id_release(struct mlx5_flow_id_pool *pool, uint32_t id)
431 if (pool->curr == pool->last) {
432 size = pool->curr - pool->free_arr;
433 size2 = size * MLX5_ID_GENERATION_ARRAY_FACTOR;
434 MLX5_ASSERT(size2 > size);
435 mem = mlx5_malloc(0, size2 * sizeof(uint32_t), 0,
438 DRV_LOG(ERR, "can't allocate mem for id pool");
442 memcpy(mem, pool->free_arr, size * sizeof(uint32_t));
443 mlx5_free(pool->free_arr);
444 pool->free_arr = mem;
445 pool->curr = pool->free_arr + size;
446 pool->last = pool->free_arr + size2;
454 * Initialize the shared aging list information per port.
457 * Pointer to mlx5_dev_ctx_shared object.
460 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
463 struct mlx5_age_info *age_info;
465 for (i = 0; i < sh->max_port; i++) {
466 age_info = &sh->port[i].age_info;
468 TAILQ_INIT(&age_info->aged_counters);
469 rte_spinlock_init(&age_info->aged_sl);
470 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
475 * Initialize the counters management structure.
478 * Pointer to mlx5_dev_ctx_shared object to free
481 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
485 memset(&sh->cmng, 0, sizeof(sh->cmng));
486 TAILQ_INIT(&sh->cmng.flow_counters);
487 sh->cmng.min_id = MLX5_CNT_BATCH_OFFSET;
488 sh->cmng.max_id = -1;
489 sh->cmng.last_pool_idx = POOL_IDX_INVALID;
490 rte_spinlock_init(&sh->cmng.pool_update_sl);
491 for (i = 0; i < MLX5_COUNTER_TYPE_MAX; i++) {
492 TAILQ_INIT(&sh->cmng.counters[i]);
493 rte_spinlock_init(&sh->cmng.csl[i]);
498 * Destroy all the resources allocated for a counter memory management.
501 * Pointer to the memory management structure.
504 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
506 uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
508 LIST_REMOVE(mng, next);
509 claim_zero(mlx5_devx_cmd_destroy(mng->dm));
510 claim_zero(mlx5_glue->devx_umem_dereg(mng->umem));
515 * Close and release all the resources of the counters management.
518 * Pointer to mlx5_dev_ctx_shared object to free.
521 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
523 struct mlx5_counter_stats_mem_mng *mng;
529 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
530 if (rte_errno != EINPROGRESS)
535 if (sh->cmng.pools) {
536 struct mlx5_flow_counter_pool *pool;
537 uint16_t n_valid = sh->cmng.n_valid;
539 for (i = 0; i < n_valid; ++i) {
540 pool = sh->cmng.pools[i];
541 if (!IS_EXT_POOL(pool) && pool->min_dcs)
542 claim_zero(mlx5_devx_cmd_destroy
544 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
545 if (MLX5_POOL_GET_CNT(pool, j)->action)
547 (mlx5_glue->destroy_flow_action
550 if (IS_EXT_POOL(pool) && MLX5_GET_POOL_CNT_EXT
552 claim_zero(mlx5_devx_cmd_destroy
553 (MLX5_GET_POOL_CNT_EXT
558 mlx5_free(sh->cmng.pools);
560 mng = LIST_FIRST(&sh->cmng.mem_mngs);
562 mlx5_flow_destroy_counter_stat_mem_mng(mng);
563 mng = LIST_FIRST(&sh->cmng.mem_mngs);
565 memset(&sh->cmng, 0, sizeof(sh->cmng));
569 * Initialize the flow resources' indexed mempool.
572 * Pointer to mlx5_dev_ctx_shared object.
574 * Pointer to user dev config.
577 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
578 const struct mlx5_dev_config *config)
581 struct mlx5_indexed_pool_config cfg;
583 for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
584 cfg = mlx5_ipool_cfg[i];
589 * Set MLX5_IPOOL_MLX5_FLOW ipool size
590 * according to PCI function flow configuration.
592 case MLX5_IPOOL_MLX5_FLOW:
593 cfg.size = config->dv_flow_en ?
594 sizeof(struct mlx5_flow_handle) :
595 MLX5_FLOW_HANDLE_VERBS_SIZE;
598 if (config->reclaim_mode)
599 cfg.release_mem_en = 1;
600 sh->ipool[i] = mlx5_ipool_create(&cfg);
605 * Release the flow resources' indexed mempool.
608 * Pointer to mlx5_dev_ctx_shared object.
611 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
615 for (i = 0; i < MLX5_IPOOL_MAX; ++i)
616 mlx5_ipool_destroy(sh->ipool[i]);
620 * Check if dynamic flex parser for eCPRI already exists.
623 * Pointer to Ethernet device structure.
626 * true on exists, false on not.
629 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
631 struct mlx5_priv *priv = dev->data->dev_private;
632 struct mlx5_flex_parser_profiles *prf =
633 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
639 * Allocation of a flex parser for eCPRI. Once created, this parser related
640 * resources will be held until the device is closed.
643 * Pointer to Ethernet device structure.
646 * 0 on success, a negative errno value otherwise and rte_errno is set.
649 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
651 struct mlx5_priv *priv = dev->data->dev_private;
652 struct mlx5_flex_parser_profiles *prf =
653 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
654 struct mlx5_devx_graph_node_attr node = {
655 .modify_field_select = 0,
660 if (!priv->config.hca_attr.parse_graph_flex_node) {
661 DRV_LOG(ERR, "Dynamic flex parser is not supported "
662 "for device %s.", priv->dev_data->name);
665 node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED;
666 /* 8 bytes now: 4B common header + 4B message body header. */
667 node.header_length_base_value = 0x8;
668 /* After MAC layer: Ether / VLAN. */
669 node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC;
670 /* Type of compared condition should be 0xAEFE in the L2 layer. */
671 node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI;
672 /* Sample #0: type in common header. */
673 node.sample[0].flow_match_sample_en = 1;
675 node.sample[0].flow_match_sample_offset_mode = 0x0;
676 /* Only the 2nd byte will be used. */
677 node.sample[0].flow_match_sample_field_base_offset = 0x0;
678 /* Sample #1: message payload. */
679 node.sample[1].flow_match_sample_en = 1;
681 node.sample[1].flow_match_sample_offset_mode = 0x0;
683 * Only the first two bytes will be used right now, and its offset will
684 * start after the common header that with the length of a DW(u32).
686 node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);
687 prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->ctx, &node);
689 DRV_LOG(ERR, "Failed to create flex parser node object.");
690 return (rte_errno == 0) ? -ENODEV : -rte_errno;
693 ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num);
695 DRV_LOG(ERR, "Failed to query sample IDs.");
696 return (rte_errno == 0) ? -ENODEV : -rte_errno;
698 prf->offset[0] = 0x0;
699 prf->offset[1] = sizeof(uint32_t);
700 prf->ids[0] = ids[0];
701 prf->ids[1] = ids[1];
706 * Destroy the flex parser node, including the parser itself, input / output
707 * arcs and DW samples. Resources could be reused then.
710 * Pointer to Ethernet device structure.
713 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
715 struct mlx5_priv *priv = dev->data->dev_private;
716 struct mlx5_flex_parser_profiles *prf =
717 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
720 mlx5_devx_cmd_destroy(prf->obj);
725 * Allocate Rx and Tx UARs in robust fashion.
726 * This routine handles the following UAR allocation issues:
728 * - tries to allocate the UAR with the most appropriate memory
729 * mapping type from the ones supported by the host
731 * - tries to allocate the UAR with non-NULL base address
732 * OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as
733 * UAR base address if UAR was not the first object in the UAR page.
734 * It caused the PMD failure and we should try to get another UAR
735 * till we get the first one with non-NULL base address returned.
738 mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh,
739 const struct mlx5_dev_config *config)
741 uint32_t uar_mapping, retry;
745 for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
746 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
747 /* Control the mapping type according to the settings. */
748 uar_mapping = (config->dbnc == MLX5_TXDB_NCACHED) ?
749 MLX5DV_UAR_ALLOC_TYPE_NC :
750 MLX5DV_UAR_ALLOC_TYPE_BF;
752 RTE_SET_USED(config);
754 * It seems we have no way to control the memory mapping type
755 * for the UAR, the default "Write-Combining" type is supposed.
756 * The UAR initialization on queue creation queries the
757 * actual mapping type done by Verbs/kernel and setups the
758 * PMD datapath accordingly.
762 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->ctx, uar_mapping);
763 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
765 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
766 if (config->dbnc == MLX5_TXDB_CACHED ||
767 config->dbnc == MLX5_TXDB_HEURISTIC)
768 DRV_LOG(WARNING, "Devarg tx_db_nc setting "
769 "is not supported by DevX");
771 * In some environments like virtual machine
772 * the Write Combining mapped might be not supported
773 * and UAR allocation fails. We try "Non-Cached"
774 * mapping for the case. The tx_burst routines take
775 * the UAR mapping type into account on UAR setup
778 DRV_LOG(WARNING, "Failed to allocate Tx DevX UAR (BF)");
779 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
780 sh->tx_uar = mlx5_glue->devx_alloc_uar
781 (sh->ctx, uar_mapping);
782 } else if (!sh->tx_uar &&
783 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_NC) {
784 if (config->dbnc == MLX5_TXDB_NCACHED)
785 DRV_LOG(WARNING, "Devarg tx_db_nc settings "
786 "is not supported by DevX");
788 * If Verbs/kernel does not support "Non-Cached"
789 * try the "Write-Combining".
791 DRV_LOG(WARNING, "Failed to allocate Tx DevX UAR (NC)");
792 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_BF;
793 sh->tx_uar = mlx5_glue->devx_alloc_uar
794 (sh->ctx, uar_mapping);
798 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (BF/NC)");
802 base_addr = mlx5_os_get_devx_uar_base_addr(sh->tx_uar);
806 * The UARs are allocated by rdma_core within the
807 * IB device context, on context closure all UARs
808 * will be freed, should be no memory/object leakage.
810 DRV_LOG(WARNING, "Retrying to allocate Tx DevX UAR");
813 /* Check whether we finally succeeded with valid UAR allocation. */
815 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (NULL base)");
819 for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
821 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
822 (sh->ctx, uar_mapping);
823 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
824 if (!sh->devx_rx_uar &&
825 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
827 * Rx UAR is used to control interrupts only,
828 * should be no datapath noticeable impact,
829 * can try "Non-Cached" mapping safely.
831 DRV_LOG(WARNING, "Failed to allocate Rx DevX UAR (BF)");
832 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
833 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
834 (sh->ctx, uar_mapping);
837 if (!sh->devx_rx_uar) {
838 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (BF/NC)");
842 base_addr = mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar);
846 * The UARs are allocated by rdma_core within the
847 * IB device context, on context closure all UARs
848 * will be freed, should be no memory/object leakage.
850 DRV_LOG(WARNING, "Retrying to allocate Rx DevX UAR");
851 sh->devx_rx_uar = NULL;
853 /* Check whether we finally succeeded with valid UAR allocation. */
854 if (!sh->devx_rx_uar) {
855 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (NULL base)");
863 * Allocate shared device context. If there is multiport device the
864 * master and representors will share this context, if there is single
865 * port dedicated device, the context will be used by only given
866 * port due to unification.
868 * Routine first searches the context for the specified device name,
869 * if found the shared context assumed and reference counter is incremented.
870 * If no context found the new one is created and initialized with specified
871 * device context and parameters.
874 * Pointer to the device attributes (name, port, etc).
876 * Pointer to device configuration structure.
879 * Pointer to mlx5_dev_ctx_shared object on success,
880 * otherwise NULL and rte_errno is set.
882 struct mlx5_dev_ctx_shared *
883 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
884 const struct mlx5_dev_config *config)
886 struct mlx5_dev_ctx_shared *sh;
889 struct mlx5_devx_tis_attr tis_attr = { 0 };
892 /* Secondary process should not create the shared context. */
893 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
894 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
895 /* Search for IB context by device name. */
896 LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
897 if (!strcmp(sh->ibdev_name,
898 mlx5_os_get_dev_device_name(spawn->phys_dev))) {
903 /* No device found, we have to create new shared context. */
904 MLX5_ASSERT(spawn->max_port);
905 sh = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
906 sizeof(struct mlx5_dev_ctx_shared) +
908 sizeof(struct mlx5_dev_shared_port),
909 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
911 DRV_LOG(ERR, "shared context allocation failure");
915 err = mlx5_os_open_device(spawn, config, sh);
918 err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
920 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
924 sh->max_port = spawn->max_port;
925 strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
926 sizeof(sh->ibdev_name) - 1);
927 strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
928 sizeof(sh->ibdev_path) - 1);
930 * Setting port_id to max unallowed value means
931 * there is no interrupt subhandler installed for
932 * the given port index i.
934 for (i = 0; i < sh->max_port; i++) {
935 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
936 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
938 sh->pd = mlx5_glue->alloc_pd(sh->ctx);
939 if (sh->pd == NULL) {
940 DRV_LOG(ERR, "PD allocation failure");
945 /* Query the EQN for this core. */
946 err = mlx5_glue->devx_query_eqn(sh->ctx, 0, &sh->eqn);
949 DRV_LOG(ERR, "Failed to query event queue number %d.",
953 err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
955 DRV_LOG(ERR, "Fail to extract pdn from PD");
958 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
960 DRV_LOG(ERR, "TD allocation failure");
964 tis_attr.transport_domain = sh->td->id;
965 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
967 DRV_LOG(ERR, "TIS allocation failure");
971 err = mlx5_alloc_rxtx_uars(sh, config);
974 MLX5_ASSERT(sh->tx_uar);
975 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->tx_uar));
977 MLX5_ASSERT(sh->devx_rx_uar);
978 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar));
980 sh->flow_id_pool = mlx5_flow_id_pool_alloc
981 ((1 << HAIRPIN_FLOW_ID_BITS) - 1);
982 if (!sh->flow_id_pool) {
983 DRV_LOG(ERR, "can't create flow id pool");
988 /* Initialize UAR access locks for 32bit implementations. */
989 rte_spinlock_init(&sh->uar_lock_cq);
990 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
991 rte_spinlock_init(&sh->uar_lock[i]);
994 * Once the device is added to the list of memory event
995 * callback, its global MR cache table cannot be expanded
996 * on the fly because of deadlock. If it overflows, lookup
997 * should be done by searching MR list linearly, which is slow.
999 * At this point the device is not added to the memory
1000 * event list yet, context is just being created.
1002 err = mlx5_mr_btree_init(&sh->share_cache.cache,
1003 MLX5_MR_BTREE_CACHE_N * 2,
1004 spawn->pci_dev->device.numa_node);
1009 mlx5_os_set_reg_mr_cb(&sh->share_cache.reg_mr_cb,
1010 &sh->share_cache.dereg_mr_cb);
1011 mlx5_os_dev_shared_handler_install(sh);
1012 sh->cnt_id_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_DWORD);
1013 if (!sh->cnt_id_tbl) {
1017 mlx5_flow_aging_init(sh);
1018 mlx5_flow_counters_mng_init(sh);
1019 mlx5_flow_ipool_create(sh, config);
1020 /* Add device to memory callback list. */
1021 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1022 LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
1024 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1025 /* Add context to the global device list. */
1026 LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
1028 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1031 pthread_mutex_destroy(&sh->txpp.mutex);
1032 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1035 mlx5_l3t_destroy(sh->cnt_id_tbl);
1037 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1039 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1040 if (sh->devx_rx_uar)
1041 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1043 mlx5_glue->devx_free_uar(sh->tx_uar);
1045 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
1047 claim_zero(mlx5_glue->close_device(sh->ctx));
1048 if (sh->flow_id_pool)
1049 mlx5_flow_id_pool_release(sh->flow_id_pool);
1051 MLX5_ASSERT(err > 0);
1057 * Free shared IB device context. Decrement counter and if zero free
1058 * all allocated resources and close handles.
1061 * Pointer to mlx5_dev_ctx_shared object to free
1064 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
1066 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1067 #ifdef RTE_LIBRTE_MLX5_DEBUG
1068 /* Check the object presence in the list. */
1069 struct mlx5_dev_ctx_shared *lctx;
1071 LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
1076 DRV_LOG(ERR, "Freeing non-existing shared IB context");
1081 MLX5_ASSERT(sh->refcnt);
1082 /* Secondary process should not free the shared context. */
1083 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1086 /* Remove from memory callback device list. */
1087 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1088 LIST_REMOVE(sh, mem_event_cb);
1089 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1090 /* Release created Memory Regions. */
1091 mlx5_mr_release_cache(&sh->share_cache);
1092 /* Remove context from the global device list. */
1093 LIST_REMOVE(sh, next);
1094 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1096 * Ensure there is no async event handler installed.
1097 * Only primary process handles async device events.
1099 mlx5_flow_counters_mng_close(sh);
1100 mlx5_flow_ipool_destroy(sh);
1101 mlx5_os_dev_shared_handler_uninstall(sh);
1102 if (sh->cnt_id_tbl) {
1103 mlx5_l3t_destroy(sh->cnt_id_tbl);
1104 sh->cnt_id_tbl = NULL;
1107 mlx5_glue->devx_free_uar(sh->tx_uar);
1111 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
1113 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1115 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1116 if (sh->devx_rx_uar)
1117 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1119 claim_zero(mlx5_glue->close_device(sh->ctx));
1120 if (sh->flow_id_pool)
1121 mlx5_flow_id_pool_release(sh->flow_id_pool);
1122 pthread_mutex_destroy(&sh->txpp.mutex);
1126 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1130 * Destroy table hash list and all the root entries per domain.
1133 * Pointer to the private device data structure.
1136 mlx5_free_table_hash_list(struct mlx5_priv *priv)
1138 struct mlx5_dev_ctx_shared *sh = priv->sh;
1139 struct mlx5_flow_tbl_data_entry *tbl_data;
1140 union mlx5_flow_tbl_key table_key = {
1148 struct mlx5_hlist_entry *pos;
1152 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
1154 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
1156 MLX5_ASSERT(tbl_data);
1157 mlx5_hlist_remove(sh->flow_tbls, pos);
1158 mlx5_free(tbl_data);
1160 table_key.direction = 1;
1161 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
1163 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
1165 MLX5_ASSERT(tbl_data);
1166 mlx5_hlist_remove(sh->flow_tbls, pos);
1167 mlx5_free(tbl_data);
1169 table_key.direction = 0;
1170 table_key.domain = 1;
1171 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
1173 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
1175 MLX5_ASSERT(tbl_data);
1176 mlx5_hlist_remove(sh->flow_tbls, pos);
1177 mlx5_free(tbl_data);
1179 mlx5_hlist_destroy(sh->flow_tbls, NULL, NULL);
1183 * Initialize flow table hash list and create the root tables entry
1187 * Pointer to the private device data structure.
1190 * Zero on success, positive error code otherwise.
1193 mlx5_alloc_table_hash_list(struct mlx5_priv *priv)
1195 struct mlx5_dev_ctx_shared *sh = priv->sh;
1196 char s[MLX5_HLIST_NAMESIZE];
1200 snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1201 sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE);
1202 if (!sh->flow_tbls) {
1203 DRV_LOG(ERR, "flow tables with hash creation failed.");
1207 #ifndef HAVE_MLX5DV_DR
1209 * In case we have not DR support, the zero tables should be created
1210 * because DV expect to see them even if they cannot be created by
1213 union mlx5_flow_tbl_key table_key = {
1221 struct mlx5_flow_tbl_data_entry *tbl_data = mlx5_malloc(MLX5_MEM_ZERO,
1222 sizeof(*tbl_data), 0,
1229 tbl_data->entry.key = table_key.v64;
1230 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1233 rte_atomic32_init(&tbl_data->tbl.refcnt);
1234 rte_atomic32_inc(&tbl_data->tbl.refcnt);
1235 table_key.direction = 1;
1236 tbl_data = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tbl_data), 0,
1242 tbl_data->entry.key = table_key.v64;
1243 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1246 rte_atomic32_init(&tbl_data->tbl.refcnt);
1247 rte_atomic32_inc(&tbl_data->tbl.refcnt);
1248 table_key.direction = 0;
1249 table_key.domain = 1;
1250 tbl_data = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tbl_data), 0,
1256 tbl_data->entry.key = table_key.v64;
1257 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1260 rte_atomic32_init(&tbl_data->tbl.refcnt);
1261 rte_atomic32_inc(&tbl_data->tbl.refcnt);
1264 mlx5_free_table_hash_list(priv);
1265 #endif /* HAVE_MLX5DV_DR */
1270 * Retrieve integer value from environment variable.
1273 * Environment variable name.
1276 * Integer value, 0 if the variable is not set.
1279 mlx5_getenv_int(const char *name)
1281 const char *val = getenv(name);
1289 * DPDK callback to add udp tunnel port
1292 * A pointer to eth_dev
1293 * @param[in] udp_tunnel
1294 * A pointer to udp tunnel
1297 * 0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1300 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1301 struct rte_eth_udp_tunnel *udp_tunnel)
1303 MLX5_ASSERT(udp_tunnel != NULL);
1304 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1305 udp_tunnel->udp_port == 4789)
1307 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1308 udp_tunnel->udp_port == 4790)
1314 * Initialize process private data structure.
1317 * Pointer to Ethernet device structure.
1320 * 0 on success, a negative errno value otherwise and rte_errno is set.
1323 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1325 struct mlx5_priv *priv = dev->data->dev_private;
1326 struct mlx5_proc_priv *ppriv;
1330 * UAR register table follows the process private structure. BlueFlame
1331 * registers for Tx queues are stored in the table.
1334 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1335 ppriv = mlx5_malloc(MLX5_MEM_RTE, ppriv_size, RTE_CACHE_LINE_SIZE,
1336 dev->device->numa_node);
1341 ppriv->uar_table_sz = ppriv_size;
1342 dev->process_private = ppriv;
1347 * Un-initialize process private data structure.
1350 * Pointer to Ethernet device structure.
1353 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1355 if (!dev->process_private)
1357 mlx5_free(dev->process_private);
1358 dev->process_private = NULL;
1362 * DPDK callback to close the device.
1364 * Destroy all queues and objects, free memory.
1367 * Pointer to Ethernet device structure.
1370 mlx5_dev_close(struct rte_eth_dev *dev)
1372 struct mlx5_priv *priv = dev->data->dev_private;
1376 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1377 /* Check if process_private released. */
1378 if (!dev->process_private)
1380 mlx5_tx_uar_uninit_secondary(dev);
1381 mlx5_proc_priv_uninit(dev);
1382 rte_eth_dev_release_port(dev);
1387 DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1389 ((priv->sh->ctx != NULL) ?
1390 mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
1392 * If default mreg copy action is removed at the stop stage,
1393 * the search will return none and nothing will be done anymore.
1395 mlx5_flow_stop_default(dev);
1396 mlx5_traffic_disable(dev);
1398 * If all the flows are already flushed in the device stop stage,
1399 * then this will return directly without any action.
1401 mlx5_flow_list_flush(dev, &priv->flows, true);
1402 mlx5_flow_meter_flush(dev, NULL);
1403 /* Free the intermediate buffers for flow creation. */
1404 mlx5_flow_free_intermediate(dev);
1405 /* Prevent crashes when queues are still in use. */
1406 dev->rx_pkt_burst = removed_rx_burst;
1407 dev->tx_pkt_burst = removed_tx_burst;
1409 /* Disable datapath on secondary process. */
1410 mlx5_mp_os_req_stop_rxtx(dev);
1411 /* Free the eCPRI flex parser resource. */
1412 mlx5_flex_parser_ecpri_release(dev);
1413 if (priv->rxqs != NULL) {
1414 /* XXX race condition if mlx5_rx_burst() is still running. */
1416 for (i = 0; (i != priv->rxqs_n); ++i)
1417 mlx5_rxq_release(dev, i);
1421 if (priv->txqs != NULL) {
1422 /* XXX race condition if mlx5_tx_burst() is still running. */
1424 for (i = 0; (i != priv->txqs_n); ++i)
1425 mlx5_txq_release(dev, i);
1429 mlx5_proc_priv_uninit(dev);
1430 if (priv->mreg_cp_tbl)
1431 mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
1432 mlx5_mprq_free_mp(dev);
1433 mlx5_os_free_shared_dr(priv);
1434 if (priv->rss_conf.rss_key != NULL)
1435 mlx5_free(priv->rss_conf.rss_key);
1436 if (priv->reta_idx != NULL)
1437 mlx5_free(priv->reta_idx);
1438 if (priv->config.vf)
1439 mlx5_os_mac_addr_flush(dev);
1440 if (priv->nl_socket_route >= 0)
1441 close(priv->nl_socket_route);
1442 if (priv->nl_socket_rdma >= 0)
1443 close(priv->nl_socket_rdma);
1444 if (priv->vmwa_context)
1445 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1446 ret = mlx5_hrxq_verify(dev);
1448 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1449 dev->data->port_id);
1450 ret = mlx5_ind_table_obj_verify(dev);
1452 DRV_LOG(WARNING, "port %u some indirection table still remain",
1453 dev->data->port_id);
1454 ret = mlx5_rxq_obj_verify(dev);
1456 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1457 dev->data->port_id);
1458 ret = mlx5_rxq_verify(dev);
1460 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1461 dev->data->port_id);
1462 ret = mlx5_txq_obj_verify(dev);
1464 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1465 dev->data->port_id);
1466 ret = mlx5_txq_verify(dev);
1468 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1469 dev->data->port_id);
1470 ret = mlx5_flow_verify(dev);
1472 DRV_LOG(WARNING, "port %u some flows still remain",
1473 dev->data->port_id);
1475 * Free the shared context in last turn, because the cleanup
1476 * routines above may use some shared fields, like
1477 * mlx5_os_mac_addr_flush() uses ibdev_path for retrieveing
1478 * ifindex if Netlink fails.
1480 mlx5_free_shared_dev_ctx(priv->sh);
1481 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1485 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1486 struct mlx5_priv *opriv =
1487 rte_eth_devices[port_id].data->dev_private;
1490 opriv->domain_id != priv->domain_id ||
1491 &rte_eth_devices[port_id] == dev)
1497 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1499 memset(priv, 0, sizeof(*priv));
1500 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1502 * Reset mac_addrs to NULL such that it is not freed as part of
1503 * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1504 * it is freed when dev_private is freed.
1506 dev->data->mac_addrs = NULL;
1511 * Verify and store value for device argument.
1514 * Key argument to verify.
1516 * Value associated with key.
1521 * 0 on success, a negative errno value otherwise and rte_errno is set.
1524 mlx5_args_check(const char *key, const char *val, void *opaque)
1526 struct mlx5_dev_config *config = opaque;
1530 /* No-op, port representors are processed in mlx5_dev_spawn(). */
1531 if (!strcmp(MLX5_REPRESENTOR, key))
1534 tmp = strtol(val, NULL, 0);
1537 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1540 if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
1541 /* Negative values are acceptable for some keys only. */
1543 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
1546 mod = tmp >= 0 ? tmp : -tmp;
1547 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1548 config->cqe_comp = !!tmp;
1549 } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
1550 config->cqe_pad = !!tmp;
1551 } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1552 config->hw_padding = !!tmp;
1553 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1554 config->mprq.enabled = !!tmp;
1555 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1556 config->mprq.stride_num_n = tmp;
1557 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1558 config->mprq.stride_size_n = tmp;
1559 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1560 config->mprq.max_memcpy_len = tmp;
1561 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1562 config->mprq.min_rxqs_num = tmp;
1563 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1564 DRV_LOG(WARNING, "%s: deprecated parameter,"
1565 " converted to txq_inline_max", key);
1566 config->txq_inline_max = tmp;
1567 } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1568 config->txq_inline_max = tmp;
1569 } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1570 config->txq_inline_min = tmp;
1571 } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1572 config->txq_inline_mpw = tmp;
1573 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1574 config->txqs_inline = tmp;
1575 } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1576 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1577 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1578 config->mps = !!tmp;
1579 } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1580 if (tmp != MLX5_TXDB_CACHED &&
1581 tmp != MLX5_TXDB_NCACHED &&
1582 tmp != MLX5_TXDB_HEURISTIC) {
1583 DRV_LOG(ERR, "invalid Tx doorbell "
1584 "mapping parameter");
1589 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1590 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1591 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1592 DRV_LOG(WARNING, "%s: deprecated parameter,"
1593 " converted to txq_inline_mpw", key);
1594 config->txq_inline_mpw = tmp;
1595 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1596 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1597 } else if (strcmp(MLX5_TX_PP, key) == 0) {
1599 DRV_LOG(ERR, "Zero Tx packet pacing parameter");
1603 config->tx_pp = tmp;
1604 } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
1605 config->tx_skew = tmp;
1606 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1607 config->rx_vec_en = !!tmp;
1608 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1609 config->l3_vxlan_en = !!tmp;
1610 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1611 config->vf_nl_en = !!tmp;
1612 } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1613 config->dv_esw_en = !!tmp;
1614 } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1615 config->dv_flow_en = !!tmp;
1616 } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1617 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1618 tmp != MLX5_XMETA_MODE_META16 &&
1619 tmp != MLX5_XMETA_MODE_META32) {
1620 DRV_LOG(ERR, "invalid extensive "
1621 "metadata parameter");
1625 config->dv_xmeta_en = tmp;
1626 } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
1627 config->lacp_by_user = !!tmp;
1628 } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1629 config->mr_ext_memseg_en = !!tmp;
1630 } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1631 config->max_dump_files_num = tmp;
1632 } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1633 config->lro.timeout = tmp;
1634 } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1635 DRV_LOG(DEBUG, "class argument is %s.", val);
1636 } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1637 config->log_hp_size = tmp;
1638 } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1639 if (tmp != MLX5_RCM_NONE &&
1640 tmp != MLX5_RCM_LIGHT &&
1641 tmp != MLX5_RCM_AGGR) {
1642 DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1646 config->reclaim_mode = tmp;
1647 } else if (strcmp(MLX5_SYS_MEM_EN, key) == 0) {
1648 config->sys_mem_en = !!tmp;
1649 } else if (strcmp(MLX5_DECAP_EN, key) == 0) {
1650 config->decap_en = !!tmp;
1652 DRV_LOG(WARNING, "%s: unknown parameter", key);
1660 * Parse device parameters.
1663 * Pointer to device configuration structure.
1665 * Device arguments structure.
1668 * 0 on success, a negative errno value otherwise and rte_errno is set.
1671 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1673 const char **params = (const char *[]){
1674 MLX5_RXQ_CQE_COMP_EN,
1675 MLX5_RXQ_CQE_PAD_EN,
1676 MLX5_RXQ_PKT_PAD_EN,
1678 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1679 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1680 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1683 MLX5_TXQ_INLINE_MIN,
1684 MLX5_TXQ_INLINE_MAX,
1685 MLX5_TXQ_INLINE_MPW,
1686 MLX5_TXQS_MIN_INLINE,
1689 MLX5_TXQ_MPW_HDR_DSEG_EN,
1690 MLX5_TXQ_MAX_INLINE_LEN,
1702 MLX5_MR_EXT_MEMSEG_EN,
1704 MLX5_MAX_DUMP_FILES_NUM,
1705 MLX5_LRO_TIMEOUT_USEC,
1706 MLX5_CLASS_ARG_NAME,
1713 struct rte_kvargs *kvlist;
1717 if (devargs == NULL)
1719 /* Following UGLY cast is done to pass checkpatch. */
1720 kvlist = rte_kvargs_parse(devargs->args, params);
1721 if (kvlist == NULL) {
1725 /* Process parameters. */
1726 for (i = 0; (params[i] != NULL); ++i) {
1727 if (rte_kvargs_count(kvlist, params[i])) {
1728 ret = rte_kvargs_process(kvlist, params[i],
1729 mlx5_args_check, config);
1732 rte_kvargs_free(kvlist);
1737 rte_kvargs_free(kvlist);
1742 * Configures the minimal amount of data to inline into WQE
1743 * while sending packets.
1745 * - the txq_inline_min has the maximal priority, if this
1746 * key is specified in devargs
1747 * - if DevX is enabled the inline mode is queried from the
1748 * device (HCA attributes and NIC vport context if needed).
1749 * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1750 * and none (0 bytes) for other NICs
1753 * Verbs device parameters (name, port, switch_info) to spawn.
1755 * Device configuration parameters.
1758 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1759 struct mlx5_dev_config *config)
1761 if (config->txq_inline_min != MLX5_ARG_UNSET) {
1762 /* Application defines size of inlined data explicitly. */
1763 switch (spawn->pci_dev->id.device_id) {
1764 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1765 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1766 if (config->txq_inline_min <
1767 (int)MLX5_INLINE_HSIZE_L2) {
1769 "txq_inline_mix aligned to minimal"
1770 " ConnectX-4 required value %d",
1771 (int)MLX5_INLINE_HSIZE_L2);
1772 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1778 if (config->hca_attr.eth_net_offloads) {
1779 /* We have DevX enabled, inline mode queried successfully. */
1780 switch (config->hca_attr.wqe_inline_mode) {
1781 case MLX5_CAP_INLINE_MODE_L2:
1782 /* outer L2 header must be inlined. */
1783 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1785 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1786 /* No inline data are required by NIC. */
1787 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1788 config->hw_vlan_insert =
1789 config->hca_attr.wqe_vlan_insert;
1790 DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1792 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1793 /* inline mode is defined by NIC vport context. */
1794 if (!config->hca_attr.eth_virt)
1796 switch (config->hca_attr.vport_inline_mode) {
1797 case MLX5_INLINE_MODE_NONE:
1798 config->txq_inline_min =
1799 MLX5_INLINE_HSIZE_NONE;
1801 case MLX5_INLINE_MODE_L2:
1802 config->txq_inline_min =
1803 MLX5_INLINE_HSIZE_L2;
1805 case MLX5_INLINE_MODE_IP:
1806 config->txq_inline_min =
1807 MLX5_INLINE_HSIZE_L3;
1809 case MLX5_INLINE_MODE_TCP_UDP:
1810 config->txq_inline_min =
1811 MLX5_INLINE_HSIZE_L4;
1813 case MLX5_INLINE_MODE_INNER_L2:
1814 config->txq_inline_min =
1815 MLX5_INLINE_HSIZE_INNER_L2;
1817 case MLX5_INLINE_MODE_INNER_IP:
1818 config->txq_inline_min =
1819 MLX5_INLINE_HSIZE_INNER_L3;
1821 case MLX5_INLINE_MODE_INNER_TCP_UDP:
1822 config->txq_inline_min =
1823 MLX5_INLINE_HSIZE_INNER_L4;
1829 * We get here if we are unable to deduce
1830 * inline data size with DevX. Try PCI ID
1831 * to determine old NICs.
1833 switch (spawn->pci_dev->id.device_id) {
1834 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1835 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1836 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
1837 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1838 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1839 config->hw_vlan_insert = 0;
1841 case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
1842 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1843 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
1844 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1846 * These NICs support VLAN insertion from WQE and
1847 * report the wqe_vlan_insert flag. But there is the bug
1848 * and PFC control may be broken, so disable feature.
1850 config->hw_vlan_insert = 0;
1851 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1854 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1858 DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
1862 * Configures the metadata mask fields in the shared context.
1865 * Pointer to Ethernet device.
1868 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
1870 struct mlx5_priv *priv = dev->data->dev_private;
1871 struct mlx5_dev_ctx_shared *sh = priv->sh;
1872 uint32_t meta, mark, reg_c0;
1874 reg_c0 = ~priv->vport_meta_mask;
1875 switch (priv->config.dv_xmeta_en) {
1876 case MLX5_XMETA_MODE_LEGACY:
1878 mark = MLX5_FLOW_MARK_MASK;
1880 case MLX5_XMETA_MODE_META16:
1881 meta = reg_c0 >> rte_bsf32(reg_c0);
1882 mark = MLX5_FLOW_MARK_MASK;
1884 case MLX5_XMETA_MODE_META32:
1886 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
1894 if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
1895 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
1896 sh->dv_mark_mask, mark);
1898 sh->dv_mark_mask = mark;
1899 if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
1900 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
1901 sh->dv_meta_mask, meta);
1903 sh->dv_meta_mask = meta;
1904 if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
1905 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
1906 sh->dv_meta_mask, reg_c0);
1908 sh->dv_regc0_mask = reg_c0;
1909 DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
1910 DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
1911 DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
1912 DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
1916 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
1918 static const char *const dynf_names[] = {
1919 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
1920 RTE_MBUF_DYNFLAG_METADATA_NAME,
1921 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
1925 if (n < RTE_DIM(dynf_names))
1927 for (i = 0; i < RTE_DIM(dynf_names); i++) {
1928 if (names[i] == NULL)
1930 strcpy(names[i], dynf_names[i]);
1932 return RTE_DIM(dynf_names);
1936 * Comparison callback to sort device data.
1938 * This is meant to be used with qsort().
1941 * Pointer to pointer to first data object.
1943 * Pointer to pointer to second data object.
1946 * 0 if both objects are equal, less than 0 if the first argument is less
1947 * than the second, greater than 0 otherwise.
1950 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
1951 struct mlx5_dev_config *config)
1953 struct mlx5_dev_ctx_shared *sh = priv->sh;
1954 struct mlx5_dev_config *sh_conf = NULL;
1958 /* Nothing to compare for the single/first device. */
1959 if (sh->refcnt == 1)
1961 /* Find the device with shared context. */
1962 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1963 struct mlx5_priv *opriv =
1964 rte_eth_devices[port_id].data->dev_private;
1966 if (opriv && opriv != priv && opriv->sh == sh) {
1967 sh_conf = &opriv->config;
1973 if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
1974 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
1975 " for shared %s context", sh->ibdev_name);
1979 if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
1980 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
1981 " for shared %s context", sh->ibdev_name);
1989 * Look for the ethernet device belonging to mlx5 driver.
1991 * @param[in] port_id
1992 * port_id to start looking for device.
1993 * @param[in] pci_dev
1994 * Pointer to the hint PCI device. When device is being probed
1995 * the its siblings (master and preceding representors might
1996 * not have assigned driver yet (because the mlx5_os_pci_probe()
1997 * is not completed yet, for this case match on hint PCI
1998 * device may be used to detect sibling device.
2001 * port_id of found device, RTE_MAX_ETHPORT if not found.
2004 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
2006 while (port_id < RTE_MAX_ETHPORTS) {
2007 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
2009 if (dev->state != RTE_ETH_DEV_UNUSED &&
2011 (dev->device == &pci_dev->device ||
2012 (dev->device->driver &&
2013 dev->device->driver->name &&
2014 !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
2018 if (port_id >= RTE_MAX_ETHPORTS)
2019 return RTE_MAX_ETHPORTS;
2024 * DPDK callback to remove a PCI device.
2026 * This function removes all Ethernet devices belong to a given PCI device.
2028 * @param[in] pci_dev
2029 * Pointer to the PCI device.
2032 * 0 on success, the function cannot fail.
2035 mlx5_pci_remove(struct rte_pci_device *pci_dev)
2040 RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
2042 * mlx5_dev_close() is not registered to secondary process,
2043 * call the close function explicitly for secondary process.
2045 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
2046 ret |= mlx5_dev_close(&rte_eth_devices[port_id]);
2048 ret |= rte_eth_dev_close(port_id);
2050 return ret == 0 ? 0 : -EIO;
2053 static const struct rte_pci_id mlx5_pci_id_map[] = {
2055 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2056 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
2059 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2060 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
2063 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2064 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
2067 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2068 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
2071 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2072 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
2075 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2076 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
2079 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2080 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
2083 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2084 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
2087 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2088 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
2091 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2092 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
2095 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2096 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
2099 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2100 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
2103 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2104 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
2107 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2108 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF)
2111 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2112 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
2115 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2116 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
2123 static struct mlx5_pci_driver mlx5_driver = {
2124 .driver_class = MLX5_CLASS_NET,
2127 .name = MLX5_DRIVER_NAME,
2129 .id_table = mlx5_pci_id_map,
2130 .probe = mlx5_os_pci_probe,
2131 .remove = mlx5_pci_remove,
2132 .dma_map = mlx5_dma_map,
2133 .dma_unmap = mlx5_dma_unmap,
2134 .drv_flags = PCI_DRV_FLAGS,
2138 /* Initialize driver log type. */
2139 RTE_LOG_REGISTER(mlx5_logtype, pmd.net.mlx5, NOTICE)
2142 * Driver initialization routine.
2144 RTE_INIT(rte_mlx5_pmd_init)
2147 /* Build the static tables for Verbs conversion. */
2148 mlx5_set_ptype_table();
2149 mlx5_set_cksum_table();
2150 mlx5_set_swp_types_table();
2152 mlx5_pci_driver_register(&mlx5_driver);
2155 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
2156 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
2157 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");