drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <stdint.h>
  10 #include <stdlib.h>
  11 #include <errno.h>
  12
  13 #include <rte_malloc.h>
  14 #include <rte_ethdev_driver.h>
  15 #include <rte_ethdev_pci.h>
  16 #include <rte_pci.h>
  17 #include <rte_bus_pci.h>
  18 #include <rte_common.h>
  19 #include <rte_kvargs.h>
  20 #include <rte_rwlock.h>
  21 #include <rte_spinlock.h>
  22 #include <rte_string_fns.h>
  23 #include <rte_alarm.h>
  24
  25 #include <mlx5_glue.h>
  26 #include <mlx5_devx_cmds.h>
  27 #include <mlx5_common.h>
  28 #include <mlx5_common_os.h>
  29 #include <mlx5_common_mp.h>
  30 #include <mlx5_common_pci.h>
  31 #include <mlx5_malloc.h>
  32
  33 #include "mlx5_defs.h"
  34 #include "mlx5.h"
  35 #include "mlx5_utils.h"
  36 #include "mlx5_rxtx.h"
  37 #include "mlx5_autoconf.h"
  38 #include "mlx5_mr.h"
  39 #include "mlx5_flow.h"
  40 #include "rte_pmd_mlx5.h"
  41
  42 /* Device parameter to enable RX completion queue compression. */
  43 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  44
  45 /* Device parameter to enable RX completion entry padding to 128B. */
  46 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
  47
  48 /* Device parameter to enable padding Rx packet to cacheline size. */
  49 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
  50
  51 /* Device parameter to enable Multi-Packet Rx queue. */
  52 #define MLX5_RX_MPRQ_EN "mprq_en"
  53
  54 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
  55 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
  56
  57 /* Device parameter to configure log 2 of the stride size for MPRQ. */
  58 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
  59
  60 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
  61 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
  62
  63 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
  64 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
  65
  66 /* Device parameter to configure inline send. Deprecated, ignored.*/
  67 #define MLX5_TXQ_INLINE "txq_inline"
  68
  69 /* Device parameter to limit packet size to inline with ordinary SEND. */
  70 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
  71
  72 /* Device parameter to configure minimal data size to inline. */
  73 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
  74
  75 /* Device parameter to limit packet size to inline with Enhanced MPW. */
  76 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
  77
  78 /*
  79  * Device parameter to configure the number of TX queues threshold for
  80  * enabling inline send.
  81  */
  82 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  83
  84 /*
  85  * Device parameter to configure the number of TX queues threshold for
  86  * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
  87  */
  88 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
  89
  90 /* Device parameter to enable multi-packet send WQEs. */
  91 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
  92
  93 /*
  94  * Device parameter to force doorbell register mapping
  95  * to non-cahed region eliminating the extra write memory barrier.
  96  */
  97 #define MLX5_TX_DB_NC "tx_db_nc"
  98
  99 /*
 100  * Device parameter to include 2 dsegs in the title WQEBB.
 101  * Deprecated, ignored.
 102  */
 103 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
 104
 105 /*
 106  * Device parameter to limit the size of inlining packet.
 107  * Deprecated, ignored.
 108  */
 109 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
 110
 111 /*
 112  * Device parameter to enable Tx scheduling on timestamps
 113  * and specify the packet pacing granularity in nanoseconds.
 114  */
 115 #define MLX5_TX_PP "tx_pp"
 116
 117 /*
 118  * Device parameter to specify skew in nanoseconds on Tx datapath,
 119  * it represents the time between SQ start WQE processing and
 120  * appearing actual packet data on the wire.
 121  */
 122 #define MLX5_TX_SKEW "tx_skew"
 123
 124 /*
 125  * Device parameter to enable hardware Tx vector.
 126  * Deprecated, ignored (no vectorized Tx routines anymore).
 127  */
 128 #define MLX5_TX_VEC_EN "tx_vec_en"
 129
 130 /* Device parameter to enable hardware Rx vector. */
 131 #define MLX5_RX_VEC_EN "rx_vec_en"
 132
 133 /* Allow L3 VXLAN flow creation. */
 134 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
 135
 136 /* Activate DV E-Switch flow steering. */
 137 #define MLX5_DV_ESW_EN "dv_esw_en"
 138
 139 /* Activate DV flow steering. */
 140 #define MLX5_DV_FLOW_EN "dv_flow_en"
 141
 142 /* Enable extensive flow metadata support. */
 143 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
 144
 145 /* Device parameter to let the user manage the lacp traffic of bonded device */
 146 #define MLX5_LACP_BY_USER "lacp_by_user"
 147
 148 /* Activate Netlink support in VF mode. */
 149 #define MLX5_VF_NL_EN "vf_nl_en"
 150
 151 /* Enable extending memsegs when creating a MR. */
 152 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
 153
 154 /* Select port representors to instantiate. */
 155 #define MLX5_REPRESENTOR "representor"
 156
 157 /* Device parameter to configure the maximum number of dump files per queue. */
 158 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
 159
 160 /* Configure timeout of LRO session (in microseconds). */
 161 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
 162
 163 /*
 164  * Device parameter to configure the total data buffer size for a single
 165  * hairpin queue (logarithm value).
 166  */
 167 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
 168
 169 /* Flow memory reclaim mode. */
 170 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
 171
 172 /* The default memory allocator used in PMD. */
 173 #define MLX5_SYS_MEM_EN "sys_mem_en"
 174 /* Decap will be used or not. */
 175 #define MLX5_DECAP_EN "decap_en"
 176
 177 /* Shared memory between primary and secondary processes. */
 178 struct mlx5_shared_data *mlx5_shared_data;
 179
 180 /** Driver-specific log messages type. */
 181 int mlx5_logtype;
 182
 183 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
 184                                                 LIST_HEAD_INITIALIZER();
 185 static pthread_mutex_t mlx5_dev_ctx_list_mutex = PTHREAD_MUTEX_INITIALIZER;
 186
 187 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
 188 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 189         {
 190                 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
 191                 .trunk_size = 64,
 192                 .grow_trunk = 3,
 193                 .grow_shift = 2,
 194                 .need_lock = 1,
 195                 .release_mem_en = 1,
 196                 .malloc = mlx5_malloc,
 197                 .free = mlx5_free,
 198                 .type = "mlx5_encap_decap_ipool",
 199         },
 200         {
 201                 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
 202                 .trunk_size = 64,
 203                 .grow_trunk = 3,
 204                 .grow_shift = 2,
 205                 .need_lock = 1,
 206                 .release_mem_en = 1,
 207                 .malloc = mlx5_malloc,
 208                 .free = mlx5_free,
 209                 .type = "mlx5_push_vlan_ipool",
 210         },
 211         {
 212                 .size = sizeof(struct mlx5_flow_dv_tag_resource),
 213                 .trunk_size = 64,
 214                 .grow_trunk = 3,
 215                 .grow_shift = 2,
 216                 .need_lock = 1,
 217                 .release_mem_en = 1,
 218                 .malloc = mlx5_malloc,
 219                 .free = mlx5_free,
 220                 .type = "mlx5_tag_ipool",
 221         },
 222         {
 223                 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
 224                 .trunk_size = 64,
 225                 .grow_trunk = 3,
 226                 .grow_shift = 2,
 227                 .need_lock = 1,
 228                 .release_mem_en = 1,
 229                 .malloc = mlx5_malloc,
 230                 .free = mlx5_free,
 231                 .type = "mlx5_port_id_ipool",
 232         },
 233         {
 234                 .size = sizeof(struct mlx5_flow_tbl_data_entry),
 235                 .trunk_size = 64,
 236                 .grow_trunk = 3,
 237                 .grow_shift = 2,
 238                 .need_lock = 1,
 239                 .release_mem_en = 1,
 240                 .malloc = mlx5_malloc,
 241                 .free = mlx5_free,
 242                 .type = "mlx5_jump_ipool",
 243         },
 244         {
 245                 .size = sizeof(struct mlx5_flow_dv_sample_resource),
 246                 .trunk_size = 64,
 247                 .grow_trunk = 3,
 248                 .grow_shift = 2,
 249                 .need_lock = 1,
 250                 .release_mem_en = 1,
 251                 .malloc = mlx5_malloc,
 252                 .free = mlx5_free,
 253                 .type = "mlx5_sample_ipool",
 254         },
 255         {
 256                 .size = sizeof(struct mlx5_flow_dv_dest_array_resource),
 257                 .trunk_size = 64,
 258                 .grow_trunk = 3,
 259                 .grow_shift = 2,
 260                 .need_lock = 1,
 261                 .release_mem_en = 1,
 262                 .malloc = mlx5_malloc,
 263                 .free = mlx5_free,
 264                 .type = "mlx5_dest_array_ipool",
 265         },
 266 #endif
 267         {
 268                 .size = sizeof(struct mlx5_flow_meter),
 269                 .trunk_size = 64,
 270                 .grow_trunk = 3,
 271                 .grow_shift = 2,
 272                 .need_lock = 1,
 273                 .release_mem_en = 1,
 274                 .malloc = mlx5_malloc,
 275                 .free = mlx5_free,
 276                 .type = "mlx5_meter_ipool",
 277         },
 278         {
 279                 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
 280                 .trunk_size = 64,
 281                 .grow_trunk = 3,
 282                 .grow_shift = 2,
 283                 .need_lock = 1,
 284                 .release_mem_en = 1,
 285                 .malloc = mlx5_malloc,
 286                 .free = mlx5_free,
 287                 .type = "mlx5_mcp_ipool",
 288         },
 289         {
 290                 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
 291                 .trunk_size = 64,
 292                 .grow_trunk = 3,
 293                 .grow_shift = 2,
 294                 .need_lock = 1,
 295                 .release_mem_en = 1,
 296                 .malloc = mlx5_malloc,
 297                 .free = mlx5_free,
 298                 .type = "mlx5_hrxq_ipool",
 299         },
 300         {
 301                 /*
 302                  * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
 303                  * It set in run time according to PCI function configuration.
 304                  */
 305                 .size = 0,
 306                 .trunk_size = 64,
 307                 .grow_trunk = 3,
 308                 .grow_shift = 2,
 309                 .need_lock = 1,
 310                 .release_mem_en = 1,
 311                 .malloc = mlx5_malloc,
 312                 .free = mlx5_free,
 313                 .type = "mlx5_flow_handle_ipool",
 314         },
 315         {
 316                 .size = sizeof(struct rte_flow),
 317                 .trunk_size = 4096,
 318                 .need_lock = 1,
 319                 .release_mem_en = 1,
 320                 .malloc = mlx5_malloc,
 321                 .free = mlx5_free,
 322                 .type = "rte_flow_ipool",
 323         },
 324         {
 325                 .size = 0,
 326                 .need_lock = 1,
 327                 .type = "mlx5_flow_rss_id_ipool",
 328         },
 329         {
 330                 .size = 0,
 331                 .need_lock = 1,
 332                 .type = "mlx5_flow_tnl_flow_ipool",
 333         },
 334         {
 335                 .size = 0,
 336                 .need_lock = 1,
 337                 .type = "mlx5_flow_tnl_tbl_ipool",
 338         },
 339         {
 340                 .size = sizeof(struct mlx5_shared_action_rss),
 341                 .trunk_size = 64,
 342                 .grow_trunk = 3,
 343                 .grow_shift = 2,
 344                 .need_lock = 1,
 345                 .release_mem_en = 1,
 346                 .malloc = mlx5_malloc,
 347                 .free = mlx5_free,
 348                 .type = "mlx5_shared_action_rss",
 349         },
 350
 351 };
 352
 353
 354 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
 355 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
 356
 357 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
 358
 359 /**
 360  * Initialize the ASO aging management structure.
 361  *
 362  * @param[in] sh
 363  *   Pointer to mlx5_dev_ctx_shared object to free
 364  *
 365  * @return
 366  *   0 on success, a negative errno value otherwise and rte_errno is set.
 367  */
 368 int
 369 mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh)
 370 {
 371         int err;
 372
 373         if (sh->aso_age_mng)
 374                 return 0;
 375         sh->aso_age_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->aso_age_mng),
 376                                       RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 377         if (!sh->aso_age_mng) {
 378                 DRV_LOG(ERR, "aso_age_mng allocation was failed.");
 379                 rte_errno = ENOMEM;
 380                 return -ENOMEM;
 381         }
 382         err = mlx5_aso_queue_init(sh);
 383         if (err) {
 384                 mlx5_free(sh->aso_age_mng);
 385                 return -1;
 386         }
 387         rte_spinlock_init(&sh->aso_age_mng->resize_sl);
 388         rte_spinlock_init(&sh->aso_age_mng->free_sl);
 389         LIST_INIT(&sh->aso_age_mng->free);
 390         return 0;
 391 }
 392
 393 /**
 394  * Close and release all the resources of the ASO aging management structure.
 395  *
 396  * @param[in] sh
 397  *   Pointer to mlx5_dev_ctx_shared object to free.
 398  */
 399 static void
 400 mlx5_flow_aso_age_mng_close(struct mlx5_dev_ctx_shared *sh)
 401 {
 402         int i, j;
 403
 404         mlx5_aso_queue_stop(sh);
 405         mlx5_aso_queue_uninit(sh);
 406         if (sh->aso_age_mng->pools) {
 407                 struct mlx5_aso_age_pool *pool;
 408
 409                 for (i = 0; i < sh->aso_age_mng->next; ++i) {
 410                         pool = sh->aso_age_mng->pools[i];
 411                         claim_zero(mlx5_devx_cmd_destroy
 412                                                 (pool->flow_hit_aso_obj));
 413                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j)
 414                                 if (pool->actions[j].dr_action)
 415                                         claim_zero
 416                                                 (mlx5_glue->destroy_flow_action
 417                                                   (pool->actions[j].dr_action));
 418                         mlx5_free(pool);
 419                 }
 420                 mlx5_free(sh->aso_age_mng->pools);
 421         }
 422         memset(&sh->aso_age_mng, 0, sizeof(sh->aso_age_mng));
 423 }
 424
 425 /**
 426  * Initialize the shared aging list information per port.
 427  *
 428  * @param[in] sh
 429  *   Pointer to mlx5_dev_ctx_shared object.
 430  */
 431 static void
 432 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
 433 {
 434         uint32_t i;
 435         struct mlx5_age_info *age_info;
 436
 437         for (i = 0; i < sh->max_port; i++) {
 438                 age_info = &sh->port[i].age_info;
 439                 age_info->flags = 0;
 440                 TAILQ_INIT(&age_info->aged_counters);
 441                 rte_spinlock_init(&age_info->aged_sl);
 442                 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
 443         }
 444 }
 445
 446 /**
 447  * Initialize the counters management structure.
 448  *
 449  * @param[in] sh
 450  *   Pointer to mlx5_dev_ctx_shared object to free
 451  */
 452 static void
 453 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
 454 {
 455         int i;
 456
 457         memset(&sh->cmng, 0, sizeof(sh->cmng));
 458         TAILQ_INIT(&sh->cmng.flow_counters);
 459         sh->cmng.min_id = MLX5_CNT_BATCH_OFFSET;
 460         sh->cmng.max_id = -1;
 461         sh->cmng.last_pool_idx = POOL_IDX_INVALID;
 462         rte_spinlock_init(&sh->cmng.pool_update_sl);
 463         for (i = 0; i < MLX5_COUNTER_TYPE_MAX; i++) {
 464                 TAILQ_INIT(&sh->cmng.counters[i]);
 465                 rte_spinlock_init(&sh->cmng.csl[i]);
 466         }
 467 }
 468
 469 /**
 470  * Destroy all the resources allocated for a counter memory management.
 471  *
 472  * @param[in] mng
 473  *   Pointer to the memory management structure.
 474  */
 475 static void
 476 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
 477 {
 478         uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
 479
 480         LIST_REMOVE(mng, next);
 481         claim_zero(mlx5_devx_cmd_destroy(mng->dm));
 482         claim_zero(mlx5_glue->devx_umem_dereg(mng->umem));
 483         mlx5_free(mem);
 484 }
 485
 486 /**
 487  * Close and release all the resources of the counters management.
 488  *
 489  * @param[in] sh
 490  *   Pointer to mlx5_dev_ctx_shared object to free.
 491  */
 492 static void
 493 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
 494 {
 495         struct mlx5_counter_stats_mem_mng *mng;
 496         int i, j;
 497         int retries = 1024;
 498
 499         rte_errno = 0;
 500         while (--retries) {
 501                 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
 502                 if (rte_errno != EINPROGRESS)
 503                         break;
 504                 rte_pause();
 505         }
 506
 507         if (sh->cmng.pools) {
 508                 struct mlx5_flow_counter_pool *pool;
 509                 uint16_t n_valid = sh->cmng.n_valid;
 510                 bool fallback = sh->cmng.counter_fallback;
 511
 512                 for (i = 0; i < n_valid; ++i) {
 513                         pool = sh->cmng.pools[i];
 514                         if (!fallback && pool->min_dcs)
 515                                 claim_zero(mlx5_devx_cmd_destroy
 516                                                                (pool->min_dcs));
 517                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
 518                                 struct mlx5_flow_counter *cnt =
 519                                                 MLX5_POOL_GET_CNT(pool, j);
 520
 521                                 if (cnt->action)
 522                                         claim_zero
 523                                          (mlx5_glue->destroy_flow_action
 524                                           (cnt->action));
 525                                 if (fallback && MLX5_POOL_GET_CNT
 526                                     (pool, j)->dcs_when_free)
 527                                         claim_zero(mlx5_devx_cmd_destroy
 528                                                    (cnt->dcs_when_free));
 529                         }
 530                         mlx5_free(pool);
 531                 }
 532                 mlx5_free(sh->cmng.pools);
 533         }
 534         mng = LIST_FIRST(&sh->cmng.mem_mngs);
 535         while (mng) {
 536                 mlx5_flow_destroy_counter_stat_mem_mng(mng);
 537                 mng = LIST_FIRST(&sh->cmng.mem_mngs);
 538         }
 539         memset(&sh->cmng, 0, sizeof(sh->cmng));
 540 }
 541
 542 /* Send FLOW_AGED event if needed. */
 543 void
 544 mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh)
 545 {
 546         struct mlx5_age_info *age_info;
 547         uint32_t i;
 548
 549         for (i = 0; i < sh->max_port; i++) {
 550                 age_info = &sh->port[i].age_info;
 551                 if (!MLX5_AGE_GET(age_info, MLX5_AGE_EVENT_NEW))
 552                         continue;
 553                 if (MLX5_AGE_GET(age_info, MLX5_AGE_TRIGGER))
 554                         rte_eth_dev_callback_process
 555                                 (&rte_eth_devices[sh->port[i].devx_ih_port_id],
 556                                 RTE_ETH_EVENT_FLOW_AGED, NULL);
 557                 age_info->flags = 0;
 558         }
 559 }
 560
 561 /**
 562  * Initialize the flow resources' indexed mempool.
 563  *
 564  * @param[in] sh
 565  *   Pointer to mlx5_dev_ctx_shared object.
 566  * @param[in] sh
 567  *   Pointer to user dev config.
 568  */
 569 static void
 570 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
 571                        const struct mlx5_dev_config *config)
 572 {
 573         uint8_t i;
 574         struct mlx5_indexed_pool_config cfg;
 575
 576         for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
 577                 cfg = mlx5_ipool_cfg[i];
 578                 switch (i) {
 579                 default:
 580                         break;
 581                 /*
 582                  * Set MLX5_IPOOL_MLX5_FLOW ipool size
 583                  * according to PCI function flow configuration.
 584                  */
 585                 case MLX5_IPOOL_MLX5_FLOW:
 586                         cfg.size = config->dv_flow_en ?
 587                                 sizeof(struct mlx5_flow_handle) :
 588                                 MLX5_FLOW_HANDLE_VERBS_SIZE;
 589                         break;
 590                 }
 591                 if (config->reclaim_mode)
 592                         cfg.release_mem_en = 1;
 593                 sh->ipool[i] = mlx5_ipool_create(&cfg);
 594         }
 595 }
 596
 597 /**
 598  * Release the flow resources' indexed mempool.
 599  *
 600  * @param[in] sh
 601  *   Pointer to mlx5_dev_ctx_shared object.
 602  */
 603 static void
 604 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
 605 {
 606         uint8_t i;
 607
 608         for (i = 0; i < MLX5_IPOOL_MAX; ++i)
 609                 mlx5_ipool_destroy(sh->ipool[i]);
 610 }
 611
 612 /*
 613  * Check if dynamic flex parser for eCPRI already exists.
 614  *
 615  * @param dev
 616  *   Pointer to Ethernet device structure.
 617  *
 618  * @return
 619  *   true on exists, false on not.
 620  */
 621 bool
 622 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
 623 {
 624         struct mlx5_priv *priv = dev->data->dev_private;
 625         struct mlx5_flex_parser_profiles *prf =
 626                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 627
 628         return !!prf->obj;
 629 }
 630
 631 /*
 632  * Allocation of a flex parser for eCPRI. Once created, this parser related
 633  * resources will be held until the device is closed.
 634  *
 635  * @param dev
 636  *   Pointer to Ethernet device structure.
 637  *
 638  * @return
 639  *   0 on success, a negative errno value otherwise and rte_errno is set.
 640  */
 641 int
 642 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
 643 {
 644         struct mlx5_priv *priv = dev->data->dev_private;
 645         struct mlx5_flex_parser_profiles *prf =
 646                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 647         struct mlx5_devx_graph_node_attr node = {
 648                 .modify_field_select = 0,
 649         };
 650         uint32_t ids[8];
 651         int ret;
 652
 653         if (!priv->config.hca_attr.parse_graph_flex_node) {
 654                 DRV_LOG(ERR, "Dynamic flex parser is not supported "
 655                         "for device %s.", priv->dev_data->name);
 656                 return -ENOTSUP;
 657         }
 658         node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED;
 659         /* 8 bytes now: 4B common header + 4B message body header. */
 660         node.header_length_base_value = 0x8;
 661         /* After MAC layer: Ether / VLAN. */
 662         node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC;
 663         /* Type of compared condition should be 0xAEFE in the L2 layer. */
 664         node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI;
 665         /* Sample #0: type in common header. */
 666         node.sample[0].flow_match_sample_en = 1;
 667         /* Fixed offset. */
 668         node.sample[0].flow_match_sample_offset_mode = 0x0;
 669         /* Only the 2nd byte will be used. */
 670         node.sample[0].flow_match_sample_field_base_offset = 0x0;
 671         /* Sample #1: message payload. */
 672         node.sample[1].flow_match_sample_en = 1;
 673         /* Fixed offset. */
 674         node.sample[1].flow_match_sample_offset_mode = 0x0;
 675         /*
 676          * Only the first two bytes will be used right now, and its offset will
 677          * start after the common header that with the length of a DW(u32).
 678          */
 679         node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);
 680         prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->ctx, &node);
 681         if (!prf->obj) {
 682                 DRV_LOG(ERR, "Failed to create flex parser node object.");
 683                 return (rte_errno == 0) ? -ENODEV : -rte_errno;
 684         }
 685         prf->num = 2;
 686         ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num);
 687         if (ret) {
 688                 DRV_LOG(ERR, "Failed to query sample IDs.");
 689                 return (rte_errno == 0) ? -ENODEV : -rte_errno;
 690         }
 691         prf->offset[0] = 0x0;
 692         prf->offset[1] = sizeof(uint32_t);
 693         prf->ids[0] = ids[0];
 694         prf->ids[1] = ids[1];
 695         return 0;
 696 }
 697
 698 /*
 699  * Destroy the flex parser node, including the parser itself, input / output
 700  * arcs and DW samples. Resources could be reused then.
 701  *
 702  * @param dev
 703  *   Pointer to Ethernet device structure.
 704  */
 705 static void
 706 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
 707 {
 708         struct mlx5_priv *priv = dev->data->dev_private;
 709         struct mlx5_flex_parser_profiles *prf =
 710                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 711
 712         if (prf->obj)
 713                 mlx5_devx_cmd_destroy(prf->obj);
 714         prf->obj = NULL;
 715 }
 716
 717 /*
 718  * Allocate Rx and Tx UARs in robust fashion.
 719  * This routine handles the following UAR allocation issues:
 720  *
 721  *  - tries to allocate the UAR with the most appropriate memory
 722  *    mapping type from the ones supported by the host
 723  *
 724  *  - tries to allocate the UAR with non-NULL base address
 725  *    OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as
 726  *    UAR base address if UAR was not the first object in the UAR page.
 727  *    It caused the PMD failure and we should try to get another UAR
 728  *    till we get the first one with non-NULL base address returned.
 729  */
 730 static int
 731 mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh,
 732                      const struct mlx5_dev_config *config)
 733 {
 734         uint32_t uar_mapping, retry;
 735         int err = 0;
 736         void *base_addr;
 737
 738         for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
 739 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
 740                 /* Control the mapping type according to the settings. */
 741                 uar_mapping = (config->dbnc == MLX5_TXDB_NCACHED) ?
 742                               MLX5DV_UAR_ALLOC_TYPE_NC :
 743                               MLX5DV_UAR_ALLOC_TYPE_BF;
 744 #else
 745                 RTE_SET_USED(config);
 746                 /*
 747                  * It seems we have no way to control the memory mapping type
 748                  * for the UAR, the default "Write-Combining" type is supposed.
 749                  * The UAR initialization on queue creation queries the
 750                  * actual mapping type done by Verbs/kernel and setups the
 751                  * PMD datapath accordingly.
 752                  */
 753                 uar_mapping = 0;
 754 #endif
 755                 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->ctx, uar_mapping);
 756 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
 757                 if (!sh->tx_uar &&
 758                     uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
 759                         if (config->dbnc == MLX5_TXDB_CACHED ||
 760                             config->dbnc == MLX5_TXDB_HEURISTIC)
 761                                 DRV_LOG(WARNING, "Devarg tx_db_nc setting "
 762                                                  "is not supported by DevX");
 763                         /*
 764                          * In some environments like virtual machine
 765                          * the Write Combining mapped might be not supported
 766                          * and UAR allocation fails. We try "Non-Cached"
 767                          * mapping for the case. The tx_burst routines take
 768                          * the UAR mapping type into account on UAR setup
 769                          * on queue creation.
 770                          */
 771                         DRV_LOG(WARNING, "Failed to allocate Tx DevX UAR (BF)");
 772                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
 773                         sh->tx_uar = mlx5_glue->devx_alloc_uar
 774                                                         (sh->ctx, uar_mapping);
 775                 } else if (!sh->tx_uar &&
 776                            uar_mapping == MLX5DV_UAR_ALLOC_TYPE_NC) {
 777                         if (config->dbnc == MLX5_TXDB_NCACHED)
 778                                 DRV_LOG(WARNING, "Devarg tx_db_nc settings "
 779                                                  "is not supported by DevX");
 780                         /*
 781                          * If Verbs/kernel does not support "Non-Cached"
 782                          * try the "Write-Combining".
 783                          */
 784                         DRV_LOG(WARNING, "Failed to allocate Tx DevX UAR (NC)");
 785                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_BF;
 786                         sh->tx_uar = mlx5_glue->devx_alloc_uar
 787                                                         (sh->ctx, uar_mapping);
 788                 }
 789 #endif
 790                 if (!sh->tx_uar) {
 791                         DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (BF/NC)");
 792                         err = ENOMEM;
 793                         goto exit;
 794                 }
 795                 base_addr = mlx5_os_get_devx_uar_base_addr(sh->tx_uar);
 796                 if (base_addr)
 797                         break;
 798                 /*
 799                  * The UARs are allocated by rdma_core within the
 800                  * IB device context, on context closure all UARs
 801                  * will be freed, should be no memory/object leakage.
 802                  */
 803                 DRV_LOG(WARNING, "Retrying to allocate Tx DevX UAR");
 804                 sh->tx_uar = NULL;
 805         }
 806         /* Check whether we finally succeeded with valid UAR allocation. */
 807         if (!sh->tx_uar) {
 808                 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (NULL base)");
 809                 err = ENOMEM;
 810                 goto exit;
 811         }
 812         for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
 813                 uar_mapping = 0;
 814                 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
 815                                                         (sh->ctx, uar_mapping);
 816 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
 817                 if (!sh->devx_rx_uar &&
 818                     uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
 819                         /*
 820                          * Rx UAR is used to control interrupts only,
 821                          * should be no datapath noticeable impact,
 822                          * can try "Non-Cached" mapping safely.
 823                          */
 824                         DRV_LOG(WARNING, "Failed to allocate Rx DevX UAR (BF)");
 825                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
 826                         sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
 827                                                         (sh->ctx, uar_mapping);
 828                 }
 829 #endif
 830                 if (!sh->devx_rx_uar) {
 831                         DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (BF/NC)");
 832                         err = ENOMEM;
 833                         goto exit;
 834                 }
 835                 base_addr = mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar);
 836                 if (base_addr)
 837                         break;
 838                 /*
 839                  * The UARs are allocated by rdma_core within the
 840                  * IB device context, on context closure all UARs
 841                  * will be freed, should be no memory/object leakage.
 842                  */
 843                 DRV_LOG(WARNING, "Retrying to allocate Rx DevX UAR");
 844                 sh->devx_rx_uar = NULL;
 845         }
 846         /* Check whether we finally succeeded with valid UAR allocation. */
 847         if (!sh->devx_rx_uar) {
 848                 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (NULL base)");
 849                 err = ENOMEM;
 850         }
 851 exit:
 852         return err;
 853 }
 854
 855 /**
 856  * Allocate shared device context. If there is multiport device the
 857  * master and representors will share this context, if there is single
 858  * port dedicated device, the context will be used by only given
 859  * port due to unification.
 860  *
 861  * Routine first searches the context for the specified device name,
 862  * if found the shared context assumed and reference counter is incremented.
 863  * If no context found the new one is created and initialized with specified
 864  * device context and parameters.
 865  *
 866  * @param[in] spawn
 867  *   Pointer to the device attributes (name, port, etc).
 868  * @param[in] config
 869  *   Pointer to device configuration structure.
 870  *
 871  * @return
 872  *   Pointer to mlx5_dev_ctx_shared object on success,
 873  *   otherwise NULL and rte_errno is set.
 874  */
 875 struct mlx5_dev_ctx_shared *
 876 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
 877                            const struct mlx5_dev_config *config)
 878 {
 879         struct mlx5_dev_ctx_shared *sh;
 880         int err = 0;
 881         uint32_t i;
 882         struct mlx5_devx_tis_attr tis_attr = { 0 };
 883
 884         MLX5_ASSERT(spawn);
 885         /* Secondary process should not create the shared context. */
 886         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 887         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
 888         /* Search for IB context by device name. */
 889         LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
 890                 if (!strcmp(sh->ibdev_name,
 891                         mlx5_os_get_dev_device_name(spawn->phys_dev))) {
 892                         sh->refcnt++;
 893                         goto exit;
 894                 }
 895         }
 896         /* No device found, we have to create new shared context. */
 897         MLX5_ASSERT(spawn->max_port);
 898         sh = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
 899                          sizeof(struct mlx5_dev_ctx_shared) +
 900                          spawn->max_port *
 901                          sizeof(struct mlx5_dev_shared_port),
 902                          RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 903         if (!sh) {
 904                 DRV_LOG(ERR, "shared context allocation failure");
 905                 rte_errno  = ENOMEM;
 906                 goto exit;
 907         }
 908         err = mlx5_os_open_device(spawn, config, sh);
 909         if (!sh->ctx)
 910                 goto error;
 911         err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
 912         if (err) {
 913                 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
 914                 goto error;
 915         }
 916         sh->refcnt = 1;
 917         sh->max_port = spawn->max_port;
 918         strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
 919                 sizeof(sh->ibdev_name) - 1);
 920         strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
 921                 sizeof(sh->ibdev_path) - 1);
 922         /*
 923          * Setting port_id to max unallowed value means
 924          * there is no interrupt subhandler installed for
 925          * the given port index i.
 926          */
 927         for (i = 0; i < sh->max_port; i++) {
 928                 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
 929                 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
 930         }
 931         sh->pd = mlx5_glue->alloc_pd(sh->ctx);
 932         if (sh->pd == NULL) {
 933                 DRV_LOG(ERR, "PD allocation failure");
 934                 err = ENOMEM;
 935                 goto error;
 936         }
 937         if (sh->devx) {
 938                 /* Query the EQN for this core. */
 939                 err = mlx5_glue->devx_query_eqn(sh->ctx, 0, &sh->eqn);
 940                 if (err) {
 941                         rte_errno = errno;
 942                         DRV_LOG(ERR, "Failed to query event queue number %d.",
 943                                 rte_errno);
 944                         goto error;
 945                 }
 946                 err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
 947                 if (err) {
 948                         DRV_LOG(ERR, "Fail to extract pdn from PD");
 949                         goto error;
 950                 }
 951                 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
 952                 if (!sh->td) {
 953                         DRV_LOG(ERR, "TD allocation failure");
 954                         err = ENOMEM;
 955                         goto error;
 956                 }
 957                 tis_attr.transport_domain = sh->td->id;
 958                 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
 959                 if (!sh->tis) {
 960                         DRV_LOG(ERR, "TIS allocation failure");
 961                         err = ENOMEM;
 962                         goto error;
 963                 }
 964                 err = mlx5_alloc_rxtx_uars(sh, config);
 965                 if (err)
 966                         goto error;
 967                 MLX5_ASSERT(sh->tx_uar);
 968                 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->tx_uar));
 969
 970                 MLX5_ASSERT(sh->devx_rx_uar);
 971                 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar));
 972         }
 973 #ifndef RTE_ARCH_64
 974         /* Initialize UAR access locks for 32bit implementations. */
 975         rte_spinlock_init(&sh->uar_lock_cq);
 976         for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
 977                 rte_spinlock_init(&sh->uar_lock[i]);
 978 #endif
 979         /*
 980          * Once the device is added to the list of memory event
 981          * callback, its global MR cache table cannot be expanded
 982          * on the fly because of deadlock. If it overflows, lookup
 983          * should be done by searching MR list linearly, which is slow.
 984          *
 985          * At this point the device is not added to the memory
 986          * event list yet, context is just being created.
 987          */
 988         err = mlx5_mr_btree_init(&sh->share_cache.cache,
 989                                  MLX5_MR_BTREE_CACHE_N * 2,
 990                                  spawn->pci_dev->device.numa_node);
 991         if (err) {
 992                 err = rte_errno;
 993                 goto error;
 994         }
 995         mlx5_os_set_reg_mr_cb(&sh->share_cache.reg_mr_cb,
 996                               &sh->share_cache.dereg_mr_cb);
 997         mlx5_os_dev_shared_handler_install(sh);
 998         sh->cnt_id_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_DWORD);
 999         if (!sh->cnt_id_tbl) {
1000                 err = rte_errno;
1001                 goto error;
1002         }
1003         mlx5_flow_aging_init(sh);
1004         mlx5_flow_counters_mng_init(sh);
1005         mlx5_flow_ipool_create(sh, config);
1006         /* Add device to memory callback list. */
1007         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1008         LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
1009                          sh, mem_event_cb);
1010         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1011         /* Add context to the global device list. */
1012         LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
1013 exit:
1014         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1015         return sh;
1016 error:
1017         pthread_mutex_destroy(&sh->txpp.mutex);
1018         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1019         MLX5_ASSERT(sh);
1020         if (sh->cnt_id_tbl)
1021                 mlx5_l3t_destroy(sh->cnt_id_tbl);
1022         if (sh->tis)
1023                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1024         if (sh->td)
1025                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1026         if (sh->devx_rx_uar)
1027                 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1028         if (sh->tx_uar)
1029                 mlx5_glue->devx_free_uar(sh->tx_uar);
1030         if (sh->pd)
1031                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
1032         if (sh->ctx)
1033                 claim_zero(mlx5_glue->close_device(sh->ctx));
1034         mlx5_free(sh);
1035         MLX5_ASSERT(err > 0);
1036         rte_errno = err;
1037         return NULL;
1038 }
1039
1040 /**
1041  * Free shared IB device context. Decrement counter and if zero free
1042  * all allocated resources and close handles.
1043  *
1044  * @param[in] sh
1045  *   Pointer to mlx5_dev_ctx_shared object to free
1046  */
1047 void
1048 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
1049 {
1050         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1051 #ifdef RTE_LIBRTE_MLX5_DEBUG
1052         /* Check the object presence in the list. */
1053         struct mlx5_dev_ctx_shared *lctx;
1054
1055         LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
1056                 if (lctx == sh)
1057                         break;
1058         MLX5_ASSERT(lctx);
1059         if (lctx != sh) {
1060                 DRV_LOG(ERR, "Freeing non-existing shared IB context");
1061                 goto exit;
1062         }
1063 #endif
1064         MLX5_ASSERT(sh);
1065         MLX5_ASSERT(sh->refcnt);
1066         /* Secondary process should not free the shared context. */
1067         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1068         if (--sh->refcnt)
1069                 goto exit;
1070         /* Remove from memory callback device list. */
1071         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1072         LIST_REMOVE(sh, mem_event_cb);
1073         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1074         /* Release created Memory Regions. */
1075         mlx5_mr_release_cache(&sh->share_cache);
1076         /* Remove context from the global device list. */
1077         LIST_REMOVE(sh, next);
1078         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1079         /*
1080          *  Ensure there is no async event handler installed.
1081          *  Only primary process handles async device events.
1082          **/
1083         mlx5_flow_counters_mng_close(sh);
1084         if (sh->aso_age_mng) {
1085                 mlx5_flow_aso_age_mng_close(sh);
1086                 sh->aso_age_mng = NULL;
1087         }
1088         mlx5_flow_ipool_destroy(sh);
1089         mlx5_os_dev_shared_handler_uninstall(sh);
1090         if (sh->cnt_id_tbl) {
1091                 mlx5_l3t_destroy(sh->cnt_id_tbl);
1092                 sh->cnt_id_tbl = NULL;
1093         }
1094         if (sh->tx_uar) {
1095                 mlx5_glue->devx_free_uar(sh->tx_uar);
1096                 sh->tx_uar = NULL;
1097         }
1098         if (sh->pd)
1099                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
1100         if (sh->tis)
1101                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1102         if (sh->td)
1103                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1104         if (sh->devx_rx_uar)
1105                 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1106         if (sh->ctx)
1107                 claim_zero(mlx5_glue->close_device(sh->ctx));
1108         pthread_mutex_destroy(&sh->txpp.mutex);
1109         mlx5_free(sh);
1110         return;
1111 exit:
1112         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1113 }
1114
1115 /**
1116  * Destroy table hash list.
1117  *
1118  * @param[in] priv
1119  *   Pointer to the private device data structure.
1120  */
1121 void
1122 mlx5_free_table_hash_list(struct mlx5_priv *priv)
1123 {
1124         struct mlx5_dev_ctx_shared *sh = priv->sh;
1125
1126         if (!sh->flow_tbls)
1127                 return;
1128         mlx5_hlist_destroy(sh->flow_tbls);
1129 }
1130
1131 /**
1132  * Initialize flow table hash list and create the root tables entry
1133  * for each domain.
1134  *
1135  * @param[in] priv
1136  *   Pointer to the private device data structure.
1137  *
1138  * @return
1139  *   Zero on success, positive error code otherwise.
1140  */
1141 int
1142 mlx5_alloc_table_hash_list(struct mlx5_priv *priv __rte_unused)
1143 {
1144         int err = 0;
1145         /* Tables are only used in DV and DR modes. */
1146 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
1147         struct mlx5_dev_ctx_shared *sh = priv->sh;
1148         char s[MLX5_HLIST_NAMESIZE];
1149
1150         MLX5_ASSERT(sh);
1151         snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1152         sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE,
1153                                           0, 0, flow_dv_tbl_create_cb, NULL,
1154                                           flow_dv_tbl_remove_cb);
1155         if (!sh->flow_tbls) {
1156                 DRV_LOG(ERR, "flow tables with hash creation failed.");
1157                 err = ENOMEM;
1158                 return err;
1159         }
1160         sh->flow_tbls->ctx = sh;
1161 #ifndef HAVE_MLX5DV_DR
1162         struct rte_flow_error error;
1163         struct rte_eth_dev *dev = &rte_eth_devices[priv->dev_data->port_id];
1164
1165         /*
1166          * In case we have not DR support, the zero tables should be created
1167          * because DV expect to see them even if they cannot be created by
1168          * RDMA-CORE.
1169          */
1170         if (!flow_dv_tbl_resource_get(dev, 0, 0, 0, 0, NULL, 0, 1, &error) ||
1171             !flow_dv_tbl_resource_get(dev, 0, 1, 0, 0, NULL, 0, 1, &error) ||
1172             !flow_dv_tbl_resource_get(dev, 0, 0, 1, 0, NULL, 0, 1, &error)) {
1173                 err = ENOMEM;
1174                 goto error;
1175         }
1176         return err;
1177 error:
1178         mlx5_free_table_hash_list(priv);
1179 #endif /* HAVE_MLX5DV_DR */
1180 #endif
1181         return err;
1182 }
1183
1184 /**
1185  * Retrieve integer value from environment variable.
1186  *
1187  * @param[in] name
1188  *   Environment variable name.
1189  *
1190  * @return
1191  *   Integer value, 0 if the variable is not set.
1192  */
1193 int
1194 mlx5_getenv_int(const char *name)
1195 {
1196         const char *val = getenv(name);
1197
1198         if (val == NULL)
1199                 return 0;
1200         return atoi(val);
1201 }
1202
1203 /**
1204  * DPDK callback to add udp tunnel port
1205  *
1206  * @param[in] dev
1207  *   A pointer to eth_dev
1208  * @param[in] udp_tunnel
1209  *   A pointer to udp tunnel
1210  *
1211  * @return
1212  *   0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1213  */
1214 int
1215 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1216                          struct rte_eth_udp_tunnel *udp_tunnel)
1217 {
1218         MLX5_ASSERT(udp_tunnel != NULL);
1219         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1220             udp_tunnel->udp_port == 4789)
1221                 return 0;
1222         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1223             udp_tunnel->udp_port == 4790)
1224                 return 0;
1225         return -ENOTSUP;
1226 }
1227
1228 /**
1229  * Initialize process private data structure.
1230  *
1231  * @param dev
1232  *   Pointer to Ethernet device structure.
1233  *
1234  * @return
1235  *   0 on success, a negative errno value otherwise and rte_errno is set.
1236  */
1237 int
1238 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1239 {
1240         struct mlx5_priv *priv = dev->data->dev_private;
1241         struct mlx5_proc_priv *ppriv;
1242         size_t ppriv_size;
1243
1244         /*
1245          * UAR register table follows the process private structure. BlueFlame
1246          * registers for Tx queues are stored in the table.
1247          */
1248         ppriv_size =
1249                 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1250         ppriv = mlx5_malloc(MLX5_MEM_RTE, ppriv_size, RTE_CACHE_LINE_SIZE,
1251                             dev->device->numa_node);
1252         if (!ppriv) {
1253                 rte_errno = ENOMEM;
1254                 return -rte_errno;
1255         }
1256         ppriv->uar_table_sz = ppriv_size;
1257         dev->process_private = ppriv;
1258         return 0;
1259 }
1260
1261 /**
1262  * Un-initialize process private data structure.
1263  *
1264  * @param dev
1265  *   Pointer to Ethernet device structure.
1266  */
1267 static void
1268 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1269 {
1270         if (!dev->process_private)
1271                 return;
1272         mlx5_free(dev->process_private);
1273         dev->process_private = NULL;
1274 }
1275
1276 /**
1277  * DPDK callback to close the device.
1278  *
1279  * Destroy all queues and objects, free memory.
1280  *
1281  * @param dev
1282  *   Pointer to Ethernet device structure.
1283  */
1284 int
1285 mlx5_dev_close(struct rte_eth_dev *dev)
1286 {
1287         struct mlx5_priv *priv = dev->data->dev_private;
1288         unsigned int i;
1289         int ret;
1290
1291         if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1292                 /* Check if process_private released. */
1293                 if (!dev->process_private)
1294                         return 0;
1295                 mlx5_tx_uar_uninit_secondary(dev);
1296                 mlx5_proc_priv_uninit(dev);
1297                 rte_eth_dev_release_port(dev);
1298                 return 0;
1299         }
1300         if (!priv->sh)
1301                 return 0;
1302         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1303                 dev->data->port_id,
1304                 ((priv->sh->ctx != NULL) ?
1305                 mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
1306         /*
1307          * If default mreg copy action is removed at the stop stage,
1308          * the search will return none and nothing will be done anymore.
1309          */
1310         mlx5_flow_stop_default(dev);
1311         mlx5_traffic_disable(dev);
1312         /*
1313          * If all the flows are already flushed in the device stop stage,
1314          * then this will return directly without any action.
1315          */
1316         mlx5_flow_list_flush(dev, &priv->flows, true);
1317         mlx5_shared_action_flush(dev);
1318         mlx5_flow_meter_flush(dev, NULL);
1319         /* Prevent crashes when queues are still in use. */
1320         dev->rx_pkt_burst = removed_rx_burst;
1321         dev->tx_pkt_burst = removed_tx_burst;
1322         rte_wmb();
1323         /* Disable datapath on secondary process. */
1324         mlx5_mp_os_req_stop_rxtx(dev);
1325         /* Free the eCPRI flex parser resource. */
1326         mlx5_flex_parser_ecpri_release(dev);
1327         if (priv->rxqs != NULL) {
1328                 /* XXX race condition if mlx5_rx_burst() is still running. */
1329                 usleep(1000);
1330                 for (i = 0; (i != priv->rxqs_n); ++i)
1331                         mlx5_rxq_release(dev, i);
1332                 priv->rxqs_n = 0;
1333                 priv->rxqs = NULL;
1334         }
1335         if (priv->txqs != NULL) {
1336                 /* XXX race condition if mlx5_tx_burst() is still running. */
1337                 usleep(1000);
1338                 for (i = 0; (i != priv->txqs_n); ++i)
1339                         mlx5_txq_release(dev, i);
1340                 priv->txqs_n = 0;
1341                 priv->txqs = NULL;
1342         }
1343         mlx5_proc_priv_uninit(dev);
1344         if (priv->drop_queue.hrxq)
1345                 mlx5_drop_action_destroy(dev);
1346         if (priv->mreg_cp_tbl)
1347                 mlx5_hlist_destroy(priv->mreg_cp_tbl);
1348         mlx5_mprq_free_mp(dev);
1349         mlx5_os_free_shared_dr(priv);
1350         if (priv->rss_conf.rss_key != NULL)
1351                 mlx5_free(priv->rss_conf.rss_key);
1352         if (priv->reta_idx != NULL)
1353                 mlx5_free(priv->reta_idx);
1354         if (priv->config.vf)
1355                 mlx5_os_mac_addr_flush(dev);
1356         if (priv->nl_socket_route >= 0)
1357                 close(priv->nl_socket_route);
1358         if (priv->nl_socket_rdma >= 0)
1359                 close(priv->nl_socket_rdma);
1360         if (priv->vmwa_context)
1361                 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1362         ret = mlx5_hrxq_verify(dev);
1363         if (ret)
1364                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1365                         dev->data->port_id);
1366         ret = mlx5_ind_table_obj_verify(dev);
1367         if (ret)
1368                 DRV_LOG(WARNING, "port %u some indirection table still remain",
1369                         dev->data->port_id);
1370         ret = mlx5_rxq_obj_verify(dev);
1371         if (ret)
1372                 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1373                         dev->data->port_id);
1374         ret = mlx5_rxq_verify(dev);
1375         if (ret)
1376                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1377                         dev->data->port_id);
1378         ret = mlx5_txq_obj_verify(dev);
1379         if (ret)
1380                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1381                         dev->data->port_id);
1382         ret = mlx5_txq_verify(dev);
1383         if (ret)
1384                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1385                         dev->data->port_id);
1386         ret = mlx5_flow_verify(dev);
1387         if (ret)
1388                 DRV_LOG(WARNING, "port %u some flows still remain",
1389                         dev->data->port_id);
1390         mlx5_cache_list_destroy(&priv->hrxqs);
1391         /*
1392          * Free the shared context in last turn, because the cleanup
1393          * routines above may use some shared fields, like
1394          * mlx5_os_mac_addr_flush() uses ibdev_path for retrieveing
1395          * ifindex if Netlink fails.
1396          */
1397         mlx5_free_shared_dev_ctx(priv->sh);
1398         if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1399                 unsigned int c = 0;
1400                 uint16_t port_id;
1401
1402                 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1403                         struct mlx5_priv *opriv =
1404                                 rte_eth_devices[port_id].data->dev_private;
1405
1406                         if (!opriv ||
1407                             opriv->domain_id != priv->domain_id ||
1408                             &rte_eth_devices[port_id] == dev)
1409                                 continue;
1410                         ++c;
1411                         break;
1412                 }
1413                 if (!c)
1414                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1415         }
1416         memset(priv, 0, sizeof(*priv));
1417         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1418         /*
1419          * Reset mac_addrs to NULL such that it is not freed as part of
1420          * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1421          * it is freed when dev_private is freed.
1422          */
1423         dev->data->mac_addrs = NULL;
1424         return 0;
1425 }
1426
1427 /**
1428  * Verify and store value for device argument.
1429  *
1430  * @param[in] key
1431  *   Key argument to verify.
1432  * @param[in] val
1433  *   Value associated with key.
1434  * @param opaque
1435  *   User data.
1436  *
1437  * @return
1438  *   0 on success, a negative errno value otherwise and rte_errno is set.
1439  */
1440 static int
1441 mlx5_args_check(const char *key, const char *val, void *opaque)
1442 {
1443         struct mlx5_dev_config *config = opaque;
1444         unsigned long mod;
1445         signed long tmp;
1446
1447         /* No-op, port representors are processed in mlx5_dev_spawn(). */
1448         if (!strcmp(MLX5_REPRESENTOR, key))
1449                 return 0;
1450         errno = 0;
1451         tmp = strtol(val, NULL, 0);
1452         if (errno) {
1453                 rte_errno = errno;
1454                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1455                 return -rte_errno;
1456         }
1457         if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
1458                 /* Negative values are acceptable for some keys only. */
1459                 rte_errno = EINVAL;
1460                 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
1461                 return -rte_errno;
1462         }
1463         mod = tmp >= 0 ? tmp : -tmp;
1464         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1465                 if (tmp > MLX5_CQE_RESP_FORMAT_L34H_STRIDX) {
1466                         DRV_LOG(ERR, "invalid CQE compression "
1467                                      "format parameter");
1468                         rte_errno = EINVAL;
1469                         return -rte_errno;
1470                 }
1471                 config->cqe_comp = !!tmp;
1472                 config->cqe_comp_fmt = tmp;
1473         } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
1474                 config->cqe_pad = !!tmp;
1475         } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1476                 config->hw_padding = !!tmp;
1477         } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1478                 config->mprq.enabled = !!tmp;
1479         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1480                 config->mprq.stride_num_n = tmp;
1481         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1482                 config->mprq.stride_size_n = tmp;
1483         } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1484                 config->mprq.max_memcpy_len = tmp;
1485         } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1486                 config->mprq.min_rxqs_num = tmp;
1487         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1488                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1489                                  " converted to txq_inline_max", key);
1490                 config->txq_inline_max = tmp;
1491         } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1492                 config->txq_inline_max = tmp;
1493         } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1494                 config->txq_inline_min = tmp;
1495         } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1496                 config->txq_inline_mpw = tmp;
1497         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1498                 config->txqs_inline = tmp;
1499         } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1500                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1501         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1502                 config->mps = !!tmp;
1503         } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1504                 if (tmp != MLX5_TXDB_CACHED &&
1505                     tmp != MLX5_TXDB_NCACHED &&
1506                     tmp != MLX5_TXDB_HEURISTIC) {
1507                         DRV_LOG(ERR, "invalid Tx doorbell "
1508                                      "mapping parameter");
1509                         rte_errno = EINVAL;
1510                         return -rte_errno;
1511                 }
1512                 config->dbnc = tmp;
1513         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1514                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1515         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1516                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1517                                  " converted to txq_inline_mpw", key);
1518                 config->txq_inline_mpw = tmp;
1519         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1520                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1521         } else if (strcmp(MLX5_TX_PP, key) == 0) {
1522                 if (!mod) {
1523                         DRV_LOG(ERR, "Zero Tx packet pacing parameter");
1524                         rte_errno = EINVAL;
1525                         return -rte_errno;
1526                 }
1527                 config->tx_pp = tmp;
1528         } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
1529                 config->tx_skew = tmp;
1530         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1531                 config->rx_vec_en = !!tmp;
1532         } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1533                 config->l3_vxlan_en = !!tmp;
1534         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1535                 config->vf_nl_en = !!tmp;
1536         } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1537                 config->dv_esw_en = !!tmp;
1538         } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1539                 config->dv_flow_en = !!tmp;
1540         } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1541                 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1542                     tmp != MLX5_XMETA_MODE_META16 &&
1543                     tmp != MLX5_XMETA_MODE_META32 &&
1544                     tmp != MLX5_XMETA_MODE_MISS_INFO) {
1545                         DRV_LOG(ERR, "invalid extensive "
1546                                      "metadata parameter");
1547                         rte_errno = EINVAL;
1548                         return -rte_errno;
1549                 }
1550                 if (tmp != MLX5_XMETA_MODE_MISS_INFO)
1551                         config->dv_xmeta_en = tmp;
1552                 else
1553                         config->dv_miss_info = 1;
1554         } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
1555                 config->lacp_by_user = !!tmp;
1556         } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1557                 config->mr_ext_memseg_en = !!tmp;
1558         } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1559                 config->max_dump_files_num = tmp;
1560         } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1561                 config->lro.timeout = tmp;
1562         } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1563                 DRV_LOG(DEBUG, "class argument is %s.", val);
1564         } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1565                 config->log_hp_size = tmp;
1566         } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1567                 if (tmp != MLX5_RCM_NONE &&
1568                     tmp != MLX5_RCM_LIGHT &&
1569                     tmp != MLX5_RCM_AGGR) {
1570                         DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1571                         rte_errno = EINVAL;
1572                         return -rte_errno;
1573                 }
1574                 config->reclaim_mode = tmp;
1575         } else if (strcmp(MLX5_SYS_MEM_EN, key) == 0) {
1576                 config->sys_mem_en = !!tmp;
1577         } else if (strcmp(MLX5_DECAP_EN, key) == 0) {
1578                 config->decap_en = !!tmp;
1579         } else {
1580                 DRV_LOG(WARNING, "%s: unknown parameter", key);
1581                 rte_errno = EINVAL;
1582                 return -rte_errno;
1583         }
1584         return 0;
1585 }
1586
1587 /**
1588  * Parse device parameters.
1589  *
1590  * @param config
1591  *   Pointer to device configuration structure.
1592  * @param devargs
1593  *   Device arguments structure.
1594  *
1595  * @return
1596  *   0 on success, a negative errno value otherwise and rte_errno is set.
1597  */
1598 int
1599 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1600 {
1601         const char **params = (const char *[]){
1602                 MLX5_RXQ_CQE_COMP_EN,
1603                 MLX5_RXQ_CQE_PAD_EN,
1604                 MLX5_RXQ_PKT_PAD_EN,
1605                 MLX5_RX_MPRQ_EN,
1606                 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1607                 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1608                 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1609                 MLX5_RXQS_MIN_MPRQ,
1610                 MLX5_TXQ_INLINE,
1611                 MLX5_TXQ_INLINE_MIN,
1612                 MLX5_TXQ_INLINE_MAX,
1613                 MLX5_TXQ_INLINE_MPW,
1614                 MLX5_TXQS_MIN_INLINE,
1615                 MLX5_TXQS_MAX_VEC,
1616                 MLX5_TXQ_MPW_EN,
1617                 MLX5_TXQ_MPW_HDR_DSEG_EN,
1618                 MLX5_TXQ_MAX_INLINE_LEN,
1619                 MLX5_TX_DB_NC,
1620                 MLX5_TX_PP,
1621                 MLX5_TX_SKEW,
1622                 MLX5_TX_VEC_EN,
1623                 MLX5_RX_VEC_EN,
1624                 MLX5_L3_VXLAN_EN,
1625                 MLX5_VF_NL_EN,
1626                 MLX5_DV_ESW_EN,
1627                 MLX5_DV_FLOW_EN,
1628                 MLX5_DV_XMETA_EN,
1629                 MLX5_LACP_BY_USER,
1630                 MLX5_MR_EXT_MEMSEG_EN,
1631                 MLX5_REPRESENTOR,
1632                 MLX5_MAX_DUMP_FILES_NUM,
1633                 MLX5_LRO_TIMEOUT_USEC,
1634                 MLX5_CLASS_ARG_NAME,
1635                 MLX5_HP_BUF_SIZE,
1636                 MLX5_RECLAIM_MEM,
1637                 MLX5_SYS_MEM_EN,
1638                 MLX5_DECAP_EN,
1639                 NULL,
1640         };
1641         struct rte_kvargs *kvlist;
1642         int ret = 0;
1643         int i;
1644
1645         if (devargs == NULL)
1646                 return 0;
1647         /* Following UGLY cast is done to pass checkpatch. */
1648         kvlist = rte_kvargs_parse(devargs->args, params);
1649         if (kvlist == NULL) {
1650                 rte_errno = EINVAL;
1651                 return -rte_errno;
1652         }
1653         /* Process parameters. */
1654         for (i = 0; (params[i] != NULL); ++i) {
1655                 if (rte_kvargs_count(kvlist, params[i])) {
1656                         ret = rte_kvargs_process(kvlist, params[i],
1657                                                  mlx5_args_check, config);
1658                         if (ret) {
1659                                 rte_errno = EINVAL;
1660                                 rte_kvargs_free(kvlist);
1661                                 return -rte_errno;
1662                         }
1663                 }
1664         }
1665         rte_kvargs_free(kvlist);
1666         return 0;
1667 }
1668
1669 /**
1670  * Configures the minimal amount of data to inline into WQE
1671  * while sending packets.
1672  *
1673  * - the txq_inline_min has the maximal priority, if this
1674  *   key is specified in devargs
1675  * - if DevX is enabled the inline mode is queried from the
1676  *   device (HCA attributes and NIC vport context if needed).
1677  * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1678  *   and none (0 bytes) for other NICs
1679  *
1680  * @param spawn
1681  *   Verbs device parameters (name, port, switch_info) to spawn.
1682  * @param config
1683  *   Device configuration parameters.
1684  */
1685 void
1686 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1687                     struct mlx5_dev_config *config)
1688 {
1689         if (config->txq_inline_min != MLX5_ARG_UNSET) {
1690                 /* Application defines size of inlined data explicitly. */
1691                 switch (spawn->pci_dev->id.device_id) {
1692                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1693                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1694                         if (config->txq_inline_min <
1695                                        (int)MLX5_INLINE_HSIZE_L2) {
1696                                 DRV_LOG(DEBUG,
1697                                         "txq_inline_mix aligned to minimal"
1698                                         " ConnectX-4 required value %d",
1699                                         (int)MLX5_INLINE_HSIZE_L2);
1700                                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1701                         }
1702                         break;
1703                 }
1704                 goto exit;
1705         }
1706         if (config->hca_attr.eth_net_offloads) {
1707                 /* We have DevX enabled, inline mode queried successfully. */
1708                 switch (config->hca_attr.wqe_inline_mode) {
1709                 case MLX5_CAP_INLINE_MODE_L2:
1710                         /* outer L2 header must be inlined. */
1711                         config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1712                         goto exit;
1713                 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1714                         /* No inline data are required by NIC. */
1715                         config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1716                         config->hw_vlan_insert =
1717                                 config->hca_attr.wqe_vlan_insert;
1718                         DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1719                         goto exit;
1720                 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1721                         /* inline mode is defined by NIC vport context. */
1722                         if (!config->hca_attr.eth_virt)
1723                                 break;
1724                         switch (config->hca_attr.vport_inline_mode) {
1725                         case MLX5_INLINE_MODE_NONE:
1726                                 config->txq_inline_min =
1727                                         MLX5_INLINE_HSIZE_NONE;
1728                                 goto exit;
1729                         case MLX5_INLINE_MODE_L2:
1730                                 config->txq_inline_min =
1731                                         MLX5_INLINE_HSIZE_L2;
1732                                 goto exit;
1733                         case MLX5_INLINE_MODE_IP:
1734                                 config->txq_inline_min =
1735                                         MLX5_INLINE_HSIZE_L3;
1736                                 goto exit;
1737                         case MLX5_INLINE_MODE_TCP_UDP:
1738                                 config->txq_inline_min =
1739                                         MLX5_INLINE_HSIZE_L4;
1740                                 goto exit;
1741                         case MLX5_INLINE_MODE_INNER_L2:
1742                                 config->txq_inline_min =
1743                                         MLX5_INLINE_HSIZE_INNER_L2;
1744                                 goto exit;
1745                         case MLX5_INLINE_MODE_INNER_IP:
1746                                 config->txq_inline_min =
1747                                         MLX5_INLINE_HSIZE_INNER_L3;
1748                                 goto exit;
1749                         case MLX5_INLINE_MODE_INNER_TCP_UDP:
1750                                 config->txq_inline_min =
1751                                         MLX5_INLINE_HSIZE_INNER_L4;
1752                                 goto exit;
1753                         }
1754                 }
1755         }
1756         /*
1757          * We get here if we are unable to deduce
1758          * inline data size with DevX. Try PCI ID
1759          * to determine old NICs.
1760          */
1761         switch (spawn->pci_dev->id.device_id) {
1762         case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1763         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1764         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
1765         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1766                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1767                 config->hw_vlan_insert = 0;
1768                 break;
1769         case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
1770         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1771         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
1772         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1773                 /*
1774                  * These NICs support VLAN insertion from WQE and
1775                  * report the wqe_vlan_insert flag. But there is the bug
1776                  * and PFC control may be broken, so disable feature.
1777                  */
1778                 config->hw_vlan_insert = 0;
1779                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1780                 break;
1781         default:
1782                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1783                 break;
1784         }
1785 exit:
1786         DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
1787 }
1788
1789 /**
1790  * Configures the metadata mask fields in the shared context.
1791  *
1792  * @param [in] dev
1793  *   Pointer to Ethernet device.
1794  */
1795 void
1796 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
1797 {
1798         struct mlx5_priv *priv = dev->data->dev_private;
1799         struct mlx5_dev_ctx_shared *sh = priv->sh;
1800         uint32_t meta, mark, reg_c0;
1801
1802         reg_c0 = ~priv->vport_meta_mask;
1803         switch (priv->config.dv_xmeta_en) {
1804         case MLX5_XMETA_MODE_LEGACY:
1805                 meta = UINT32_MAX;
1806                 mark = MLX5_FLOW_MARK_MASK;
1807                 break;
1808         case MLX5_XMETA_MODE_META16:
1809                 meta = reg_c0 >> rte_bsf32(reg_c0);
1810                 mark = MLX5_FLOW_MARK_MASK;
1811                 break;
1812         case MLX5_XMETA_MODE_META32:
1813                 meta = UINT32_MAX;
1814                 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
1815                 break;
1816         default:
1817                 meta = 0;
1818                 mark = 0;
1819                 MLX5_ASSERT(false);
1820                 break;
1821         }
1822         if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
1823                 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
1824                                  sh->dv_mark_mask, mark);
1825         else
1826                 sh->dv_mark_mask = mark;
1827         if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
1828                 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
1829                                  sh->dv_meta_mask, meta);
1830         else
1831                 sh->dv_meta_mask = meta;
1832         if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
1833                 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
1834                                  sh->dv_meta_mask, reg_c0);
1835         else
1836                 sh->dv_regc0_mask = reg_c0;
1837         DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
1838         DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
1839         DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
1840         DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
1841 }
1842
1843 int
1844 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
1845 {
1846         static const char *const dynf_names[] = {
1847                 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
1848                 RTE_MBUF_DYNFLAG_METADATA_NAME,
1849                 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
1850         };
1851         unsigned int i;
1852
1853         if (n < RTE_DIM(dynf_names))
1854                 return -ENOMEM;
1855         for (i = 0; i < RTE_DIM(dynf_names); i++) {
1856                 if (names[i] == NULL)
1857                         return -EINVAL;
1858                 strcpy(names[i], dynf_names[i]);
1859         }
1860         return RTE_DIM(dynf_names);
1861 }
1862
1863 /**
1864  * Comparison callback to sort device data.
1865  *
1866  * This is meant to be used with qsort().
1867  *
1868  * @param a[in]
1869  *   Pointer to pointer to first data object.
1870  * @param b[in]
1871  *   Pointer to pointer to second data object.
1872  *
1873  * @return
1874  *   0 if both objects are equal, less than 0 if the first argument is less
1875  *   than the second, greater than 0 otherwise.
1876  */
1877 int
1878 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
1879                               struct mlx5_dev_config *config)
1880 {
1881         struct mlx5_dev_ctx_shared *sh = priv->sh;
1882         struct mlx5_dev_config *sh_conf = NULL;
1883         uint16_t port_id;
1884
1885         MLX5_ASSERT(sh);
1886         /* Nothing to compare for the single/first device. */
1887         if (sh->refcnt == 1)
1888                 return 0;
1889         /* Find the device with shared context. */
1890         MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1891                 struct mlx5_priv *opriv =
1892                         rte_eth_devices[port_id].data->dev_private;
1893
1894                 if (opriv && opriv != priv && opriv->sh == sh) {
1895                         sh_conf = &opriv->config;
1896                         break;
1897                 }
1898         }
1899         if (!sh_conf)
1900                 return 0;
1901         if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
1902                 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
1903                              " for shared %s context", sh->ibdev_name);
1904                 rte_errno = EINVAL;
1905                 return rte_errno;
1906         }
1907         if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
1908                 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
1909                              " for shared %s context", sh->ibdev_name);
1910                 rte_errno = EINVAL;
1911                 return rte_errno;
1912         }
1913         return 0;
1914 }
1915
1916 /**
1917  * Look for the ethernet device belonging to mlx5 driver.
1918  *
1919  * @param[in] port_id
1920  *   port_id to start looking for device.
1921  * @param[in] pci_dev
1922  *   Pointer to the hint PCI device. When device is being probed
1923  *   the its siblings (master and preceding representors might
1924  *   not have assigned driver yet (because the mlx5_os_pci_probe()
1925  *   is not completed yet, for this case match on hint PCI
1926  *   device may be used to detect sibling device.
1927  *
1928  * @return
1929  *   port_id of found device, RTE_MAX_ETHPORT if not found.
1930  */
1931 uint16_t
1932 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
1933 {
1934         while (port_id < RTE_MAX_ETHPORTS) {
1935                 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
1936
1937                 if (dev->state != RTE_ETH_DEV_UNUSED &&
1938                     dev->device &&
1939                     (dev->device == &pci_dev->device ||
1940                      (dev->device->driver &&
1941                      dev->device->driver->name &&
1942                      !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
1943                         break;
1944                 port_id++;
1945         }
1946         if (port_id >= RTE_MAX_ETHPORTS)
1947                 return RTE_MAX_ETHPORTS;
1948         return port_id;
1949 }
1950
1951 /**
1952  * DPDK callback to remove a PCI device.
1953  *
1954  * This function removes all Ethernet devices belong to a given PCI device.
1955  *
1956  * @param[in] pci_dev
1957  *   Pointer to the PCI device.
1958  *
1959  * @return
1960  *   0 on success, the function cannot fail.
1961  */
1962 static int
1963 mlx5_pci_remove(struct rte_pci_device *pci_dev)
1964 {
1965         uint16_t port_id;
1966         int ret = 0;
1967
1968         RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
1969                 /*
1970                  * mlx5_dev_close() is not registered to secondary process,
1971                  * call the close function explicitly for secondary process.
1972                  */
1973                 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
1974                         ret |= mlx5_dev_close(&rte_eth_devices[port_id]);
1975                 else
1976                         ret |= rte_eth_dev_close(port_id);
1977         }
1978         return ret == 0 ? 0 : -EIO;
1979 }
1980
1981 static const struct rte_pci_id mlx5_pci_id_map[] = {
1982         {
1983                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1984                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
1985         },
1986         {
1987                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1988                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
1989         },
1990         {
1991                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1992                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
1993         },
1994         {
1995                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1996                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
1997         },
1998         {
1999                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2000                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
2001         },
2002         {
2003                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2004                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
2005         },
2006         {
2007                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2008                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
2009         },
2010         {
2011                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2012                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
2013         },
2014         {
2015                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2016                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
2017         },
2018         {
2019                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2020                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
2021         },
2022         {
2023                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2024                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
2025         },
2026         {
2027                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2028                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
2029         },
2030         {
2031                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2032                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
2033         },
2034         {
2035                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2036                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF)
2037         },
2038         {
2039                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2040                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
2041         },
2042         {
2043                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2044                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
2045         },
2046         {
2047                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2048                                 PCI_DEVICE_ID_MELLANOX_CONNECTX7)
2049         },
2050         {
2051                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2052                                 PCI_DEVICE_ID_MELLANOX_CONNECTX7BF)
2053         },
2054         {
2055                 .vendor_id = 0
2056         }
2057 };
2058
2059 static struct mlx5_pci_driver mlx5_driver = {
2060         .driver_class = MLX5_CLASS_NET,
2061         .pci_driver = {
2062                 .driver = {
2063                         .name = MLX5_DRIVER_NAME,
2064                 },
2065                 .id_table = mlx5_pci_id_map,
2066                 .probe = mlx5_os_pci_probe,
2067                 .remove = mlx5_pci_remove,
2068                 .dma_map = mlx5_dma_map,
2069                 .dma_unmap = mlx5_dma_unmap,
2070                 .drv_flags = PCI_DRV_FLAGS,
2071         },
2072 };
2073
2074 /* Initialize driver log type. */
2075 RTE_LOG_REGISTER(mlx5_logtype, pmd.net.mlx5, NOTICE)
2076
2077 /**
2078  * Driver initialization routine.
2079  */
2080 RTE_INIT(rte_mlx5_pmd_init)
2081 {
2082         mlx5_common_init();
2083         /* Build the static tables for Verbs conversion. */
2084         mlx5_set_ptype_table();
2085         mlx5_set_cksum_table();
2086         mlx5_set_swp_types_table();
2087         if (mlx5_glue)
2088                 mlx5_pci_driver_register(&mlx5_driver);
2089 }
2090
2091 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
2092 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
2093 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");