1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
13 #include <rte_malloc.h>
14 #include <rte_ethdev_driver.h>
15 #include <rte_ethdev_pci.h>
17 #include <rte_bus_pci.h>
18 #include <rte_common.h>
19 #include <rte_kvargs.h>
20 #include <rte_rwlock.h>
21 #include <rte_spinlock.h>
22 #include <rte_string_fns.h>
23 #include <rte_alarm.h>
24 #include <rte_cycles.h>
26 #include <mlx5_glue.h>
27 #include <mlx5_devx_cmds.h>
28 #include <mlx5_common.h>
29 #include <mlx5_common_os.h>
30 #include <mlx5_common_mp.h>
31 #include <mlx5_common_pci.h>
32 #include <mlx5_malloc.h>
34 #include "mlx5_defs.h"
36 #include "mlx5_utils.h"
37 #include "mlx5_rxtx.h"
38 #include "mlx5_autoconf.h"
40 #include "mlx5_flow.h"
41 #include "mlx5_flow_os.h"
42 #include "rte_pmd_mlx5.h"
44 /* Device parameter to enable RX completion queue compression. */
45 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
47 /* Device parameter to enable padding Rx packet to cacheline size. */
48 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
50 /* Device parameter to enable Multi-Packet Rx queue. */
51 #define MLX5_RX_MPRQ_EN "mprq_en"
53 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
54 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
56 /* Device parameter to configure log 2 of the stride size for MPRQ. */
57 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
59 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
60 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
62 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
63 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
65 /* Device parameter to configure inline send. Deprecated, ignored.*/
66 #define MLX5_TXQ_INLINE "txq_inline"
68 /* Device parameter to limit packet size to inline with ordinary SEND. */
69 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
71 /* Device parameter to configure minimal data size to inline. */
72 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
74 /* Device parameter to limit packet size to inline with Enhanced MPW. */
75 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
78 * Device parameter to configure the number of TX queues threshold for
79 * enabling inline send.
81 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
84 * Device parameter to configure the number of TX queues threshold for
85 * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
87 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
89 /* Device parameter to enable multi-packet send WQEs. */
90 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
93 * Device parameter to force doorbell register mapping
94 * to non-cahed region eliminating the extra write memory barrier.
96 #define MLX5_TX_DB_NC "tx_db_nc"
99 * Device parameter to include 2 dsegs in the title WQEBB.
100 * Deprecated, ignored.
102 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
105 * Device parameter to limit the size of inlining packet.
106 * Deprecated, ignored.
108 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
111 * Device parameter to enable Tx scheduling on timestamps
112 * and specify the packet pacing granularity in nanoseconds.
114 #define MLX5_TX_PP "tx_pp"
117 * Device parameter to specify skew in nanoseconds on Tx datapath,
118 * it represents the time between SQ start WQE processing and
119 * appearing actual packet data on the wire.
121 #define MLX5_TX_SKEW "tx_skew"
124 * Device parameter to enable hardware Tx vector.
125 * Deprecated, ignored (no vectorized Tx routines anymore).
127 #define MLX5_TX_VEC_EN "tx_vec_en"
129 /* Device parameter to enable hardware Rx vector. */
130 #define MLX5_RX_VEC_EN "rx_vec_en"
132 /* Allow L3 VXLAN flow creation. */
133 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
135 /* Activate DV E-Switch flow steering. */
136 #define MLX5_DV_ESW_EN "dv_esw_en"
138 /* Activate DV flow steering. */
139 #define MLX5_DV_FLOW_EN "dv_flow_en"
141 /* Enable extensive flow metadata support. */
142 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
144 /* Device parameter to let the user manage the lacp traffic of bonded device */
145 #define MLX5_LACP_BY_USER "lacp_by_user"
147 /* Activate Netlink support in VF mode. */
148 #define MLX5_VF_NL_EN "vf_nl_en"
150 /* Enable extending memsegs when creating a MR. */
151 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
153 /* Select port representors to instantiate. */
154 #define MLX5_REPRESENTOR "representor"
156 /* Device parameter to configure the maximum number of dump files per queue. */
157 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
159 /* Configure timeout of LRO session (in microseconds). */
160 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
163 * Device parameter to configure the total data buffer size for a single
164 * hairpin queue (logarithm value).
166 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
168 /* Flow memory reclaim mode. */
169 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
171 /* The default memory allocator used in PMD. */
172 #define MLX5_SYS_MEM_EN "sys_mem_en"
173 /* Decap will be used or not. */
174 #define MLX5_DECAP_EN "decap_en"
176 /* Shared memory between primary and secondary processes. */
177 struct mlx5_shared_data *mlx5_shared_data;
179 /** Driver-specific log messages type. */
182 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
183 LIST_HEAD_INITIALIZER();
184 static pthread_mutex_t mlx5_dev_ctx_list_mutex;
185 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
186 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
187 [MLX5_IPOOL_DECAP_ENCAP] = {
188 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
194 .malloc = mlx5_malloc,
196 .type = "mlx5_encap_decap_ipool",
198 [MLX5_IPOOL_PUSH_VLAN] = {
199 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
205 .malloc = mlx5_malloc,
207 .type = "mlx5_push_vlan_ipool",
210 .size = sizeof(struct mlx5_flow_dv_tag_resource),
216 .malloc = mlx5_malloc,
218 .type = "mlx5_tag_ipool",
220 [MLX5_IPOOL_PORT_ID] = {
221 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
227 .malloc = mlx5_malloc,
229 .type = "mlx5_port_id_ipool",
231 [MLX5_IPOOL_JUMP] = {
232 .size = sizeof(struct mlx5_flow_tbl_data_entry),
238 .malloc = mlx5_malloc,
240 .type = "mlx5_jump_ipool",
242 [MLX5_IPOOL_SAMPLE] = {
243 .size = sizeof(struct mlx5_flow_dv_sample_resource),
249 .malloc = mlx5_malloc,
251 .type = "mlx5_sample_ipool",
253 [MLX5_IPOOL_DEST_ARRAY] = {
254 .size = sizeof(struct mlx5_flow_dv_dest_array_resource),
260 .malloc = mlx5_malloc,
262 .type = "mlx5_dest_array_ipool",
264 [MLX5_IPOOL_TUNNEL_ID] = {
265 .size = sizeof(struct mlx5_flow_tunnel),
266 .trunk_size = MLX5_MAX_TUNNELS,
269 .type = "mlx5_tunnel_offload",
271 [MLX5_IPOOL_TNL_TBL_ID] = {
274 .type = "mlx5_flow_tnl_tbl_ipool",
278 .size = sizeof(struct mlx5_flow_meter),
284 .malloc = mlx5_malloc,
286 .type = "mlx5_meter_ipool",
289 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
295 .malloc = mlx5_malloc,
297 .type = "mlx5_mcp_ipool",
299 [MLX5_IPOOL_HRXQ] = {
300 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
306 .malloc = mlx5_malloc,
308 .type = "mlx5_hrxq_ipool",
310 [MLX5_IPOOL_MLX5_FLOW] = {
312 * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
313 * It set in run time according to PCI function configuration.
321 .malloc = mlx5_malloc,
323 .type = "mlx5_flow_handle_ipool",
325 [MLX5_IPOOL_RTE_FLOW] = {
326 .size = sizeof(struct rte_flow),
330 .malloc = mlx5_malloc,
332 .type = "rte_flow_ipool",
334 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID] = {
337 .type = "mlx5_flow_rss_id_ipool",
339 [MLX5_IPOOL_RSS_SHARED_ACTIONS] = {
340 .size = sizeof(struct mlx5_shared_action_rss),
346 .malloc = mlx5_malloc,
348 .type = "mlx5_shared_action_rss",
353 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
354 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
356 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
359 * Initialize the ASO aging management structure.
362 * Pointer to mlx5_dev_ctx_shared object to free
365 * 0 on success, a negative errno value otherwise and rte_errno is set.
368 mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh)
374 sh->aso_age_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->aso_age_mng),
375 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
376 if (!sh->aso_age_mng) {
377 DRV_LOG(ERR, "aso_age_mng allocation was failed.");
381 err = mlx5_aso_queue_init(sh);
383 mlx5_free(sh->aso_age_mng);
386 rte_spinlock_init(&sh->aso_age_mng->resize_sl);
387 rte_spinlock_init(&sh->aso_age_mng->free_sl);
388 LIST_INIT(&sh->aso_age_mng->free);
393 * Close and release all the resources of the ASO aging management structure.
396 * Pointer to mlx5_dev_ctx_shared object to free.
399 mlx5_flow_aso_age_mng_close(struct mlx5_dev_ctx_shared *sh)
403 mlx5_aso_queue_stop(sh);
404 mlx5_aso_queue_uninit(sh);
405 if (sh->aso_age_mng->pools) {
406 struct mlx5_aso_age_pool *pool;
408 for (i = 0; i < sh->aso_age_mng->next; ++i) {
409 pool = sh->aso_age_mng->pools[i];
410 claim_zero(mlx5_devx_cmd_destroy
411 (pool->flow_hit_aso_obj));
412 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j)
413 if (pool->actions[j].dr_action)
415 (mlx5_flow_os_destroy_flow_action
416 (pool->actions[j].dr_action));
419 mlx5_free(sh->aso_age_mng->pools);
421 mlx5_free(sh->aso_age_mng);
425 * Initialize the shared aging list information per port.
428 * Pointer to mlx5_dev_ctx_shared object.
431 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
434 struct mlx5_age_info *age_info;
436 for (i = 0; i < sh->max_port; i++) {
437 age_info = &sh->port[i].age_info;
439 TAILQ_INIT(&age_info->aged_counters);
440 LIST_INIT(&age_info->aged_aso);
441 rte_spinlock_init(&age_info->aged_sl);
442 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
447 * Initialize the counters management structure.
450 * Pointer to mlx5_dev_ctx_shared object to free
453 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
457 memset(&sh->cmng, 0, sizeof(sh->cmng));
458 TAILQ_INIT(&sh->cmng.flow_counters);
459 sh->cmng.min_id = MLX5_CNT_BATCH_OFFSET;
460 sh->cmng.max_id = -1;
461 sh->cmng.last_pool_idx = POOL_IDX_INVALID;
462 rte_spinlock_init(&sh->cmng.pool_update_sl);
463 for (i = 0; i < MLX5_COUNTER_TYPE_MAX; i++) {
464 TAILQ_INIT(&sh->cmng.counters[i]);
465 rte_spinlock_init(&sh->cmng.csl[i]);
470 * Destroy all the resources allocated for a counter memory management.
473 * Pointer to the memory management structure.
476 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
478 uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
480 LIST_REMOVE(mng, next);
481 claim_zero(mlx5_devx_cmd_destroy(mng->dm));
482 claim_zero(mlx5_os_umem_dereg(mng->umem));
487 * Close and release all the resources of the counters management.
490 * Pointer to mlx5_dev_ctx_shared object to free.
493 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
495 struct mlx5_counter_stats_mem_mng *mng;
501 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
502 if (rte_errno != EINPROGRESS)
507 if (sh->cmng.pools) {
508 struct mlx5_flow_counter_pool *pool;
509 uint16_t n_valid = sh->cmng.n_valid;
510 bool fallback = sh->cmng.counter_fallback;
512 for (i = 0; i < n_valid; ++i) {
513 pool = sh->cmng.pools[i];
514 if (!fallback && pool->min_dcs)
515 claim_zero(mlx5_devx_cmd_destroy
517 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
518 struct mlx5_flow_counter *cnt =
519 MLX5_POOL_GET_CNT(pool, j);
523 (mlx5_flow_os_destroy_flow_action
525 if (fallback && MLX5_POOL_GET_CNT
526 (pool, j)->dcs_when_free)
527 claim_zero(mlx5_devx_cmd_destroy
528 (cnt->dcs_when_free));
532 mlx5_free(sh->cmng.pools);
534 mng = LIST_FIRST(&sh->cmng.mem_mngs);
536 mlx5_flow_destroy_counter_stat_mem_mng(mng);
537 mng = LIST_FIRST(&sh->cmng.mem_mngs);
539 memset(&sh->cmng, 0, sizeof(sh->cmng));
542 /* Send FLOW_AGED event if needed. */
544 mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh)
546 struct mlx5_age_info *age_info;
549 for (i = 0; i < sh->max_port; i++) {
550 age_info = &sh->port[i].age_info;
551 if (!MLX5_AGE_GET(age_info, MLX5_AGE_EVENT_NEW))
553 if (MLX5_AGE_GET(age_info, MLX5_AGE_TRIGGER))
554 rte_eth_dev_callback_process
555 (&rte_eth_devices[sh->port[i].devx_ih_port_id],
556 RTE_ETH_EVENT_FLOW_AGED, NULL);
562 * Initialize the flow resources' indexed mempool.
565 * Pointer to mlx5_dev_ctx_shared object.
567 * Pointer to user dev config.
570 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
571 const struct mlx5_dev_config *config)
574 struct mlx5_indexed_pool_config cfg;
576 for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
577 cfg = mlx5_ipool_cfg[i];
582 * Set MLX5_IPOOL_MLX5_FLOW ipool size
583 * according to PCI function flow configuration.
585 case MLX5_IPOOL_MLX5_FLOW:
586 cfg.size = config->dv_flow_en ?
587 sizeof(struct mlx5_flow_handle) :
588 MLX5_FLOW_HANDLE_VERBS_SIZE;
591 if (config->reclaim_mode)
592 cfg.release_mem_en = 1;
593 sh->ipool[i] = mlx5_ipool_create(&cfg);
598 * Release the flow resources' indexed mempool.
601 * Pointer to mlx5_dev_ctx_shared object.
604 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
608 for (i = 0; i < MLX5_IPOOL_MAX; ++i)
609 mlx5_ipool_destroy(sh->ipool[i]);
613 * Check if dynamic flex parser for eCPRI already exists.
616 * Pointer to Ethernet device structure.
619 * true on exists, false on not.
622 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
624 struct mlx5_priv *priv = dev->data->dev_private;
625 struct mlx5_flex_parser_profiles *prf =
626 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
632 * Allocation of a flex parser for eCPRI. Once created, this parser related
633 * resources will be held until the device is closed.
636 * Pointer to Ethernet device structure.
639 * 0 on success, a negative errno value otherwise and rte_errno is set.
642 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
644 struct mlx5_priv *priv = dev->data->dev_private;
645 struct mlx5_flex_parser_profiles *prf =
646 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
647 struct mlx5_devx_graph_node_attr node = {
648 .modify_field_select = 0,
653 if (!priv->config.hca_attr.parse_graph_flex_node) {
654 DRV_LOG(ERR, "Dynamic flex parser is not supported "
655 "for device %s.", priv->dev_data->name);
658 node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED;
659 /* 8 bytes now: 4B common header + 4B message body header. */
660 node.header_length_base_value = 0x8;
661 /* After MAC layer: Ether / VLAN. */
662 node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC;
663 /* Type of compared condition should be 0xAEFE in the L2 layer. */
664 node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI;
665 /* Sample #0: type in common header. */
666 node.sample[0].flow_match_sample_en = 1;
668 node.sample[0].flow_match_sample_offset_mode = 0x0;
669 /* Only the 2nd byte will be used. */
670 node.sample[0].flow_match_sample_field_base_offset = 0x0;
671 /* Sample #1: message payload. */
672 node.sample[1].flow_match_sample_en = 1;
674 node.sample[1].flow_match_sample_offset_mode = 0x0;
676 * Only the first two bytes will be used right now, and its offset will
677 * start after the common header that with the length of a DW(u32).
679 node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);
680 prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->ctx, &node);
682 DRV_LOG(ERR, "Failed to create flex parser node object.");
683 return (rte_errno == 0) ? -ENODEV : -rte_errno;
686 ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num);
688 DRV_LOG(ERR, "Failed to query sample IDs.");
689 return (rte_errno == 0) ? -ENODEV : -rte_errno;
691 prf->offset[0] = 0x0;
692 prf->offset[1] = sizeof(uint32_t);
693 prf->ids[0] = ids[0];
694 prf->ids[1] = ids[1];
699 * Destroy the flex parser node, including the parser itself, input / output
700 * arcs and DW samples. Resources could be reused then.
703 * Pointer to Ethernet device structure.
706 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
708 struct mlx5_priv *priv = dev->data->dev_private;
709 struct mlx5_flex_parser_profiles *prf =
710 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
713 mlx5_devx_cmd_destroy(prf->obj);
718 * Allocate Rx and Tx UARs in robust fashion.
719 * This routine handles the following UAR allocation issues:
721 * - tries to allocate the UAR with the most appropriate memory
722 * mapping type from the ones supported by the host
724 * - tries to allocate the UAR with non-NULL base address
725 * OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as
726 * UAR base address if UAR was not the first object in the UAR page.
727 * It caused the PMD failure and we should try to get another UAR
728 * till we get the first one with non-NULL base address returned.
731 mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh,
732 const struct mlx5_dev_config *config)
734 uint32_t uar_mapping, retry;
738 for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
739 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
740 /* Control the mapping type according to the settings. */
741 uar_mapping = (config->dbnc == MLX5_TXDB_NCACHED) ?
742 MLX5DV_UAR_ALLOC_TYPE_NC :
743 MLX5DV_UAR_ALLOC_TYPE_BF;
745 RTE_SET_USED(config);
747 * It seems we have no way to control the memory mapping type
748 * for the UAR, the default "Write-Combining" type is supposed.
749 * The UAR initialization on queue creation queries the
750 * actual mapping type done by Verbs/kernel and setups the
751 * PMD datapath accordingly.
755 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->ctx, uar_mapping);
756 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
758 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
759 if (config->dbnc == MLX5_TXDB_CACHED ||
760 config->dbnc == MLX5_TXDB_HEURISTIC)
761 DRV_LOG(WARNING, "Devarg tx_db_nc setting "
762 "is not supported by DevX");
764 * In some environments like virtual machine
765 * the Write Combining mapped might be not supported
766 * and UAR allocation fails. We try "Non-Cached"
767 * mapping for the case. The tx_burst routines take
768 * the UAR mapping type into account on UAR setup
771 DRV_LOG(WARNING, "Failed to allocate Tx DevX UAR (BF)");
772 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
773 sh->tx_uar = mlx5_glue->devx_alloc_uar
774 (sh->ctx, uar_mapping);
775 } else if (!sh->tx_uar &&
776 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_NC) {
777 if (config->dbnc == MLX5_TXDB_NCACHED)
778 DRV_LOG(WARNING, "Devarg tx_db_nc settings "
779 "is not supported by DevX");
781 * If Verbs/kernel does not support "Non-Cached"
782 * try the "Write-Combining".
784 DRV_LOG(WARNING, "Failed to allocate Tx DevX UAR (NC)");
785 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_BF;
786 sh->tx_uar = mlx5_glue->devx_alloc_uar
787 (sh->ctx, uar_mapping);
791 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (BF/NC)");
795 base_addr = mlx5_os_get_devx_uar_base_addr(sh->tx_uar);
799 * The UARs are allocated by rdma_core within the
800 * IB device context, on context closure all UARs
801 * will be freed, should be no memory/object leakage.
803 DRV_LOG(WARNING, "Retrying to allocate Tx DevX UAR");
806 /* Check whether we finally succeeded with valid UAR allocation. */
808 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (NULL base)");
812 for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
814 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
815 (sh->ctx, uar_mapping);
816 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
817 if (!sh->devx_rx_uar &&
818 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
820 * Rx UAR is used to control interrupts only,
821 * should be no datapath noticeable impact,
822 * can try "Non-Cached" mapping safely.
824 DRV_LOG(WARNING, "Failed to allocate Rx DevX UAR (BF)");
825 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
826 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
827 (sh->ctx, uar_mapping);
830 if (!sh->devx_rx_uar) {
831 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (BF/NC)");
835 base_addr = mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar);
839 * The UARs are allocated by rdma_core within the
840 * IB device context, on context closure all UARs
841 * will be freed, should be no memory/object leakage.
843 DRV_LOG(WARNING, "Retrying to allocate Rx DevX UAR");
844 sh->devx_rx_uar = NULL;
846 /* Check whether we finally succeeded with valid UAR allocation. */
847 if (!sh->devx_rx_uar) {
848 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (NULL base)");
856 * Allocate shared device context. If there is multiport device the
857 * master and representors will share this context, if there is single
858 * port dedicated device, the context will be used by only given
859 * port due to unification.
861 * Routine first searches the context for the specified device name,
862 * if found the shared context assumed and reference counter is incremented.
863 * If no context found the new one is created and initialized with specified
864 * device context and parameters.
867 * Pointer to the device attributes (name, port, etc).
869 * Pointer to device configuration structure.
872 * Pointer to mlx5_dev_ctx_shared object on success,
873 * otherwise NULL and rte_errno is set.
875 struct mlx5_dev_ctx_shared *
876 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
877 const struct mlx5_dev_config *config)
879 struct mlx5_dev_ctx_shared *sh;
882 struct mlx5_devx_tis_attr tis_attr = { 0 };
885 /* Secondary process should not create the shared context. */
886 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
887 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
888 /* Search for IB context by device name. */
889 LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
890 if (!strcmp(sh->ibdev_name,
891 mlx5_os_get_dev_device_name(spawn->phys_dev))) {
896 /* No device found, we have to create new shared context. */
897 MLX5_ASSERT(spawn->max_port);
898 sh = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
899 sizeof(struct mlx5_dev_ctx_shared) +
901 sizeof(struct mlx5_dev_shared_port),
902 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
904 DRV_LOG(ERR, "shared context allocation failure");
908 err = mlx5_os_open_device(spawn, config, sh);
911 err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
913 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
917 sh->bond_dev = UINT16_MAX;
918 sh->max_port = spawn->max_port;
919 strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
920 sizeof(sh->ibdev_name) - 1);
921 strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
922 sizeof(sh->ibdev_path) - 1);
924 * Setting port_id to max unallowed value means
925 * there is no interrupt subhandler installed for
926 * the given port index i.
928 for (i = 0; i < sh->max_port; i++) {
929 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
930 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
932 sh->pd = mlx5_os_alloc_pd(sh->ctx);
933 if (sh->pd == NULL) {
934 DRV_LOG(ERR, "PD allocation failure");
939 err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
941 DRV_LOG(ERR, "Fail to extract pdn from PD");
944 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
946 DRV_LOG(ERR, "TD allocation failure");
950 tis_attr.transport_domain = sh->td->id;
951 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
953 DRV_LOG(ERR, "TIS allocation failure");
957 err = mlx5_alloc_rxtx_uars(sh, config);
960 MLX5_ASSERT(sh->tx_uar);
961 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->tx_uar));
963 MLX5_ASSERT(sh->devx_rx_uar);
964 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar));
967 /* Initialize UAR access locks for 32bit implementations. */
968 rte_spinlock_init(&sh->uar_lock_cq);
969 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
970 rte_spinlock_init(&sh->uar_lock[i]);
973 * Once the device is added to the list of memory event
974 * callback, its global MR cache table cannot be expanded
975 * on the fly because of deadlock. If it overflows, lookup
976 * should be done by searching MR list linearly, which is slow.
978 * At this point the device is not added to the memory
979 * event list yet, context is just being created.
981 err = mlx5_mr_btree_init(&sh->share_cache.cache,
982 MLX5_MR_BTREE_CACHE_N * 2,
983 spawn->pci_dev->device.numa_node);
988 mlx5_os_set_reg_mr_cb(&sh->share_cache.reg_mr_cb,
989 &sh->share_cache.dereg_mr_cb);
990 mlx5_os_dev_shared_handler_install(sh);
991 sh->cnt_id_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_DWORD);
992 if (!sh->cnt_id_tbl) {
996 if (LIST_EMPTY(&mlx5_dev_ctx_list)) {
997 err = mlx5_flow_os_init_workspace_once();
1001 mlx5_flow_aging_init(sh);
1002 mlx5_flow_counters_mng_init(sh);
1003 mlx5_flow_ipool_create(sh, config);
1004 /* Add device to memory callback list. */
1005 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1006 LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
1008 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1009 /* Add context to the global device list. */
1010 LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
1012 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1015 pthread_mutex_destroy(&sh->txpp.mutex);
1016 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1019 mlx5_l3t_destroy(sh->cnt_id_tbl);
1021 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1023 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1024 if (sh->devx_rx_uar)
1025 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1027 mlx5_glue->devx_free_uar(sh->tx_uar);
1029 claim_zero(mlx5_os_dealloc_pd(sh->pd));
1031 claim_zero(mlx5_glue->close_device(sh->ctx));
1033 MLX5_ASSERT(err > 0);
1039 * Free shared IB device context. Decrement counter and if zero free
1040 * all allocated resources and close handles.
1043 * Pointer to mlx5_dev_ctx_shared object to free
1046 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
1048 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1049 #ifdef RTE_LIBRTE_MLX5_DEBUG
1050 /* Check the object presence in the list. */
1051 struct mlx5_dev_ctx_shared *lctx;
1053 LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
1058 DRV_LOG(ERR, "Freeing non-existing shared IB context");
1063 MLX5_ASSERT(sh->refcnt);
1064 /* Secondary process should not free the shared context. */
1065 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1068 /* Remove from memory callback device list. */
1069 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1070 LIST_REMOVE(sh, mem_event_cb);
1071 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1072 /* Release created Memory Regions. */
1073 mlx5_mr_release_cache(&sh->share_cache);
1074 /* Remove context from the global device list. */
1075 LIST_REMOVE(sh, next);
1076 /* Release flow workspaces objects on the last device. */
1077 if (LIST_EMPTY(&mlx5_dev_ctx_list))
1078 mlx5_flow_os_release_workspace();
1079 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1081 * Ensure there is no async event handler installed.
1082 * Only primary process handles async device events.
1084 mlx5_flow_counters_mng_close(sh);
1085 if (sh->aso_age_mng) {
1086 mlx5_flow_aso_age_mng_close(sh);
1087 sh->aso_age_mng = NULL;
1089 mlx5_flow_ipool_destroy(sh);
1090 mlx5_os_dev_shared_handler_uninstall(sh);
1091 if (sh->cnt_id_tbl) {
1092 mlx5_l3t_destroy(sh->cnt_id_tbl);
1093 sh->cnt_id_tbl = NULL;
1096 mlx5_glue->devx_free_uar(sh->tx_uar);
1100 claim_zero(mlx5_os_dealloc_pd(sh->pd));
1102 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1104 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1105 if (sh->devx_rx_uar)
1106 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1108 claim_zero(mlx5_glue->close_device(sh->ctx));
1109 pthread_mutex_destroy(&sh->txpp.mutex);
1113 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1117 * Destroy table hash list.
1120 * Pointer to the private device data structure.
1123 mlx5_free_table_hash_list(struct mlx5_priv *priv)
1125 struct mlx5_dev_ctx_shared *sh = priv->sh;
1129 mlx5_hlist_destroy(sh->flow_tbls);
1133 * Initialize flow table hash list and create the root tables entry
1137 * Pointer to the private device data structure.
1140 * Zero on success, positive error code otherwise.
1143 mlx5_alloc_table_hash_list(struct mlx5_priv *priv __rte_unused)
1146 /* Tables are only used in DV and DR modes. */
1147 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
1148 struct mlx5_dev_ctx_shared *sh = priv->sh;
1149 char s[MLX5_HLIST_NAMESIZE];
1152 snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1153 sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE,
1154 0, 0, flow_dv_tbl_create_cb,
1155 flow_dv_tbl_match_cb,
1156 flow_dv_tbl_remove_cb);
1157 if (!sh->flow_tbls) {
1158 DRV_LOG(ERR, "flow tables with hash creation failed.");
1162 sh->flow_tbls->ctx = sh;
1163 #ifndef HAVE_MLX5DV_DR
1164 struct rte_flow_error error;
1165 struct rte_eth_dev *dev = &rte_eth_devices[priv->dev_data->port_id];
1168 * In case we have not DR support, the zero tables should be created
1169 * because DV expect to see them even if they cannot be created by
1172 if (!flow_dv_tbl_resource_get(dev, 0, 0, 0, 0, NULL, 0, 1, &error) ||
1173 !flow_dv_tbl_resource_get(dev, 0, 1, 0, 0, NULL, 0, 1, &error) ||
1174 !flow_dv_tbl_resource_get(dev, 0, 0, 1, 0, NULL, 0, 1, &error)) {
1180 mlx5_free_table_hash_list(priv);
1181 #endif /* HAVE_MLX5DV_DR */
1187 * Retrieve integer value from environment variable.
1190 * Environment variable name.
1193 * Integer value, 0 if the variable is not set.
1196 mlx5_getenv_int(const char *name)
1198 const char *val = getenv(name);
1206 * DPDK callback to add udp tunnel port
1209 * A pointer to eth_dev
1210 * @param[in] udp_tunnel
1211 * A pointer to udp tunnel
1214 * 0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1217 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1218 struct rte_eth_udp_tunnel *udp_tunnel)
1220 MLX5_ASSERT(udp_tunnel != NULL);
1221 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1222 udp_tunnel->udp_port == 4789)
1224 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1225 udp_tunnel->udp_port == 4790)
1231 * Initialize process private data structure.
1234 * Pointer to Ethernet device structure.
1237 * 0 on success, a negative errno value otherwise and rte_errno is set.
1240 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1242 struct mlx5_priv *priv = dev->data->dev_private;
1243 struct mlx5_proc_priv *ppriv;
1247 * UAR register table follows the process private structure. BlueFlame
1248 * registers for Tx queues are stored in the table.
1251 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1252 ppriv = mlx5_malloc(MLX5_MEM_RTE, ppriv_size, RTE_CACHE_LINE_SIZE,
1253 dev->device->numa_node);
1258 ppriv->uar_table_sz = ppriv_size;
1259 dev->process_private = ppriv;
1264 * Un-initialize process private data structure.
1267 * Pointer to Ethernet device structure.
1270 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1272 if (!dev->process_private)
1274 mlx5_free(dev->process_private);
1275 dev->process_private = NULL;
1279 * DPDK callback to close the device.
1281 * Destroy all queues and objects, free memory.
1284 * Pointer to Ethernet device structure.
1287 mlx5_dev_close(struct rte_eth_dev *dev)
1289 struct mlx5_priv *priv = dev->data->dev_private;
1293 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1294 /* Check if process_private released. */
1295 if (!dev->process_private)
1297 mlx5_tx_uar_uninit_secondary(dev);
1298 mlx5_proc_priv_uninit(dev);
1299 rte_eth_dev_release_port(dev);
1304 DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1306 ((priv->sh->ctx != NULL) ?
1307 mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
1309 * If default mreg copy action is removed at the stop stage,
1310 * the search will return none and nothing will be done anymore.
1312 mlx5_flow_stop_default(dev);
1313 mlx5_traffic_disable(dev);
1315 * If all the flows are already flushed in the device stop stage,
1316 * then this will return directly without any action.
1318 mlx5_flow_list_flush(dev, &priv->flows, true);
1319 mlx5_shared_action_flush(dev);
1320 mlx5_flow_meter_flush(dev, NULL);
1321 /* Prevent crashes when queues are still in use. */
1322 dev->rx_pkt_burst = removed_rx_burst;
1323 dev->tx_pkt_burst = removed_tx_burst;
1325 /* Disable datapath on secondary process. */
1326 mlx5_mp_os_req_stop_rxtx(dev);
1327 /* Free the eCPRI flex parser resource. */
1328 mlx5_flex_parser_ecpri_release(dev);
1329 if (priv->rxqs != NULL) {
1330 /* XXX race condition if mlx5_rx_burst() is still running. */
1331 rte_delay_us_sleep(1000);
1332 for (i = 0; (i != priv->rxqs_n); ++i)
1333 mlx5_rxq_release(dev, i);
1337 if (priv->txqs != NULL) {
1338 /* XXX race condition if mlx5_tx_burst() is still running. */
1339 rte_delay_us_sleep(1000);
1340 for (i = 0; (i != priv->txqs_n); ++i)
1341 mlx5_txq_release(dev, i);
1345 mlx5_proc_priv_uninit(dev);
1346 if (priv->drop_queue.hrxq)
1347 mlx5_drop_action_destroy(dev);
1348 if (priv->mreg_cp_tbl)
1349 mlx5_hlist_destroy(priv->mreg_cp_tbl);
1350 mlx5_mprq_free_mp(dev);
1351 mlx5_os_free_shared_dr(priv);
1352 if (priv->rss_conf.rss_key != NULL)
1353 mlx5_free(priv->rss_conf.rss_key);
1354 if (priv->reta_idx != NULL)
1355 mlx5_free(priv->reta_idx);
1356 if (priv->config.vf)
1357 mlx5_os_mac_addr_flush(dev);
1358 if (priv->nl_socket_route >= 0)
1359 close(priv->nl_socket_route);
1360 if (priv->nl_socket_rdma >= 0)
1361 close(priv->nl_socket_rdma);
1362 if (priv->vmwa_context)
1363 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1364 ret = mlx5_hrxq_verify(dev);
1366 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1367 dev->data->port_id);
1368 ret = mlx5_ind_table_obj_verify(dev);
1370 DRV_LOG(WARNING, "port %u some indirection table still remain",
1371 dev->data->port_id);
1372 ret = mlx5_rxq_obj_verify(dev);
1374 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1375 dev->data->port_id);
1376 ret = mlx5_rxq_verify(dev);
1378 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1379 dev->data->port_id);
1380 ret = mlx5_txq_obj_verify(dev);
1382 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1383 dev->data->port_id);
1384 ret = mlx5_txq_verify(dev);
1386 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1387 dev->data->port_id);
1388 ret = mlx5_flow_verify(dev);
1390 DRV_LOG(WARNING, "port %u some flows still remain",
1391 dev->data->port_id);
1392 mlx5_cache_list_destroy(&priv->hrxqs);
1394 * Free the shared context in last turn, because the cleanup
1395 * routines above may use some shared fields, like
1396 * mlx5_os_mac_addr_flush() uses ibdev_path for retrieveing
1397 * ifindex if Netlink fails.
1399 mlx5_free_shared_dev_ctx(priv->sh);
1400 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1404 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1405 struct mlx5_priv *opriv =
1406 rte_eth_devices[port_id].data->dev_private;
1409 opriv->domain_id != priv->domain_id ||
1410 &rte_eth_devices[port_id] == dev)
1416 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1418 memset(priv, 0, sizeof(*priv));
1419 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1421 * Reset mac_addrs to NULL such that it is not freed as part of
1422 * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1423 * it is freed when dev_private is freed.
1425 dev->data->mac_addrs = NULL;
1429 const struct eth_dev_ops mlx5_dev_ops = {
1430 .dev_configure = mlx5_dev_configure,
1431 .dev_start = mlx5_dev_start,
1432 .dev_stop = mlx5_dev_stop,
1433 .dev_set_link_down = mlx5_set_link_down,
1434 .dev_set_link_up = mlx5_set_link_up,
1435 .dev_close = mlx5_dev_close,
1436 .promiscuous_enable = mlx5_promiscuous_enable,
1437 .promiscuous_disable = mlx5_promiscuous_disable,
1438 .allmulticast_enable = mlx5_allmulticast_enable,
1439 .allmulticast_disable = mlx5_allmulticast_disable,
1440 .link_update = mlx5_link_update,
1441 .stats_get = mlx5_stats_get,
1442 .stats_reset = mlx5_stats_reset,
1443 .xstats_get = mlx5_xstats_get,
1444 .xstats_reset = mlx5_xstats_reset,
1445 .xstats_get_names = mlx5_xstats_get_names,
1446 .fw_version_get = mlx5_fw_version_get,
1447 .dev_infos_get = mlx5_dev_infos_get,
1448 .read_clock = mlx5_txpp_read_clock,
1449 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1450 .vlan_filter_set = mlx5_vlan_filter_set,
1451 .rx_queue_setup = mlx5_rx_queue_setup,
1452 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1453 .tx_queue_setup = mlx5_tx_queue_setup,
1454 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1455 .rx_queue_release = mlx5_rx_queue_release,
1456 .tx_queue_release = mlx5_tx_queue_release,
1457 .rx_queue_start = mlx5_rx_queue_start,
1458 .rx_queue_stop = mlx5_rx_queue_stop,
1459 .tx_queue_start = mlx5_tx_queue_start,
1460 .tx_queue_stop = mlx5_tx_queue_stop,
1461 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1462 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1463 .mac_addr_remove = mlx5_mac_addr_remove,
1464 .mac_addr_add = mlx5_mac_addr_add,
1465 .mac_addr_set = mlx5_mac_addr_set,
1466 .set_mc_addr_list = mlx5_set_mc_addr_list,
1467 .mtu_set = mlx5_dev_set_mtu,
1468 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1469 .vlan_offload_set = mlx5_vlan_offload_set,
1470 .reta_update = mlx5_dev_rss_reta_update,
1471 .reta_query = mlx5_dev_rss_reta_query,
1472 .rss_hash_update = mlx5_rss_hash_update,
1473 .rss_hash_conf_get = mlx5_rss_hash_conf_get,
1474 .filter_ctrl = mlx5_dev_filter_ctrl,
1475 .rxq_info_get = mlx5_rxq_info_get,
1476 .txq_info_get = mlx5_txq_info_get,
1477 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1478 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1479 .rx_queue_intr_enable = mlx5_rx_intr_enable,
1480 .rx_queue_intr_disable = mlx5_rx_intr_disable,
1481 .is_removed = mlx5_is_removed,
1482 .udp_tunnel_port_add = mlx5_udp_tunnel_port_add,
1483 .get_module_info = mlx5_get_module_info,
1484 .get_module_eeprom = mlx5_get_module_eeprom,
1485 .hairpin_cap_get = mlx5_hairpin_cap_get,
1486 .mtr_ops_get = mlx5_flow_meter_ops_get,
1487 .hairpin_bind = mlx5_hairpin_bind,
1488 .hairpin_unbind = mlx5_hairpin_unbind,
1489 .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1490 .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1491 .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1492 .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1495 /* Available operations from secondary process. */
1496 const struct eth_dev_ops mlx5_dev_sec_ops = {
1497 .stats_get = mlx5_stats_get,
1498 .stats_reset = mlx5_stats_reset,
1499 .xstats_get = mlx5_xstats_get,
1500 .xstats_reset = mlx5_xstats_reset,
1501 .xstats_get_names = mlx5_xstats_get_names,
1502 .fw_version_get = mlx5_fw_version_get,
1503 .dev_infos_get = mlx5_dev_infos_get,
1504 .read_clock = mlx5_txpp_read_clock,
1505 .rx_queue_start = mlx5_rx_queue_start,
1506 .rx_queue_stop = mlx5_rx_queue_stop,
1507 .tx_queue_start = mlx5_tx_queue_start,
1508 .tx_queue_stop = mlx5_tx_queue_stop,
1509 .rxq_info_get = mlx5_rxq_info_get,
1510 .txq_info_get = mlx5_txq_info_get,
1511 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1512 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1513 .get_module_info = mlx5_get_module_info,
1514 .get_module_eeprom = mlx5_get_module_eeprom,
1517 /* Available operations in flow isolated mode. */
1518 const struct eth_dev_ops mlx5_dev_ops_isolate = {
1519 .dev_configure = mlx5_dev_configure,
1520 .dev_start = mlx5_dev_start,
1521 .dev_stop = mlx5_dev_stop,
1522 .dev_set_link_down = mlx5_set_link_down,
1523 .dev_set_link_up = mlx5_set_link_up,
1524 .dev_close = mlx5_dev_close,
1525 .promiscuous_enable = mlx5_promiscuous_enable,
1526 .promiscuous_disable = mlx5_promiscuous_disable,
1527 .allmulticast_enable = mlx5_allmulticast_enable,
1528 .allmulticast_disable = mlx5_allmulticast_disable,
1529 .link_update = mlx5_link_update,
1530 .stats_get = mlx5_stats_get,
1531 .stats_reset = mlx5_stats_reset,
1532 .xstats_get = mlx5_xstats_get,
1533 .xstats_reset = mlx5_xstats_reset,
1534 .xstats_get_names = mlx5_xstats_get_names,
1535 .fw_version_get = mlx5_fw_version_get,
1536 .dev_infos_get = mlx5_dev_infos_get,
1537 .read_clock = mlx5_txpp_read_clock,
1538 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1539 .vlan_filter_set = mlx5_vlan_filter_set,
1540 .rx_queue_setup = mlx5_rx_queue_setup,
1541 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1542 .tx_queue_setup = mlx5_tx_queue_setup,
1543 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1544 .rx_queue_release = mlx5_rx_queue_release,
1545 .tx_queue_release = mlx5_tx_queue_release,
1546 .rx_queue_start = mlx5_rx_queue_start,
1547 .rx_queue_stop = mlx5_rx_queue_stop,
1548 .tx_queue_start = mlx5_tx_queue_start,
1549 .tx_queue_stop = mlx5_tx_queue_stop,
1550 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1551 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1552 .mac_addr_remove = mlx5_mac_addr_remove,
1553 .mac_addr_add = mlx5_mac_addr_add,
1554 .mac_addr_set = mlx5_mac_addr_set,
1555 .set_mc_addr_list = mlx5_set_mc_addr_list,
1556 .mtu_set = mlx5_dev_set_mtu,
1557 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1558 .vlan_offload_set = mlx5_vlan_offload_set,
1559 .filter_ctrl = mlx5_dev_filter_ctrl,
1560 .rxq_info_get = mlx5_rxq_info_get,
1561 .txq_info_get = mlx5_txq_info_get,
1562 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1563 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1564 .rx_queue_intr_enable = mlx5_rx_intr_enable,
1565 .rx_queue_intr_disable = mlx5_rx_intr_disable,
1566 .is_removed = mlx5_is_removed,
1567 .get_module_info = mlx5_get_module_info,
1568 .get_module_eeprom = mlx5_get_module_eeprom,
1569 .hairpin_cap_get = mlx5_hairpin_cap_get,
1570 .mtr_ops_get = mlx5_flow_meter_ops_get,
1571 .hairpin_bind = mlx5_hairpin_bind,
1572 .hairpin_unbind = mlx5_hairpin_unbind,
1573 .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1574 .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1575 .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1576 .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1580 * Verify and store value for device argument.
1583 * Key argument to verify.
1585 * Value associated with key.
1590 * 0 on success, a negative errno value otherwise and rte_errno is set.
1593 mlx5_args_check(const char *key, const char *val, void *opaque)
1595 struct mlx5_dev_config *config = opaque;
1599 /* No-op, port representors are processed in mlx5_dev_spawn(). */
1600 if (!strcmp(MLX5_REPRESENTOR, key))
1603 tmp = strtol(val, NULL, 0);
1606 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1609 if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
1610 /* Negative values are acceptable for some keys only. */
1612 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
1615 mod = tmp >= 0 ? tmp : -tmp;
1616 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1617 if (tmp > MLX5_CQE_RESP_FORMAT_L34H_STRIDX) {
1618 DRV_LOG(ERR, "invalid CQE compression "
1619 "format parameter");
1623 config->cqe_comp = !!tmp;
1624 config->cqe_comp_fmt = tmp;
1625 } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1626 config->hw_padding = !!tmp;
1627 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1628 config->mprq.enabled = !!tmp;
1629 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1630 config->mprq.stride_num_n = tmp;
1631 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1632 config->mprq.stride_size_n = tmp;
1633 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1634 config->mprq.max_memcpy_len = tmp;
1635 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1636 config->mprq.min_rxqs_num = tmp;
1637 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1638 DRV_LOG(WARNING, "%s: deprecated parameter,"
1639 " converted to txq_inline_max", key);
1640 config->txq_inline_max = tmp;
1641 } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1642 config->txq_inline_max = tmp;
1643 } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1644 config->txq_inline_min = tmp;
1645 } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1646 config->txq_inline_mpw = tmp;
1647 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1648 config->txqs_inline = tmp;
1649 } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1650 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1651 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1652 config->mps = !!tmp;
1653 } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1654 if (tmp != MLX5_TXDB_CACHED &&
1655 tmp != MLX5_TXDB_NCACHED &&
1656 tmp != MLX5_TXDB_HEURISTIC) {
1657 DRV_LOG(ERR, "invalid Tx doorbell "
1658 "mapping parameter");
1663 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1664 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1665 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1666 DRV_LOG(WARNING, "%s: deprecated parameter,"
1667 " converted to txq_inline_mpw", key);
1668 config->txq_inline_mpw = tmp;
1669 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1670 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1671 } else if (strcmp(MLX5_TX_PP, key) == 0) {
1673 DRV_LOG(ERR, "Zero Tx packet pacing parameter");
1677 config->tx_pp = tmp;
1678 } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
1679 config->tx_skew = tmp;
1680 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1681 config->rx_vec_en = !!tmp;
1682 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1683 config->l3_vxlan_en = !!tmp;
1684 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1685 config->vf_nl_en = !!tmp;
1686 } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1687 config->dv_esw_en = !!tmp;
1688 } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1689 config->dv_flow_en = !!tmp;
1690 } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1691 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1692 tmp != MLX5_XMETA_MODE_META16 &&
1693 tmp != MLX5_XMETA_MODE_META32 &&
1694 tmp != MLX5_XMETA_MODE_MISS_INFO) {
1695 DRV_LOG(ERR, "invalid extensive "
1696 "metadata parameter");
1700 if (tmp != MLX5_XMETA_MODE_MISS_INFO)
1701 config->dv_xmeta_en = tmp;
1703 config->dv_miss_info = 1;
1704 } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
1705 config->lacp_by_user = !!tmp;
1706 } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1707 config->mr_ext_memseg_en = !!tmp;
1708 } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1709 config->max_dump_files_num = tmp;
1710 } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1711 config->lro.timeout = tmp;
1712 } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1713 DRV_LOG(DEBUG, "class argument is %s.", val);
1714 } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1715 config->log_hp_size = tmp;
1716 } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1717 if (tmp != MLX5_RCM_NONE &&
1718 tmp != MLX5_RCM_LIGHT &&
1719 tmp != MLX5_RCM_AGGR) {
1720 DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1724 config->reclaim_mode = tmp;
1725 } else if (strcmp(MLX5_SYS_MEM_EN, key) == 0) {
1726 config->sys_mem_en = !!tmp;
1727 } else if (strcmp(MLX5_DECAP_EN, key) == 0) {
1728 config->decap_en = !!tmp;
1730 DRV_LOG(WARNING, "%s: unknown parameter", key);
1738 * Parse device parameters.
1741 * Pointer to device configuration structure.
1743 * Device arguments structure.
1746 * 0 on success, a negative errno value otherwise and rte_errno is set.
1749 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1751 const char **params = (const char *[]){
1752 MLX5_RXQ_CQE_COMP_EN,
1753 MLX5_RXQ_PKT_PAD_EN,
1755 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1756 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1757 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1760 MLX5_TXQ_INLINE_MIN,
1761 MLX5_TXQ_INLINE_MAX,
1762 MLX5_TXQ_INLINE_MPW,
1763 MLX5_TXQS_MIN_INLINE,
1766 MLX5_TXQ_MPW_HDR_DSEG_EN,
1767 MLX5_TXQ_MAX_INLINE_LEN,
1779 MLX5_MR_EXT_MEMSEG_EN,
1781 MLX5_MAX_DUMP_FILES_NUM,
1782 MLX5_LRO_TIMEOUT_USEC,
1783 MLX5_CLASS_ARG_NAME,
1790 struct rte_kvargs *kvlist;
1794 if (devargs == NULL)
1796 /* Following UGLY cast is done to pass checkpatch. */
1797 kvlist = rte_kvargs_parse(devargs->args, params);
1798 if (kvlist == NULL) {
1802 /* Process parameters. */
1803 for (i = 0; (params[i] != NULL); ++i) {
1804 if (rte_kvargs_count(kvlist, params[i])) {
1805 ret = rte_kvargs_process(kvlist, params[i],
1806 mlx5_args_check, config);
1809 rte_kvargs_free(kvlist);
1814 rte_kvargs_free(kvlist);
1819 * Configures the minimal amount of data to inline into WQE
1820 * while sending packets.
1822 * - the txq_inline_min has the maximal priority, if this
1823 * key is specified in devargs
1824 * - if DevX is enabled the inline mode is queried from the
1825 * device (HCA attributes and NIC vport context if needed).
1826 * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1827 * and none (0 bytes) for other NICs
1830 * Verbs device parameters (name, port, switch_info) to spawn.
1832 * Device configuration parameters.
1835 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1836 struct mlx5_dev_config *config)
1838 if (config->txq_inline_min != MLX5_ARG_UNSET) {
1839 /* Application defines size of inlined data explicitly. */
1840 switch (spawn->pci_dev->id.device_id) {
1841 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1842 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1843 if (config->txq_inline_min <
1844 (int)MLX5_INLINE_HSIZE_L2) {
1846 "txq_inline_mix aligned to minimal"
1847 " ConnectX-4 required value %d",
1848 (int)MLX5_INLINE_HSIZE_L2);
1849 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1855 if (config->hca_attr.eth_net_offloads) {
1856 /* We have DevX enabled, inline mode queried successfully. */
1857 switch (config->hca_attr.wqe_inline_mode) {
1858 case MLX5_CAP_INLINE_MODE_L2:
1859 /* outer L2 header must be inlined. */
1860 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1862 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1863 /* No inline data are required by NIC. */
1864 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1865 config->hw_vlan_insert =
1866 config->hca_attr.wqe_vlan_insert;
1867 DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1869 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1870 /* inline mode is defined by NIC vport context. */
1871 if (!config->hca_attr.eth_virt)
1873 switch (config->hca_attr.vport_inline_mode) {
1874 case MLX5_INLINE_MODE_NONE:
1875 config->txq_inline_min =
1876 MLX5_INLINE_HSIZE_NONE;
1878 case MLX5_INLINE_MODE_L2:
1879 config->txq_inline_min =
1880 MLX5_INLINE_HSIZE_L2;
1882 case MLX5_INLINE_MODE_IP:
1883 config->txq_inline_min =
1884 MLX5_INLINE_HSIZE_L3;
1886 case MLX5_INLINE_MODE_TCP_UDP:
1887 config->txq_inline_min =
1888 MLX5_INLINE_HSIZE_L4;
1890 case MLX5_INLINE_MODE_INNER_L2:
1891 config->txq_inline_min =
1892 MLX5_INLINE_HSIZE_INNER_L2;
1894 case MLX5_INLINE_MODE_INNER_IP:
1895 config->txq_inline_min =
1896 MLX5_INLINE_HSIZE_INNER_L3;
1898 case MLX5_INLINE_MODE_INNER_TCP_UDP:
1899 config->txq_inline_min =
1900 MLX5_INLINE_HSIZE_INNER_L4;
1906 * We get here if we are unable to deduce
1907 * inline data size with DevX. Try PCI ID
1908 * to determine old NICs.
1910 switch (spawn->pci_dev->id.device_id) {
1911 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1912 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1913 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
1914 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1915 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1916 config->hw_vlan_insert = 0;
1918 case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
1919 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1920 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
1921 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1923 * These NICs support VLAN insertion from WQE and
1924 * report the wqe_vlan_insert flag. But there is the bug
1925 * and PFC control may be broken, so disable feature.
1927 config->hw_vlan_insert = 0;
1928 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1931 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1935 DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
1939 * Configures the metadata mask fields in the shared context.
1942 * Pointer to Ethernet device.
1945 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
1947 struct mlx5_priv *priv = dev->data->dev_private;
1948 struct mlx5_dev_ctx_shared *sh = priv->sh;
1949 uint32_t meta, mark, reg_c0;
1951 reg_c0 = ~priv->vport_meta_mask;
1952 switch (priv->config.dv_xmeta_en) {
1953 case MLX5_XMETA_MODE_LEGACY:
1955 mark = MLX5_FLOW_MARK_MASK;
1957 case MLX5_XMETA_MODE_META16:
1958 meta = reg_c0 >> rte_bsf32(reg_c0);
1959 mark = MLX5_FLOW_MARK_MASK;
1961 case MLX5_XMETA_MODE_META32:
1963 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
1971 if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
1972 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
1973 sh->dv_mark_mask, mark);
1975 sh->dv_mark_mask = mark;
1976 if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
1977 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
1978 sh->dv_meta_mask, meta);
1980 sh->dv_meta_mask = meta;
1981 if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
1982 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
1983 sh->dv_meta_mask, reg_c0);
1985 sh->dv_regc0_mask = reg_c0;
1986 DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
1987 DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
1988 DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
1989 DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
1993 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
1995 static const char *const dynf_names[] = {
1996 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
1997 RTE_MBUF_DYNFLAG_METADATA_NAME,
1998 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
2002 if (n < RTE_DIM(dynf_names))
2004 for (i = 0; i < RTE_DIM(dynf_names); i++) {
2005 if (names[i] == NULL)
2007 strcpy(names[i], dynf_names[i]);
2009 return RTE_DIM(dynf_names);
2013 * Comparison callback to sort device data.
2015 * This is meant to be used with qsort().
2018 * Pointer to pointer to first data object.
2020 * Pointer to pointer to second data object.
2023 * 0 if both objects are equal, less than 0 if the first argument is less
2024 * than the second, greater than 0 otherwise.
2027 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
2028 struct mlx5_dev_config *config)
2030 struct mlx5_dev_ctx_shared *sh = priv->sh;
2031 struct mlx5_dev_config *sh_conf = NULL;
2035 /* Nothing to compare for the single/first device. */
2036 if (sh->refcnt == 1)
2038 /* Find the device with shared context. */
2039 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
2040 struct mlx5_priv *opriv =
2041 rte_eth_devices[port_id].data->dev_private;
2043 if (opriv && opriv != priv && opriv->sh == sh) {
2044 sh_conf = &opriv->config;
2050 if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
2051 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
2052 " for shared %s context", sh->ibdev_name);
2056 if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
2057 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
2058 " for shared %s context", sh->ibdev_name);
2066 * Look for the ethernet device belonging to mlx5 driver.
2068 * @param[in] port_id
2069 * port_id to start looking for device.
2070 * @param[in] pci_dev
2071 * Pointer to the hint PCI device. When device is being probed
2072 * the its siblings (master and preceding representors might
2073 * not have assigned driver yet (because the mlx5_os_pci_probe()
2074 * is not completed yet, for this case match on hint PCI
2075 * device may be used to detect sibling device.
2078 * port_id of found device, RTE_MAX_ETHPORT if not found.
2081 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
2083 while (port_id < RTE_MAX_ETHPORTS) {
2084 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
2086 if (dev->state != RTE_ETH_DEV_UNUSED &&
2088 (dev->device == &pci_dev->device ||
2089 (dev->device->driver &&
2090 dev->device->driver->name &&
2091 !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
2095 if (port_id >= RTE_MAX_ETHPORTS)
2096 return RTE_MAX_ETHPORTS;
2101 * DPDK callback to remove a PCI device.
2103 * This function removes all Ethernet devices belong to a given PCI device.
2105 * @param[in] pci_dev
2106 * Pointer to the PCI device.
2109 * 0 on success, the function cannot fail.
2112 mlx5_pci_remove(struct rte_pci_device *pci_dev)
2117 RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
2119 * mlx5_dev_close() is not registered to secondary process,
2120 * call the close function explicitly for secondary process.
2122 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
2123 ret |= mlx5_dev_close(&rte_eth_devices[port_id]);
2125 ret |= rte_eth_dev_close(port_id);
2127 return ret == 0 ? 0 : -EIO;
2130 static const struct rte_pci_id mlx5_pci_id_map[] = {
2132 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2133 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
2136 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2137 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
2140 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2141 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
2144 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2145 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
2148 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2149 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
2152 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2153 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
2156 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2157 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
2160 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2161 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
2164 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2165 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
2168 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2169 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
2172 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2173 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
2176 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2177 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
2180 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2181 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
2184 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2185 PCI_DEVICE_ID_MELLANOX_CONNECTXVF)
2188 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2189 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
2192 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2193 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
2196 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2197 PCI_DEVICE_ID_MELLANOX_CONNECTX7)
2200 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2201 PCI_DEVICE_ID_MELLANOX_CONNECTX7BF)
2208 static struct mlx5_pci_driver mlx5_driver = {
2209 .driver_class = MLX5_CLASS_NET,
2212 .name = MLX5_DRIVER_NAME,
2214 .id_table = mlx5_pci_id_map,
2215 .probe = mlx5_os_pci_probe,
2216 .remove = mlx5_pci_remove,
2217 .dma_map = mlx5_dma_map,
2218 .dma_unmap = mlx5_dma_unmap,
2219 .drv_flags = PCI_DRV_FLAGS,
2223 /* Initialize driver log type. */
2224 RTE_LOG_REGISTER(mlx5_logtype, pmd.net.mlx5, NOTICE)
2227 * Driver initialization routine.
2229 RTE_INIT(rte_mlx5_pmd_init)
2231 pthread_mutex_init(&mlx5_dev_ctx_list_mutex, NULL);
2233 /* Build the static tables for Verbs conversion. */
2234 mlx5_set_ptype_table();
2235 mlx5_set_cksum_table();
2236 mlx5_set_swp_types_table();
2238 mlx5_pci_driver_register(&mlx5_driver);
2241 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
2242 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
2243 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");