1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
13 #include <rte_malloc.h>
14 #include <ethdev_driver.h>
16 #include <rte_bus_pci.h>
17 #include <rte_common.h>
18 #include <rte_kvargs.h>
19 #include <rte_rwlock.h>
20 #include <rte_spinlock.h>
21 #include <rte_string_fns.h>
22 #include <rte_alarm.h>
23 #include <rte_cycles.h>
25 #include <mlx5_glue.h>
26 #include <mlx5_devx_cmds.h>
27 #include <mlx5_common.h>
28 #include <mlx5_common_os.h>
29 #include <mlx5_common_mp.h>
30 #include <mlx5_malloc.h>
32 #include "mlx5_defs.h"
34 #include "mlx5_utils.h"
35 #include "mlx5_rxtx.h"
38 #include "mlx5_autoconf.h"
40 #include "mlx5_flow.h"
41 #include "mlx5_flow_os.h"
42 #include "rte_pmd_mlx5.h"
44 #define MLX5_ETH_DRIVER_NAME mlx5_eth
46 /* Driver type key for new device global syntax. */
47 #define MLX5_DRIVER_KEY "driver"
49 /* Device parameter to enable RX completion queue compression. */
50 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
52 /* Device parameter to enable padding Rx packet to cacheline size. */
53 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
55 /* Device parameter to enable Multi-Packet Rx queue. */
56 #define MLX5_RX_MPRQ_EN "mprq_en"
58 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
59 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
61 /* Device parameter to configure log 2 of the stride size for MPRQ. */
62 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
64 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
65 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
67 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
68 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
70 /* Device parameter to configure inline send. Deprecated, ignored.*/
71 #define MLX5_TXQ_INLINE "txq_inline"
73 /* Device parameter to limit packet size to inline with ordinary SEND. */
74 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
76 /* Device parameter to configure minimal data size to inline. */
77 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
79 /* Device parameter to limit packet size to inline with Enhanced MPW. */
80 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
83 * Device parameter to configure the number of TX queues threshold for
84 * enabling inline send.
86 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
89 * Device parameter to configure the number of TX queues threshold for
90 * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
92 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
94 /* Device parameter to enable multi-packet send WQEs. */
95 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
98 * Device parameter to force doorbell register mapping
99 * to non-cahed region eliminating the extra write memory barrier.
101 #define MLX5_TX_DB_NC "tx_db_nc"
104 * Device parameter to include 2 dsegs in the title WQEBB.
105 * Deprecated, ignored.
107 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
110 * Device parameter to limit the size of inlining packet.
111 * Deprecated, ignored.
113 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
116 * Device parameter to enable Tx scheduling on timestamps
117 * and specify the packet pacing granularity in nanoseconds.
119 #define MLX5_TX_PP "tx_pp"
122 * Device parameter to specify skew in nanoseconds on Tx datapath,
123 * it represents the time between SQ start WQE processing and
124 * appearing actual packet data on the wire.
126 #define MLX5_TX_SKEW "tx_skew"
129 * Device parameter to enable hardware Tx vector.
130 * Deprecated, ignored (no vectorized Tx routines anymore).
132 #define MLX5_TX_VEC_EN "tx_vec_en"
134 /* Device parameter to enable hardware Rx vector. */
135 #define MLX5_RX_VEC_EN "rx_vec_en"
137 /* Allow L3 VXLAN flow creation. */
138 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
140 /* Activate DV E-Switch flow steering. */
141 #define MLX5_DV_ESW_EN "dv_esw_en"
143 /* Activate DV flow steering. */
144 #define MLX5_DV_FLOW_EN "dv_flow_en"
146 /* Enable extensive flow metadata support. */
147 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
149 /* Device parameter to let the user manage the lacp traffic of bonded device */
150 #define MLX5_LACP_BY_USER "lacp_by_user"
152 /* Activate Netlink support in VF mode. */
153 #define MLX5_VF_NL_EN "vf_nl_en"
155 /* Enable extending memsegs when creating a MR. */
156 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
158 /* Select port representors to instantiate. */
159 #define MLX5_REPRESENTOR "representor"
161 /* Device parameter to configure the maximum number of dump files per queue. */
162 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
164 /* Configure timeout of LRO session (in microseconds). */
165 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
168 * Device parameter to configure the total data buffer size for a single
169 * hairpin queue (logarithm value).
171 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
173 /* Flow memory reclaim mode. */
174 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
176 /* The default memory allocator used in PMD. */
177 #define MLX5_SYS_MEM_EN "sys_mem_en"
178 /* Decap will be used or not. */
179 #define MLX5_DECAP_EN "decap_en"
181 /* Device parameter to configure allow or prevent duplicate rules pattern. */
182 #define MLX5_ALLOW_DUPLICATE_PATTERN "allow_duplicate_pattern"
184 /* Device parameter to configure implicit registration of mempool memory. */
185 #define MLX5_MR_MEMPOOL_REG_EN "mr_mempool_reg_en"
187 /* Shared memory between primary and secondary processes. */
188 struct mlx5_shared_data *mlx5_shared_data;
190 /** Driver-specific log messages type. */
193 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
194 LIST_HEAD_INITIALIZER();
195 static pthread_mutex_t mlx5_dev_ctx_list_mutex;
196 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
197 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
198 [MLX5_IPOOL_DECAP_ENCAP] = {
199 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
205 .malloc = mlx5_malloc,
207 .type = "mlx5_encap_decap_ipool",
209 [MLX5_IPOOL_PUSH_VLAN] = {
210 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
216 .malloc = mlx5_malloc,
218 .type = "mlx5_push_vlan_ipool",
221 .size = sizeof(struct mlx5_flow_dv_tag_resource),
227 .per_core_cache = (1 << 16),
228 .malloc = mlx5_malloc,
230 .type = "mlx5_tag_ipool",
232 [MLX5_IPOOL_PORT_ID] = {
233 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
239 .malloc = mlx5_malloc,
241 .type = "mlx5_port_id_ipool",
243 [MLX5_IPOOL_JUMP] = {
244 .size = sizeof(struct mlx5_flow_tbl_data_entry),
250 .malloc = mlx5_malloc,
252 .type = "mlx5_jump_ipool",
254 [MLX5_IPOOL_SAMPLE] = {
255 .size = sizeof(struct mlx5_flow_dv_sample_resource),
261 .malloc = mlx5_malloc,
263 .type = "mlx5_sample_ipool",
265 [MLX5_IPOOL_DEST_ARRAY] = {
266 .size = sizeof(struct mlx5_flow_dv_dest_array_resource),
272 .malloc = mlx5_malloc,
274 .type = "mlx5_dest_array_ipool",
276 [MLX5_IPOOL_TUNNEL_ID] = {
277 .size = sizeof(struct mlx5_flow_tunnel),
278 .trunk_size = MLX5_MAX_TUNNELS,
281 .type = "mlx5_tunnel_offload",
283 [MLX5_IPOOL_TNL_TBL_ID] = {
286 .type = "mlx5_flow_tnl_tbl_ipool",
291 * The ipool index should grow continually from small to big,
292 * for meter idx, so not set grow_trunk to avoid meter index
293 * not jump continually.
295 .size = sizeof(struct mlx5_legacy_flow_meter),
299 .malloc = mlx5_malloc,
301 .type = "mlx5_meter_ipool",
304 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
310 .malloc = mlx5_malloc,
312 .type = "mlx5_mcp_ipool",
314 [MLX5_IPOOL_HRXQ] = {
315 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
321 .malloc = mlx5_malloc,
323 .type = "mlx5_hrxq_ipool",
325 [MLX5_IPOOL_MLX5_FLOW] = {
327 * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
328 * It set in run time according to PCI function configuration.
336 .per_core_cache = 1 << 19,
337 .malloc = mlx5_malloc,
339 .type = "mlx5_flow_handle_ipool",
341 [MLX5_IPOOL_RTE_FLOW] = {
342 .size = sizeof(struct rte_flow),
346 .malloc = mlx5_malloc,
348 .type = "rte_flow_ipool",
350 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID] = {
353 .type = "mlx5_flow_rss_id_ipool",
355 [MLX5_IPOOL_RSS_SHARED_ACTIONS] = {
356 .size = sizeof(struct mlx5_shared_action_rss),
362 .malloc = mlx5_malloc,
364 .type = "mlx5_shared_action_rss",
366 [MLX5_IPOOL_MTR_POLICY] = {
368 * The ipool index should grow continually from small to big,
369 * for policy idx, so not set grow_trunk to avoid policy index
370 * not jump continually.
372 .size = sizeof(struct mlx5_flow_meter_sub_policy),
376 .malloc = mlx5_malloc,
378 .type = "mlx5_meter_policy_ipool",
383 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
384 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
386 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 1024
389 * Decide whether representor ID is a HPF(host PF) port on BF2.
392 * Pointer to Ethernet device structure.
395 * Non-zero if HPF, otherwise 0.
398 mlx5_is_hpf(struct rte_eth_dev *dev)
400 struct mlx5_priv *priv = dev->data->dev_private;
401 uint16_t repr = MLX5_REPRESENTOR_REPR(priv->representor_id);
402 int type = MLX5_REPRESENTOR_TYPE(priv->representor_id);
404 return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_VF &&
405 MLX5_REPRESENTOR_REPR(-1) == repr;
409 * Decide whether representor ID is a SF port representor.
412 * Pointer to Ethernet device structure.
415 * Non-zero if HPF, otherwise 0.
418 mlx5_is_sf_repr(struct rte_eth_dev *dev)
420 struct mlx5_priv *priv = dev->data->dev_private;
421 int type = MLX5_REPRESENTOR_TYPE(priv->representor_id);
423 return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_SF;
427 * Initialize the ASO aging management structure.
430 * Pointer to mlx5_dev_ctx_shared object to free
433 * 0 on success, a negative errno value otherwise and rte_errno is set.
436 mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh)
442 sh->aso_age_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->aso_age_mng),
443 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
444 if (!sh->aso_age_mng) {
445 DRV_LOG(ERR, "aso_age_mng allocation was failed.");
449 err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_FLOW_HIT);
451 mlx5_free(sh->aso_age_mng);
454 rte_spinlock_init(&sh->aso_age_mng->resize_sl);
455 rte_spinlock_init(&sh->aso_age_mng->free_sl);
456 LIST_INIT(&sh->aso_age_mng->free);
461 * Close and release all the resources of the ASO aging management structure.
464 * Pointer to mlx5_dev_ctx_shared object to free.
467 mlx5_flow_aso_age_mng_close(struct mlx5_dev_ctx_shared *sh)
471 mlx5_aso_flow_hit_queue_poll_stop(sh);
472 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_FLOW_HIT);
473 if (sh->aso_age_mng->pools) {
474 struct mlx5_aso_age_pool *pool;
476 for (i = 0; i < sh->aso_age_mng->next; ++i) {
477 pool = sh->aso_age_mng->pools[i];
478 claim_zero(mlx5_devx_cmd_destroy
479 (pool->flow_hit_aso_obj));
480 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j)
481 if (pool->actions[j].dr_action)
483 (mlx5_flow_os_destroy_flow_action
484 (pool->actions[j].dr_action));
487 mlx5_free(sh->aso_age_mng->pools);
489 mlx5_free(sh->aso_age_mng);
493 * Initialize the shared aging list information per port.
496 * Pointer to mlx5_dev_ctx_shared object.
499 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
502 struct mlx5_age_info *age_info;
504 for (i = 0; i < sh->max_port; i++) {
505 age_info = &sh->port[i].age_info;
507 TAILQ_INIT(&age_info->aged_counters);
508 LIST_INIT(&age_info->aged_aso);
509 rte_spinlock_init(&age_info->aged_sl);
510 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
515 * Initialize the counters management structure.
518 * Pointer to mlx5_dev_ctx_shared object to free
521 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
525 memset(&sh->cmng, 0, sizeof(sh->cmng));
526 TAILQ_INIT(&sh->cmng.flow_counters);
527 sh->cmng.min_id = MLX5_CNT_BATCH_OFFSET;
528 sh->cmng.max_id = -1;
529 sh->cmng.last_pool_idx = POOL_IDX_INVALID;
530 rte_spinlock_init(&sh->cmng.pool_update_sl);
531 for (i = 0; i < MLX5_COUNTER_TYPE_MAX; i++) {
532 TAILQ_INIT(&sh->cmng.counters[i]);
533 rte_spinlock_init(&sh->cmng.csl[i]);
538 * Destroy all the resources allocated for a counter memory management.
541 * Pointer to the memory management structure.
544 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
546 uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
548 LIST_REMOVE(mng, next);
549 claim_zero(mlx5_devx_cmd_destroy(mng->dm));
550 claim_zero(mlx5_os_umem_dereg(mng->umem));
555 * Close and release all the resources of the counters management.
558 * Pointer to mlx5_dev_ctx_shared object to free.
561 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
563 struct mlx5_counter_stats_mem_mng *mng;
569 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
570 if (rte_errno != EINPROGRESS)
575 if (sh->cmng.pools) {
576 struct mlx5_flow_counter_pool *pool;
577 uint16_t n_valid = sh->cmng.n_valid;
578 bool fallback = sh->cmng.counter_fallback;
580 for (i = 0; i < n_valid; ++i) {
581 pool = sh->cmng.pools[i];
582 if (!fallback && pool->min_dcs)
583 claim_zero(mlx5_devx_cmd_destroy
585 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
586 struct mlx5_flow_counter *cnt =
587 MLX5_POOL_GET_CNT(pool, j);
591 (mlx5_flow_os_destroy_flow_action
593 if (fallback && MLX5_POOL_GET_CNT
594 (pool, j)->dcs_when_free)
595 claim_zero(mlx5_devx_cmd_destroy
596 (cnt->dcs_when_free));
600 mlx5_free(sh->cmng.pools);
602 mng = LIST_FIRST(&sh->cmng.mem_mngs);
604 mlx5_flow_destroy_counter_stat_mem_mng(mng);
605 mng = LIST_FIRST(&sh->cmng.mem_mngs);
607 memset(&sh->cmng, 0, sizeof(sh->cmng));
611 * Initialize the aso flow meters management structure.
614 * Pointer to mlx5_dev_ctx_shared object to free
617 mlx5_aso_flow_mtrs_mng_init(struct mlx5_dev_ctx_shared *sh)
620 sh->mtrmng = mlx5_malloc(MLX5_MEM_ZERO,
622 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
625 "meter management allocation was failed.");
629 if (sh->meter_aso_en) {
630 rte_spinlock_init(&sh->mtrmng->pools_mng.mtrsl);
631 LIST_INIT(&sh->mtrmng->pools_mng.meters);
633 sh->mtrmng->def_policy_id = MLX5_INVALID_POLICY_ID;
639 * Close and release all the resources of
640 * the ASO flow meter management structure.
643 * Pointer to mlx5_dev_ctx_shared object to free.
646 mlx5_aso_flow_mtrs_mng_close(struct mlx5_dev_ctx_shared *sh)
648 struct mlx5_aso_mtr_pool *mtr_pool;
649 struct mlx5_flow_mtr_mng *mtrmng = sh->mtrmng;
651 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
652 struct mlx5_aso_mtr *aso_mtr;
654 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
656 if (sh->meter_aso_en) {
657 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_POLICER);
658 idx = mtrmng->pools_mng.n_valid;
660 mtr_pool = mtrmng->pools_mng.pools[idx];
661 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
662 for (i = 0; i < MLX5_ASO_MTRS_PER_POOL; i++) {
663 aso_mtr = &mtr_pool->mtrs[i];
664 if (aso_mtr->fm.meter_action)
666 (mlx5_glue->destroy_flow_action
667 (aso_mtr->fm.meter_action));
669 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
670 claim_zero(mlx5_devx_cmd_destroy
671 (mtr_pool->devx_obj));
672 mtrmng->pools_mng.n_valid--;
675 mlx5_free(sh->mtrmng->pools_mng.pools);
677 mlx5_free(sh->mtrmng);
681 /* Send FLOW_AGED event if needed. */
683 mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh)
685 struct mlx5_age_info *age_info;
688 for (i = 0; i < sh->max_port; i++) {
689 age_info = &sh->port[i].age_info;
690 if (!MLX5_AGE_GET(age_info, MLX5_AGE_EVENT_NEW))
692 MLX5_AGE_UNSET(age_info, MLX5_AGE_EVENT_NEW);
693 if (MLX5_AGE_GET(age_info, MLX5_AGE_TRIGGER)) {
694 MLX5_AGE_UNSET(age_info, MLX5_AGE_TRIGGER);
695 rte_eth_dev_callback_process
696 (&rte_eth_devices[sh->port[i].devx_ih_port_id],
697 RTE_ETH_EVENT_FLOW_AGED, NULL);
703 * Initialize the ASO connection tracking structure.
706 * Pointer to mlx5_dev_ctx_shared object.
709 * 0 on success, a negative errno value otherwise and rte_errno is set.
712 mlx5_flow_aso_ct_mng_init(struct mlx5_dev_ctx_shared *sh)
718 sh->ct_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->ct_mng),
719 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
721 DRV_LOG(ERR, "ASO CT management allocation failed.");
725 err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_CONNECTION_TRACKING);
727 mlx5_free(sh->ct_mng);
728 /* rte_errno should be extracted from the failure. */
732 rte_spinlock_init(&sh->ct_mng->ct_sl);
733 rte_rwlock_init(&sh->ct_mng->resize_rwl);
734 LIST_INIT(&sh->ct_mng->free_cts);
739 * Close and release all the resources of the
740 * ASO connection tracking management structure.
743 * Pointer to mlx5_dev_ctx_shared object to free.
746 mlx5_flow_aso_ct_mng_close(struct mlx5_dev_ctx_shared *sh)
748 struct mlx5_aso_ct_pools_mng *mng = sh->ct_mng;
749 struct mlx5_aso_ct_pool *ct_pool;
750 struct mlx5_aso_ct_action *ct;
756 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_CONNECTION_TRACKING);
760 ct_pool = mng->pools[idx];
761 for (i = 0; i < MLX5_ASO_CT_ACTIONS_PER_POOL; i++) {
762 ct = &ct_pool->actions[i];
763 val = __atomic_fetch_sub(&ct->refcnt, 1,
765 MLX5_ASSERT(val == 1);
768 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
769 if (ct->dr_action_orig)
770 claim_zero(mlx5_glue->destroy_flow_action
771 (ct->dr_action_orig));
772 if (ct->dr_action_rply)
773 claim_zero(mlx5_glue->destroy_flow_action
774 (ct->dr_action_rply));
777 claim_zero(mlx5_devx_cmd_destroy(ct_pool->devx_obj));
779 DRV_LOG(DEBUG, "%u ASO CT objects are being used in the pool %u",
783 /* in case of failure. */
786 mlx5_free(mng->pools);
788 /* Management structure must be cleared to 0s during allocation. */
793 * Initialize the flow resources' indexed mempool.
796 * Pointer to mlx5_dev_ctx_shared object.
798 * Pointer to user dev config.
801 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
802 const struct mlx5_dev_config *config)
805 struct mlx5_indexed_pool_config cfg;
807 for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
808 cfg = mlx5_ipool_cfg[i];
813 * Set MLX5_IPOOL_MLX5_FLOW ipool size
814 * according to PCI function flow configuration.
816 case MLX5_IPOOL_MLX5_FLOW:
817 cfg.size = config->dv_flow_en ?
818 sizeof(struct mlx5_flow_handle) :
819 MLX5_FLOW_HANDLE_VERBS_SIZE;
822 if (config->reclaim_mode) {
823 cfg.release_mem_en = 1;
824 cfg.per_core_cache = 0;
826 cfg.release_mem_en = 0;
828 sh->ipool[i] = mlx5_ipool_create(&cfg);
834 * Release the flow resources' indexed mempool.
837 * Pointer to mlx5_dev_ctx_shared object.
840 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
844 for (i = 0; i < MLX5_IPOOL_MAX; ++i)
845 mlx5_ipool_destroy(sh->ipool[i]);
846 for (i = 0; i < MLX5_MAX_MODIFY_NUM; ++i)
847 if (sh->mdh_ipools[i])
848 mlx5_ipool_destroy(sh->mdh_ipools[i]);
852 * Check if dynamic flex parser for eCPRI already exists.
855 * Pointer to Ethernet device structure.
858 * true on exists, false on not.
861 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
863 struct mlx5_priv *priv = dev->data->dev_private;
864 struct mlx5_flex_parser_profiles *prf =
865 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
871 * Allocation of a flex parser for eCPRI. Once created, this parser related
872 * resources will be held until the device is closed.
875 * Pointer to Ethernet device structure.
878 * 0 on success, a negative errno value otherwise and rte_errno is set.
881 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
883 struct mlx5_priv *priv = dev->data->dev_private;
884 struct mlx5_flex_parser_profiles *prf =
885 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
886 struct mlx5_devx_graph_node_attr node = {
887 .modify_field_select = 0,
892 if (!priv->config.hca_attr.parse_graph_flex_node) {
893 DRV_LOG(ERR, "Dynamic flex parser is not supported "
894 "for device %s.", priv->dev_data->name);
897 node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED;
898 /* 8 bytes now: 4B common header + 4B message body header. */
899 node.header_length_base_value = 0x8;
900 /* After MAC layer: Ether / VLAN. */
901 node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC;
902 /* Type of compared condition should be 0xAEFE in the L2 layer. */
903 node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI;
904 /* Sample #0: type in common header. */
905 node.sample[0].flow_match_sample_en = 1;
907 node.sample[0].flow_match_sample_offset_mode = 0x0;
908 /* Only the 2nd byte will be used. */
909 node.sample[0].flow_match_sample_field_base_offset = 0x0;
910 /* Sample #1: message payload. */
911 node.sample[1].flow_match_sample_en = 1;
913 node.sample[1].flow_match_sample_offset_mode = 0x0;
915 * Only the first two bytes will be used right now, and its offset will
916 * start after the common header that with the length of a DW(u32).
918 node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);
919 prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->ctx, &node);
921 DRV_LOG(ERR, "Failed to create flex parser node object.");
922 return (rte_errno == 0) ? -ENODEV : -rte_errno;
925 ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num);
927 DRV_LOG(ERR, "Failed to query sample IDs.");
928 return (rte_errno == 0) ? -ENODEV : -rte_errno;
930 prf->offset[0] = 0x0;
931 prf->offset[1] = sizeof(uint32_t);
932 prf->ids[0] = ids[0];
933 prf->ids[1] = ids[1];
938 * Destroy the flex parser node, including the parser itself, input / output
939 * arcs and DW samples. Resources could be reused then.
942 * Pointer to Ethernet device structure.
945 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
947 struct mlx5_priv *priv = dev->data->dev_private;
948 struct mlx5_flex_parser_profiles *prf =
949 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
952 mlx5_devx_cmd_destroy(prf->obj);
957 mlx5_get_supported_sw_parsing_offloads(const struct mlx5_hca_attr *attr)
959 uint32_t sw_parsing_offloads = 0;
962 sw_parsing_offloads |= MLX5_SW_PARSING_CAP;
964 sw_parsing_offloads |= MLX5_SW_PARSING_CSUM_CAP;
967 sw_parsing_offloads |= MLX5_SW_PARSING_TSO_CAP;
969 return sw_parsing_offloads;
973 mlx5_get_supported_tunneling_offloads(const struct mlx5_hca_attr *attr)
975 uint32_t tn_offloads = 0;
977 if (attr->tunnel_stateless_vxlan)
978 tn_offloads |= MLX5_TUNNELED_OFFLOADS_VXLAN_CAP;
979 if (attr->tunnel_stateless_gre)
980 tn_offloads |= MLX5_TUNNELED_OFFLOADS_GRE_CAP;
981 if (attr->tunnel_stateless_geneve_rx)
982 tn_offloads |= MLX5_TUNNELED_OFFLOADS_GENEVE_CAP;
987 * Allocate Rx and Tx UARs in robust fashion.
988 * This routine handles the following UAR allocation issues:
990 * - tries to allocate the UAR with the most appropriate memory
991 * mapping type from the ones supported by the host
993 * - tries to allocate the UAR with non-NULL base address
994 * OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as
995 * UAR base address if UAR was not the first object in the UAR page.
996 * It caused the PMD failure and we should try to get another UAR
997 * till we get the first one with non-NULL base address returned.
1000 mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh,
1001 const struct mlx5_dev_config *config)
1003 uint32_t uar_mapping, retry;
1007 for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
1008 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
1009 /* Control the mapping type according to the settings. */
1010 uar_mapping = (config->dbnc == MLX5_TXDB_NCACHED) ?
1011 MLX5DV_UAR_ALLOC_TYPE_NC :
1012 MLX5DV_UAR_ALLOC_TYPE_BF;
1014 RTE_SET_USED(config);
1016 * It seems we have no way to control the memory mapping type
1017 * for the UAR, the default "Write-Combining" type is supposed.
1018 * The UAR initialization on queue creation queries the
1019 * actual mapping type done by Verbs/kernel and setups the
1020 * PMD datapath accordingly.
1024 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->ctx, uar_mapping);
1025 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
1027 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
1028 if (config->dbnc == MLX5_TXDB_CACHED ||
1029 config->dbnc == MLX5_TXDB_HEURISTIC)
1030 DRV_LOG(WARNING, "Devarg tx_db_nc setting "
1031 "is not supported by DevX");
1033 * In some environments like virtual machine
1034 * the Write Combining mapped might be not supported
1035 * and UAR allocation fails. We try "Non-Cached"
1036 * mapping for the case. The tx_burst routines take
1037 * the UAR mapping type into account on UAR setup
1038 * on queue creation.
1040 DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (BF)");
1041 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
1042 sh->tx_uar = mlx5_glue->devx_alloc_uar
1043 (sh->ctx, uar_mapping);
1044 } else if (!sh->tx_uar &&
1045 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_NC) {
1046 if (config->dbnc == MLX5_TXDB_NCACHED)
1047 DRV_LOG(WARNING, "Devarg tx_db_nc settings "
1048 "is not supported by DevX");
1050 * If Verbs/kernel does not support "Non-Cached"
1051 * try the "Write-Combining".
1053 DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (NC)");
1054 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_BF;
1055 sh->tx_uar = mlx5_glue->devx_alloc_uar
1056 (sh->ctx, uar_mapping);
1060 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (BF/NC)");
1064 base_addr = mlx5_os_get_devx_uar_base_addr(sh->tx_uar);
1068 * The UARs are allocated by rdma_core within the
1069 * IB device context, on context closure all UARs
1070 * will be freed, should be no memory/object leakage.
1072 DRV_LOG(DEBUG, "Retrying to allocate Tx DevX UAR");
1075 /* Check whether we finally succeeded with valid UAR allocation. */
1077 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (NULL base)");
1081 for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
1083 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
1084 (sh->ctx, uar_mapping);
1085 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
1086 if (!sh->devx_rx_uar &&
1087 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
1089 * Rx UAR is used to control interrupts only,
1090 * should be no datapath noticeable impact,
1091 * can try "Non-Cached" mapping safely.
1093 DRV_LOG(DEBUG, "Failed to allocate Rx DevX UAR (BF)");
1094 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
1095 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
1096 (sh->ctx, uar_mapping);
1099 if (!sh->devx_rx_uar) {
1100 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (BF/NC)");
1104 base_addr = mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar);
1108 * The UARs are allocated by rdma_core within the
1109 * IB device context, on context closure all UARs
1110 * will be freed, should be no memory/object leakage.
1112 DRV_LOG(DEBUG, "Retrying to allocate Rx DevX UAR");
1113 sh->devx_rx_uar = NULL;
1115 /* Check whether we finally succeeded with valid UAR allocation. */
1116 if (!sh->devx_rx_uar) {
1117 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (NULL base)");
1125 * Unregister the mempool from the protection domain.
1128 * Pointer to the device shared context.
1130 * Mempool being unregistered.
1133 mlx5_dev_ctx_shared_mempool_unregister(struct mlx5_dev_ctx_shared *sh,
1134 struct rte_mempool *mp)
1136 struct mlx5_mp_id mp_id;
1138 mlx5_mp_id_init(&mp_id, 0);
1139 if (mlx5_mr_mempool_unregister(&sh->share_cache, mp, &mp_id) < 0)
1140 DRV_LOG(WARNING, "Failed to unregister mempool %s for PD %p: %s",
1141 mp->name, sh->pd, rte_strerror(rte_errno));
1145 * rte_mempool_walk() callback to register mempools
1146 * for the protection domain.
1149 * The mempool being walked.
1151 * Pointer to the device shared context.
1154 mlx5_dev_ctx_shared_mempool_register_cb(struct rte_mempool *mp, void *arg)
1156 struct mlx5_dev_ctx_shared *sh = arg;
1157 struct mlx5_mp_id mp_id;
1160 mlx5_mp_id_init(&mp_id, 0);
1161 ret = mlx5_mr_mempool_register(&sh->share_cache, sh->pd, mp, &mp_id);
1162 if (ret < 0 && rte_errno != EEXIST)
1163 DRV_LOG(ERR, "Failed to register existing mempool %s for PD %p: %s",
1164 mp->name, sh->pd, rte_strerror(rte_errno));
1168 * rte_mempool_walk() callback to unregister mempools
1169 * from the protection domain.
1172 * The mempool being walked.
1174 * Pointer to the device shared context.
1177 mlx5_dev_ctx_shared_mempool_unregister_cb(struct rte_mempool *mp, void *arg)
1179 mlx5_dev_ctx_shared_mempool_unregister
1180 ((struct mlx5_dev_ctx_shared *)arg, mp);
1184 * Mempool life cycle callback for Ethernet devices.
1187 * Mempool life cycle event.
1189 * Associated mempool.
1191 * Pointer to a device shared context.
1194 mlx5_dev_ctx_shared_mempool_event_cb(enum rte_mempool_event event,
1195 struct rte_mempool *mp, void *arg)
1197 struct mlx5_dev_ctx_shared *sh = arg;
1198 struct mlx5_mp_id mp_id;
1201 case RTE_MEMPOOL_EVENT_READY:
1202 mlx5_mp_id_init(&mp_id, 0);
1203 if (mlx5_mr_mempool_register(&sh->share_cache, sh->pd, mp,
1205 DRV_LOG(ERR, "Failed to register new mempool %s for PD %p: %s",
1206 mp->name, sh->pd, rte_strerror(rte_errno));
1208 case RTE_MEMPOOL_EVENT_DESTROY:
1209 mlx5_dev_ctx_shared_mempool_unregister(sh, mp);
1215 * Callback used when implicit mempool registration is disabled
1216 * in order to track Rx mempool destruction.
1219 * Mempool life cycle event.
1221 * An Rx mempool registered explicitly when the port is started.
1223 * Pointer to a device shared context.
1226 mlx5_dev_ctx_shared_rx_mempool_event_cb(enum rte_mempool_event event,
1227 struct rte_mempool *mp, void *arg)
1229 struct mlx5_dev_ctx_shared *sh = arg;
1231 if (event == RTE_MEMPOOL_EVENT_DESTROY)
1232 mlx5_dev_ctx_shared_mempool_unregister(sh, mp);
1236 mlx5_dev_ctx_shared_mempool_subscribe(struct rte_eth_dev *dev)
1238 struct mlx5_priv *priv = dev->data->dev_private;
1239 struct mlx5_dev_ctx_shared *sh = priv->sh;
1242 /* Check if we only need to track Rx mempool destruction. */
1243 if (!priv->config.mr_mempool_reg_en) {
1244 ret = rte_mempool_event_callback_register
1245 (mlx5_dev_ctx_shared_rx_mempool_event_cb, sh);
1246 return ret == 0 || rte_errno == EEXIST ? 0 : ret;
1248 /* Callback for this shared context may be already registered. */
1249 ret = rte_mempool_event_callback_register
1250 (mlx5_dev_ctx_shared_mempool_event_cb, sh);
1251 if (ret != 0 && rte_errno != EEXIST)
1253 /* Register mempools only once for this shared context. */
1255 rte_mempool_walk(mlx5_dev_ctx_shared_mempool_register_cb, sh);
1260 * Allocate shared device context. If there is multiport device the
1261 * master and representors will share this context, if there is single
1262 * port dedicated device, the context will be used by only given
1263 * port due to unification.
1265 * Routine first searches the context for the specified device name,
1266 * if found the shared context assumed and reference counter is incremented.
1267 * If no context found the new one is created and initialized with specified
1268 * device context and parameters.
1271 * Pointer to the device attributes (name, port, etc).
1273 * Pointer to device configuration structure.
1276 * Pointer to mlx5_dev_ctx_shared object on success,
1277 * otherwise NULL and rte_errno is set.
1279 struct mlx5_dev_ctx_shared *
1280 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
1281 const struct mlx5_dev_config *config)
1283 struct mlx5_dev_ctx_shared *sh;
1286 struct mlx5_devx_tis_attr tis_attr = { 0 };
1289 /* Secondary process should not create the shared context. */
1290 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1291 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1292 /* Search for IB context by device name. */
1293 LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
1294 if (!strcmp(sh->ibdev_name,
1295 mlx5_os_get_dev_device_name(spawn->phys_dev))) {
1300 /* No device found, we have to create new shared context. */
1301 MLX5_ASSERT(spawn->max_port);
1302 sh = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
1303 sizeof(struct mlx5_dev_ctx_shared) +
1305 sizeof(struct mlx5_dev_shared_port),
1306 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
1308 DRV_LOG(ERR, "shared context allocation failure");
1312 sh->numa_node = spawn->numa_node;
1313 if (spawn->bond_info)
1314 sh->bond = *spawn->bond_info;
1315 err = mlx5_os_open_device(spawn, config, sh);
1318 err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
1320 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
1324 sh->max_port = spawn->max_port;
1325 sh->reclaim_mode = config->reclaim_mode;
1326 strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
1327 sizeof(sh->ibdev_name) - 1);
1328 strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
1329 sizeof(sh->ibdev_path) - 1);
1331 * Setting port_id to max unallowed value means
1332 * there is no interrupt subhandler installed for
1333 * the given port index i.
1335 for (i = 0; i < sh->max_port; i++) {
1336 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
1337 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
1339 sh->pd = mlx5_os_alloc_pd(sh->ctx);
1340 if (sh->pd == NULL) {
1341 DRV_LOG(ERR, "PD allocation failure");
1346 err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
1348 DRV_LOG(ERR, "Fail to extract pdn from PD");
1351 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
1353 DRV_LOG(ERR, "TD allocation failure");
1357 tis_attr.transport_domain = sh->td->id;
1358 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
1360 DRV_LOG(ERR, "TIS allocation failure");
1364 err = mlx5_alloc_rxtx_uars(sh, config);
1367 MLX5_ASSERT(sh->tx_uar);
1368 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->tx_uar));
1370 MLX5_ASSERT(sh->devx_rx_uar);
1371 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar));
1374 /* Initialize UAR access locks for 32bit implementations. */
1375 rte_spinlock_init(&sh->uar_lock_cq);
1376 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
1377 rte_spinlock_init(&sh->uar_lock[i]);
1380 * Once the device is added to the list of memory event
1381 * callback, its global MR cache table cannot be expanded
1382 * on the fly because of deadlock. If it overflows, lookup
1383 * should be done by searching MR list linearly, which is slow.
1385 * At this point the device is not added to the memory
1386 * event list yet, context is just being created.
1388 err = mlx5_mr_btree_init(&sh->share_cache.cache,
1389 MLX5_MR_BTREE_CACHE_N * 2,
1395 mlx5_os_set_reg_mr_cb(&sh->share_cache.reg_mr_cb,
1396 &sh->share_cache.dereg_mr_cb);
1397 mlx5_os_dev_shared_handler_install(sh);
1398 if (LIST_EMPTY(&mlx5_dev_ctx_list)) {
1399 err = mlx5_flow_os_init_workspace_once();
1403 mlx5_flow_aging_init(sh);
1404 mlx5_flow_counters_mng_init(sh);
1405 mlx5_flow_ipool_create(sh, config);
1406 /* Add device to memory callback list. */
1407 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1408 LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
1410 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1411 /* Add context to the global device list. */
1412 LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
1413 rte_spinlock_init(&sh->geneve_tlv_opt_sl);
1415 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1418 pthread_mutex_destroy(&sh->txpp.mutex);
1419 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1421 if (sh->share_cache.cache.table)
1422 mlx5_mr_btree_free(&sh->share_cache.cache);
1424 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1426 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1427 if (sh->devx_rx_uar)
1428 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1430 mlx5_glue->devx_free_uar(sh->tx_uar);
1432 claim_zero(mlx5_os_dealloc_pd(sh->pd));
1434 claim_zero(mlx5_glue->close_device(sh->ctx));
1436 MLX5_ASSERT(err > 0);
1442 * Free shared IB device context. Decrement counter and if zero free
1443 * all allocated resources and close handles.
1446 * Pointer to mlx5_dev_ctx_shared object to free
1449 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
1453 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1454 #ifdef RTE_LIBRTE_MLX5_DEBUG
1455 /* Check the object presence in the list. */
1456 struct mlx5_dev_ctx_shared *lctx;
1458 LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
1463 DRV_LOG(ERR, "Freeing non-existing shared IB context");
1468 MLX5_ASSERT(sh->refcnt);
1469 /* Secondary process should not free the shared context. */
1470 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1473 /* Stop watching for mempool events and unregister all mempools. */
1474 ret = rte_mempool_event_callback_unregister
1475 (mlx5_dev_ctx_shared_mempool_event_cb, sh);
1476 if (ret < 0 && rte_errno == ENOENT)
1477 ret = rte_mempool_event_callback_unregister
1478 (mlx5_dev_ctx_shared_rx_mempool_event_cb, sh);
1480 rte_mempool_walk(mlx5_dev_ctx_shared_mempool_unregister_cb,
1482 /* Remove from memory callback device list. */
1483 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1484 LIST_REMOVE(sh, mem_event_cb);
1485 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1486 /* Release created Memory Regions. */
1487 mlx5_mr_release_cache(&sh->share_cache);
1488 /* Remove context from the global device list. */
1489 LIST_REMOVE(sh, next);
1490 /* Release flow workspaces objects on the last device. */
1491 if (LIST_EMPTY(&mlx5_dev_ctx_list))
1492 mlx5_flow_os_release_workspace();
1493 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1495 * Ensure there is no async event handler installed.
1496 * Only primary process handles async device events.
1498 mlx5_flow_counters_mng_close(sh);
1499 if (sh->aso_age_mng) {
1500 mlx5_flow_aso_age_mng_close(sh);
1501 sh->aso_age_mng = NULL;
1504 mlx5_aso_flow_mtrs_mng_close(sh);
1505 mlx5_flow_ipool_destroy(sh);
1506 mlx5_os_dev_shared_handler_uninstall(sh);
1508 mlx5_glue->devx_free_uar(sh->tx_uar);
1512 claim_zero(mlx5_os_dealloc_pd(sh->pd));
1514 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1516 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1517 if (sh->devx_rx_uar)
1518 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1520 claim_zero(mlx5_glue->close_device(sh->ctx));
1521 MLX5_ASSERT(sh->geneve_tlv_option_resource == NULL);
1522 pthread_mutex_destroy(&sh->txpp.mutex);
1526 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1530 * Destroy table hash list.
1533 * Pointer to the private device data structure.
1536 mlx5_free_table_hash_list(struct mlx5_priv *priv)
1538 struct mlx5_dev_ctx_shared *sh = priv->sh;
1542 mlx5_hlist_destroy(sh->flow_tbls);
1543 sh->flow_tbls = NULL;
1547 * Initialize flow table hash list and create the root tables entry
1551 * Pointer to the private device data structure.
1554 * Zero on success, positive error code otherwise.
1557 mlx5_alloc_table_hash_list(struct mlx5_priv *priv __rte_unused)
1560 /* Tables are only used in DV and DR modes. */
1561 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
1562 struct mlx5_dev_ctx_shared *sh = priv->sh;
1563 char s[MLX5_NAME_SIZE];
1566 snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1567 sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE,
1569 flow_dv_tbl_create_cb,
1570 flow_dv_tbl_match_cb,
1571 flow_dv_tbl_remove_cb,
1572 flow_dv_tbl_clone_cb,
1573 flow_dv_tbl_clone_free_cb);
1574 if (!sh->flow_tbls) {
1575 DRV_LOG(ERR, "flow tables with hash creation failed.");
1579 #ifndef HAVE_MLX5DV_DR
1580 struct rte_flow_error error;
1581 struct rte_eth_dev *dev = &rte_eth_devices[priv->dev_data->port_id];
1584 * In case we have not DR support, the zero tables should be created
1585 * because DV expect to see them even if they cannot be created by
1588 if (!flow_dv_tbl_resource_get(dev, 0, 0, 0, 0,
1589 NULL, 0, 1, 0, &error) ||
1590 !flow_dv_tbl_resource_get(dev, 0, 1, 0, 0,
1591 NULL, 0, 1, 0, &error) ||
1592 !flow_dv_tbl_resource_get(dev, 0, 0, 1, 0,
1593 NULL, 0, 1, 0, &error)) {
1599 mlx5_free_table_hash_list(priv);
1600 #endif /* HAVE_MLX5DV_DR */
1606 * Retrieve integer value from environment variable.
1609 * Environment variable name.
1612 * Integer value, 0 if the variable is not set.
1615 mlx5_getenv_int(const char *name)
1617 const char *val = getenv(name);
1625 * DPDK callback to add udp tunnel port
1628 * A pointer to eth_dev
1629 * @param[in] udp_tunnel
1630 * A pointer to udp tunnel
1633 * 0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1636 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1637 struct rte_eth_udp_tunnel *udp_tunnel)
1639 MLX5_ASSERT(udp_tunnel != NULL);
1640 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1641 udp_tunnel->udp_port == 4789)
1643 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1644 udp_tunnel->udp_port == 4790)
1650 * Initialize process private data structure.
1653 * Pointer to Ethernet device structure.
1656 * 0 on success, a negative errno value otherwise and rte_errno is set.
1659 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1661 struct mlx5_priv *priv = dev->data->dev_private;
1662 struct mlx5_proc_priv *ppriv;
1665 mlx5_proc_priv_uninit(dev);
1667 * UAR register table follows the process private structure. BlueFlame
1668 * registers for Tx queues are stored in the table.
1671 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1672 ppriv = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, ppriv_size,
1673 RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1678 ppriv->uar_table_sz = priv->txqs_n;
1679 dev->process_private = ppriv;
1684 * Un-initialize process private data structure.
1687 * Pointer to Ethernet device structure.
1690 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1692 if (!dev->process_private)
1694 mlx5_free(dev->process_private);
1695 dev->process_private = NULL;
1699 * DPDK callback to close the device.
1701 * Destroy all queues and objects, free memory.
1704 * Pointer to Ethernet device structure.
1707 mlx5_dev_close(struct rte_eth_dev *dev)
1709 struct mlx5_priv *priv = dev->data->dev_private;
1713 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1714 /* Check if process_private released. */
1715 if (!dev->process_private)
1717 mlx5_tx_uar_uninit_secondary(dev);
1718 mlx5_proc_priv_uninit(dev);
1719 rte_eth_dev_release_port(dev);
1724 DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1726 ((priv->sh->ctx != NULL) ?
1727 mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
1729 * If default mreg copy action is removed at the stop stage,
1730 * the search will return none and nothing will be done anymore.
1732 mlx5_flow_stop_default(dev);
1733 mlx5_traffic_disable(dev);
1735 * If all the flows are already flushed in the device stop stage,
1736 * then this will return directly without any action.
1738 mlx5_flow_list_flush(dev, MLX5_FLOW_TYPE_GEN, true);
1739 mlx5_action_handle_flush(dev);
1740 mlx5_flow_meter_flush(dev, NULL);
1741 /* Prevent crashes when queues are still in use. */
1742 dev->rx_pkt_burst = removed_rx_burst;
1743 dev->tx_pkt_burst = removed_tx_burst;
1745 /* Disable datapath on secondary process. */
1746 mlx5_mp_os_req_stop_rxtx(dev);
1747 /* Free the eCPRI flex parser resource. */
1748 mlx5_flex_parser_ecpri_release(dev);
1749 if (priv->rxqs != NULL) {
1750 /* XXX race condition if mlx5_rx_burst() is still running. */
1751 rte_delay_us_sleep(1000);
1752 for (i = 0; (i != priv->rxqs_n); ++i)
1753 mlx5_rxq_release(dev, i);
1757 if (priv->representor) {
1758 /* Each representor has a dedicated interrupts handler */
1759 mlx5_free(dev->intr_handle);
1760 dev->intr_handle = NULL;
1762 if (priv->txqs != NULL) {
1763 /* XXX race condition if mlx5_tx_burst() is still running. */
1764 rte_delay_us_sleep(1000);
1765 for (i = 0; (i != priv->txqs_n); ++i)
1766 mlx5_txq_release(dev, i);
1770 mlx5_proc_priv_uninit(dev);
1771 if (priv->q_counters) {
1772 mlx5_devx_cmd_destroy(priv->q_counters);
1773 priv->q_counters = NULL;
1775 if (priv->drop_queue.hrxq)
1776 mlx5_drop_action_destroy(dev);
1777 if (priv->mreg_cp_tbl)
1778 mlx5_hlist_destroy(priv->mreg_cp_tbl);
1779 mlx5_mprq_free_mp(dev);
1780 if (priv->sh->ct_mng)
1781 mlx5_flow_aso_ct_mng_close(priv->sh);
1782 mlx5_os_free_shared_dr(priv);
1783 if (priv->rss_conf.rss_key != NULL)
1784 mlx5_free(priv->rss_conf.rss_key);
1785 if (priv->reta_idx != NULL)
1786 mlx5_free(priv->reta_idx);
1787 if (priv->config.vf)
1788 mlx5_os_mac_addr_flush(dev);
1789 if (priv->nl_socket_route >= 0)
1790 close(priv->nl_socket_route);
1791 if (priv->nl_socket_rdma >= 0)
1792 close(priv->nl_socket_rdma);
1793 if (priv->vmwa_context)
1794 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1795 ret = mlx5_hrxq_verify(dev);
1797 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1798 dev->data->port_id);
1799 ret = mlx5_ind_table_obj_verify(dev);
1801 DRV_LOG(WARNING, "port %u some indirection table still remain",
1802 dev->data->port_id);
1803 ret = mlx5_rxq_obj_verify(dev);
1805 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1806 dev->data->port_id);
1807 ret = mlx5_rxq_verify(dev);
1809 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1810 dev->data->port_id);
1811 ret = mlx5_txq_obj_verify(dev);
1813 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1814 dev->data->port_id);
1815 ret = mlx5_txq_verify(dev);
1817 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1818 dev->data->port_id);
1819 ret = mlx5_flow_verify(dev);
1821 DRV_LOG(WARNING, "port %u some flows still remain",
1822 dev->data->port_id);
1824 mlx5_list_destroy(priv->hrxqs);
1826 * Free the shared context in last turn, because the cleanup
1827 * routines above may use some shared fields, like
1828 * mlx5_os_mac_addr_flush() uses ibdev_path for retrieveing
1829 * ifindex if Netlink fails.
1831 mlx5_free_shared_dev_ctx(priv->sh);
1832 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1836 MLX5_ETH_FOREACH_DEV(port_id, dev->device) {
1837 struct mlx5_priv *opriv =
1838 rte_eth_devices[port_id].data->dev_private;
1841 opriv->domain_id != priv->domain_id ||
1842 &rte_eth_devices[port_id] == dev)
1848 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1850 memset(priv, 0, sizeof(*priv));
1851 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1853 * Reset mac_addrs to NULL such that it is not freed as part of
1854 * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1855 * it is freed when dev_private is freed.
1857 dev->data->mac_addrs = NULL;
1861 const struct eth_dev_ops mlx5_dev_ops = {
1862 .dev_configure = mlx5_dev_configure,
1863 .dev_start = mlx5_dev_start,
1864 .dev_stop = mlx5_dev_stop,
1865 .dev_set_link_down = mlx5_set_link_down,
1866 .dev_set_link_up = mlx5_set_link_up,
1867 .dev_close = mlx5_dev_close,
1868 .promiscuous_enable = mlx5_promiscuous_enable,
1869 .promiscuous_disable = mlx5_promiscuous_disable,
1870 .allmulticast_enable = mlx5_allmulticast_enable,
1871 .allmulticast_disable = mlx5_allmulticast_disable,
1872 .link_update = mlx5_link_update,
1873 .stats_get = mlx5_stats_get,
1874 .stats_reset = mlx5_stats_reset,
1875 .xstats_get = mlx5_xstats_get,
1876 .xstats_reset = mlx5_xstats_reset,
1877 .xstats_get_names = mlx5_xstats_get_names,
1878 .fw_version_get = mlx5_fw_version_get,
1879 .dev_infos_get = mlx5_dev_infos_get,
1880 .representor_info_get = mlx5_representor_info_get,
1881 .read_clock = mlx5_txpp_read_clock,
1882 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1883 .vlan_filter_set = mlx5_vlan_filter_set,
1884 .rx_queue_setup = mlx5_rx_queue_setup,
1885 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1886 .tx_queue_setup = mlx5_tx_queue_setup,
1887 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1888 .rx_queue_release = mlx5_rx_queue_release,
1889 .tx_queue_release = mlx5_tx_queue_release,
1890 .rx_queue_start = mlx5_rx_queue_start,
1891 .rx_queue_stop = mlx5_rx_queue_stop,
1892 .tx_queue_start = mlx5_tx_queue_start,
1893 .tx_queue_stop = mlx5_tx_queue_stop,
1894 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1895 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1896 .mac_addr_remove = mlx5_mac_addr_remove,
1897 .mac_addr_add = mlx5_mac_addr_add,
1898 .mac_addr_set = mlx5_mac_addr_set,
1899 .set_mc_addr_list = mlx5_set_mc_addr_list,
1900 .mtu_set = mlx5_dev_set_mtu,
1901 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1902 .vlan_offload_set = mlx5_vlan_offload_set,
1903 .reta_update = mlx5_dev_rss_reta_update,
1904 .reta_query = mlx5_dev_rss_reta_query,
1905 .rss_hash_update = mlx5_rss_hash_update,
1906 .rss_hash_conf_get = mlx5_rss_hash_conf_get,
1907 .flow_ops_get = mlx5_flow_ops_get,
1908 .rxq_info_get = mlx5_rxq_info_get,
1909 .txq_info_get = mlx5_txq_info_get,
1910 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1911 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1912 .rx_queue_intr_enable = mlx5_rx_intr_enable,
1913 .rx_queue_intr_disable = mlx5_rx_intr_disable,
1914 .is_removed = mlx5_is_removed,
1915 .udp_tunnel_port_add = mlx5_udp_tunnel_port_add,
1916 .get_module_info = mlx5_get_module_info,
1917 .get_module_eeprom = mlx5_get_module_eeprom,
1918 .hairpin_cap_get = mlx5_hairpin_cap_get,
1919 .mtr_ops_get = mlx5_flow_meter_ops_get,
1920 .hairpin_bind = mlx5_hairpin_bind,
1921 .hairpin_unbind = mlx5_hairpin_unbind,
1922 .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1923 .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1924 .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1925 .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1926 .get_monitor_addr = mlx5_get_monitor_addr,
1929 /* Available operations from secondary process. */
1930 const struct eth_dev_ops mlx5_dev_sec_ops = {
1931 .stats_get = mlx5_stats_get,
1932 .stats_reset = mlx5_stats_reset,
1933 .xstats_get = mlx5_xstats_get,
1934 .xstats_reset = mlx5_xstats_reset,
1935 .xstats_get_names = mlx5_xstats_get_names,
1936 .fw_version_get = mlx5_fw_version_get,
1937 .dev_infos_get = mlx5_dev_infos_get,
1938 .representor_info_get = mlx5_representor_info_get,
1939 .read_clock = mlx5_txpp_read_clock,
1940 .rx_queue_start = mlx5_rx_queue_start,
1941 .rx_queue_stop = mlx5_rx_queue_stop,
1942 .tx_queue_start = mlx5_tx_queue_start,
1943 .tx_queue_stop = mlx5_tx_queue_stop,
1944 .rxq_info_get = mlx5_rxq_info_get,
1945 .txq_info_get = mlx5_txq_info_get,
1946 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1947 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1948 .get_module_info = mlx5_get_module_info,
1949 .get_module_eeprom = mlx5_get_module_eeprom,
1952 /* Available operations in flow isolated mode. */
1953 const struct eth_dev_ops mlx5_dev_ops_isolate = {
1954 .dev_configure = mlx5_dev_configure,
1955 .dev_start = mlx5_dev_start,
1956 .dev_stop = mlx5_dev_stop,
1957 .dev_set_link_down = mlx5_set_link_down,
1958 .dev_set_link_up = mlx5_set_link_up,
1959 .dev_close = mlx5_dev_close,
1960 .promiscuous_enable = mlx5_promiscuous_enable,
1961 .promiscuous_disable = mlx5_promiscuous_disable,
1962 .allmulticast_enable = mlx5_allmulticast_enable,
1963 .allmulticast_disable = mlx5_allmulticast_disable,
1964 .link_update = mlx5_link_update,
1965 .stats_get = mlx5_stats_get,
1966 .stats_reset = mlx5_stats_reset,
1967 .xstats_get = mlx5_xstats_get,
1968 .xstats_reset = mlx5_xstats_reset,
1969 .xstats_get_names = mlx5_xstats_get_names,
1970 .fw_version_get = mlx5_fw_version_get,
1971 .dev_infos_get = mlx5_dev_infos_get,
1972 .representor_info_get = mlx5_representor_info_get,
1973 .read_clock = mlx5_txpp_read_clock,
1974 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1975 .vlan_filter_set = mlx5_vlan_filter_set,
1976 .rx_queue_setup = mlx5_rx_queue_setup,
1977 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1978 .tx_queue_setup = mlx5_tx_queue_setup,
1979 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1980 .rx_queue_release = mlx5_rx_queue_release,
1981 .tx_queue_release = mlx5_tx_queue_release,
1982 .rx_queue_start = mlx5_rx_queue_start,
1983 .rx_queue_stop = mlx5_rx_queue_stop,
1984 .tx_queue_start = mlx5_tx_queue_start,
1985 .tx_queue_stop = mlx5_tx_queue_stop,
1986 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1987 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1988 .mac_addr_remove = mlx5_mac_addr_remove,
1989 .mac_addr_add = mlx5_mac_addr_add,
1990 .mac_addr_set = mlx5_mac_addr_set,
1991 .set_mc_addr_list = mlx5_set_mc_addr_list,
1992 .mtu_set = mlx5_dev_set_mtu,
1993 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1994 .vlan_offload_set = mlx5_vlan_offload_set,
1995 .flow_ops_get = mlx5_flow_ops_get,
1996 .rxq_info_get = mlx5_rxq_info_get,
1997 .txq_info_get = mlx5_txq_info_get,
1998 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1999 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
2000 .rx_queue_intr_enable = mlx5_rx_intr_enable,
2001 .rx_queue_intr_disable = mlx5_rx_intr_disable,
2002 .is_removed = mlx5_is_removed,
2003 .get_module_info = mlx5_get_module_info,
2004 .get_module_eeprom = mlx5_get_module_eeprom,
2005 .hairpin_cap_get = mlx5_hairpin_cap_get,
2006 .mtr_ops_get = mlx5_flow_meter_ops_get,
2007 .hairpin_bind = mlx5_hairpin_bind,
2008 .hairpin_unbind = mlx5_hairpin_unbind,
2009 .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
2010 .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
2011 .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
2012 .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
2013 .get_monitor_addr = mlx5_get_monitor_addr,
2017 * Verify and store value for device argument.
2020 * Key argument to verify.
2022 * Value associated with key.
2027 * 0 on success, a negative errno value otherwise and rte_errno is set.
2030 mlx5_args_check(const char *key, const char *val, void *opaque)
2032 struct mlx5_dev_config *config = opaque;
2036 /* No-op, port representors are processed in mlx5_dev_spawn(). */
2037 if (!strcmp(MLX5_DRIVER_KEY, key) || !strcmp(MLX5_REPRESENTOR, key))
2040 tmp = strtol(val, NULL, 0);
2043 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
2046 if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
2047 /* Negative values are acceptable for some keys only. */
2049 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
2052 mod = tmp >= 0 ? tmp : -tmp;
2053 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
2054 if (tmp > MLX5_CQE_RESP_FORMAT_L34H_STRIDX) {
2055 DRV_LOG(ERR, "invalid CQE compression "
2056 "format parameter");
2060 config->cqe_comp = !!tmp;
2061 config->cqe_comp_fmt = tmp;
2062 } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
2063 config->hw_padding = !!tmp;
2064 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
2065 config->mprq.enabled = !!tmp;
2066 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
2067 config->mprq.stride_num_n = tmp;
2068 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
2069 config->mprq.stride_size_n = tmp;
2070 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
2071 config->mprq.max_memcpy_len = tmp;
2072 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
2073 config->mprq.min_rxqs_num = tmp;
2074 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
2075 DRV_LOG(WARNING, "%s: deprecated parameter,"
2076 " converted to txq_inline_max", key);
2077 config->txq_inline_max = tmp;
2078 } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
2079 config->txq_inline_max = tmp;
2080 } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
2081 config->txq_inline_min = tmp;
2082 } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
2083 config->txq_inline_mpw = tmp;
2084 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
2085 config->txqs_inline = tmp;
2086 } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
2087 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
2088 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
2089 config->mps = !!tmp;
2090 } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
2091 if (tmp != MLX5_TXDB_CACHED &&
2092 tmp != MLX5_TXDB_NCACHED &&
2093 tmp != MLX5_TXDB_HEURISTIC) {
2094 DRV_LOG(ERR, "invalid Tx doorbell "
2095 "mapping parameter");
2100 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
2101 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
2102 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
2103 DRV_LOG(WARNING, "%s: deprecated parameter,"
2104 " converted to txq_inline_mpw", key);
2105 config->txq_inline_mpw = tmp;
2106 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
2107 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
2108 } else if (strcmp(MLX5_TX_PP, key) == 0) {
2110 DRV_LOG(ERR, "Zero Tx packet pacing parameter");
2114 config->tx_pp = tmp;
2115 } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
2116 config->tx_skew = tmp;
2117 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
2118 config->rx_vec_en = !!tmp;
2119 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
2120 config->l3_vxlan_en = !!tmp;
2121 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
2122 config->vf_nl_en = !!tmp;
2123 } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
2124 config->dv_esw_en = !!tmp;
2125 } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
2126 config->dv_flow_en = !!tmp;
2127 } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
2128 if (tmp != MLX5_XMETA_MODE_LEGACY &&
2129 tmp != MLX5_XMETA_MODE_META16 &&
2130 tmp != MLX5_XMETA_MODE_META32 &&
2131 tmp != MLX5_XMETA_MODE_MISS_INFO) {
2132 DRV_LOG(ERR, "invalid extensive "
2133 "metadata parameter");
2137 if (tmp != MLX5_XMETA_MODE_MISS_INFO)
2138 config->dv_xmeta_en = tmp;
2140 config->dv_miss_info = 1;
2141 } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
2142 config->lacp_by_user = !!tmp;
2143 } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
2144 config->mr_ext_memseg_en = !!tmp;
2145 } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
2146 config->max_dump_files_num = tmp;
2147 } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
2148 config->lro.timeout = tmp;
2149 } else if (strcmp(RTE_DEVARGS_KEY_CLASS, key) == 0) {
2150 DRV_LOG(DEBUG, "class argument is %s.", val);
2151 } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
2152 config->log_hp_size = tmp;
2153 } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
2154 if (tmp != MLX5_RCM_NONE &&
2155 tmp != MLX5_RCM_LIGHT &&
2156 tmp != MLX5_RCM_AGGR) {
2157 DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
2161 config->reclaim_mode = tmp;
2162 } else if (strcmp(MLX5_SYS_MEM_EN, key) == 0) {
2163 config->sys_mem_en = !!tmp;
2164 } else if (strcmp(MLX5_DECAP_EN, key) == 0) {
2165 config->decap_en = !!tmp;
2166 } else if (strcmp(MLX5_ALLOW_DUPLICATE_PATTERN, key) == 0) {
2167 config->allow_duplicate_pattern = !!tmp;
2168 } else if (strcmp(MLX5_MR_MEMPOOL_REG_EN, key) == 0) {
2169 config->mr_mempool_reg_en = !!tmp;
2171 DRV_LOG(WARNING, "%s: unknown parameter", key);
2179 * Parse device parameters.
2182 * Pointer to device configuration structure.
2184 * Device arguments structure.
2187 * 0 on success, a negative errno value otherwise and rte_errno is set.
2190 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
2192 const char **params = (const char *[]){
2194 MLX5_RXQ_CQE_COMP_EN,
2195 MLX5_RXQ_PKT_PAD_EN,
2197 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
2198 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
2199 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
2202 MLX5_TXQ_INLINE_MIN,
2203 MLX5_TXQ_INLINE_MAX,
2204 MLX5_TXQ_INLINE_MPW,
2205 MLX5_TXQS_MIN_INLINE,
2208 MLX5_TXQ_MPW_HDR_DSEG_EN,
2209 MLX5_TXQ_MAX_INLINE_LEN,
2221 MLX5_MR_EXT_MEMSEG_EN,
2223 MLX5_MAX_DUMP_FILES_NUM,
2224 MLX5_LRO_TIMEOUT_USEC,
2225 RTE_DEVARGS_KEY_CLASS,
2230 MLX5_ALLOW_DUPLICATE_PATTERN,
2231 MLX5_MR_MEMPOOL_REG_EN,
2234 struct rte_kvargs *kvlist;
2238 if (devargs == NULL)
2240 /* Following UGLY cast is done to pass checkpatch. */
2241 kvlist = rte_kvargs_parse(devargs->args, params);
2242 if (kvlist == NULL) {
2246 /* Process parameters. */
2247 for (i = 0; (params[i] != NULL); ++i) {
2248 if (rte_kvargs_count(kvlist, params[i])) {
2249 ret = rte_kvargs_process(kvlist, params[i],
2250 mlx5_args_check, config);
2253 rte_kvargs_free(kvlist);
2258 rte_kvargs_free(kvlist);
2263 * Configures the minimal amount of data to inline into WQE
2264 * while sending packets.
2266 * - the txq_inline_min has the maximal priority, if this
2267 * key is specified in devargs
2268 * - if DevX is enabled the inline mode is queried from the
2269 * device (HCA attributes and NIC vport context if needed).
2270 * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
2271 * and none (0 bytes) for other NICs
2274 * Verbs device parameters (name, port, switch_info) to spawn.
2276 * Device configuration parameters.
2279 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
2280 struct mlx5_dev_config *config)
2282 if (config->txq_inline_min != MLX5_ARG_UNSET) {
2283 /* Application defines size of inlined data explicitly. */
2284 if (spawn->pci_dev != NULL) {
2285 switch (spawn->pci_dev->id.device_id) {
2286 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2287 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2288 if (config->txq_inline_min <
2289 (int)MLX5_INLINE_HSIZE_L2) {
2291 "txq_inline_mix aligned to minimal ConnectX-4 required value %d",
2292 (int)MLX5_INLINE_HSIZE_L2);
2293 config->txq_inline_min =
2294 MLX5_INLINE_HSIZE_L2;
2301 if (config->hca_attr.eth_net_offloads) {
2302 /* We have DevX enabled, inline mode queried successfully. */
2303 switch (config->hca_attr.wqe_inline_mode) {
2304 case MLX5_CAP_INLINE_MODE_L2:
2305 /* outer L2 header must be inlined. */
2306 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2308 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
2309 /* No inline data are required by NIC. */
2310 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2311 config->hw_vlan_insert =
2312 config->hca_attr.wqe_vlan_insert;
2313 DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
2315 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
2316 /* inline mode is defined by NIC vport context. */
2317 if (!config->hca_attr.eth_virt)
2319 switch (config->hca_attr.vport_inline_mode) {
2320 case MLX5_INLINE_MODE_NONE:
2321 config->txq_inline_min =
2322 MLX5_INLINE_HSIZE_NONE;
2324 case MLX5_INLINE_MODE_L2:
2325 config->txq_inline_min =
2326 MLX5_INLINE_HSIZE_L2;
2328 case MLX5_INLINE_MODE_IP:
2329 config->txq_inline_min =
2330 MLX5_INLINE_HSIZE_L3;
2332 case MLX5_INLINE_MODE_TCP_UDP:
2333 config->txq_inline_min =
2334 MLX5_INLINE_HSIZE_L4;
2336 case MLX5_INLINE_MODE_INNER_L2:
2337 config->txq_inline_min =
2338 MLX5_INLINE_HSIZE_INNER_L2;
2340 case MLX5_INLINE_MODE_INNER_IP:
2341 config->txq_inline_min =
2342 MLX5_INLINE_HSIZE_INNER_L3;
2344 case MLX5_INLINE_MODE_INNER_TCP_UDP:
2345 config->txq_inline_min =
2346 MLX5_INLINE_HSIZE_INNER_L4;
2351 if (spawn->pci_dev == NULL) {
2352 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2356 * We get here if we are unable to deduce
2357 * inline data size with DevX. Try PCI ID
2358 * to determine old NICs.
2360 switch (spawn->pci_dev->id.device_id) {
2361 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2362 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2363 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
2364 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
2365 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2366 config->hw_vlan_insert = 0;
2368 case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
2369 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
2370 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
2371 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
2373 * These NICs support VLAN insertion from WQE and
2374 * report the wqe_vlan_insert flag. But there is the bug
2375 * and PFC control may be broken, so disable feature.
2377 config->hw_vlan_insert = 0;
2378 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2381 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2385 DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
2389 * Configures the metadata mask fields in the shared context.
2392 * Pointer to Ethernet device.
2395 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
2397 struct mlx5_priv *priv = dev->data->dev_private;
2398 struct mlx5_dev_ctx_shared *sh = priv->sh;
2399 uint32_t meta, mark, reg_c0;
2401 reg_c0 = ~priv->vport_meta_mask;
2402 switch (priv->config.dv_xmeta_en) {
2403 case MLX5_XMETA_MODE_LEGACY:
2405 mark = MLX5_FLOW_MARK_MASK;
2407 case MLX5_XMETA_MODE_META16:
2408 meta = reg_c0 >> rte_bsf32(reg_c0);
2409 mark = MLX5_FLOW_MARK_MASK;
2411 case MLX5_XMETA_MODE_META32:
2413 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
2421 if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
2422 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
2423 sh->dv_mark_mask, mark);
2425 sh->dv_mark_mask = mark;
2426 if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
2427 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
2428 sh->dv_meta_mask, meta);
2430 sh->dv_meta_mask = meta;
2431 if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
2432 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
2433 sh->dv_meta_mask, reg_c0);
2435 sh->dv_regc0_mask = reg_c0;
2436 DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
2437 DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
2438 DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
2439 DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
2443 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
2445 static const char *const dynf_names[] = {
2446 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
2447 RTE_MBUF_DYNFLAG_METADATA_NAME,
2448 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
2452 if (n < RTE_DIM(dynf_names))
2454 for (i = 0; i < RTE_DIM(dynf_names); i++) {
2455 if (names[i] == NULL)
2457 strcpy(names[i], dynf_names[i]);
2459 return RTE_DIM(dynf_names);
2463 * Comparison callback to sort device data.
2465 * This is meant to be used with qsort().
2468 * Pointer to pointer to first data object.
2470 * Pointer to pointer to second data object.
2473 * 0 if both objects are equal, less than 0 if the first argument is less
2474 * than the second, greater than 0 otherwise.
2477 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
2478 struct mlx5_dev_config *config,
2479 struct rte_device *dpdk_dev)
2481 struct mlx5_dev_ctx_shared *sh = priv->sh;
2482 struct mlx5_dev_config *sh_conf = NULL;
2486 /* Nothing to compare for the single/first device. */
2487 if (sh->refcnt == 1)
2489 /* Find the device with shared context. */
2490 MLX5_ETH_FOREACH_DEV(port_id, dpdk_dev) {
2491 struct mlx5_priv *opriv =
2492 rte_eth_devices[port_id].data->dev_private;
2494 if (opriv && opriv != priv && opriv->sh == sh) {
2495 sh_conf = &opriv->config;
2501 if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
2502 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
2503 " for shared %s context", sh->ibdev_name);
2507 if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
2508 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
2509 " for shared %s context", sh->ibdev_name);
2517 * Look for the ethernet device belonging to mlx5 driver.
2519 * @param[in] port_id
2520 * port_id to start looking for device.
2522 * Pointer to the hint device. When device is being probed
2523 * the its siblings (master and preceding representors might
2524 * not have assigned driver yet (because the mlx5_os_pci_probe()
2525 * is not completed yet, for this case match on hint
2526 * device may be used to detect sibling device.
2529 * port_id of found device, RTE_MAX_ETHPORT if not found.
2532 mlx5_eth_find_next(uint16_t port_id, struct rte_device *odev)
2534 while (port_id < RTE_MAX_ETHPORTS) {
2535 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
2537 if (dev->state != RTE_ETH_DEV_UNUSED &&
2539 (dev->device == odev ||
2540 (dev->device->driver &&
2541 dev->device->driver->name &&
2542 ((strcmp(dev->device->driver->name,
2543 MLX5_PCI_DRIVER_NAME) == 0) ||
2544 (strcmp(dev->device->driver->name,
2545 MLX5_AUXILIARY_DRIVER_NAME) == 0)))))
2549 if (port_id >= RTE_MAX_ETHPORTS)
2550 return RTE_MAX_ETHPORTS;
2555 * Callback to remove a device.
2557 * This function removes all Ethernet devices belong to a given device.
2560 * Pointer to the generic device.
2563 * 0 on success, the function cannot fail.
2566 mlx5_net_remove(struct rte_device *dev)
2571 RTE_ETH_FOREACH_DEV_OF(port_id, dev) {
2573 * mlx5_dev_close() is not registered to secondary process,
2574 * call the close function explicitly for secondary process.
2576 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
2577 ret |= mlx5_dev_close(&rte_eth_devices[port_id]);
2579 ret |= rte_eth_dev_close(port_id);
2581 return ret == 0 ? 0 : -EIO;
2584 static const struct rte_pci_id mlx5_pci_id_map[] = {
2586 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2587 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
2590 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2591 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
2594 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2595 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
2598 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2599 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
2602 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2603 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
2606 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2607 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
2610 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2611 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
2614 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2615 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
2618 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2619 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
2622 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2623 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
2626 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2627 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
2630 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2631 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
2634 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2635 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
2638 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2639 PCI_DEVICE_ID_MELLANOX_CONNECTXVF)
2642 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2643 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
2646 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2647 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
2650 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2651 PCI_DEVICE_ID_MELLANOX_CONNECTX7)
2654 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2655 PCI_DEVICE_ID_MELLANOX_CONNECTX7BF)
2662 static struct mlx5_class_driver mlx5_net_driver = {
2663 .drv_class = MLX5_CLASS_ETH,
2664 .name = RTE_STR(MLX5_ETH_DRIVER_NAME),
2665 .id_table = mlx5_pci_id_map,
2666 .probe = mlx5_os_net_probe,
2667 .remove = mlx5_net_remove,
2668 .dma_map = mlx5_net_dma_map,
2669 .dma_unmap = mlx5_net_dma_unmap,
2675 /* Initialize driver log type. */
2676 RTE_LOG_REGISTER_DEFAULT(mlx5_logtype, NOTICE)
2679 * Driver initialization routine.
2681 RTE_INIT(rte_mlx5_pmd_init)
2683 pthread_mutex_init(&mlx5_dev_ctx_list_mutex, NULL);
2685 /* Build the static tables for Verbs conversion. */
2686 mlx5_set_ptype_table();
2687 mlx5_set_cksum_table();
2688 mlx5_set_swp_types_table();
2690 mlx5_class_driver_register(&mlx5_net_driver);
2693 RTE_PMD_EXPORT_NAME(MLX5_ETH_DRIVER_NAME, __COUNTER__);
2694 RTE_PMD_REGISTER_PCI_TABLE(MLX5_ETH_DRIVER_NAME, mlx5_pci_id_map);
2695 RTE_PMD_REGISTER_KMOD_DEP(MLX5_ETH_DRIVER_NAME, "* ib_uverbs & mlx5_core & mlx5_ib");