1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
16 #include <linux/netlink.h>
17 #include <linux/rtnetlink.h>
20 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
22 #pragma GCC diagnostic ignored "-Wpedantic"
24 #include <infiniband/verbs.h>
26 #pragma GCC diagnostic error "-Wpedantic"
29 #include <rte_malloc.h>
30 #include <rte_ethdev_driver.h>
31 #include <rte_ethdev_pci.h>
33 #include <rte_bus_pci.h>
34 #include <rte_common.h>
35 #include <rte_config.h>
36 #include <rte_eal_memconfig.h>
37 #include <rte_kvargs.h>
38 #include <rte_rwlock.h>
39 #include <rte_spinlock.h>
40 #include <rte_string_fns.h>
43 #include "mlx5_utils.h"
44 #include "mlx5_rxtx.h"
45 #include "mlx5_autoconf.h"
46 #include "mlx5_defs.h"
47 #include "mlx5_glue.h"
49 #include "mlx5_flow.h"
51 /* Device parameter to enable RX completion queue compression. */
52 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
54 /* Device parameter to enable Multi-Packet Rx queue. */
55 #define MLX5_RX_MPRQ_EN "mprq_en"
57 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
58 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
60 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
61 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
63 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
64 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
66 /* Device parameter to configure inline send. */
67 #define MLX5_TXQ_INLINE "txq_inline"
70 * Device parameter to configure the number of TX queues threshold for
71 * enabling inline send.
73 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
75 /* Device parameter to enable multi-packet send WQEs. */
76 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
78 /* Device parameter to include 2 dsegs in the title WQEBB. */
79 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
81 /* Device parameter to limit the size of inlining packet. */
82 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
84 /* Device parameter to enable hardware Tx vector. */
85 #define MLX5_TX_VEC_EN "tx_vec_en"
87 /* Device parameter to enable hardware Rx vector. */
88 #define MLX5_RX_VEC_EN "rx_vec_en"
90 /* Allow L3 VXLAN flow creation. */
91 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
93 /* Activate Netlink support in VF mode. */
94 #define MLX5_VF_NL_EN "vf_nl_en"
96 /* Select port representors to instantiate. */
97 #define MLX5_REPRESENTOR "representor"
99 #ifndef HAVE_IBV_MLX5_MOD_MPW
100 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2)
101 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3)
104 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP
105 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4)
108 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
110 /* Shared memory between primary and secondary processes. */
111 struct mlx5_shared_data *mlx5_shared_data;
113 /* Spinlock for mlx5_shared_data allocation. */
114 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
116 /** Driver-specific log messages type. */
120 * Prepare shared data between primary and secondary process.
123 mlx5_prepare_shared_data(void)
125 const struct rte_memzone *mz;
127 rte_spinlock_lock(&mlx5_shared_data_lock);
128 if (mlx5_shared_data == NULL) {
129 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
130 /* Allocate shared memory. */
131 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
132 sizeof(*mlx5_shared_data),
135 /* Lookup allocated shared memory. */
136 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA);
139 rte_panic("Cannot allocate mlx5 shared data\n");
140 mlx5_shared_data = mz->addr;
141 /* Initialize shared data. */
142 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
143 LIST_INIT(&mlx5_shared_data->mem_event_cb_list);
144 rte_rwlock_init(&mlx5_shared_data->mem_event_rwlock);
146 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
147 mlx5_mr_mem_event_cb, NULL);
149 rte_spinlock_unlock(&mlx5_shared_data_lock);
153 * Retrieve integer value from environment variable.
156 * Environment variable name.
159 * Integer value, 0 if the variable is not set.
162 mlx5_getenv_int(const char *name)
164 const char *val = getenv(name);
172 * Verbs callback to allocate a memory. This function should allocate the space
173 * according to the size provided residing inside a huge page.
174 * Please note that all allocation must respect the alignment from libmlx5
175 * (i.e. currently sysconf(_SC_PAGESIZE)).
178 * The size in bytes of the memory to allocate.
180 * A pointer to the callback data.
183 * Allocated buffer, NULL otherwise and rte_errno is set.
186 mlx5_alloc_verbs_buf(size_t size, void *data)
188 struct priv *priv = data;
190 size_t alignment = sysconf(_SC_PAGESIZE);
191 unsigned int socket = SOCKET_ID_ANY;
193 if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) {
194 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
196 socket = ctrl->socket;
197 } else if (priv->verbs_alloc_ctx.type ==
198 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) {
199 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
201 socket = ctrl->socket;
203 assert(data != NULL);
204 ret = rte_malloc_socket(__func__, size, alignment, socket);
211 * Verbs callback to free a memory.
214 * A pointer to the memory to free.
216 * A pointer to the callback data.
219 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused)
221 assert(data != NULL);
226 * DPDK callback to close the device.
228 * Destroy all queues and objects, free memory.
231 * Pointer to Ethernet device structure.
234 mlx5_dev_close(struct rte_eth_dev *dev)
236 struct priv *priv = dev->data->dev_private;
240 DRV_LOG(DEBUG, "port %u closing device \"%s\"",
242 ((priv->ctx != NULL) ? priv->ctx->device->name : ""));
243 /* In case mlx5_dev_stop() has not been called. */
244 mlx5_dev_interrupt_handler_uninstall(dev);
245 mlx5_traffic_disable(dev);
246 mlx5_flow_flush(dev, NULL);
247 /* Prevent crashes when queues are still in use. */
248 dev->rx_pkt_burst = removed_rx_burst;
249 dev->tx_pkt_burst = removed_tx_burst;
250 if (priv->rxqs != NULL) {
251 /* XXX race condition if mlx5_rx_burst() is still running. */
253 for (i = 0; (i != priv->rxqs_n); ++i)
254 mlx5_rxq_release(dev, i);
258 if (priv->txqs != NULL) {
259 /* XXX race condition if mlx5_tx_burst() is still running. */
261 for (i = 0; (i != priv->txqs_n); ++i)
262 mlx5_txq_release(dev, i);
266 mlx5_mprq_free_mp(dev);
267 mlx5_mr_release(dev);
268 if (priv->pd != NULL) {
269 assert(priv->ctx != NULL);
270 claim_zero(mlx5_glue->dealloc_pd(priv->pd));
271 claim_zero(mlx5_glue->close_device(priv->ctx));
273 assert(priv->ctx == NULL);
274 if (priv->rss_conf.rss_key != NULL)
275 rte_free(priv->rss_conf.rss_key);
276 if (priv->reta_idx != NULL)
277 rte_free(priv->reta_idx);
278 if (priv->primary_socket)
279 mlx5_socket_uninit(dev);
281 mlx5_nl_mac_addr_flush(dev);
282 if (priv->nl_socket_route >= 0)
283 close(priv->nl_socket_route);
284 if (priv->nl_socket_rdma >= 0)
285 close(priv->nl_socket_rdma);
286 if (priv->mnl_socket)
287 mlx5_nl_flow_socket_destroy(priv->mnl_socket);
288 ret = mlx5_hrxq_ibv_verify(dev);
290 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
292 ret = mlx5_ind_table_ibv_verify(dev);
294 DRV_LOG(WARNING, "port %u some indirection table still remain",
296 ret = mlx5_rxq_ibv_verify(dev);
298 DRV_LOG(WARNING, "port %u some Verbs Rx queue still remain",
300 ret = mlx5_rxq_verify(dev);
302 DRV_LOG(WARNING, "port %u some Rx queues still remain",
304 ret = mlx5_txq_ibv_verify(dev);
306 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
308 ret = mlx5_txq_verify(dev);
310 DRV_LOG(WARNING, "port %u some Tx queues still remain",
312 ret = mlx5_flow_verify(dev);
314 DRV_LOG(WARNING, "port %u some flows still remain",
316 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
318 unsigned int i = mlx5_dev_to_port_id(dev->device, NULL, 0);
321 i = RTE_MIN(mlx5_dev_to_port_id(dev->device, port_id, i), i);
324 rte_eth_devices[port_id[i]].data->dev_private;
327 opriv->domain_id != priv->domain_id ||
328 &rte_eth_devices[port_id[i]] == dev)
333 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
335 memset(priv, 0, sizeof(*priv));
336 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
339 const struct eth_dev_ops mlx5_dev_ops = {
340 .dev_configure = mlx5_dev_configure,
341 .dev_start = mlx5_dev_start,
342 .dev_stop = mlx5_dev_stop,
343 .dev_set_link_down = mlx5_set_link_down,
344 .dev_set_link_up = mlx5_set_link_up,
345 .dev_close = mlx5_dev_close,
346 .promiscuous_enable = mlx5_promiscuous_enable,
347 .promiscuous_disable = mlx5_promiscuous_disable,
348 .allmulticast_enable = mlx5_allmulticast_enable,
349 .allmulticast_disable = mlx5_allmulticast_disable,
350 .link_update = mlx5_link_update,
351 .stats_get = mlx5_stats_get,
352 .stats_reset = mlx5_stats_reset,
353 .xstats_get = mlx5_xstats_get,
354 .xstats_reset = mlx5_xstats_reset,
355 .xstats_get_names = mlx5_xstats_get_names,
356 .dev_infos_get = mlx5_dev_infos_get,
357 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
358 .vlan_filter_set = mlx5_vlan_filter_set,
359 .rx_queue_setup = mlx5_rx_queue_setup,
360 .tx_queue_setup = mlx5_tx_queue_setup,
361 .rx_queue_release = mlx5_rx_queue_release,
362 .tx_queue_release = mlx5_tx_queue_release,
363 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
364 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
365 .mac_addr_remove = mlx5_mac_addr_remove,
366 .mac_addr_add = mlx5_mac_addr_add,
367 .mac_addr_set = mlx5_mac_addr_set,
368 .set_mc_addr_list = mlx5_set_mc_addr_list,
369 .mtu_set = mlx5_dev_set_mtu,
370 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
371 .vlan_offload_set = mlx5_vlan_offload_set,
372 .reta_update = mlx5_dev_rss_reta_update,
373 .reta_query = mlx5_dev_rss_reta_query,
374 .rss_hash_update = mlx5_rss_hash_update,
375 .rss_hash_conf_get = mlx5_rss_hash_conf_get,
376 .filter_ctrl = mlx5_dev_filter_ctrl,
377 .rx_descriptor_status = mlx5_rx_descriptor_status,
378 .tx_descriptor_status = mlx5_tx_descriptor_status,
379 .rx_queue_intr_enable = mlx5_rx_intr_enable,
380 .rx_queue_intr_disable = mlx5_rx_intr_disable,
381 .is_removed = mlx5_is_removed,
384 static const struct eth_dev_ops mlx5_dev_sec_ops = {
385 .stats_get = mlx5_stats_get,
386 .stats_reset = mlx5_stats_reset,
387 .xstats_get = mlx5_xstats_get,
388 .xstats_reset = mlx5_xstats_reset,
389 .xstats_get_names = mlx5_xstats_get_names,
390 .dev_infos_get = mlx5_dev_infos_get,
391 .rx_descriptor_status = mlx5_rx_descriptor_status,
392 .tx_descriptor_status = mlx5_tx_descriptor_status,
395 /* Available operators in flow isolated mode. */
396 const struct eth_dev_ops mlx5_dev_ops_isolate = {
397 .dev_configure = mlx5_dev_configure,
398 .dev_start = mlx5_dev_start,
399 .dev_stop = mlx5_dev_stop,
400 .dev_set_link_down = mlx5_set_link_down,
401 .dev_set_link_up = mlx5_set_link_up,
402 .dev_close = mlx5_dev_close,
403 .promiscuous_enable = mlx5_promiscuous_enable,
404 .promiscuous_disable = mlx5_promiscuous_disable,
405 .allmulticast_enable = mlx5_allmulticast_enable,
406 .allmulticast_disable = mlx5_allmulticast_disable,
407 .link_update = mlx5_link_update,
408 .stats_get = mlx5_stats_get,
409 .stats_reset = mlx5_stats_reset,
410 .xstats_get = mlx5_xstats_get,
411 .xstats_reset = mlx5_xstats_reset,
412 .xstats_get_names = mlx5_xstats_get_names,
413 .dev_infos_get = mlx5_dev_infos_get,
414 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
415 .vlan_filter_set = mlx5_vlan_filter_set,
416 .rx_queue_setup = mlx5_rx_queue_setup,
417 .tx_queue_setup = mlx5_tx_queue_setup,
418 .rx_queue_release = mlx5_rx_queue_release,
419 .tx_queue_release = mlx5_tx_queue_release,
420 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
421 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
422 .mac_addr_remove = mlx5_mac_addr_remove,
423 .mac_addr_add = mlx5_mac_addr_add,
424 .mac_addr_set = mlx5_mac_addr_set,
425 .set_mc_addr_list = mlx5_set_mc_addr_list,
426 .mtu_set = mlx5_dev_set_mtu,
427 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
428 .vlan_offload_set = mlx5_vlan_offload_set,
429 .filter_ctrl = mlx5_dev_filter_ctrl,
430 .rx_descriptor_status = mlx5_rx_descriptor_status,
431 .tx_descriptor_status = mlx5_tx_descriptor_status,
432 .rx_queue_intr_enable = mlx5_rx_intr_enable,
433 .rx_queue_intr_disable = mlx5_rx_intr_disable,
434 .is_removed = mlx5_is_removed,
438 * Verify and store value for device argument.
441 * Key argument to verify.
443 * Value associated with key.
448 * 0 on success, a negative errno value otherwise and rte_errno is set.
451 mlx5_args_check(const char *key, const char *val, void *opaque)
453 struct mlx5_dev_config *config = opaque;
456 /* No-op, port representors are processed in mlx5_dev_spawn(). */
457 if (!strcmp(MLX5_REPRESENTOR, key))
460 tmp = strtoul(val, NULL, 0);
463 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
466 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
467 config->cqe_comp = !!tmp;
468 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
469 config->mprq.enabled = !!tmp;
470 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
471 config->mprq.stride_num_n = tmp;
472 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
473 config->mprq.max_memcpy_len = tmp;
474 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
475 config->mprq.min_rxqs_num = tmp;
476 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
477 config->txq_inline = tmp;
478 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
479 config->txqs_inline = tmp;
480 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
482 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
483 config->mpw_hdr_dseg = !!tmp;
484 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
485 config->inline_max_packet_sz = tmp;
486 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
487 config->tx_vec_en = !!tmp;
488 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
489 config->rx_vec_en = !!tmp;
490 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
491 config->l3_vxlan_en = !!tmp;
492 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
493 config->vf_nl_en = !!tmp;
495 DRV_LOG(WARNING, "%s: unknown parameter", key);
503 * Parse device parameters.
506 * Pointer to device configuration structure.
508 * Device arguments structure.
511 * 0 on success, a negative errno value otherwise and rte_errno is set.
514 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
516 const char **params = (const char *[]){
517 MLX5_RXQ_CQE_COMP_EN,
519 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
520 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
523 MLX5_TXQS_MIN_INLINE,
525 MLX5_TXQ_MPW_HDR_DSEG_EN,
526 MLX5_TXQ_MAX_INLINE_LEN,
534 struct rte_kvargs *kvlist;
540 /* Following UGLY cast is done to pass checkpatch. */
541 kvlist = rte_kvargs_parse(devargs->args, params);
544 /* Process parameters. */
545 for (i = 0; (params[i] != NULL); ++i) {
546 if (rte_kvargs_count(kvlist, params[i])) {
547 ret = rte_kvargs_process(kvlist, params[i],
548 mlx5_args_check, config);
551 rte_kvargs_free(kvlist);
556 rte_kvargs_free(kvlist);
560 static struct rte_pci_driver mlx5_driver;
563 * Reserved UAR address space for TXQ UAR(hw doorbell) mapping, process
564 * local resource used by both primary and secondary to avoid duplicate
566 * The space has to be available on both primary and secondary process,
567 * TXQ UAR maps to this area using fixed mmap w/o double check.
569 static void *uar_base;
572 find_lower_va_bound(const struct rte_memseg_list *msl,
573 const struct rte_memseg *ms, void *arg)
582 *addr = RTE_MIN(*addr, ms->addr);
588 * Reserve UAR address space for primary process.
591 * Pointer to Ethernet device.
594 * 0 on success, a negative errno value otherwise and rte_errno is set.
597 mlx5_uar_init_primary(struct rte_eth_dev *dev)
599 struct priv *priv = dev->data->dev_private;
600 void *addr = (void *)0;
602 if (uar_base) { /* UAR address space mapped. */
603 priv->uar_base = uar_base;
606 /* find out lower bound of hugepage segments */
607 rte_memseg_walk(find_lower_va_bound, &addr);
609 /* keep distance to hugepages to minimize potential conflicts. */
610 addr = RTE_PTR_SUB(addr, (uintptr_t)(MLX5_UAR_OFFSET + MLX5_UAR_SIZE));
611 /* anonymous mmap, no real memory consumption. */
612 addr = mmap(addr, MLX5_UAR_SIZE,
613 PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
614 if (addr == MAP_FAILED) {
616 "port %u failed to reserve UAR address space, please"
617 " adjust MLX5_UAR_SIZE or try --base-virtaddr",
622 /* Accept either same addr or a new addr returned from mmap if target
625 DRV_LOG(INFO, "port %u reserved UAR address space: %p",
626 dev->data->port_id, addr);
627 priv->uar_base = addr; /* for primary and secondary UAR re-mmap. */
628 uar_base = addr; /* process local, don't reserve again. */
633 * Reserve UAR address space for secondary process, align with
637 * Pointer to Ethernet device.
640 * 0 on success, a negative errno value otherwise and rte_errno is set.
643 mlx5_uar_init_secondary(struct rte_eth_dev *dev)
645 struct priv *priv = dev->data->dev_private;
648 assert(priv->uar_base);
649 if (uar_base) { /* already reserved. */
650 assert(uar_base == priv->uar_base);
653 /* anonymous mmap, no real memory consumption. */
654 addr = mmap(priv->uar_base, MLX5_UAR_SIZE,
655 PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
656 if (addr == MAP_FAILED) {
657 DRV_LOG(ERR, "port %u UAR mmap failed: %p size: %llu",
658 dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE);
662 if (priv->uar_base != addr) {
664 "port %u UAR address %p size %llu occupied, please"
665 " adjust MLX5_UAR_OFFSET or try EAL parameter"
667 dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE);
671 uar_base = addr; /* process local, don't reserve again */
672 DRV_LOG(INFO, "port %u reserved UAR address space: %p",
673 dev->data->port_id, addr);
678 * Spawn an Ethernet device from Verbs information.
681 * Backing DPDK device.
685 * If nonzero, enable VF-specific features.
686 * @param[in] switch_info
687 * Switch properties of Ethernet device.
690 * A valid Ethernet device object on success, NULL otherwise and rte_errno
691 * is set. The following error is defined:
693 * EBUSY: device is not supposed to be spawned.
695 static struct rte_eth_dev *
696 mlx5_dev_spawn(struct rte_device *dpdk_dev,
697 struct ibv_device *ibv_dev,
699 const struct mlx5_switch_info *switch_info)
701 struct ibv_context *ctx;
702 struct ibv_device_attr_ex attr;
703 struct ibv_port_attr port_attr;
704 struct ibv_pd *pd = NULL;
705 struct mlx5dv_context dv_attr = { .comp_mask = 0 };
706 struct mlx5_dev_config config = {
708 .mps = MLX5_ARG_UNSET,
712 .txq_inline = MLX5_ARG_UNSET,
713 .txqs_inline = MLX5_ARG_UNSET,
714 .inline_max_packet_sz = MLX5_ARG_UNSET,
718 .stride_num_n = MLX5_MPRQ_STRIDE_NUM_N,
719 .max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN,
720 .min_rxqs_num = MLX5_MPRQ_MIN_RXQS,
723 struct rte_eth_dev *eth_dev = NULL;
724 struct priv *priv = NULL;
727 unsigned int cqe_comp;
728 unsigned int tunnel_en = 0;
729 unsigned int mpls_en = 0;
730 unsigned int swp = 0;
731 unsigned int mprq = 0;
732 unsigned int mprq_min_stride_size_n = 0;
733 unsigned int mprq_max_stride_size_n = 0;
734 unsigned int mprq_min_stride_num_n = 0;
735 unsigned int mprq_max_stride_num_n = 0;
736 #ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT
737 struct ibv_counter_set_description cs_desc = { .counter_type = 0 };
739 struct ether_addr mac;
740 char name[RTE_ETH_NAME_MAX_LEN];
741 int own_domain_id = 0;
744 /* Determine if this port representor is supposed to be spawned. */
745 if (switch_info->representor && dpdk_dev->devargs) {
746 struct rte_eth_devargs eth_da;
748 err = rte_eth_devargs_parse(dpdk_dev->devargs->args, ð_da);
751 DRV_LOG(ERR, "failed to process device arguments: %s",
752 strerror(rte_errno));
755 for (i = 0; i < eth_da.nb_representor_ports; ++i)
756 if (eth_da.representor_ports[i] ==
757 (uint16_t)switch_info->port_name)
759 if (i == eth_da.nb_representor_ports) {
764 /* Prepare shared data between primary and secondary process. */
765 mlx5_prepare_shared_data();
767 ctx = mlx5_glue->open_device(ibv_dev);
769 rte_errno = errno ? errno : ENODEV;
772 #ifdef HAVE_IBV_MLX5_MOD_SWP
773 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP;
776 * Multi-packet send is supported by ConnectX-4 Lx PF as well
777 * as all ConnectX-5 devices.
779 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
780 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS;
782 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
783 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ;
785 mlx5_glue->dv_query_device(ctx, &dv_attr);
786 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
787 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) {
788 DRV_LOG(DEBUG, "enhanced MPW is supported");
789 mps = MLX5_MPW_ENHANCED;
791 DRV_LOG(DEBUG, "MPW is supported");
795 DRV_LOG(DEBUG, "MPW isn't supported");
796 mps = MLX5_MPW_DISABLED;
798 #ifdef HAVE_IBV_MLX5_MOD_SWP
799 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP)
800 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads;
801 DRV_LOG(DEBUG, "SWP support: %u", swp);
804 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
805 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) {
806 struct mlx5dv_striding_rq_caps mprq_caps =
807 dv_attr.striding_rq_caps;
809 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d",
810 mprq_caps.min_single_stride_log_num_of_bytes);
811 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d",
812 mprq_caps.max_single_stride_log_num_of_bytes);
813 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d",
814 mprq_caps.min_single_wqe_log_num_of_strides);
815 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d",
816 mprq_caps.max_single_wqe_log_num_of_strides);
817 DRV_LOG(DEBUG, "\tsupported_qpts: %d",
818 mprq_caps.supported_qpts);
819 DRV_LOG(DEBUG, "device supports Multi-Packet RQ");
821 mprq_min_stride_size_n =
822 mprq_caps.min_single_stride_log_num_of_bytes;
823 mprq_max_stride_size_n =
824 mprq_caps.max_single_stride_log_num_of_bytes;
825 mprq_min_stride_num_n =
826 mprq_caps.min_single_wqe_log_num_of_strides;
827 mprq_max_stride_num_n =
828 mprq_caps.max_single_wqe_log_num_of_strides;
829 config.mprq.stride_num_n = RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,
830 mprq_min_stride_num_n);
833 if (RTE_CACHE_LINE_SIZE == 128 &&
834 !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP))
838 config.cqe_comp = cqe_comp;
839 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
840 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) {
841 tunnel_en = ((dv_attr.tunnel_offloads_caps &
842 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) &&
843 (dv_attr.tunnel_offloads_caps &
844 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE));
846 DRV_LOG(DEBUG, "tunnel offloading is %ssupported",
847 tunnel_en ? "" : "not ");
850 "tunnel offloading disabled due to old OFED/rdma-core version");
852 config.tunnel_en = tunnel_en;
853 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
854 mpls_en = ((dv_attr.tunnel_offloads_caps &
855 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) &&
856 (dv_attr.tunnel_offloads_caps &
857 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP));
858 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported",
859 mpls_en ? "" : "not ");
861 DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to"
862 " old OFED/rdma-core version or firmware configuration");
864 config.mpls_en = mpls_en;
865 err = mlx5_glue->query_device_ex(ctx, NULL, &attr);
867 DEBUG("ibv_query_device_ex() failed");
870 if (!switch_info->representor)
871 rte_strlcpy(name, dpdk_dev->name, sizeof(name));
873 snprintf(name, sizeof(name), "%s_representor_%u",
874 dpdk_dev->name, switch_info->port_name);
875 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name);
876 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
877 eth_dev = rte_eth_dev_attach_secondary(name);
878 if (eth_dev == NULL) {
879 DRV_LOG(ERR, "can not attach rte ethdev");
884 eth_dev->device = dpdk_dev;
885 eth_dev->dev_ops = &mlx5_dev_sec_ops;
886 err = mlx5_uar_init_secondary(eth_dev);
891 /* Receive command fd from primary process */
892 err = mlx5_socket_connect(eth_dev);
897 /* Remap UAR for Tx queues. */
898 err = mlx5_tx_uar_remap(eth_dev, err);
904 * Ethdev pointer is still required as input since
905 * the primary device is not accessible from the
908 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev);
909 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev);
910 claim_zero(mlx5_glue->close_device(ctx));
913 /* Check port status. */
914 err = mlx5_glue->query_port(ctx, 1, &port_attr);
916 DRV_LOG(ERR, "port query failed: %s", strerror(err));
919 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
920 DRV_LOG(ERR, "port is not configured in Ethernet mode");
924 if (port_attr.state != IBV_PORT_ACTIVE)
925 DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)",
926 mlx5_glue->port_state_str(port_attr.state),
928 /* Allocate protection domain. */
929 pd = mlx5_glue->alloc_pd(ctx);
931 DRV_LOG(ERR, "PD allocation failure");
935 priv = rte_zmalloc("ethdev private structure",
937 RTE_CACHE_LINE_SIZE);
939 DRV_LOG(ERR, "priv allocation failure");
944 strncpy(priv->ibdev_name, priv->ctx->device->name,
945 sizeof(priv->ibdev_name));
946 strncpy(priv->ibdev_path, priv->ctx->device->ibdev_path,
947 sizeof(priv->ibdev_path));
948 priv->device_attr = attr;
950 priv->mtu = ETHER_MTU;
952 /* Initialize UAR access locks for 32bit implementations. */
953 rte_spinlock_init(&priv->uar_lock_cq);
954 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
955 rte_spinlock_init(&priv->uar_lock[i]);
957 /* Some internal functions rely on Netlink sockets, open them now. */
958 priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA);
959 priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE);
961 priv->representor = !!switch_info->representor;
962 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
963 priv->representor_id =
964 switch_info->representor ? switch_info->port_name : -1;
966 * Look for sibling devices in order to reuse their switch domain
967 * if any, otherwise allocate one.
969 i = mlx5_dev_to_port_id(dpdk_dev, NULL, 0);
973 i = RTE_MIN(mlx5_dev_to_port_id(dpdk_dev, port_id, i), i);
975 const struct priv *opriv =
976 rte_eth_devices[port_id[i]].data->dev_private;
980 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID)
982 priv->domain_id = opriv->domain_id;
986 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
987 err = rte_eth_switch_domain_alloc(&priv->domain_id);
990 DRV_LOG(ERR, "unable to allocate switch domain: %s",
991 strerror(rte_errno));
996 err = mlx5_args(&config, dpdk_dev->devargs);
999 DRV_LOG(ERR, "failed to process device arguments: %s",
1000 strerror(rte_errno));
1003 config.hw_csum = !!(attr.device_cap_flags_ex & IBV_DEVICE_RAW_IP_CSUM);
1004 DRV_LOG(DEBUG, "checksum offloading is %ssupported",
1005 (config.hw_csum ? "" : "not "));
1006 #ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT
1007 config.flow_counter_en = !!attr.max_counter_sets;
1008 mlx5_glue->describe_counter_set(ctx, 0, &cs_desc);
1009 DRV_LOG(DEBUG, "counter type = %d, num of cs = %ld, attributes = %d",
1010 cs_desc.counter_type, cs_desc.num_of_cs,
1011 cs_desc.attributes);
1013 config.ind_table_max_size =
1014 attr.rss_caps.max_rwq_indirection_table_size;
1016 * Remove this check once DPDK supports larger/variable
1017 * indirection tables.
1019 if (config.ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512)
1020 config.ind_table_max_size = ETH_RSS_RETA_SIZE_512;
1021 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u",
1022 config.ind_table_max_size);
1023 config.hw_vlan_strip = !!(attr.raw_packet_caps &
1024 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
1025 DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
1026 (config.hw_vlan_strip ? "" : "not "));
1027 config.hw_fcs_strip = !!(attr.raw_packet_caps &
1028 IBV_RAW_PACKET_CAP_SCATTER_FCS);
1029 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported",
1030 (config.hw_fcs_strip ? "" : "not "));
1031 #ifdef HAVE_IBV_WQ_FLAG_RX_END_PADDING
1032 config.hw_padding = !!attr.rx_pad_end_addr_align;
1034 DRV_LOG(DEBUG, "hardware Rx end alignment padding is %ssupported",
1035 (config.hw_padding ? "" : "not "));
1036 config.tso = (attr.tso_caps.max_tso > 0 &&
1037 (attr.tso_caps.supported_qpts &
1038 (1 << IBV_QPT_RAW_PACKET)));
1040 config.tso_max_payload_sz = attr.tso_caps.max_tso;
1042 * MPW is disabled by default, while the Enhanced MPW is enabled
1045 if (config.mps == MLX5_ARG_UNSET)
1046 config.mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED :
1049 config.mps = config.mps ? mps : MLX5_MPW_DISABLED;
1050 DRV_LOG(INFO, "%sMPS is %s",
1051 config.mps == MLX5_MPW_ENHANCED ? "enhanced " : "",
1052 config.mps != MLX5_MPW_DISABLED ? "enabled" : "disabled");
1053 if (config.cqe_comp && !cqe_comp) {
1054 DRV_LOG(WARNING, "Rx CQE compression isn't supported");
1055 config.cqe_comp = 0;
1057 if (config.mprq.enabled && mprq) {
1058 if (config.mprq.stride_num_n > mprq_max_stride_num_n ||
1059 config.mprq.stride_num_n < mprq_min_stride_num_n) {
1060 config.mprq.stride_num_n =
1061 RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,
1062 mprq_min_stride_num_n);
1064 "the number of strides"
1065 " for Multi-Packet RQ is out of range,"
1066 " setting default value (%u)",
1067 1 << config.mprq.stride_num_n);
1069 config.mprq.min_stride_size_n = mprq_min_stride_size_n;
1070 config.mprq.max_stride_size_n = mprq_max_stride_size_n;
1071 } else if (config.mprq.enabled && !mprq) {
1072 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported");
1073 config.mprq.enabled = 0;
1075 eth_dev = rte_eth_dev_allocate(name);
1076 if (eth_dev == NULL) {
1077 DRV_LOG(ERR, "can not allocate rte ethdev");
1081 if (priv->representor)
1082 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR;
1083 eth_dev->data->dev_private = priv;
1084 priv->dev_data = eth_dev->data;
1085 eth_dev->data->mac_addrs = priv->mac;
1086 eth_dev->device = dpdk_dev;
1087 eth_dev->device->driver = &mlx5_driver.driver;
1088 err = mlx5_uar_init_primary(eth_dev);
1093 /* Configure the first MAC address by default. */
1094 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) {
1096 "port %u cannot get MAC address, is mlx5_en"
1097 " loaded? (errno: %s)",
1098 eth_dev->data->port_id, strerror(rte_errno));
1103 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x",
1104 eth_dev->data->port_id,
1105 mac.addr_bytes[0], mac.addr_bytes[1],
1106 mac.addr_bytes[2], mac.addr_bytes[3],
1107 mac.addr_bytes[4], mac.addr_bytes[5]);
1110 char ifname[IF_NAMESIZE];
1112 if (mlx5_get_ifname(eth_dev, &ifname) == 0)
1113 DRV_LOG(DEBUG, "port %u ifname is \"%s\"",
1114 eth_dev->data->port_id, ifname);
1116 DRV_LOG(DEBUG, "port %u ifname is unknown",
1117 eth_dev->data->port_id);
1120 /* Get actual MTU if possible. */
1121 err = mlx5_get_mtu(eth_dev, &priv->mtu);
1126 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id,
1128 /* Initialize burst functions to prevent crashes before link-up. */
1129 eth_dev->rx_pkt_burst = removed_rx_burst;
1130 eth_dev->tx_pkt_burst = removed_tx_burst;
1131 eth_dev->dev_ops = &mlx5_dev_ops;
1132 /* Register MAC address. */
1133 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
1134 if (vf && config.vf_nl_en)
1135 mlx5_nl_mac_addr_sync(eth_dev);
1136 priv->mnl_socket = mlx5_nl_flow_socket_create();
1137 if (!priv->mnl_socket) {
1140 "flow rules relying on switch offloads will not be"
1141 " supported: cannot open libmnl socket: %s",
1142 strerror(rte_errno));
1144 struct rte_flow_error error;
1145 unsigned int ifindex = mlx5_ifindex(eth_dev);
1150 "cannot retrieve network interface index";
1152 err = mlx5_nl_flow_init(priv->mnl_socket, ifindex,
1157 "flow rules relying on switch offloads will"
1158 " not be supported: %s: %s",
1159 error.message, strerror(rte_errno));
1160 mlx5_nl_flow_socket_destroy(priv->mnl_socket);
1161 priv->mnl_socket = NULL;
1164 TAILQ_INIT(&priv->flows);
1165 TAILQ_INIT(&priv->ctrl_flows);
1166 /* Hint libmlx5 to use PMD allocator for data plane resources */
1167 struct mlx5dv_ctx_allocators alctr = {
1168 .alloc = &mlx5_alloc_verbs_buf,
1169 .free = &mlx5_free_verbs_buf,
1172 mlx5_glue->dv_set_context_attr(ctx, MLX5DV_CTX_ATTR_BUF_ALLOCATORS,
1173 (void *)((uintptr_t)&alctr));
1174 /* Bring Ethernet device up. */
1175 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up",
1176 eth_dev->data->port_id);
1177 mlx5_set_link_up(eth_dev);
1179 * Even though the interrupt handler is not installed yet,
1180 * interrupts will still trigger on the asyn_fd from
1181 * Verbs context returned by ibv_open_device().
1183 mlx5_link_update(eth_dev, 0);
1184 /* Store device configuration on private structure. */
1185 priv->config = config;
1186 /* Supported Verbs flow priority number detection. */
1187 err = mlx5_flow_discover_priorities(eth_dev);
1190 priv->config.flow_prio = err;
1191 mlx5_flow_init_driver_ops(eth_dev);
1193 * Once the device is added to the list of memory event
1194 * callback, its global MR cache table cannot be expanded
1195 * on the fly because of deadlock. If it overflows, lookup
1196 * should be done by searching MR list linearly, which is slow.
1198 err = mlx5_mr_btree_init(&priv->mr.cache,
1199 MLX5_MR_BTREE_CACHE_N * 2,
1200 eth_dev->device->numa_node);
1205 /* Add device to memory callback list. */
1206 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1207 LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
1208 priv, mem_event_cb);
1209 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1213 if (priv->nl_socket_route >= 0)
1214 close(priv->nl_socket_route);
1215 if (priv->nl_socket_rdma >= 0)
1216 close(priv->nl_socket_rdma);
1217 if (priv->mnl_socket)
1218 mlx5_nl_flow_socket_destroy(priv->mnl_socket);
1220 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1224 claim_zero(mlx5_glue->dealloc_pd(pd));
1226 rte_eth_dev_release_port(eth_dev);
1228 claim_zero(mlx5_glue->close_device(ctx));
1234 /** Data associated with devices to spawn. */
1235 struct mlx5_dev_spawn_data {
1236 unsigned int ifindex; /**< Network interface index. */
1237 struct mlx5_switch_info info; /**< Switch information. */
1238 struct ibv_device *ibv_dev; /**< Associated IB device. */
1239 struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */
1243 * Comparison callback to sort device data.
1245 * This is meant to be used with qsort().
1248 * Pointer to pointer to first data object.
1250 * Pointer to pointer to second data object.
1253 * 0 if both objects are equal, less than 0 if the first argument is less
1254 * than the second, greater than 0 otherwise.
1257 mlx5_dev_spawn_data_cmp(const void *a, const void *b)
1259 const struct mlx5_switch_info *si_a =
1260 &((const struct mlx5_dev_spawn_data *)a)->info;
1261 const struct mlx5_switch_info *si_b =
1262 &((const struct mlx5_dev_spawn_data *)b)->info;
1265 /* Master device first. */
1266 ret = si_b->master - si_a->master;
1269 /* Then representor devices. */
1270 ret = si_b->representor - si_a->representor;
1273 /* Unidentified devices come last in no specific order. */
1274 if (!si_a->representor)
1276 /* Order representors by name. */
1277 return si_a->port_name - si_b->port_name;
1281 * DPDK callback to register a PCI device.
1283 * This function spawns Ethernet devices out of a given PCI device.
1285 * @param[in] pci_drv
1286 * PCI driver structure (mlx5_driver).
1287 * @param[in] pci_dev
1288 * PCI device information.
1291 * 0 on success, a negative errno value otherwise and rte_errno is set.
1294 mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1295 struct rte_pci_device *pci_dev)
1297 struct ibv_device **ibv_list;
1302 assert(pci_drv == &mlx5_driver);
1304 ibv_list = mlx5_glue->get_device_list(&ret);
1306 rte_errno = errno ? errno : ENOSYS;
1307 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?");
1311 struct ibv_device *ibv_match[ret + 1];
1314 struct rte_pci_addr pci_addr;
1316 DRV_LOG(DEBUG, "checking device \"%s\"", ibv_list[ret]->name);
1317 if (mlx5_ibv_device_to_pci_addr(ibv_list[ret], &pci_addr))
1319 if (pci_dev->addr.domain != pci_addr.domain ||
1320 pci_dev->addr.bus != pci_addr.bus ||
1321 pci_dev->addr.devid != pci_addr.devid ||
1322 pci_dev->addr.function != pci_addr.function)
1324 DRV_LOG(INFO, "PCI information matches for device \"%s\"",
1325 ibv_list[ret]->name);
1326 ibv_match[n++] = ibv_list[ret];
1328 ibv_match[n] = NULL;
1330 struct mlx5_dev_spawn_data list[n];
1331 int nl_route = n ? mlx5_nl_init(NETLINK_ROUTE) : -1;
1332 int nl_rdma = n ? mlx5_nl_init(NETLINK_RDMA) : -1;
1337 * The existence of several matching entries (n > 1) means port
1338 * representors have been instantiated. No existing Verbs call nor
1339 * /sys entries can tell them apart, this can only be done through
1340 * Netlink calls assuming kernel drivers are recent enough to
1343 * In the event of identification failure through Netlink, try again
1344 * through sysfs, then either:
1346 * 1. No device matches (n == 0), complain and bail out.
1347 * 2. A single IB device matches (n == 1) and is not a representor,
1348 * assume no switch support.
1349 * 3. Otherwise no safe assumptions can be made; complain louder and
1352 for (i = 0; i != n; ++i) {
1353 list[i].ibv_dev = ibv_match[i];
1354 list[i].eth_dev = NULL;
1356 list[i].ifindex = 0;
1358 list[i].ifindex = mlx5_nl_ifindex
1359 (nl_rdma, list[i].ibv_dev->name);
1362 mlx5_nl_switch_info(nl_route, list[i].ifindex,
1364 ((!list[i].info.representor && !list[i].info.master) &&
1365 mlx5_sysfs_switch_info(list[i].ifindex, &list[i].info))) {
1366 list[i].ifindex = 0;
1367 memset(&list[i].info, 0, sizeof(list[i].info));
1375 /* Count unidentified devices. */
1376 for (u = 0, i = 0; i != n; ++i)
1377 if (!list[i].info.master && !list[i].info.representor)
1380 if (n == 1 && u == 1) {
1382 DRV_LOG(INFO, "no switch support detected");
1386 "unable to tell which of the matching devices"
1387 " is the master (lack of kernel support?)");
1392 * Sort list to probe devices in natural order for users convenience
1393 * (i.e. master first, then representors from lowest to highest ID).
1396 qsort(list, n, sizeof(*list), mlx5_dev_spawn_data_cmp);
1397 switch (pci_dev->id.device_id) {
1398 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1399 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1400 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1401 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1407 for (i = 0; i != n; ++i) {
1410 list[i].eth_dev = mlx5_dev_spawn
1411 (&pci_dev->device, list[i].ibv_dev, vf, &list[i].info);
1412 if (!list[i].eth_dev) {
1413 if (rte_errno != EBUSY)
1415 /* Device is disabled, ignore it. */
1418 restore = list[i].eth_dev->data->dev_flags;
1419 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev);
1420 /* Restore non-PCI flags cleared by the above call. */
1421 list[i].eth_dev->data->dev_flags |= restore;
1422 rte_eth_dev_probing_finish(list[i].eth_dev);
1424 mlx5_glue->free_device_list(ibv_list);
1427 "no Verbs device matches PCI device " PCI_PRI_FMT ","
1428 " are kernel drivers loaded?",
1429 pci_dev->addr.domain, pci_dev->addr.bus,
1430 pci_dev->addr.devid, pci_dev->addr.function);
1433 } else if (i != n) {
1435 "probe of PCI device " PCI_PRI_FMT " aborted after"
1436 " encountering an error: %s",
1437 pci_dev->addr.domain, pci_dev->addr.bus,
1438 pci_dev->addr.devid, pci_dev->addr.function,
1439 strerror(rte_errno));
1443 if (!list[i].eth_dev)
1445 mlx5_dev_close(list[i].eth_dev);
1446 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
1447 rte_free(list[i].eth_dev->data->dev_private);
1448 claim_zero(rte_eth_dev_release_port(list[i].eth_dev));
1450 /* Restore original error. */
1458 static const struct rte_pci_id mlx5_pci_id_map[] = {
1460 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1461 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
1464 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1465 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
1468 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1469 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
1472 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1473 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
1476 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1477 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
1480 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1481 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
1484 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1485 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
1488 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1489 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
1492 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1493 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
1496 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1497 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
1504 static struct rte_pci_driver mlx5_driver = {
1506 .name = MLX5_DRIVER_NAME
1508 .id_table = mlx5_pci_id_map,
1509 .probe = mlx5_pci_probe,
1510 .drv_flags = RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV,
1513 #ifdef RTE_LIBRTE_MLX5_DLOPEN_DEPS
1516 * Suffix RTE_EAL_PMD_PATH with "-glue".
1518 * This function performs a sanity check on RTE_EAL_PMD_PATH before
1519 * suffixing its last component.
1522 * Output buffer, should be large enough otherwise NULL is returned.
1527 * Pointer to @p buf or @p NULL in case suffix cannot be appended.
1530 mlx5_glue_path(char *buf, size_t size)
1532 static const char *const bad[] = { "/", ".", "..", NULL };
1533 const char *path = RTE_EAL_PMD_PATH;
1534 size_t len = strlen(path);
1538 while (len && path[len - 1] == '/')
1540 for (off = len; off && path[off - 1] != '/'; --off)
1542 for (i = 0; bad[i]; ++i)
1543 if (!strncmp(path + off, bad[i], (int)(len - off)))
1545 i = snprintf(buf, size, "%.*s-glue", (int)len, path);
1546 if (i == -1 || (size_t)i >= size)
1551 "unable to append \"-glue\" to last component of"
1552 " RTE_EAL_PMD_PATH (\"" RTE_EAL_PMD_PATH "\"),"
1553 " please re-configure DPDK");
1558 * Initialization routine for run-time dependency on rdma-core.
1561 mlx5_glue_init(void)
1563 char glue_path[sizeof(RTE_EAL_PMD_PATH) - 1 + sizeof("-glue")];
1564 const char *path[] = {
1566 * A basic security check is necessary before trusting
1567 * MLX5_GLUE_PATH, which may override RTE_EAL_PMD_PATH.
1569 (geteuid() == getuid() && getegid() == getgid() ?
1570 getenv("MLX5_GLUE_PATH") : NULL),
1572 * When RTE_EAL_PMD_PATH is set, use its glue-suffixed
1573 * variant, otherwise let dlopen() look up libraries on its
1576 (*RTE_EAL_PMD_PATH ?
1577 mlx5_glue_path(glue_path, sizeof(glue_path)) : ""),
1580 void *handle = NULL;
1584 while (!handle && i != RTE_DIM(path)) {
1593 end = strpbrk(path[i], ":;");
1595 end = path[i] + strlen(path[i]);
1596 len = end - path[i];
1601 ret = snprintf(name, sizeof(name), "%.*s%s" MLX5_GLUE,
1603 (!len || *(end - 1) == '/') ? "" : "/");
1606 if (sizeof(name) != (size_t)ret + 1)
1608 DRV_LOG(DEBUG, "looking for rdma-core glue as \"%s\"",
1610 handle = dlopen(name, RTLD_LAZY);
1621 DRV_LOG(WARNING, "cannot load glue library: %s", dlmsg);
1624 sym = dlsym(handle, "mlx5_glue");
1625 if (!sym || !*sym) {
1629 DRV_LOG(ERR, "cannot resolve glue symbol: %s", dlmsg);
1638 "cannot initialize PMD due to missing run-time dependency on"
1639 " rdma-core libraries (libibverbs, libmlx5)");
1646 * Driver initialization routine.
1648 RTE_INIT(rte_mlx5_pmd_init)
1650 /* Initialize driver log type. */
1651 mlx5_logtype = rte_log_register("pmd.net.mlx5");
1652 if (mlx5_logtype >= 0)
1653 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE);
1655 /* Build the static tables for Verbs conversion. */
1656 mlx5_set_ptype_table();
1657 mlx5_set_cksum_table();
1658 mlx5_set_swp_types_table();
1660 * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use
1661 * huge pages. Calling ibv_fork_init() during init allows
1662 * applications to use fork() safely for purposes other than
1663 * using this PMD, which is not supported in forked processes.
1665 setenv("RDMAV_HUGEPAGES_SAFE", "1", 1);
1666 /* Match the size of Rx completion entry to the size of a cacheline. */
1667 if (RTE_CACHE_LINE_SIZE == 128)
1668 setenv("MLX5_CQE_SIZE", "128", 0);
1670 * MLX5_DEVICE_FATAL_CLEANUP tells ibv_destroy functions to
1671 * cleanup all the Verbs resources even when the device was removed.
1673 setenv("MLX5_DEVICE_FATAL_CLEANUP", "1", 1);
1674 #ifdef RTE_LIBRTE_MLX5_DLOPEN_DEPS
1675 if (mlx5_glue_init())
1680 /* Glue structure must not contain any NULL pointers. */
1684 for (i = 0; i != sizeof(*mlx5_glue) / sizeof(void *); ++i)
1685 assert(((const void *const *)mlx5_glue)[i]);
1688 if (strcmp(mlx5_glue->version, MLX5_GLUE_VERSION)) {
1690 "rdma-core glue \"%s\" mismatch: \"%s\" is required",
1691 mlx5_glue->version, MLX5_GLUE_VERSION);
1694 mlx5_glue->fork_init();
1695 rte_pci_register(&mlx5_driver);
1698 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
1699 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
1700 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");