drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <stdint.h>
  10 #include <stdlib.h>
  11 #include <errno.h>
  12
  13 #include <rte_malloc.h>
  14 #include <ethdev_driver.h>
  15 #include <rte_pci.h>
  16 #include <rte_bus_pci.h>
  17 #include <rte_common.h>
  18 #include <rte_kvargs.h>
  19 #include <rte_rwlock.h>
  20 #include <rte_spinlock.h>
  21 #include <rte_string_fns.h>
  22 #include <rte_alarm.h>
  23 #include <rte_cycles.h>
  24
  25 #include <mlx5_glue.h>
  26 #include <mlx5_devx_cmds.h>
  27 #include <mlx5_common.h>
  28 #include <mlx5_common_os.h>
  29 #include <mlx5_common_mp.h>
  30 #include <mlx5_malloc.h>
  31
  32 #include "mlx5_defs.h"
  33 #include "mlx5.h"
  34 #include "mlx5_utils.h"
  35 #include "mlx5_rxtx.h"
  36 #include "mlx5_rx.h"
  37 #include "mlx5_tx.h"
  38 #include "mlx5_autoconf.h"
  39 #include "mlx5_flow.h"
  40 #include "mlx5_flow_os.h"
  41 #include "rte_pmd_mlx5.h"
  42
  43 #define MLX5_ETH_DRIVER_NAME mlx5_eth
  44
  45 /* Driver type key for new device global syntax. */
  46 #define MLX5_DRIVER_KEY "driver"
  47
  48 /* Device parameter to enable RX completion queue compression. */
  49 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  50
  51 /* Device parameter to enable padding Rx packet to cacheline size. */
  52 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
  53
  54 /* Device parameter to enable Multi-Packet Rx queue. */
  55 #define MLX5_RX_MPRQ_EN "mprq_en"
  56
  57 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
  58 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
  59
  60 /* Device parameter to configure log 2 of the stride size for MPRQ. */
  61 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
  62
  63 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
  64 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
  65
  66 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
  67 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
  68
  69 /* Device parameter to configure inline send. Deprecated, ignored.*/
  70 #define MLX5_TXQ_INLINE "txq_inline"
  71
  72 /* Device parameter to limit packet size to inline with ordinary SEND. */
  73 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
  74
  75 /* Device parameter to configure minimal data size to inline. */
  76 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
  77
  78 /* Device parameter to limit packet size to inline with Enhanced MPW. */
  79 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
  80
  81 /*
  82  * Device parameter to configure the number of TX queues threshold for
  83  * enabling inline send.
  84  */
  85 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  86
  87 /*
  88  * Device parameter to configure the number of TX queues threshold for
  89  * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
  90  */
  91 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
  92
  93 /* Device parameter to enable multi-packet send WQEs. */
  94 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
  95
  96 /*
  97  * Device parameter to force doorbell register mapping
  98  * to non-cahed region eliminating the extra write memory barrier.
  99  */
 100 #define MLX5_TX_DB_NC "tx_db_nc"
 101
 102 /*
 103  * Device parameter to include 2 dsegs in the title WQEBB.
 104  * Deprecated, ignored.
 105  */
 106 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
 107
 108 /*
 109  * Device parameter to limit the size of inlining packet.
 110  * Deprecated, ignored.
 111  */
 112 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
 113
 114 /*
 115  * Device parameter to enable Tx scheduling on timestamps
 116  * and specify the packet pacing granularity in nanoseconds.
 117  */
 118 #define MLX5_TX_PP "tx_pp"
 119
 120 /*
 121  * Device parameter to specify skew in nanoseconds on Tx datapath,
 122  * it represents the time between SQ start WQE processing and
 123  * appearing actual packet data on the wire.
 124  */
 125 #define MLX5_TX_SKEW "tx_skew"
 126
 127 /*
 128  * Device parameter to enable hardware Tx vector.
 129  * Deprecated, ignored (no vectorized Tx routines anymore).
 130  */
 131 #define MLX5_TX_VEC_EN "tx_vec_en"
 132
 133 /* Device parameter to enable hardware Rx vector. */
 134 #define MLX5_RX_VEC_EN "rx_vec_en"
 135
 136 /* Allow L3 VXLAN flow creation. */
 137 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
 138
 139 /* Activate DV E-Switch flow steering. */
 140 #define MLX5_DV_ESW_EN "dv_esw_en"
 141
 142 /* Activate DV flow steering. */
 143 #define MLX5_DV_FLOW_EN "dv_flow_en"
 144
 145 /* Enable extensive flow metadata support. */
 146 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
 147
 148 /* Device parameter to let the user manage the lacp traffic of bonded device */
 149 #define MLX5_LACP_BY_USER "lacp_by_user"
 150
 151 /* Activate Netlink support in VF mode. */
 152 #define MLX5_VF_NL_EN "vf_nl_en"
 153
 154 /* Enable extending memsegs when creating a MR. */
 155 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
 156
 157 /* Select port representors to instantiate. */
 158 #define MLX5_REPRESENTOR "representor"
 159
 160 /* Device parameter to configure the maximum number of dump files per queue. */
 161 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
 162
 163 /* Configure timeout of LRO session (in microseconds). */
 164 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
 165
 166 /*
 167  * Device parameter to configure the total data buffer size for a single
 168  * hairpin queue (logarithm value).
 169  */
 170 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
 171
 172 /* Flow memory reclaim mode. */
 173 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
 174
 175 /* The default memory allocator used in PMD. */
 176 #define MLX5_SYS_MEM_EN "sys_mem_en"
 177 /* Decap will be used or not. */
 178 #define MLX5_DECAP_EN "decap_en"
 179
 180 /* Device parameter to configure allow or prevent duplicate rules pattern. */
 181 #define MLX5_ALLOW_DUPLICATE_PATTERN "allow_duplicate_pattern"
 182
 183 /* Device parameter to configure implicit registration of mempool memory. */
 184 #define MLX5_MR_MEMPOOL_REG_EN "mr_mempool_reg_en"
 185
 186 /* Shared memory between primary and secondary processes. */
 187 struct mlx5_shared_data *mlx5_shared_data;
 188
 189 /** Driver-specific log messages type. */
 190 int mlx5_logtype;
 191
 192 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
 193                                                 LIST_HEAD_INITIALIZER();
 194 static pthread_mutex_t mlx5_dev_ctx_list_mutex;
 195 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
 196 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
 197         [MLX5_IPOOL_DECAP_ENCAP] = {
 198                 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
 199                 .trunk_size = 64,
 200                 .grow_trunk = 3,
 201                 .grow_shift = 2,
 202                 .need_lock = 1,
 203                 .release_mem_en = 1,
 204                 .malloc = mlx5_malloc,
 205                 .free = mlx5_free,
 206                 .type = "mlx5_encap_decap_ipool",
 207         },
 208         [MLX5_IPOOL_PUSH_VLAN] = {
 209                 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
 210                 .trunk_size = 64,
 211                 .grow_trunk = 3,
 212                 .grow_shift = 2,
 213                 .need_lock = 1,
 214                 .release_mem_en = 1,
 215                 .malloc = mlx5_malloc,
 216                 .free = mlx5_free,
 217                 .type = "mlx5_push_vlan_ipool",
 218         },
 219         [MLX5_IPOOL_TAG] = {
 220                 .size = sizeof(struct mlx5_flow_dv_tag_resource),
 221                 .trunk_size = 64,
 222                 .grow_trunk = 3,
 223                 .grow_shift = 2,
 224                 .need_lock = 1,
 225                 .release_mem_en = 0,
 226                 .per_core_cache = (1 << 16),
 227                 .malloc = mlx5_malloc,
 228                 .free = mlx5_free,
 229                 .type = "mlx5_tag_ipool",
 230         },
 231         [MLX5_IPOOL_PORT_ID] = {
 232                 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
 233                 .trunk_size = 64,
 234                 .grow_trunk = 3,
 235                 .grow_shift = 2,
 236                 .need_lock = 1,
 237                 .release_mem_en = 1,
 238                 .malloc = mlx5_malloc,
 239                 .free = mlx5_free,
 240                 .type = "mlx5_port_id_ipool",
 241         },
 242         [MLX5_IPOOL_JUMP] = {
 243                 .size = sizeof(struct mlx5_flow_tbl_data_entry),
 244                 .trunk_size = 64,
 245                 .grow_trunk = 3,
 246                 .grow_shift = 2,
 247                 .need_lock = 1,
 248                 .release_mem_en = 1,
 249                 .malloc = mlx5_malloc,
 250                 .free = mlx5_free,
 251                 .type = "mlx5_jump_ipool",
 252         },
 253         [MLX5_IPOOL_SAMPLE] = {
 254                 .size = sizeof(struct mlx5_flow_dv_sample_resource),
 255                 .trunk_size = 64,
 256                 .grow_trunk = 3,
 257                 .grow_shift = 2,
 258                 .need_lock = 1,
 259                 .release_mem_en = 1,
 260                 .malloc = mlx5_malloc,
 261                 .free = mlx5_free,
 262                 .type = "mlx5_sample_ipool",
 263         },
 264         [MLX5_IPOOL_DEST_ARRAY] = {
 265                 .size = sizeof(struct mlx5_flow_dv_dest_array_resource),
 266                 .trunk_size = 64,
 267                 .grow_trunk = 3,
 268                 .grow_shift = 2,
 269                 .need_lock = 1,
 270                 .release_mem_en = 1,
 271                 .malloc = mlx5_malloc,
 272                 .free = mlx5_free,
 273                 .type = "mlx5_dest_array_ipool",
 274         },
 275         [MLX5_IPOOL_TUNNEL_ID] = {
 276                 .size = sizeof(struct mlx5_flow_tunnel),
 277                 .trunk_size = MLX5_MAX_TUNNELS,
 278                 .need_lock = 1,
 279                 .release_mem_en = 1,
 280                 .type = "mlx5_tunnel_offload",
 281         },
 282         [MLX5_IPOOL_TNL_TBL_ID] = {
 283                 .size = 0,
 284                 .need_lock = 1,
 285                 .type = "mlx5_flow_tnl_tbl_ipool",
 286         },
 287 #endif
 288         [MLX5_IPOOL_MTR] = {
 289                 /**
 290                  * The ipool index should grow continually from small to big,
 291                  * for meter idx, so not set grow_trunk to avoid meter index
 292                  * not jump continually.
 293                  */
 294                 .size = sizeof(struct mlx5_legacy_flow_meter),
 295                 .trunk_size = 64,
 296                 .need_lock = 1,
 297                 .release_mem_en = 1,
 298                 .malloc = mlx5_malloc,
 299                 .free = mlx5_free,
 300                 .type = "mlx5_meter_ipool",
 301         },
 302         [MLX5_IPOOL_MCP] = {
 303                 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
 304                 .trunk_size = 64,
 305                 .grow_trunk = 3,
 306                 .grow_shift = 2,
 307                 .need_lock = 1,
 308                 .release_mem_en = 1,
 309                 .malloc = mlx5_malloc,
 310                 .free = mlx5_free,
 311                 .type = "mlx5_mcp_ipool",
 312         },
 313         [MLX5_IPOOL_HRXQ] = {
 314                 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
 315                 .trunk_size = 64,
 316                 .grow_trunk = 3,
 317                 .grow_shift = 2,
 318                 .need_lock = 1,
 319                 .release_mem_en = 1,
 320                 .malloc = mlx5_malloc,
 321                 .free = mlx5_free,
 322                 .type = "mlx5_hrxq_ipool",
 323         },
 324         [MLX5_IPOOL_MLX5_FLOW] = {
 325                 /*
 326                  * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
 327                  * It set in run time according to PCI function configuration.
 328                  */
 329                 .size = 0,
 330                 .trunk_size = 64,
 331                 .grow_trunk = 3,
 332                 .grow_shift = 2,
 333                 .need_lock = 1,
 334                 .release_mem_en = 0,
 335                 .per_core_cache = 1 << 19,
 336                 .malloc = mlx5_malloc,
 337                 .free = mlx5_free,
 338                 .type = "mlx5_flow_handle_ipool",
 339         },
 340         [MLX5_IPOOL_RTE_FLOW] = {
 341                 .size = sizeof(struct rte_flow),
 342                 .trunk_size = 4096,
 343                 .need_lock = 1,
 344                 .release_mem_en = 1,
 345                 .malloc = mlx5_malloc,
 346                 .free = mlx5_free,
 347                 .type = "rte_flow_ipool",
 348         },
 349         [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID] = {
 350                 .size = 0,
 351                 .need_lock = 1,
 352                 .type = "mlx5_flow_rss_id_ipool",
 353         },
 354         [MLX5_IPOOL_RSS_SHARED_ACTIONS] = {
 355                 .size = sizeof(struct mlx5_shared_action_rss),
 356                 .trunk_size = 64,
 357                 .grow_trunk = 3,
 358                 .grow_shift = 2,
 359                 .need_lock = 1,
 360                 .release_mem_en = 1,
 361                 .malloc = mlx5_malloc,
 362                 .free = mlx5_free,
 363                 .type = "mlx5_shared_action_rss",
 364         },
 365         [MLX5_IPOOL_MTR_POLICY] = {
 366                 /**
 367                  * The ipool index should grow continually from small to big,
 368                  * for policy idx, so not set grow_trunk to avoid policy index
 369                  * not jump continually.
 370                  */
 371                 .size = sizeof(struct mlx5_flow_meter_sub_policy),
 372                 .trunk_size = 64,
 373                 .need_lock = 1,
 374                 .release_mem_en = 1,
 375                 .malloc = mlx5_malloc,
 376                 .free = mlx5_free,
 377                 .type = "mlx5_meter_policy_ipool",
 378         },
 379 };
 380
 381
 382 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
 383 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
 384
 385 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 1024
 386
 387 /**
 388  * Decide whether representor ID is a HPF(host PF) port on BF2.
 389  *
 390  * @param dev
 391  *   Pointer to Ethernet device structure.
 392  *
 393  * @return
 394  *   Non-zero if HPF, otherwise 0.
 395  */
 396 bool
 397 mlx5_is_hpf(struct rte_eth_dev *dev)
 398 {
 399         struct mlx5_priv *priv = dev->data->dev_private;
 400         uint16_t repr = MLX5_REPRESENTOR_REPR(priv->representor_id);
 401         int type = MLX5_REPRESENTOR_TYPE(priv->representor_id);
 402
 403         return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_VF &&
 404                MLX5_REPRESENTOR_REPR(-1) == repr;
 405 }
 406
 407 /**
 408  * Decide whether representor ID is a SF port representor.
 409  *
 410  * @param dev
 411  *   Pointer to Ethernet device structure.
 412  *
 413  * @return
 414  *   Non-zero if HPF, otherwise 0.
 415  */
 416 bool
 417 mlx5_is_sf_repr(struct rte_eth_dev *dev)
 418 {
 419         struct mlx5_priv *priv = dev->data->dev_private;
 420         int type = MLX5_REPRESENTOR_TYPE(priv->representor_id);
 421
 422         return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_SF;
 423 }
 424
 425 /**
 426  * Initialize the ASO aging management structure.
 427  *
 428  * @param[in] sh
 429  *   Pointer to mlx5_dev_ctx_shared object to free
 430  *
 431  * @return
 432  *   0 on success, a negative errno value otherwise and rte_errno is set.
 433  */
 434 int
 435 mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh)
 436 {
 437         int err;
 438
 439         if (sh->aso_age_mng)
 440                 return 0;
 441         sh->aso_age_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->aso_age_mng),
 442                                       RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 443         if (!sh->aso_age_mng) {
 444                 DRV_LOG(ERR, "aso_age_mng allocation was failed.");
 445                 rte_errno = ENOMEM;
 446                 return -ENOMEM;
 447         }
 448         err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_FLOW_HIT);
 449         if (err) {
 450                 mlx5_free(sh->aso_age_mng);
 451                 return -1;
 452         }
 453         rte_spinlock_init(&sh->aso_age_mng->resize_sl);
 454         rte_spinlock_init(&sh->aso_age_mng->free_sl);
 455         LIST_INIT(&sh->aso_age_mng->free);
 456         return 0;
 457 }
 458
 459 /**
 460  * Close and release all the resources of the ASO aging management structure.
 461  *
 462  * @param[in] sh
 463  *   Pointer to mlx5_dev_ctx_shared object to free.
 464  */
 465 static void
 466 mlx5_flow_aso_age_mng_close(struct mlx5_dev_ctx_shared *sh)
 467 {
 468         int i, j;
 469
 470         mlx5_aso_flow_hit_queue_poll_stop(sh);
 471         mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_FLOW_HIT);
 472         if (sh->aso_age_mng->pools) {
 473                 struct mlx5_aso_age_pool *pool;
 474
 475                 for (i = 0; i < sh->aso_age_mng->next; ++i) {
 476                         pool = sh->aso_age_mng->pools[i];
 477                         claim_zero(mlx5_devx_cmd_destroy
 478                                                 (pool->flow_hit_aso_obj));
 479                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j)
 480                                 if (pool->actions[j].dr_action)
 481                                         claim_zero
 482                                             (mlx5_flow_os_destroy_flow_action
 483                                               (pool->actions[j].dr_action));
 484                         mlx5_free(pool);
 485                 }
 486                 mlx5_free(sh->aso_age_mng->pools);
 487         }
 488         mlx5_free(sh->aso_age_mng);
 489 }
 490
 491 /**
 492  * Initialize the shared aging list information per port.
 493  *
 494  * @param[in] sh
 495  *   Pointer to mlx5_dev_ctx_shared object.
 496  */
 497 static void
 498 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
 499 {
 500         uint32_t i;
 501         struct mlx5_age_info *age_info;
 502
 503         for (i = 0; i < sh->max_port; i++) {
 504                 age_info = &sh->port[i].age_info;
 505                 age_info->flags = 0;
 506                 TAILQ_INIT(&age_info->aged_counters);
 507                 LIST_INIT(&age_info->aged_aso);
 508                 rte_spinlock_init(&age_info->aged_sl);
 509                 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
 510         }
 511 }
 512
 513 /**
 514  * Initialize the counters management structure.
 515  *
 516  * @param[in] sh
 517  *   Pointer to mlx5_dev_ctx_shared object to free
 518  */
 519 static void
 520 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
 521 {
 522         struct mlx5_hca_attr *attr = &sh->cdev->config.hca_attr;
 523         int i;
 524
 525         memset(&sh->cmng, 0, sizeof(sh->cmng));
 526         TAILQ_INIT(&sh->cmng.flow_counters);
 527         sh->cmng.min_id = MLX5_CNT_BATCH_OFFSET;
 528         sh->cmng.max_id = -1;
 529         sh->cmng.last_pool_idx = POOL_IDX_INVALID;
 530         rte_spinlock_init(&sh->cmng.pool_update_sl);
 531         for (i = 0; i < MLX5_COUNTER_TYPE_MAX; i++) {
 532                 TAILQ_INIT(&sh->cmng.counters[i]);
 533                 rte_spinlock_init(&sh->cmng.csl[i]);
 534         }
 535         if (sh->devx && !haswell_broadwell_cpu) {
 536                 sh->cmng.relaxed_ordering_write = attr->relaxed_ordering_write;
 537                 sh->cmng.relaxed_ordering_read = attr->relaxed_ordering_read;
 538         }
 539 }
 540
 541 /**
 542  * Destroy all the resources allocated for a counter memory management.
 543  *
 544  * @param[in] mng
 545  *   Pointer to the memory management structure.
 546  */
 547 static void
 548 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
 549 {
 550         uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
 551
 552         LIST_REMOVE(mng, next);
 553         claim_zero(mlx5_devx_cmd_destroy(mng->dm));
 554         claim_zero(mlx5_os_umem_dereg(mng->umem));
 555         mlx5_free(mem);
 556 }
 557
 558 /**
 559  * Close and release all the resources of the counters management.
 560  *
 561  * @param[in] sh
 562  *   Pointer to mlx5_dev_ctx_shared object to free.
 563  */
 564 static void
 565 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
 566 {
 567         struct mlx5_counter_stats_mem_mng *mng;
 568         int i, j;
 569         int retries = 1024;
 570
 571         rte_errno = 0;
 572         while (--retries) {
 573                 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
 574                 if (rte_errno != EINPROGRESS)
 575                         break;
 576                 rte_pause();
 577         }
 578
 579         if (sh->cmng.pools) {
 580                 struct mlx5_flow_counter_pool *pool;
 581                 uint16_t n_valid = sh->cmng.n_valid;
 582                 bool fallback = sh->cmng.counter_fallback;
 583
 584                 for (i = 0; i < n_valid; ++i) {
 585                         pool = sh->cmng.pools[i];
 586                         if (!fallback && pool->min_dcs)
 587                                 claim_zero(mlx5_devx_cmd_destroy
 588                                                                (pool->min_dcs));
 589                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
 590                                 struct mlx5_flow_counter *cnt =
 591                                                 MLX5_POOL_GET_CNT(pool, j);
 592
 593                                 if (cnt->action)
 594                                         claim_zero
 595                                          (mlx5_flow_os_destroy_flow_action
 596                                           (cnt->action));
 597                                 if (fallback && MLX5_POOL_GET_CNT
 598                                     (pool, j)->dcs_when_free)
 599                                         claim_zero(mlx5_devx_cmd_destroy
 600                                                    (cnt->dcs_when_free));
 601                         }
 602                         mlx5_free(pool);
 603                 }
 604                 mlx5_free(sh->cmng.pools);
 605         }
 606         mng = LIST_FIRST(&sh->cmng.mem_mngs);
 607         while (mng) {
 608                 mlx5_flow_destroy_counter_stat_mem_mng(mng);
 609                 mng = LIST_FIRST(&sh->cmng.mem_mngs);
 610         }
 611         memset(&sh->cmng, 0, sizeof(sh->cmng));
 612 }
 613
 614 /**
 615  * Initialize the aso flow meters management structure.
 616  *
 617  * @param[in] sh
 618  *   Pointer to mlx5_dev_ctx_shared object to free
 619  */
 620 int
 621 mlx5_aso_flow_mtrs_mng_init(struct mlx5_dev_ctx_shared *sh)
 622 {
 623         if (!sh->mtrmng) {
 624                 sh->mtrmng = mlx5_malloc(MLX5_MEM_ZERO,
 625                         sizeof(*sh->mtrmng),
 626                         RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 627                 if (!sh->mtrmng) {
 628                         DRV_LOG(ERR,
 629                         "meter management allocation was failed.");
 630                         rte_errno = ENOMEM;
 631                         return -ENOMEM;
 632                 }
 633                 if (sh->meter_aso_en) {
 634                         rte_spinlock_init(&sh->mtrmng->pools_mng.mtrsl);
 635                         LIST_INIT(&sh->mtrmng->pools_mng.meters);
 636                 }
 637                 sh->mtrmng->def_policy_id = MLX5_INVALID_POLICY_ID;
 638         }
 639         return 0;
 640 }
 641
 642 /**
 643  * Close and release all the resources of
 644  * the ASO flow meter management structure.
 645  *
 646  * @param[in] sh
 647  *   Pointer to mlx5_dev_ctx_shared object to free.
 648  */
 649 static void
 650 mlx5_aso_flow_mtrs_mng_close(struct mlx5_dev_ctx_shared *sh)
 651 {
 652         struct mlx5_aso_mtr_pool *mtr_pool;
 653         struct mlx5_flow_mtr_mng *mtrmng = sh->mtrmng;
 654         uint32_t idx;
 655 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
 656         struct mlx5_aso_mtr *aso_mtr;
 657         int i;
 658 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
 659
 660         if (sh->meter_aso_en) {
 661                 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_POLICER);
 662                 idx = mtrmng->pools_mng.n_valid;
 663                 while (idx--) {
 664                         mtr_pool = mtrmng->pools_mng.pools[idx];
 665 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
 666                         for (i = 0; i < MLX5_ASO_MTRS_PER_POOL; i++) {
 667                                 aso_mtr = &mtr_pool->mtrs[i];
 668                                 if (aso_mtr->fm.meter_action)
 669                                         claim_zero
 670                                         (mlx5_glue->destroy_flow_action
 671                                         (aso_mtr->fm.meter_action));
 672                         }
 673 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
 674                         claim_zero(mlx5_devx_cmd_destroy
 675                                                 (mtr_pool->devx_obj));
 676                         mtrmng->pools_mng.n_valid--;
 677                         mlx5_free(mtr_pool);
 678                 }
 679                 mlx5_free(sh->mtrmng->pools_mng.pools);
 680         }
 681         mlx5_free(sh->mtrmng);
 682         sh->mtrmng = NULL;
 683 }
 684
 685 /* Send FLOW_AGED event if needed. */
 686 void
 687 mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh)
 688 {
 689         struct mlx5_age_info *age_info;
 690         uint32_t i;
 691
 692         for (i = 0; i < sh->max_port; i++) {
 693                 age_info = &sh->port[i].age_info;
 694                 if (!MLX5_AGE_GET(age_info, MLX5_AGE_EVENT_NEW))
 695                         continue;
 696                 MLX5_AGE_UNSET(age_info, MLX5_AGE_EVENT_NEW);
 697                 if (MLX5_AGE_GET(age_info, MLX5_AGE_TRIGGER)) {
 698                         MLX5_AGE_UNSET(age_info, MLX5_AGE_TRIGGER);
 699                         rte_eth_dev_callback_process
 700                                 (&rte_eth_devices[sh->port[i].devx_ih_port_id],
 701                                 RTE_ETH_EVENT_FLOW_AGED, NULL);
 702                 }
 703         }
 704 }
 705
 706 /*
 707  * Initialize the ASO connection tracking structure.
 708  *
 709  * @param[in] sh
 710  *   Pointer to mlx5_dev_ctx_shared object.
 711  *
 712  * @return
 713  *   0 on success, a negative errno value otherwise and rte_errno is set.
 714  */
 715 int
 716 mlx5_flow_aso_ct_mng_init(struct mlx5_dev_ctx_shared *sh)
 717 {
 718         int err;
 719
 720         if (sh->ct_mng)
 721                 return 0;
 722         sh->ct_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->ct_mng),
 723                                  RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 724         if (!sh->ct_mng) {
 725                 DRV_LOG(ERR, "ASO CT management allocation failed.");
 726                 rte_errno = ENOMEM;
 727                 return -rte_errno;
 728         }
 729         err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_CONNECTION_TRACKING);
 730         if (err) {
 731                 mlx5_free(sh->ct_mng);
 732                 /* rte_errno should be extracted from the failure. */
 733                 rte_errno = EINVAL;
 734                 return -rte_errno;
 735         }
 736         rte_spinlock_init(&sh->ct_mng->ct_sl);
 737         rte_rwlock_init(&sh->ct_mng->resize_rwl);
 738         LIST_INIT(&sh->ct_mng->free_cts);
 739         return 0;
 740 }
 741
 742 /*
 743  * Close and release all the resources of the
 744  * ASO connection tracking management structure.
 745  *
 746  * @param[in] sh
 747  *   Pointer to mlx5_dev_ctx_shared object to free.
 748  */
 749 static void
 750 mlx5_flow_aso_ct_mng_close(struct mlx5_dev_ctx_shared *sh)
 751 {
 752         struct mlx5_aso_ct_pools_mng *mng = sh->ct_mng;
 753         struct mlx5_aso_ct_pool *ct_pool;
 754         struct mlx5_aso_ct_action *ct;
 755         uint32_t idx;
 756         uint32_t val;
 757         uint32_t cnt;
 758         int i;
 759
 760         mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_CONNECTION_TRACKING);
 761         idx = mng->next;
 762         while (idx--) {
 763                 cnt = 0;
 764                 ct_pool = mng->pools[idx];
 765                 for (i = 0; i < MLX5_ASO_CT_ACTIONS_PER_POOL; i++) {
 766                         ct = &ct_pool->actions[i];
 767                         val = __atomic_fetch_sub(&ct->refcnt, 1,
 768                                                  __ATOMIC_RELAXED);
 769                         MLX5_ASSERT(val == 1);
 770                         if (val > 1)
 771                                 cnt++;
 772 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
 773                         if (ct->dr_action_orig)
 774                                 claim_zero(mlx5_glue->destroy_flow_action
 775                                                         (ct->dr_action_orig));
 776                         if (ct->dr_action_rply)
 777                                 claim_zero(mlx5_glue->destroy_flow_action
 778                                                         (ct->dr_action_rply));
 779 #endif
 780                 }
 781                 claim_zero(mlx5_devx_cmd_destroy(ct_pool->devx_obj));
 782                 if (cnt) {
 783                         DRV_LOG(DEBUG, "%u ASO CT objects are being used in the pool %u",
 784                                 cnt, i);
 785                 }
 786                 mlx5_free(ct_pool);
 787                 /* in case of failure. */
 788                 mng->next--;
 789         }
 790         mlx5_free(mng->pools);
 791         mlx5_free(mng);
 792         /* Management structure must be cleared to 0s during allocation. */
 793         sh->ct_mng = NULL;
 794 }
 795
 796 /**
 797  * Initialize the flow resources' indexed mempool.
 798  *
 799  * @param[in] sh
 800  *   Pointer to mlx5_dev_ctx_shared object.
 801  * @param[in] config
 802  *   Pointer to user dev config.
 803  */
 804 static void
 805 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
 806                        const struct mlx5_dev_config *config)
 807 {
 808         uint8_t i;
 809         struct mlx5_indexed_pool_config cfg;
 810
 811         for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
 812                 cfg = mlx5_ipool_cfg[i];
 813                 switch (i) {
 814                 default:
 815                         break;
 816                 /*
 817                  * Set MLX5_IPOOL_MLX5_FLOW ipool size
 818                  * according to PCI function flow configuration.
 819                  */
 820                 case MLX5_IPOOL_MLX5_FLOW:
 821                         cfg.size = config->dv_flow_en ?
 822                                 sizeof(struct mlx5_flow_handle) :
 823                                 MLX5_FLOW_HANDLE_VERBS_SIZE;
 824                         break;
 825                 }
 826                 if (config->reclaim_mode) {
 827                         cfg.release_mem_en = 1;
 828                         cfg.per_core_cache = 0;
 829                 } else {
 830                         cfg.release_mem_en = 0;
 831                 }
 832                 sh->ipool[i] = mlx5_ipool_create(&cfg);
 833         }
 834 }
 835
 836
 837 /**
 838  * Release the flow resources' indexed mempool.
 839  *
 840  * @param[in] sh
 841  *   Pointer to mlx5_dev_ctx_shared object.
 842  */
 843 static void
 844 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
 845 {
 846         uint8_t i;
 847
 848         for (i = 0; i < MLX5_IPOOL_MAX; ++i)
 849                 mlx5_ipool_destroy(sh->ipool[i]);
 850         for (i = 0; i < MLX5_MAX_MODIFY_NUM; ++i)
 851                 if (sh->mdh_ipools[i])
 852                         mlx5_ipool_destroy(sh->mdh_ipools[i]);
 853 }
 854
 855 /*
 856  * Check if dynamic flex parser for eCPRI already exists.
 857  *
 858  * @param dev
 859  *   Pointer to Ethernet device structure.
 860  *
 861  * @return
 862  *   true on exists, false on not.
 863  */
 864 bool
 865 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
 866 {
 867         struct mlx5_priv *priv = dev->data->dev_private;
 868         struct mlx5_flex_parser_profiles *prf =
 869                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 870
 871         return !!prf->obj;
 872 }
 873
 874 /*
 875  * Allocation of a flex parser for eCPRI. Once created, this parser related
 876  * resources will be held until the device is closed.
 877  *
 878  * @param dev
 879  *   Pointer to Ethernet device structure.
 880  *
 881  * @return
 882  *   0 on success, a negative errno value otherwise and rte_errno is set.
 883  */
 884 int
 885 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
 886 {
 887         struct mlx5_priv *priv = dev->data->dev_private;
 888         struct mlx5_flex_parser_profiles *prf =
 889                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 890         struct mlx5_devx_graph_node_attr node = {
 891                 .modify_field_select = 0,
 892         };
 893         uint32_t ids[8];
 894         int ret;
 895
 896         if (!priv->config.hca_attr.parse_graph_flex_node) {
 897                 DRV_LOG(ERR, "Dynamic flex parser is not supported "
 898                         "for device %s.", priv->dev_data->name);
 899                 return -ENOTSUP;
 900         }
 901         node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED;
 902         /* 8 bytes now: 4B common header + 4B message body header. */
 903         node.header_length_base_value = 0x8;
 904         /* After MAC layer: Ether / VLAN. */
 905         node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC;
 906         /* Type of compared condition should be 0xAEFE in the L2 layer. */
 907         node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI;
 908         /* Sample #0: type in common header. */
 909         node.sample[0].flow_match_sample_en = 1;
 910         /* Fixed offset. */
 911         node.sample[0].flow_match_sample_offset_mode = 0x0;
 912         /* Only the 2nd byte will be used. */
 913         node.sample[0].flow_match_sample_field_base_offset = 0x0;
 914         /* Sample #1: message payload. */
 915         node.sample[1].flow_match_sample_en = 1;
 916         /* Fixed offset. */
 917         node.sample[1].flow_match_sample_offset_mode = 0x0;
 918         /*
 919          * Only the first two bytes will be used right now, and its offset will
 920          * start after the common header that with the length of a DW(u32).
 921          */
 922         node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);
 923         prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->cdev->ctx, &node);
 924         if (!prf->obj) {
 925                 DRV_LOG(ERR, "Failed to create flex parser node object.");
 926                 return (rte_errno == 0) ? -ENODEV : -rte_errno;
 927         }
 928         prf->num = 2;
 929         ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num);
 930         if (ret) {
 931                 DRV_LOG(ERR, "Failed to query sample IDs.");
 932                 return (rte_errno == 0) ? -ENODEV : -rte_errno;
 933         }
 934         prf->offset[0] = 0x0;
 935         prf->offset[1] = sizeof(uint32_t);
 936         prf->ids[0] = ids[0];
 937         prf->ids[1] = ids[1];
 938         return 0;
 939 }
 940
 941 /*
 942  * Destroy the flex parser node, including the parser itself, input / output
 943  * arcs and DW samples. Resources could be reused then.
 944  *
 945  * @param dev
 946  *   Pointer to Ethernet device structure.
 947  */
 948 static void
 949 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
 950 {
 951         struct mlx5_priv *priv = dev->data->dev_private;
 952         struct mlx5_flex_parser_profiles *prf =
 953                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 954
 955         if (prf->obj)
 956                 mlx5_devx_cmd_destroy(prf->obj);
 957         prf->obj = NULL;
 958 }
 959
 960 uint32_t
 961 mlx5_get_supported_sw_parsing_offloads(const struct mlx5_hca_attr *attr)
 962 {
 963         uint32_t sw_parsing_offloads = 0;
 964
 965         if (attr->swp) {
 966                 sw_parsing_offloads |= MLX5_SW_PARSING_CAP;
 967                 if (attr->swp_csum)
 968                         sw_parsing_offloads |= MLX5_SW_PARSING_CSUM_CAP;
 969
 970                 if (attr->swp_lso)
 971                         sw_parsing_offloads |= MLX5_SW_PARSING_TSO_CAP;
 972         }
 973         return sw_parsing_offloads;
 974 }
 975
 976 uint32_t
 977 mlx5_get_supported_tunneling_offloads(const struct mlx5_hca_attr *attr)
 978 {
 979         uint32_t tn_offloads = 0;
 980
 981         if (attr->tunnel_stateless_vxlan)
 982                 tn_offloads |= MLX5_TUNNELED_OFFLOADS_VXLAN_CAP;
 983         if (attr->tunnel_stateless_gre)
 984                 tn_offloads |= MLX5_TUNNELED_OFFLOADS_GRE_CAP;
 985         if (attr->tunnel_stateless_geneve_rx)
 986                 tn_offloads |= MLX5_TUNNELED_OFFLOADS_GENEVE_CAP;
 987         return tn_offloads;
 988 }
 989
 990 /*
 991  * Allocate Rx and Tx UARs in robust fashion.
 992  * This routine handles the following UAR allocation issues:
 993  *
 994  *  - tries to allocate the UAR with the most appropriate memory
 995  *    mapping type from the ones supported by the host
 996  *
 997  *  - tries to allocate the UAR with non-NULL base address
 998  *    OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as
 999  *    UAR base address if UAR was not the first object in the UAR page.
1000  *    It caused the PMD failure and we should try to get another UAR
1001  *    till we get the first one with non-NULL base address returned.
1002  */
1003 static int
1004 mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh,
1005                      const struct mlx5_common_dev_config *config)
1006 {
1007         uint32_t uar_mapping, retry;
1008         int err = 0;
1009         void *base_addr;
1010
1011         for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
1012 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
1013                 /* Control the mapping type according to the settings. */
1014                 uar_mapping = (config->dbnc == MLX5_TXDB_NCACHED) ?
1015                               MLX5DV_UAR_ALLOC_TYPE_NC :
1016                               MLX5DV_UAR_ALLOC_TYPE_BF;
1017 #else
1018                 RTE_SET_USED(config);
1019                 /*
1020                  * It seems we have no way to control the memory mapping type
1021                  * for the UAR, the default "Write-Combining" type is supposed.
1022                  * The UAR initialization on queue creation queries the
1023                  * actual mapping type done by Verbs/kernel and setups the
1024                  * PMD datapath accordingly.
1025                  */
1026                 uar_mapping = 0;
1027 #endif
1028                 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->cdev->ctx,
1029                                                        uar_mapping);
1030 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
1031                 if (!sh->tx_uar &&
1032                     uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
1033                         if (config->dbnc == MLX5_TXDB_CACHED ||
1034                             config->dbnc == MLX5_TXDB_HEURISTIC)
1035                                 DRV_LOG(WARNING, "Devarg tx_db_nc setting "
1036                                                  "is not supported by DevX");
1037                         /*
1038                          * In some environments like virtual machine
1039                          * the Write Combining mapped might be not supported
1040                          * and UAR allocation fails. We try "Non-Cached"
1041                          * mapping for the case. The tx_burst routines take
1042                          * the UAR mapping type into account on UAR setup
1043                          * on queue creation.
1044                          */
1045                         DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (BF)");
1046                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
1047                         sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->cdev->ctx,
1048                                                                uar_mapping);
1049                 } else if (!sh->tx_uar &&
1050                            uar_mapping == MLX5DV_UAR_ALLOC_TYPE_NC) {
1051                         if (config->dbnc == MLX5_TXDB_NCACHED)
1052                                 DRV_LOG(WARNING, "Devarg tx_db_nc settings "
1053                                                  "is not supported by DevX");
1054                         /*
1055                          * If Verbs/kernel does not support "Non-Cached"
1056                          * try the "Write-Combining".
1057                          */
1058                         DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (NC)");
1059                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_BF;
1060                         sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->cdev->ctx,
1061                                                                uar_mapping);
1062                 }
1063 #endif
1064                 if (!sh->tx_uar) {
1065                         DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (BF/NC)");
1066                         err = ENOMEM;
1067                         goto exit;
1068                 }
1069                 base_addr = mlx5_os_get_devx_uar_base_addr(sh->tx_uar);
1070                 if (base_addr)
1071                         break;
1072                 /*
1073                  * The UARs are allocated by rdma_core within the
1074                  * IB device context, on context closure all UARs
1075                  * will be freed, should be no memory/object leakage.
1076                  */
1077                 DRV_LOG(DEBUG, "Retrying to allocate Tx DevX UAR");
1078                 sh->tx_uar = NULL;
1079         }
1080         /* Check whether we finally succeeded with valid UAR allocation. */
1081         if (!sh->tx_uar) {
1082                 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (NULL base)");
1083                 err = ENOMEM;
1084                 goto exit;
1085         }
1086         for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
1087                 uar_mapping = 0;
1088                 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar(sh->cdev->ctx,
1089                                                             uar_mapping);
1090 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
1091                 if (!sh->devx_rx_uar &&
1092                     uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
1093                         /*
1094                          * Rx UAR is used to control interrupts only,
1095                          * should be no datapath noticeable impact,
1096                          * can try "Non-Cached" mapping safely.
1097                          */
1098                         DRV_LOG(DEBUG, "Failed to allocate Rx DevX UAR (BF)");
1099                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
1100                         sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
1101                                                    (sh->cdev->ctx, uar_mapping);
1102                 }
1103 #endif
1104                 if (!sh->devx_rx_uar) {
1105                         DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (BF/NC)");
1106                         err = ENOMEM;
1107                         goto exit;
1108                 }
1109                 base_addr = mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar);
1110                 if (base_addr)
1111                         break;
1112                 /*
1113                  * The UARs are allocated by rdma_core within the
1114                  * IB device context, on context closure all UARs
1115                  * will be freed, should be no memory/object leakage.
1116                  */
1117                 DRV_LOG(DEBUG, "Retrying to allocate Rx DevX UAR");
1118                 sh->devx_rx_uar = NULL;
1119         }
1120         /* Check whether we finally succeeded with valid UAR allocation. */
1121         if (!sh->devx_rx_uar) {
1122                 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (NULL base)");
1123                 err = ENOMEM;
1124         }
1125 exit:
1126         return err;
1127 }
1128
1129 /**
1130  * Unregister the mempool from the protection domain.
1131  *
1132  * @param sh
1133  *   Pointer to the device shared context.
1134  * @param mp
1135  *   Mempool being unregistered.
1136  */
1137 static void
1138 mlx5_dev_ctx_shared_mempool_unregister(struct mlx5_dev_ctx_shared *sh,
1139                                        struct rte_mempool *mp)
1140 {
1141         struct mlx5_mp_id mp_id;
1142
1143         mlx5_mp_id_init(&mp_id, 0);
1144         if (mlx5_mr_mempool_unregister(&sh->cdev->mr_scache, mp, &mp_id) < 0)
1145                 DRV_LOG(WARNING, "Failed to unregister mempool %s for PD %p: %s",
1146                         mp->name, sh->cdev->pd, rte_strerror(rte_errno));
1147 }
1148
1149 /**
1150  * rte_mempool_walk() callback to register mempools
1151  * for the protection domain.
1152  *
1153  * @param mp
1154  *   The mempool being walked.
1155  * @param arg
1156  *   Pointer to the device shared context.
1157  */
1158 static void
1159 mlx5_dev_ctx_shared_mempool_register_cb(struct rte_mempool *mp, void *arg)
1160 {
1161         struct mlx5_dev_ctx_shared *sh = arg;
1162         struct mlx5_mp_id mp_id;
1163         int ret;
1164
1165         mlx5_mp_id_init(&mp_id, 0);
1166         ret = mlx5_mr_mempool_register(&sh->cdev->mr_scache, sh->cdev->pd, mp,
1167                                        &mp_id);
1168         if (ret < 0 && rte_errno != EEXIST)
1169                 DRV_LOG(ERR, "Failed to register existing mempool %s for PD %p: %s",
1170                         mp->name, sh->cdev->pd, rte_strerror(rte_errno));
1171 }
1172
1173 /**
1174  * rte_mempool_walk() callback to unregister mempools
1175  * from the protection domain.
1176  *
1177  * @param mp
1178  *   The mempool being walked.
1179  * @param arg
1180  *   Pointer to the device shared context.
1181  */
1182 static void
1183 mlx5_dev_ctx_shared_mempool_unregister_cb(struct rte_mempool *mp, void *arg)
1184 {
1185         mlx5_dev_ctx_shared_mempool_unregister
1186                                 ((struct mlx5_dev_ctx_shared *)arg, mp);
1187 }
1188
1189 /**
1190  * Mempool life cycle callback for Ethernet devices.
1191  *
1192  * @param event
1193  *   Mempool life cycle event.
1194  * @param mp
1195  *   Associated mempool.
1196  * @param arg
1197  *   Pointer to a device shared context.
1198  */
1199 static void
1200 mlx5_dev_ctx_shared_mempool_event_cb(enum rte_mempool_event event,
1201                                      struct rte_mempool *mp, void *arg)
1202 {
1203         struct mlx5_dev_ctx_shared *sh = arg;
1204         struct mlx5_mp_id mp_id;
1205
1206         switch (event) {
1207         case RTE_MEMPOOL_EVENT_READY:
1208                 mlx5_mp_id_init(&mp_id, 0);
1209                 if (mlx5_mr_mempool_register(&sh->cdev->mr_scache, sh->cdev->pd,
1210                                              mp, &mp_id) < 0)
1211                         DRV_LOG(ERR, "Failed to register new mempool %s for PD %p: %s",
1212                                 mp->name, sh->cdev->pd,
1213                                 rte_strerror(rte_errno));
1214                 break;
1215         case RTE_MEMPOOL_EVENT_DESTROY:
1216                 mlx5_dev_ctx_shared_mempool_unregister(sh, mp);
1217                 break;
1218         }
1219 }
1220
1221 /**
1222  * Callback used when implicit mempool registration is disabled
1223  * in order to track Rx mempool destruction.
1224  *
1225  * @param event
1226  *   Mempool life cycle event.
1227  * @param mp
1228  *   An Rx mempool registered explicitly when the port is started.
1229  * @param arg
1230  *   Pointer to a device shared context.
1231  */
1232 static void
1233 mlx5_dev_ctx_shared_rx_mempool_event_cb(enum rte_mempool_event event,
1234                                         struct rte_mempool *mp, void *arg)
1235 {
1236         struct mlx5_dev_ctx_shared *sh = arg;
1237
1238         if (event == RTE_MEMPOOL_EVENT_DESTROY)
1239                 mlx5_dev_ctx_shared_mempool_unregister(sh, mp);
1240 }
1241
1242 int
1243 mlx5_dev_ctx_shared_mempool_subscribe(struct rte_eth_dev *dev)
1244 {
1245         struct mlx5_priv *priv = dev->data->dev_private;
1246         struct mlx5_dev_ctx_shared *sh = priv->sh;
1247         int ret;
1248
1249         /* Check if we only need to track Rx mempool destruction. */
1250         if (!sh->cdev->config.mr_mempool_reg_en) {
1251                 ret = rte_mempool_event_callback_register
1252                                 (mlx5_dev_ctx_shared_rx_mempool_event_cb, sh);
1253                 return ret == 0 || rte_errno == EEXIST ? 0 : ret;
1254         }
1255         /* Callback for this shared context may be already registered. */
1256         ret = rte_mempool_event_callback_register
1257                                 (mlx5_dev_ctx_shared_mempool_event_cb, sh);
1258         if (ret != 0 && rte_errno != EEXIST)
1259                 return ret;
1260         /* Register mempools only once for this shared context. */
1261         if (ret == 0)
1262                 rte_mempool_walk(mlx5_dev_ctx_shared_mempool_register_cb, sh);
1263         return 0;
1264 }
1265
1266 /**
1267  * Allocate shared device context. If there is multiport device the
1268  * master and representors will share this context, if there is single
1269  * port dedicated device, the context will be used by only given
1270  * port due to unification.
1271  *
1272  * Routine first searches the context for the specified device name,
1273  * if found the shared context assumed and reference counter is incremented.
1274  * If no context found the new one is created and initialized with specified
1275  * device context and parameters.
1276  *
1277  * @param[in] spawn
1278  *   Pointer to the device attributes (name, port, etc).
1279  * @param[in] config
1280  *   Pointer to device configuration structure.
1281  *
1282  * @return
1283  *   Pointer to mlx5_dev_ctx_shared object on success,
1284  *   otherwise NULL and rte_errno is set.
1285  */
1286 struct mlx5_dev_ctx_shared *
1287 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
1288                           const struct mlx5_dev_config *config)
1289 {
1290         struct mlx5_dev_ctx_shared *sh;
1291         int err = 0;
1292         uint32_t i;
1293         struct mlx5_devx_tis_attr tis_attr = { 0 };
1294
1295         MLX5_ASSERT(spawn);
1296         /* Secondary process should not create the shared context. */
1297         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1298         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1299         /* Search for IB context by device name. */
1300         LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
1301                 if (!strcmp(sh->ibdev_name, spawn->phys_dev_name)) {
1302                         sh->refcnt++;
1303                         goto exit;
1304                 }
1305         }
1306         /* No device found, we have to create new shared context. */
1307         MLX5_ASSERT(spawn->max_port);
1308         sh = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
1309                          sizeof(struct mlx5_dev_ctx_shared) +
1310                          spawn->max_port *
1311                          sizeof(struct mlx5_dev_shared_port),
1312                          RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
1313         if (!sh) {
1314                 DRV_LOG(ERR, "shared context allocation failure");
1315                 rte_errno  = ENOMEM;
1316                 goto exit;
1317         }
1318         pthread_mutex_init(&sh->txpp.mutex, NULL);
1319         sh->numa_node = spawn->cdev->dev->numa_node;
1320         sh->cdev = spawn->cdev;
1321         sh->devx = sh->cdev->config.devx;
1322         if (spawn->bond_info)
1323                 sh->bond = *spawn->bond_info;
1324         err = mlx5_os_get_dev_attr(sh->cdev, &sh->device_attr);
1325         if (err) {
1326                 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
1327                 goto error;
1328         }
1329         sh->refcnt = 1;
1330         sh->max_port = spawn->max_port;
1331         sh->reclaim_mode = config->reclaim_mode;
1332         strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->cdev->ctx),
1333                 sizeof(sh->ibdev_name) - 1);
1334         strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->cdev->ctx),
1335                 sizeof(sh->ibdev_path) - 1);
1336         /*
1337          * Setting port_id to max unallowed value means
1338          * there is no interrupt subhandler installed for
1339          * the given port index i.
1340          */
1341         for (i = 0; i < sh->max_port; i++) {
1342                 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
1343                 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
1344         }
1345         if (sh->devx) {
1346                 sh->td = mlx5_devx_cmd_create_td(sh->cdev->ctx);
1347                 if (!sh->td) {
1348                         DRV_LOG(ERR, "TD allocation failure");
1349                         err = ENOMEM;
1350                         goto error;
1351                 }
1352                 tis_attr.transport_domain = sh->td->id;
1353                 sh->tis = mlx5_devx_cmd_create_tis(sh->cdev->ctx, &tis_attr);
1354                 if (!sh->tis) {
1355                         DRV_LOG(ERR, "TIS allocation failure");
1356                         err = ENOMEM;
1357                         goto error;
1358                 }
1359                 err = mlx5_alloc_rxtx_uars(sh, &sh->cdev->config);
1360                 if (err)
1361                         goto error;
1362                 MLX5_ASSERT(sh->tx_uar);
1363                 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->tx_uar));
1364
1365                 MLX5_ASSERT(sh->devx_rx_uar);
1366                 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar));
1367         }
1368 #ifndef RTE_ARCH_64
1369         /* Initialize UAR access locks for 32bit implementations. */
1370         rte_spinlock_init(&sh->uar_lock_cq);
1371         for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
1372                 rte_spinlock_init(&sh->uar_lock[i]);
1373 #endif
1374         mlx5_os_dev_shared_handler_install(sh);
1375         if (LIST_EMPTY(&mlx5_dev_ctx_list)) {
1376                 err = mlx5_flow_os_init_workspace_once();
1377                 if (err)
1378                         goto error;
1379         }
1380         mlx5_flow_aging_init(sh);
1381         mlx5_flow_counters_mng_init(sh);
1382         mlx5_flow_ipool_create(sh, config);
1383         /* Add context to the global device list. */
1384         LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
1385         rte_spinlock_init(&sh->geneve_tlv_opt_sl);
1386 exit:
1387         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1388         return sh;
1389 error:
1390         pthread_mutex_destroy(&sh->txpp.mutex);
1391         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1392         MLX5_ASSERT(sh);
1393         if (sh->tis)
1394                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1395         if (sh->td)
1396                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1397         if (sh->devx_rx_uar)
1398                 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1399         if (sh->tx_uar)
1400                 mlx5_glue->devx_free_uar(sh->tx_uar);
1401         mlx5_free(sh);
1402         MLX5_ASSERT(err > 0);
1403         rte_errno = err;
1404         return NULL;
1405 }
1406
1407 /**
1408  * Free shared IB device context. Decrement counter and if zero free
1409  * all allocated resources and close handles.
1410  *
1411  * @param[in] sh
1412  *   Pointer to mlx5_dev_ctx_shared object to free
1413  */
1414 void
1415 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
1416 {
1417         int ret;
1418
1419         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1420 #ifdef RTE_LIBRTE_MLX5_DEBUG
1421         /* Check the object presence in the list. */
1422         struct mlx5_dev_ctx_shared *lctx;
1423
1424         LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
1425                 if (lctx == sh)
1426                         break;
1427         MLX5_ASSERT(lctx);
1428         if (lctx != sh) {
1429                 DRV_LOG(ERR, "Freeing non-existing shared IB context");
1430                 goto exit;
1431         }
1432 #endif
1433         MLX5_ASSERT(sh);
1434         MLX5_ASSERT(sh->refcnt);
1435         /* Secondary process should not free the shared context. */
1436         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1437         if (--sh->refcnt)
1438                 goto exit;
1439         /* Stop watching for mempool events and unregister all mempools. */
1440         ret = rte_mempool_event_callback_unregister
1441                                 (mlx5_dev_ctx_shared_mempool_event_cb, sh);
1442         if (ret < 0 && rte_errno == ENOENT)
1443                 ret = rte_mempool_event_callback_unregister
1444                                 (mlx5_dev_ctx_shared_rx_mempool_event_cb, sh);
1445         if (ret == 0)
1446                 rte_mempool_walk(mlx5_dev_ctx_shared_mempool_unregister_cb,
1447                                  sh);
1448         /* Remove context from the global device list. */
1449         LIST_REMOVE(sh, next);
1450         /* Release flow workspaces objects on the last device. */
1451         if (LIST_EMPTY(&mlx5_dev_ctx_list))
1452                 mlx5_flow_os_release_workspace();
1453         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1454         /*
1455          *  Ensure there is no async event handler installed.
1456          *  Only primary process handles async device events.
1457          **/
1458         mlx5_flow_counters_mng_close(sh);
1459         if (sh->aso_age_mng) {
1460                 mlx5_flow_aso_age_mng_close(sh);
1461                 sh->aso_age_mng = NULL;
1462         }
1463         if (sh->mtrmng)
1464                 mlx5_aso_flow_mtrs_mng_close(sh);
1465         mlx5_flow_ipool_destroy(sh);
1466         mlx5_os_dev_shared_handler_uninstall(sh);
1467         if (sh->tx_uar) {
1468                 mlx5_glue->devx_free_uar(sh->tx_uar);
1469                 sh->tx_uar = NULL;
1470         }
1471         if (sh->tis)
1472                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1473         if (sh->td)
1474                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1475         if (sh->devx_rx_uar)
1476                 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1477         MLX5_ASSERT(sh->geneve_tlv_option_resource == NULL);
1478         pthread_mutex_destroy(&sh->txpp.mutex);
1479         mlx5_free(sh);
1480         return;
1481 exit:
1482         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1483 }
1484
1485 /**
1486  * Destroy table hash list.
1487  *
1488  * @param[in] priv
1489  *   Pointer to the private device data structure.
1490  */
1491 void
1492 mlx5_free_table_hash_list(struct mlx5_priv *priv)
1493 {
1494         struct mlx5_dev_ctx_shared *sh = priv->sh;
1495
1496         if (!sh->flow_tbls)
1497                 return;
1498         mlx5_hlist_destroy(sh->flow_tbls);
1499         sh->flow_tbls = NULL;
1500 }
1501
1502 /**
1503  * Initialize flow table hash list and create the root tables entry
1504  * for each domain.
1505  *
1506  * @param[in] priv
1507  *   Pointer to the private device data structure.
1508  *
1509  * @return
1510  *   Zero on success, positive error code otherwise.
1511  */
1512 int
1513 mlx5_alloc_table_hash_list(struct mlx5_priv *priv __rte_unused)
1514 {
1515         int err = 0;
1516         /* Tables are only used in DV and DR modes. */
1517 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
1518         struct mlx5_dev_ctx_shared *sh = priv->sh;
1519         char s[MLX5_NAME_SIZE];
1520
1521         MLX5_ASSERT(sh);
1522         snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1523         sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE,
1524                                           false, true, sh,
1525                                           flow_dv_tbl_create_cb,
1526                                           flow_dv_tbl_match_cb,
1527                                           flow_dv_tbl_remove_cb,
1528                                           flow_dv_tbl_clone_cb,
1529                                           flow_dv_tbl_clone_free_cb);
1530         if (!sh->flow_tbls) {
1531                 DRV_LOG(ERR, "flow tables with hash creation failed.");
1532                 err = ENOMEM;
1533                 return err;
1534         }
1535 #ifndef HAVE_MLX5DV_DR
1536         struct rte_flow_error error;
1537         struct rte_eth_dev *dev = &rte_eth_devices[priv->dev_data->port_id];
1538
1539         /*
1540          * In case we have not DR support, the zero tables should be created
1541          * because DV expect to see them even if they cannot be created by
1542          * RDMA-CORE.
1543          */
1544         if (!flow_dv_tbl_resource_get(dev, 0, 0, 0, 0,
1545                 NULL, 0, 1, 0, &error) ||
1546             !flow_dv_tbl_resource_get(dev, 0, 1, 0, 0,
1547                 NULL, 0, 1, 0, &error) ||
1548             !flow_dv_tbl_resource_get(dev, 0, 0, 1, 0,
1549                 NULL, 0, 1, 0, &error)) {
1550                 err = ENOMEM;
1551                 goto error;
1552         }
1553         return err;
1554 error:
1555         mlx5_free_table_hash_list(priv);
1556 #endif /* HAVE_MLX5DV_DR */
1557 #endif
1558         return err;
1559 }
1560
1561 /**
1562  * Retrieve integer value from environment variable.
1563  *
1564  * @param[in] name
1565  *   Environment variable name.
1566  *
1567  * @return
1568  *   Integer value, 0 if the variable is not set.
1569  */
1570 int
1571 mlx5_getenv_int(const char *name)
1572 {
1573         const char *val = getenv(name);
1574
1575         if (val == NULL)
1576                 return 0;
1577         return atoi(val);
1578 }
1579
1580 /**
1581  * DPDK callback to add udp tunnel port
1582  *
1583  * @param[in] dev
1584  *   A pointer to eth_dev
1585  * @param[in] udp_tunnel
1586  *   A pointer to udp tunnel
1587  *
1588  * @return
1589  *   0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1590  */
1591 int
1592 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1593                          struct rte_eth_udp_tunnel *udp_tunnel)
1594 {
1595         MLX5_ASSERT(udp_tunnel != NULL);
1596         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1597             udp_tunnel->udp_port == 4789)
1598                 return 0;
1599         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1600             udp_tunnel->udp_port == 4790)
1601                 return 0;
1602         return -ENOTSUP;
1603 }
1604
1605 /**
1606  * Initialize process private data structure.
1607  *
1608  * @param dev
1609  *   Pointer to Ethernet device structure.
1610  *
1611  * @return
1612  *   0 on success, a negative errno value otherwise and rte_errno is set.
1613  */
1614 int
1615 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1616 {
1617         struct mlx5_priv *priv = dev->data->dev_private;
1618         struct mlx5_proc_priv *ppriv;
1619         size_t ppriv_size;
1620
1621         mlx5_proc_priv_uninit(dev);
1622         /*
1623          * UAR register table follows the process private structure. BlueFlame
1624          * registers for Tx queues are stored in the table.
1625          */
1626         ppriv_size =
1627                 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1628         ppriv = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, ppriv_size,
1629                             RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1630         if (!ppriv) {
1631                 rte_errno = ENOMEM;
1632                 return -rte_errno;
1633         }
1634         ppriv->uar_table_sz = priv->txqs_n;
1635         dev->process_private = ppriv;
1636         return 0;
1637 }
1638
1639 /**
1640  * Un-initialize process private data structure.
1641  *
1642  * @param dev
1643  *   Pointer to Ethernet device structure.
1644  */
1645 void
1646 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1647 {
1648         if (!dev->process_private)
1649                 return;
1650         mlx5_free(dev->process_private);
1651         dev->process_private = NULL;
1652 }
1653
1654 /**
1655  * DPDK callback to close the device.
1656  *
1657  * Destroy all queues and objects, free memory.
1658  *
1659  * @param dev
1660  *   Pointer to Ethernet device structure.
1661  */
1662 int
1663 mlx5_dev_close(struct rte_eth_dev *dev)
1664 {
1665         struct mlx5_priv *priv = dev->data->dev_private;
1666         unsigned int i;
1667         int ret;
1668
1669         if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1670                 /* Check if process_private released. */
1671                 if (!dev->process_private)
1672                         return 0;
1673                 mlx5_tx_uar_uninit_secondary(dev);
1674                 mlx5_proc_priv_uninit(dev);
1675                 rte_eth_dev_release_port(dev);
1676                 return 0;
1677         }
1678         if (!priv->sh)
1679                 return 0;
1680         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1681                 dev->data->port_id,
1682                 ((priv->sh->cdev->ctx != NULL) ?
1683                 mlx5_os_get_ctx_device_name(priv->sh->cdev->ctx) : ""));
1684         /*
1685          * If default mreg copy action is removed at the stop stage,
1686          * the search will return none and nothing will be done anymore.
1687          */
1688         mlx5_flow_stop_default(dev);
1689         mlx5_traffic_disable(dev);
1690         /*
1691          * If all the flows are already flushed in the device stop stage,
1692          * then this will return directly without any action.
1693          */
1694         mlx5_flow_list_flush(dev, MLX5_FLOW_TYPE_GEN, true);
1695         mlx5_action_handle_flush(dev);
1696         mlx5_flow_meter_flush(dev, NULL);
1697         /* Prevent crashes when queues are still in use. */
1698         dev->rx_pkt_burst = removed_rx_burst;
1699         dev->tx_pkt_burst = removed_tx_burst;
1700         rte_wmb();
1701         /* Disable datapath on secondary process. */
1702         mlx5_mp_os_req_stop_rxtx(dev);
1703         /* Free the eCPRI flex parser resource. */
1704         mlx5_flex_parser_ecpri_release(dev);
1705         if (priv->rxqs != NULL) {
1706                 /* XXX race condition if mlx5_rx_burst() is still running. */
1707                 rte_delay_us_sleep(1000);
1708                 for (i = 0; (i != priv->rxqs_n); ++i)
1709                         mlx5_rxq_release(dev, i);
1710                 priv->rxqs_n = 0;
1711                 priv->rxqs = NULL;
1712         }
1713         if (priv->representor) {
1714                 /* Each representor has a dedicated interrupts handler */
1715                 mlx5_free(dev->intr_handle);
1716                 dev->intr_handle = NULL;
1717         }
1718         if (priv->txqs != NULL) {
1719                 /* XXX race condition if mlx5_tx_burst() is still running. */
1720                 rte_delay_us_sleep(1000);
1721                 for (i = 0; (i != priv->txqs_n); ++i)
1722                         mlx5_txq_release(dev, i);
1723                 priv->txqs_n = 0;
1724                 priv->txqs = NULL;
1725         }
1726         mlx5_proc_priv_uninit(dev);
1727         if (priv->q_counters) {
1728                 mlx5_devx_cmd_destroy(priv->q_counters);
1729                 priv->q_counters = NULL;
1730         }
1731         if (priv->drop_queue.hrxq)
1732                 mlx5_drop_action_destroy(dev);
1733         if (priv->mreg_cp_tbl)
1734                 mlx5_hlist_destroy(priv->mreg_cp_tbl);
1735         mlx5_mprq_free_mp(dev);
1736         if (priv->sh->ct_mng)
1737                 mlx5_flow_aso_ct_mng_close(priv->sh);
1738         mlx5_os_free_shared_dr(priv);
1739         if (priv->rss_conf.rss_key != NULL)
1740                 mlx5_free(priv->rss_conf.rss_key);
1741         if (priv->reta_idx != NULL)
1742                 mlx5_free(priv->reta_idx);
1743         if (priv->config.vf)
1744                 mlx5_os_mac_addr_flush(dev);
1745         if (priv->nl_socket_route >= 0)
1746                 close(priv->nl_socket_route);
1747         if (priv->nl_socket_rdma >= 0)
1748                 close(priv->nl_socket_rdma);
1749         if (priv->vmwa_context)
1750                 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1751         ret = mlx5_hrxq_verify(dev);
1752         if (ret)
1753                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1754                         dev->data->port_id);
1755         ret = mlx5_ind_table_obj_verify(dev);
1756         if (ret)
1757                 DRV_LOG(WARNING, "port %u some indirection table still remain",
1758                         dev->data->port_id);
1759         ret = mlx5_rxq_obj_verify(dev);
1760         if (ret)
1761                 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1762                         dev->data->port_id);
1763         ret = mlx5_rxq_verify(dev);
1764         if (ret)
1765                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1766                         dev->data->port_id);
1767         ret = mlx5_txq_obj_verify(dev);
1768         if (ret)
1769                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1770                         dev->data->port_id);
1771         ret = mlx5_txq_verify(dev);
1772         if (ret)
1773                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1774                         dev->data->port_id);
1775         ret = mlx5_flow_verify(dev);
1776         if (ret)
1777                 DRV_LOG(WARNING, "port %u some flows still remain",
1778                         dev->data->port_id);
1779         if (priv->hrxqs)
1780                 mlx5_list_destroy(priv->hrxqs);
1781         /*
1782          * Free the shared context in last turn, because the cleanup
1783          * routines above may use some shared fields, like
1784          * mlx5_os_mac_addr_flush() uses ibdev_path for retrieveing
1785          * ifindex if Netlink fails.
1786          */
1787         mlx5_free_shared_dev_ctx(priv->sh);
1788         if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1789                 unsigned int c = 0;
1790                 uint16_t port_id;
1791
1792                 MLX5_ETH_FOREACH_DEV(port_id, dev->device) {
1793                         struct mlx5_priv *opriv =
1794                                 rte_eth_devices[port_id].data->dev_private;
1795
1796                         if (!opriv ||
1797                             opriv->domain_id != priv->domain_id ||
1798                             &rte_eth_devices[port_id] == dev)
1799                                 continue;
1800                         ++c;
1801                         break;
1802                 }
1803                 if (!c)
1804                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1805         }
1806         memset(priv, 0, sizeof(*priv));
1807         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1808         /*
1809          * Reset mac_addrs to NULL such that it is not freed as part of
1810          * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1811          * it is freed when dev_private is freed.
1812          */
1813         dev->data->mac_addrs = NULL;
1814         return 0;
1815 }
1816
1817 const struct eth_dev_ops mlx5_dev_ops = {
1818         .dev_configure = mlx5_dev_configure,
1819         .dev_start = mlx5_dev_start,
1820         .dev_stop = mlx5_dev_stop,
1821         .dev_set_link_down = mlx5_set_link_down,
1822         .dev_set_link_up = mlx5_set_link_up,
1823         .dev_close = mlx5_dev_close,
1824         .promiscuous_enable = mlx5_promiscuous_enable,
1825         .promiscuous_disable = mlx5_promiscuous_disable,
1826         .allmulticast_enable = mlx5_allmulticast_enable,
1827         .allmulticast_disable = mlx5_allmulticast_disable,
1828         .link_update = mlx5_link_update,
1829         .stats_get = mlx5_stats_get,
1830         .stats_reset = mlx5_stats_reset,
1831         .xstats_get = mlx5_xstats_get,
1832         .xstats_reset = mlx5_xstats_reset,
1833         .xstats_get_names = mlx5_xstats_get_names,
1834         .fw_version_get = mlx5_fw_version_get,
1835         .dev_infos_get = mlx5_dev_infos_get,
1836         .representor_info_get = mlx5_representor_info_get,
1837         .read_clock = mlx5_txpp_read_clock,
1838         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1839         .vlan_filter_set = mlx5_vlan_filter_set,
1840         .rx_queue_setup = mlx5_rx_queue_setup,
1841         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1842         .tx_queue_setup = mlx5_tx_queue_setup,
1843         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1844         .rx_queue_release = mlx5_rx_queue_release,
1845         .tx_queue_release = mlx5_tx_queue_release,
1846         .rx_queue_start = mlx5_rx_queue_start,
1847         .rx_queue_stop = mlx5_rx_queue_stop,
1848         .tx_queue_start = mlx5_tx_queue_start,
1849         .tx_queue_stop = mlx5_tx_queue_stop,
1850         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1851         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1852         .mac_addr_remove = mlx5_mac_addr_remove,
1853         .mac_addr_add = mlx5_mac_addr_add,
1854         .mac_addr_set = mlx5_mac_addr_set,
1855         .set_mc_addr_list = mlx5_set_mc_addr_list,
1856         .mtu_set = mlx5_dev_set_mtu,
1857         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1858         .vlan_offload_set = mlx5_vlan_offload_set,
1859         .reta_update = mlx5_dev_rss_reta_update,
1860         .reta_query = mlx5_dev_rss_reta_query,
1861         .rss_hash_update = mlx5_rss_hash_update,
1862         .rss_hash_conf_get = mlx5_rss_hash_conf_get,
1863         .flow_ops_get = mlx5_flow_ops_get,
1864         .rxq_info_get = mlx5_rxq_info_get,
1865         .txq_info_get = mlx5_txq_info_get,
1866         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1867         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1868         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1869         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1870         .is_removed = mlx5_is_removed,
1871         .udp_tunnel_port_add  = mlx5_udp_tunnel_port_add,
1872         .get_module_info = mlx5_get_module_info,
1873         .get_module_eeprom = mlx5_get_module_eeprom,
1874         .hairpin_cap_get = mlx5_hairpin_cap_get,
1875         .mtr_ops_get = mlx5_flow_meter_ops_get,
1876         .hairpin_bind = mlx5_hairpin_bind,
1877         .hairpin_unbind = mlx5_hairpin_unbind,
1878         .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1879         .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1880         .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1881         .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1882         .get_monitor_addr = mlx5_get_monitor_addr,
1883 };
1884
1885 /* Available operations from secondary process. */
1886 const struct eth_dev_ops mlx5_dev_sec_ops = {
1887         .stats_get = mlx5_stats_get,
1888         .stats_reset = mlx5_stats_reset,
1889         .xstats_get = mlx5_xstats_get,
1890         .xstats_reset = mlx5_xstats_reset,
1891         .xstats_get_names = mlx5_xstats_get_names,
1892         .fw_version_get = mlx5_fw_version_get,
1893         .dev_infos_get = mlx5_dev_infos_get,
1894         .representor_info_get = mlx5_representor_info_get,
1895         .read_clock = mlx5_txpp_read_clock,
1896         .rx_queue_start = mlx5_rx_queue_start,
1897         .rx_queue_stop = mlx5_rx_queue_stop,
1898         .tx_queue_start = mlx5_tx_queue_start,
1899         .tx_queue_stop = mlx5_tx_queue_stop,
1900         .rxq_info_get = mlx5_rxq_info_get,
1901         .txq_info_get = mlx5_txq_info_get,
1902         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1903         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1904         .get_module_info = mlx5_get_module_info,
1905         .get_module_eeprom = mlx5_get_module_eeprom,
1906 };
1907
1908 /* Available operations in flow isolated mode. */
1909 const struct eth_dev_ops mlx5_dev_ops_isolate = {
1910         .dev_configure = mlx5_dev_configure,
1911         .dev_start = mlx5_dev_start,
1912         .dev_stop = mlx5_dev_stop,
1913         .dev_set_link_down = mlx5_set_link_down,
1914         .dev_set_link_up = mlx5_set_link_up,
1915         .dev_close = mlx5_dev_close,
1916         .promiscuous_enable = mlx5_promiscuous_enable,
1917         .promiscuous_disable = mlx5_promiscuous_disable,
1918         .allmulticast_enable = mlx5_allmulticast_enable,
1919         .allmulticast_disable = mlx5_allmulticast_disable,
1920         .link_update = mlx5_link_update,
1921         .stats_get = mlx5_stats_get,
1922         .stats_reset = mlx5_stats_reset,
1923         .xstats_get = mlx5_xstats_get,
1924         .xstats_reset = mlx5_xstats_reset,
1925         .xstats_get_names = mlx5_xstats_get_names,
1926         .fw_version_get = mlx5_fw_version_get,
1927         .dev_infos_get = mlx5_dev_infos_get,
1928         .representor_info_get = mlx5_representor_info_get,
1929         .read_clock = mlx5_txpp_read_clock,
1930         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1931         .vlan_filter_set = mlx5_vlan_filter_set,
1932         .rx_queue_setup = mlx5_rx_queue_setup,
1933         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1934         .tx_queue_setup = mlx5_tx_queue_setup,
1935         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1936         .rx_queue_release = mlx5_rx_queue_release,
1937         .tx_queue_release = mlx5_tx_queue_release,
1938         .rx_queue_start = mlx5_rx_queue_start,
1939         .rx_queue_stop = mlx5_rx_queue_stop,
1940         .tx_queue_start = mlx5_tx_queue_start,
1941         .tx_queue_stop = mlx5_tx_queue_stop,
1942         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1943         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1944         .mac_addr_remove = mlx5_mac_addr_remove,
1945         .mac_addr_add = mlx5_mac_addr_add,
1946         .mac_addr_set = mlx5_mac_addr_set,
1947         .set_mc_addr_list = mlx5_set_mc_addr_list,
1948         .mtu_set = mlx5_dev_set_mtu,
1949         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1950         .vlan_offload_set = mlx5_vlan_offload_set,
1951         .flow_ops_get = mlx5_flow_ops_get,
1952         .rxq_info_get = mlx5_rxq_info_get,
1953         .txq_info_get = mlx5_txq_info_get,
1954         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1955         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1956         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1957         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1958         .is_removed = mlx5_is_removed,
1959         .get_module_info = mlx5_get_module_info,
1960         .get_module_eeprom = mlx5_get_module_eeprom,
1961         .hairpin_cap_get = mlx5_hairpin_cap_get,
1962         .mtr_ops_get = mlx5_flow_meter_ops_get,
1963         .hairpin_bind = mlx5_hairpin_bind,
1964         .hairpin_unbind = mlx5_hairpin_unbind,
1965         .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1966         .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1967         .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1968         .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1969         .get_monitor_addr = mlx5_get_monitor_addr,
1970 };
1971
1972 /**
1973  * Verify and store value for device argument.
1974  *
1975  * @param[in] key
1976  *   Key argument to verify.
1977  * @param[in] val
1978  *   Value associated with key.
1979  * @param opaque
1980  *   User data.
1981  *
1982  * @return
1983  *   0 on success, a negative errno value otherwise and rte_errno is set.
1984  */
1985 static int
1986 mlx5_args_check(const char *key, const char *val, void *opaque)
1987 {
1988         struct mlx5_dev_config *config = opaque;
1989         unsigned long mod;
1990         signed long tmp;
1991
1992         /* No-op, port representors are processed in mlx5_dev_spawn(). */
1993         if (!strcmp(MLX5_DRIVER_KEY, key) || !strcmp(MLX5_REPRESENTOR, key) ||
1994             !strcmp(MLX5_SYS_MEM_EN, key) || !strcmp(MLX5_TX_DB_NC, key) ||
1995             !strcmp(MLX5_MR_MEMPOOL_REG_EN, key) ||
1996             !strcmp(MLX5_MR_EXT_MEMSEG_EN, key))
1997                 return 0;
1998         errno = 0;
1999         tmp = strtol(val, NULL, 0);
2000         if (errno) {
2001                 rte_errno = errno;
2002                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
2003                 return -rte_errno;
2004         }
2005         if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
2006                 /* Negative values are acceptable for some keys only. */
2007                 rte_errno = EINVAL;
2008                 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
2009                 return -rte_errno;
2010         }
2011         mod = tmp >= 0 ? tmp : -tmp;
2012         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
2013                 if (tmp > MLX5_CQE_RESP_FORMAT_L34H_STRIDX) {
2014                         DRV_LOG(ERR, "invalid CQE compression "
2015                                      "format parameter");
2016                         rte_errno = EINVAL;
2017                         return -rte_errno;
2018                 }
2019                 config->cqe_comp = !!tmp;
2020                 config->cqe_comp_fmt = tmp;
2021         } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
2022                 config->hw_padding = !!tmp;
2023         } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
2024                 config->mprq.enabled = !!tmp;
2025         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
2026                 config->mprq.stride_num_n = tmp;
2027         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
2028                 config->mprq.stride_size_n = tmp;
2029         } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
2030                 config->mprq.max_memcpy_len = tmp;
2031         } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
2032                 config->mprq.min_rxqs_num = tmp;
2033         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
2034                 DRV_LOG(WARNING, "%s: deprecated parameter,"
2035                                  " converted to txq_inline_max", key);
2036                 config->txq_inline_max = tmp;
2037         } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
2038                 config->txq_inline_max = tmp;
2039         } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
2040                 config->txq_inline_min = tmp;
2041         } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
2042                 config->txq_inline_mpw = tmp;
2043         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
2044                 config->txqs_inline = tmp;
2045         } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
2046                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
2047         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
2048                 config->mps = !!tmp;
2049         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
2050                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
2051         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
2052                 DRV_LOG(WARNING, "%s: deprecated parameter,"
2053                                  " converted to txq_inline_mpw", key);
2054                 config->txq_inline_mpw = tmp;
2055         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
2056                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
2057         } else if (strcmp(MLX5_TX_PP, key) == 0) {
2058                 if (!mod) {
2059                         DRV_LOG(ERR, "Zero Tx packet pacing parameter");
2060                         rte_errno = EINVAL;
2061                         return -rte_errno;
2062                 }
2063                 config->tx_pp = tmp;
2064         } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
2065                 config->tx_skew = tmp;
2066         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
2067                 config->rx_vec_en = !!tmp;
2068         } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
2069                 config->l3_vxlan_en = !!tmp;
2070         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
2071                 config->vf_nl_en = !!tmp;
2072         } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
2073                 config->dv_esw_en = !!tmp;
2074         } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
2075                 config->dv_flow_en = !!tmp;
2076         } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
2077                 if (tmp != MLX5_XMETA_MODE_LEGACY &&
2078                     tmp != MLX5_XMETA_MODE_META16 &&
2079                     tmp != MLX5_XMETA_MODE_META32 &&
2080                     tmp != MLX5_XMETA_MODE_MISS_INFO) {
2081                         DRV_LOG(ERR, "invalid extensive "
2082                                      "metadata parameter");
2083                         rte_errno = EINVAL;
2084                         return -rte_errno;
2085                 }
2086                 if (tmp != MLX5_XMETA_MODE_MISS_INFO)
2087                         config->dv_xmeta_en = tmp;
2088                 else
2089                         config->dv_miss_info = 1;
2090         } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
2091                 config->lacp_by_user = !!tmp;
2092         } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
2093                 config->max_dump_files_num = tmp;
2094         } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
2095                 config->lro.timeout = tmp;
2096         } else if (strcmp(RTE_DEVARGS_KEY_CLASS, key) == 0) {
2097                 DRV_LOG(DEBUG, "class argument is %s.", val);
2098         } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
2099                 config->log_hp_size = tmp;
2100         } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
2101                 if (tmp != MLX5_RCM_NONE &&
2102                     tmp != MLX5_RCM_LIGHT &&
2103                     tmp != MLX5_RCM_AGGR) {
2104                         DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
2105                         rte_errno = EINVAL;
2106                         return -rte_errno;
2107                 }
2108                 config->reclaim_mode = tmp;
2109         } else if (strcmp(MLX5_DECAP_EN, key) == 0) {
2110                 config->decap_en = !!tmp;
2111         } else if (strcmp(MLX5_ALLOW_DUPLICATE_PATTERN, key) == 0) {
2112                 config->allow_duplicate_pattern = !!tmp;
2113         } else {
2114                 DRV_LOG(WARNING, "%s: unknown parameter", key);
2115                 rte_errno = EINVAL;
2116                 return -rte_errno;
2117         }
2118         return 0;
2119 }
2120
2121 /**
2122  * Parse device parameters.
2123  *
2124  * @param config
2125  *   Pointer to device configuration structure.
2126  * @param devargs
2127  *   Device arguments structure.
2128  *
2129  * @return
2130  *   0 on success, a negative errno value otherwise and rte_errno is set.
2131  */
2132 int
2133 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
2134 {
2135         const char **params = (const char *[]){
2136                 MLX5_DRIVER_KEY,
2137                 MLX5_RXQ_CQE_COMP_EN,
2138                 MLX5_RXQ_PKT_PAD_EN,
2139                 MLX5_RX_MPRQ_EN,
2140                 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
2141                 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
2142                 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
2143                 MLX5_RXQS_MIN_MPRQ,
2144                 MLX5_TXQ_INLINE,
2145                 MLX5_TXQ_INLINE_MIN,
2146                 MLX5_TXQ_INLINE_MAX,
2147                 MLX5_TXQ_INLINE_MPW,
2148                 MLX5_TXQS_MIN_INLINE,
2149                 MLX5_TXQS_MAX_VEC,
2150                 MLX5_TXQ_MPW_EN,
2151                 MLX5_TXQ_MPW_HDR_DSEG_EN,
2152                 MLX5_TXQ_MAX_INLINE_LEN,
2153                 MLX5_TX_DB_NC,
2154                 MLX5_TX_PP,
2155                 MLX5_TX_SKEW,
2156                 MLX5_TX_VEC_EN,
2157                 MLX5_RX_VEC_EN,
2158                 MLX5_L3_VXLAN_EN,
2159                 MLX5_VF_NL_EN,
2160                 MLX5_DV_ESW_EN,
2161                 MLX5_DV_FLOW_EN,
2162                 MLX5_DV_XMETA_EN,
2163                 MLX5_LACP_BY_USER,
2164                 MLX5_MR_EXT_MEMSEG_EN,
2165                 MLX5_REPRESENTOR,
2166                 MLX5_MAX_DUMP_FILES_NUM,
2167                 MLX5_LRO_TIMEOUT_USEC,
2168                 RTE_DEVARGS_KEY_CLASS,
2169                 MLX5_HP_BUF_SIZE,
2170                 MLX5_RECLAIM_MEM,
2171                 MLX5_SYS_MEM_EN,
2172                 MLX5_DECAP_EN,
2173                 MLX5_ALLOW_DUPLICATE_PATTERN,
2174                 MLX5_MR_MEMPOOL_REG_EN,
2175                 NULL,
2176         };
2177         struct rte_kvargs *kvlist;
2178         int ret = 0;
2179         int i;
2180
2181         if (devargs == NULL)
2182                 return 0;
2183         /* Following UGLY cast is done to pass checkpatch. */
2184         kvlist = rte_kvargs_parse(devargs->args, params);
2185         if (kvlist == NULL) {
2186                 rte_errno = EINVAL;
2187                 return -rte_errno;
2188         }
2189         /* Process parameters. */
2190         for (i = 0; (params[i] != NULL); ++i) {
2191                 if (rte_kvargs_count(kvlist, params[i])) {
2192                         ret = rte_kvargs_process(kvlist, params[i],
2193                                                  mlx5_args_check, config);
2194                         if (ret) {
2195                                 rte_errno = EINVAL;
2196                                 rte_kvargs_free(kvlist);
2197                                 return -rte_errno;
2198                         }
2199                 }
2200         }
2201         rte_kvargs_free(kvlist);
2202         return 0;
2203 }
2204
2205 /**
2206  * Configures the minimal amount of data to inline into WQE
2207  * while sending packets.
2208  *
2209  * - the txq_inline_min has the maximal priority, if this
2210  *   key is specified in devargs
2211  * - if DevX is enabled the inline mode is queried from the
2212  *   device (HCA attributes and NIC vport context if needed).
2213  * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
2214  *   and none (0 bytes) for other NICs
2215  *
2216  * @param spawn
2217  *   Verbs device parameters (name, port, switch_info) to spawn.
2218  * @param config
2219  *   Device configuration parameters.
2220  */
2221 void
2222 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
2223                     struct mlx5_dev_config *config)
2224 {
2225         if (config->txq_inline_min != MLX5_ARG_UNSET) {
2226                 /* Application defines size of inlined data explicitly. */
2227                 if (spawn->pci_dev != NULL) {
2228                         switch (spawn->pci_dev->id.device_id) {
2229                         case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2230                         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2231                                 if (config->txq_inline_min <
2232                                                (int)MLX5_INLINE_HSIZE_L2) {
2233                                         DRV_LOG(DEBUG,
2234                                                 "txq_inline_mix aligned to minimal ConnectX-4 required value %d",
2235                                                 (int)MLX5_INLINE_HSIZE_L2);
2236                                         config->txq_inline_min =
2237                                                         MLX5_INLINE_HSIZE_L2;
2238                                 }
2239                                 break;
2240                         }
2241                 }
2242                 goto exit;
2243         }
2244         if (config->hca_attr.eth_net_offloads) {
2245                 /* We have DevX enabled, inline mode queried successfully. */
2246                 switch (config->hca_attr.wqe_inline_mode) {
2247                 case MLX5_CAP_INLINE_MODE_L2:
2248                         /* outer L2 header must be inlined. */
2249                         config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2250                         goto exit;
2251                 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
2252                         /* No inline data are required by NIC. */
2253                         config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2254                         config->hw_vlan_insert =
2255                                 config->hca_attr.wqe_vlan_insert;
2256                         DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
2257                         goto exit;
2258                 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
2259                         /* inline mode is defined by NIC vport context. */
2260                         if (!config->hca_attr.eth_virt)
2261                                 break;
2262                         switch (config->hca_attr.vport_inline_mode) {
2263                         case MLX5_INLINE_MODE_NONE:
2264                                 config->txq_inline_min =
2265                                         MLX5_INLINE_HSIZE_NONE;
2266                                 goto exit;
2267                         case MLX5_INLINE_MODE_L2:
2268                                 config->txq_inline_min =
2269                                         MLX5_INLINE_HSIZE_L2;
2270                                 goto exit;
2271                         case MLX5_INLINE_MODE_IP:
2272                                 config->txq_inline_min =
2273                                         MLX5_INLINE_HSIZE_L3;
2274                                 goto exit;
2275                         case MLX5_INLINE_MODE_TCP_UDP:
2276                                 config->txq_inline_min =
2277                                         MLX5_INLINE_HSIZE_L4;
2278                                 goto exit;
2279                         case MLX5_INLINE_MODE_INNER_L2:
2280                                 config->txq_inline_min =
2281                                         MLX5_INLINE_HSIZE_INNER_L2;
2282                                 goto exit;
2283                         case MLX5_INLINE_MODE_INNER_IP:
2284                                 config->txq_inline_min =
2285                                         MLX5_INLINE_HSIZE_INNER_L3;
2286                                 goto exit;
2287                         case MLX5_INLINE_MODE_INNER_TCP_UDP:
2288                                 config->txq_inline_min =
2289                                         MLX5_INLINE_HSIZE_INNER_L4;
2290                                 goto exit;
2291                         }
2292                 }
2293         }
2294         if (spawn->pci_dev == NULL) {
2295                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2296                 goto exit;
2297         }
2298         /*
2299          * We get here if we are unable to deduce
2300          * inline data size with DevX. Try PCI ID
2301          * to determine old NICs.
2302          */
2303         switch (spawn->pci_dev->id.device_id) {
2304         case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2305         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2306         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
2307         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
2308                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2309                 config->hw_vlan_insert = 0;
2310                 break;
2311         case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
2312         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
2313         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
2314         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
2315                 /*
2316                  * These NICs support VLAN insertion from WQE and
2317                  * report the wqe_vlan_insert flag. But there is the bug
2318                  * and PFC control may be broken, so disable feature.
2319                  */
2320                 config->hw_vlan_insert = 0;
2321                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2322                 break;
2323         default:
2324                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2325                 break;
2326         }
2327 exit:
2328         DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
2329 }
2330
2331 /**
2332  * Configures the metadata mask fields in the shared context.
2333  *
2334  * @param [in] dev
2335  *   Pointer to Ethernet device.
2336  */
2337 void
2338 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
2339 {
2340         struct mlx5_priv *priv = dev->data->dev_private;
2341         struct mlx5_dev_ctx_shared *sh = priv->sh;
2342         uint32_t meta, mark, reg_c0;
2343
2344         reg_c0 = ~priv->vport_meta_mask;
2345         switch (priv->config.dv_xmeta_en) {
2346         case MLX5_XMETA_MODE_LEGACY:
2347                 meta = UINT32_MAX;
2348                 mark = MLX5_FLOW_MARK_MASK;
2349                 break;
2350         case MLX5_XMETA_MODE_META16:
2351                 meta = reg_c0 >> rte_bsf32(reg_c0);
2352                 mark = MLX5_FLOW_MARK_MASK;
2353                 break;
2354         case MLX5_XMETA_MODE_META32:
2355                 meta = UINT32_MAX;
2356                 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
2357                 break;
2358         default:
2359                 meta = 0;
2360                 mark = 0;
2361                 MLX5_ASSERT(false);
2362                 break;
2363         }
2364         if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
2365                 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
2366                                  sh->dv_mark_mask, mark);
2367         else
2368                 sh->dv_mark_mask = mark;
2369         if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
2370                 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
2371                                  sh->dv_meta_mask, meta);
2372         else
2373                 sh->dv_meta_mask = meta;
2374         if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
2375                 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
2376                                  sh->dv_meta_mask, reg_c0);
2377         else
2378                 sh->dv_regc0_mask = reg_c0;
2379         DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
2380         DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
2381         DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
2382         DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
2383 }
2384
2385 int
2386 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
2387 {
2388         static const char *const dynf_names[] = {
2389                 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
2390                 RTE_MBUF_DYNFLAG_METADATA_NAME,
2391                 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
2392         };
2393         unsigned int i;
2394
2395         if (n < RTE_DIM(dynf_names))
2396                 return -ENOMEM;
2397         for (i = 0; i < RTE_DIM(dynf_names); i++) {
2398                 if (names[i] == NULL)
2399                         return -EINVAL;
2400                 strcpy(names[i], dynf_names[i]);
2401         }
2402         return RTE_DIM(dynf_names);
2403 }
2404
2405 /**
2406  * Comparison callback to sort device data.
2407  *
2408  * This is meant to be used with qsort().
2409  *
2410  * @param a[in]
2411  *   Pointer to pointer to first data object.
2412  * @param b[in]
2413  *   Pointer to pointer to second data object.
2414  *
2415  * @return
2416  *   0 if both objects are equal, less than 0 if the first argument is less
2417  *   than the second, greater than 0 otherwise.
2418  */
2419 int
2420 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
2421                               struct mlx5_dev_config *config,
2422                               struct rte_device *dpdk_dev)
2423 {
2424         struct mlx5_dev_ctx_shared *sh = priv->sh;
2425         struct mlx5_dev_config *sh_conf = NULL;
2426         uint16_t port_id;
2427
2428         MLX5_ASSERT(sh);
2429         /* Nothing to compare for the single/first device. */
2430         if (sh->refcnt == 1)
2431                 return 0;
2432         /* Find the device with shared context. */
2433         MLX5_ETH_FOREACH_DEV(port_id, dpdk_dev) {
2434                 struct mlx5_priv *opriv =
2435                         rte_eth_devices[port_id].data->dev_private;
2436
2437                 if (opriv && opriv != priv && opriv->sh == sh) {
2438                         sh_conf = &opriv->config;
2439                         break;
2440                 }
2441         }
2442         if (!sh_conf)
2443                 return 0;
2444         if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
2445                 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
2446                              " for shared %s context", sh->ibdev_name);
2447                 rte_errno = EINVAL;
2448                 return rte_errno;
2449         }
2450         if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
2451                 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
2452                              " for shared %s context", sh->ibdev_name);
2453                 rte_errno = EINVAL;
2454                 return rte_errno;
2455         }
2456         return 0;
2457 }
2458
2459 /**
2460  * Look for the ethernet device belonging to mlx5 driver.
2461  *
2462  * @param[in] port_id
2463  *   port_id to start looking for device.
2464  * @param[in] odev
2465  *   Pointer to the hint device. When device is being probed
2466  *   the its siblings (master and preceding representors might
2467  *   not have assigned driver yet (because the mlx5_os_pci_probe()
2468  *   is not completed yet, for this case match on hint
2469  *   device may be used to detect sibling device.
2470  *
2471  * @return
2472  *   port_id of found device, RTE_MAX_ETHPORT if not found.
2473  */
2474 uint16_t
2475 mlx5_eth_find_next(uint16_t port_id, struct rte_device *odev)
2476 {
2477         while (port_id < RTE_MAX_ETHPORTS) {
2478                 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
2479
2480                 if (dev->state != RTE_ETH_DEV_UNUSED &&
2481                     dev->device &&
2482                     (dev->device == odev ||
2483                      (dev->device->driver &&
2484                      dev->device->driver->name &&
2485                      ((strcmp(dev->device->driver->name,
2486                               MLX5_PCI_DRIVER_NAME) == 0) ||
2487                       (strcmp(dev->device->driver->name,
2488                               MLX5_AUXILIARY_DRIVER_NAME) == 0)))))
2489                         break;
2490                 port_id++;
2491         }
2492         if (port_id >= RTE_MAX_ETHPORTS)
2493                 return RTE_MAX_ETHPORTS;
2494         return port_id;
2495 }
2496
2497 /**
2498  * Callback to remove a device.
2499  *
2500  * This function removes all Ethernet devices belong to a given device.
2501  *
2502  * @param[in] cdev
2503  *   Pointer to the generic device.
2504  *
2505  * @return
2506  *   0 on success, the function cannot fail.
2507  */
2508 int
2509 mlx5_net_remove(struct mlx5_common_device *cdev)
2510 {
2511         uint16_t port_id;
2512         int ret = 0;
2513
2514         RTE_ETH_FOREACH_DEV_OF(port_id, cdev->dev) {
2515                 /*
2516                  * mlx5_dev_close() is not registered to secondary process,
2517                  * call the close function explicitly for secondary process.
2518                  */
2519                 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
2520                         ret |= mlx5_dev_close(&rte_eth_devices[port_id]);
2521                 else
2522                         ret |= rte_eth_dev_close(port_id);
2523         }
2524         return ret == 0 ? 0 : -EIO;
2525 }
2526
2527 static const struct rte_pci_id mlx5_pci_id_map[] = {
2528         {
2529                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2530                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
2531         },
2532         {
2533                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2534                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
2535         },
2536         {
2537                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2538                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
2539         },
2540         {
2541                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2542                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
2543         },
2544         {
2545                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2546                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
2547         },
2548         {
2549                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2550                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
2551         },
2552         {
2553                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2554                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
2555         },
2556         {
2557                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2558                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
2559         },
2560         {
2561                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2562                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
2563         },
2564         {
2565                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2566                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
2567         },
2568         {
2569                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2570                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
2571         },
2572         {
2573                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2574                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
2575         },
2576         {
2577                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2578                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
2579         },
2580         {
2581                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2582                                 PCI_DEVICE_ID_MELLANOX_CONNECTXVF)
2583         },
2584         {
2585                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2586                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
2587         },
2588         {
2589                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2590                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
2591         },
2592         {
2593                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2594                                 PCI_DEVICE_ID_MELLANOX_CONNECTX7)
2595         },
2596         {
2597                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2598                                 PCI_DEVICE_ID_MELLANOX_CONNECTX7BF)
2599         },
2600         {
2601                 .vendor_id = 0
2602         }
2603 };
2604
2605 static struct mlx5_class_driver mlx5_net_driver = {
2606         .drv_class = MLX5_CLASS_ETH,
2607         .name = RTE_STR(MLX5_ETH_DRIVER_NAME),
2608         .id_table = mlx5_pci_id_map,
2609         .probe = mlx5_os_net_probe,
2610         .remove = mlx5_net_remove,
2611         .dma_map = mlx5_net_dma_map,
2612         .dma_unmap = mlx5_net_dma_unmap,
2613         .probe_again = 1,
2614         .intr_lsc = 1,
2615         .intr_rmv = 1,
2616 };
2617
2618 /* Initialize driver log type. */
2619 RTE_LOG_REGISTER_DEFAULT(mlx5_logtype, NOTICE)
2620
2621 /**
2622  * Driver initialization routine.
2623  */
2624 RTE_INIT(rte_mlx5_pmd_init)
2625 {
2626         pthread_mutex_init(&mlx5_dev_ctx_list_mutex, NULL);
2627         mlx5_common_init();
2628         /* Build the static tables for Verbs conversion. */
2629         mlx5_set_ptype_table();
2630         mlx5_set_cksum_table();
2631         mlx5_set_swp_types_table();
2632         if (mlx5_glue)
2633                 mlx5_class_driver_register(&mlx5_net_driver);
2634 }
2635
2636 RTE_PMD_EXPORT_NAME(MLX5_ETH_DRIVER_NAME, __COUNTER__);
2637 RTE_PMD_REGISTER_PCI_TABLE(MLX5_ETH_DRIVER_NAME, mlx5_pci_id_map);
2638 RTE_PMD_REGISTER_KMOD_DEP(MLX5_ETH_DRIVER_NAME, "* ib_uverbs & mlx5_core & mlx5_ib");