drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox.
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <assert.h>
  10 #include <dlfcn.h>
  11 #include <stdint.h>
  12 #include <stdlib.h>
  13 #include <errno.h>
  14 #include <net/if.h>
  15 #include <sys/mman.h>
  16
  17 /* Verbs header. */
  18 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  19 #ifdef PEDANTIC
  20 #pragma GCC diagnostic ignored "-Wpedantic"
  21 #endif
  22 #include <infiniband/verbs.h>
  23 #ifdef PEDANTIC
  24 #pragma GCC diagnostic error "-Wpedantic"
  25 #endif
  26
  27 #include <rte_malloc.h>
  28 #include <rte_ethdev_driver.h>
  29 #include <rte_ethdev_pci.h>
  30 #include <rte_pci.h>
  31 #include <rte_bus_pci.h>
  32 #include <rte_common.h>
  33 #include <rte_config.h>
  34 #include <rte_eal_memconfig.h>
  35 #include <rte_kvargs.h>
  36
  37 #include "mlx5.h"
  38 #include "mlx5_utils.h"
  39 #include "mlx5_rxtx.h"
  40 #include "mlx5_autoconf.h"
  41 #include "mlx5_defs.h"
  42 #include "mlx5_glue.h"
  43
  44 /* Device parameter to enable RX completion queue compression. */
  45 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  46
  47 /* Device parameter to configure inline send. */
  48 #define MLX5_TXQ_INLINE "txq_inline"
  49
  50 /*
  51  * Device parameter to configure the number of TX queues threshold for
  52  * enabling inline send.
  53  */
  54 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  55
  56 /* Device parameter to enable multi-packet send WQEs. */
  57 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
  58
  59 /* Device parameter to include 2 dsegs in the title WQEBB. */
  60 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
  61
  62 /* Device parameter to limit the size of inlining packet. */
  63 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
  64
  65 /* Device parameter to enable hardware Tx vector. */
  66 #define MLX5_TX_VEC_EN "tx_vec_en"
  67
  68 /* Device parameter to enable hardware Rx vector. */
  69 #define MLX5_RX_VEC_EN "rx_vec_en"
  70
  71 #ifndef HAVE_IBV_MLX5_MOD_MPW
  72 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2)
  73 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3)
  74 #endif
  75
  76 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP
  77 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4)
  78 #endif
  79
  80 /** Driver-specific log messages type. */
  81 int mlx5_logtype;
  82
  83 /**
  84  * Retrieve integer value from environment variable.
  85  *
  86  * @param[in] name
  87  *   Environment variable name.
  88  *
  89  * @return
  90  *   Integer value, 0 if the variable is not set.
  91  */
  92 int
  93 mlx5_getenv_int(const char *name)
  94 {
  95         const char *val = getenv(name);
  96
  97         if (val == NULL)
  98                 return 0;
  99         return atoi(val);
 100 }
 101
 102 /**
 103  * Verbs callback to allocate a memory. This function should allocate the space
 104  * according to the size provided residing inside a huge page.
 105  * Please note that all allocation must respect the alignment from libmlx5
 106  * (i.e. currently sysconf(_SC_PAGESIZE)).
 107  *
 108  * @param[in] size
 109  *   The size in bytes of the memory to allocate.
 110  * @param[in] data
 111  *   A pointer to the callback data.
 112  *
 113  * @return
 114  *   Allocated buffer, NULL otherwise and rte_errno is set.
 115  */
 116 static void *
 117 mlx5_alloc_verbs_buf(size_t size, void *data)
 118 {
 119         struct priv *priv = data;
 120         void *ret;
 121         size_t alignment = sysconf(_SC_PAGESIZE);
 122         unsigned int socket = SOCKET_ID_ANY;
 123
 124         if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) {
 125                 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
 126
 127                 socket = ctrl->socket;
 128         } else if (priv->verbs_alloc_ctx.type ==
 129                    MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) {
 130                 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
 131
 132                 socket = ctrl->socket;
 133         }
 134         assert(data != NULL);
 135         ret = rte_malloc_socket(__func__, size, alignment, socket);
 136         if (!ret && size)
 137                 rte_errno = ENOMEM;
 138         return ret;
 139 }
 140
 141 /**
 142  * Verbs callback to free a memory.
 143  *
 144  * @param[in] ptr
 145  *   A pointer to the memory to free.
 146  * @param[in] data
 147  *   A pointer to the callback data.
 148  */
 149 static void
 150 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused)
 151 {
 152         assert(data != NULL);
 153         rte_free(ptr);
 154 }
 155
 156 /**
 157  * DPDK callback to close the device.
 158  *
 159  * Destroy all queues and objects, free memory.
 160  *
 161  * @param dev
 162  *   Pointer to Ethernet device structure.
 163  */
 164 static void
 165 mlx5_dev_close(struct rte_eth_dev *dev)
 166 {
 167         struct priv *priv = dev->data->dev_private;
 168         unsigned int i;
 169         int ret;
 170
 171         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
 172                 dev->data->port_id,
 173                 ((priv->ctx != NULL) ? priv->ctx->device->name : ""));
 174         /* In case mlx5_dev_stop() has not been called. */
 175         mlx5_dev_interrupt_handler_uninstall(dev);
 176         mlx5_traffic_disable(dev);
 177         /* Prevent crashes when queues are still in use. */
 178         dev->rx_pkt_burst = removed_rx_burst;
 179         dev->tx_pkt_burst = removed_tx_burst;
 180         if (priv->rxqs != NULL) {
 181                 /* XXX race condition if mlx5_rx_burst() is still running. */
 182                 usleep(1000);
 183                 for (i = 0; (i != priv->rxqs_n); ++i)
 184                         mlx5_rxq_release(dev, i);
 185                 priv->rxqs_n = 0;
 186                 priv->rxqs = NULL;
 187         }
 188         if (priv->txqs != NULL) {
 189                 /* XXX race condition if mlx5_tx_burst() is still running. */
 190                 usleep(1000);
 191                 for (i = 0; (i != priv->txqs_n); ++i)
 192                         mlx5_txq_release(dev, i);
 193                 priv->txqs_n = 0;
 194                 priv->txqs = NULL;
 195         }
 196         if (priv->pd != NULL) {
 197                 assert(priv->ctx != NULL);
 198                 claim_zero(mlx5_glue->dealloc_pd(priv->pd));
 199                 claim_zero(mlx5_glue->close_device(priv->ctx));
 200         } else
 201                 assert(priv->ctx == NULL);
 202         if (priv->rss_conf.rss_key != NULL)
 203                 rte_free(priv->rss_conf.rss_key);
 204         if (priv->reta_idx != NULL)
 205                 rte_free(priv->reta_idx);
 206         if (priv->primary_socket)
 207                 mlx5_socket_uninit(dev);
 208         ret = mlx5_hrxq_ibv_verify(dev);
 209         if (ret)
 210                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
 211                         dev->data->port_id);
 212         ret = mlx5_ind_table_ibv_verify(dev);
 213         if (ret)
 214                 DRV_LOG(WARNING, "port %u some indirection table still remain",
 215                         dev->data->port_id);
 216         ret = mlx5_rxq_ibv_verify(dev);
 217         if (ret)
 218                 DRV_LOG(WARNING, "port %u some Verbs Rx queue still remain",
 219                         dev->data->port_id);
 220         ret = mlx5_rxq_verify(dev);
 221         if (ret)
 222                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
 223                         dev->data->port_id);
 224         ret = mlx5_txq_ibv_verify(dev);
 225         if (ret)
 226                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
 227                         dev->data->port_id);
 228         ret = mlx5_txq_verify(dev);
 229         if (ret)
 230                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
 231                         dev->data->port_id);
 232         ret = mlx5_flow_verify(dev);
 233         if (ret)
 234                 DRV_LOG(WARNING, "port %u some flows still remain",
 235                         dev->data->port_id);
 236         ret = mlx5_mr_verify(dev);
 237         if (ret)
 238                 DRV_LOG(WARNING, "port %u some memory region still remain",
 239                         dev->data->port_id);
 240         memset(priv, 0, sizeof(*priv));
 241 }
 242
 243 const struct eth_dev_ops mlx5_dev_ops = {
 244         .dev_configure = mlx5_dev_configure,
 245         .dev_start = mlx5_dev_start,
 246         .dev_stop = mlx5_dev_stop,
 247         .dev_set_link_down = mlx5_set_link_down,
 248         .dev_set_link_up = mlx5_set_link_up,
 249         .dev_close = mlx5_dev_close,
 250         .promiscuous_enable = mlx5_promiscuous_enable,
 251         .promiscuous_disable = mlx5_promiscuous_disable,
 252         .allmulticast_enable = mlx5_allmulticast_enable,
 253         .allmulticast_disable = mlx5_allmulticast_disable,
 254         .link_update = mlx5_link_update,
 255         .stats_get = mlx5_stats_get,
 256         .stats_reset = mlx5_stats_reset,
 257         .xstats_get = mlx5_xstats_get,
 258         .xstats_reset = mlx5_xstats_reset,
 259         .xstats_get_names = mlx5_xstats_get_names,
 260         .dev_infos_get = mlx5_dev_infos_get,
 261         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
 262         .vlan_filter_set = mlx5_vlan_filter_set,
 263         .rx_queue_setup = mlx5_rx_queue_setup,
 264         .tx_queue_setup = mlx5_tx_queue_setup,
 265         .rx_queue_release = mlx5_rx_queue_release,
 266         .tx_queue_release = mlx5_tx_queue_release,
 267         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
 268         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
 269         .mac_addr_remove = mlx5_mac_addr_remove,
 270         .mac_addr_add = mlx5_mac_addr_add,
 271         .mac_addr_set = mlx5_mac_addr_set,
 272         .mtu_set = mlx5_dev_set_mtu,
 273         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
 274         .vlan_offload_set = mlx5_vlan_offload_set,
 275         .reta_update = mlx5_dev_rss_reta_update,
 276         .reta_query = mlx5_dev_rss_reta_query,
 277         .rss_hash_update = mlx5_rss_hash_update,
 278         .rss_hash_conf_get = mlx5_rss_hash_conf_get,
 279         .filter_ctrl = mlx5_dev_filter_ctrl,
 280         .rx_descriptor_status = mlx5_rx_descriptor_status,
 281         .tx_descriptor_status = mlx5_tx_descriptor_status,
 282         .rx_queue_intr_enable = mlx5_rx_intr_enable,
 283         .rx_queue_intr_disable = mlx5_rx_intr_disable,
 284         .is_removed = mlx5_is_removed,
 285 };
 286
 287 static const struct eth_dev_ops mlx5_dev_sec_ops = {
 288         .stats_get = mlx5_stats_get,
 289         .stats_reset = mlx5_stats_reset,
 290         .xstats_get = mlx5_xstats_get,
 291         .xstats_reset = mlx5_xstats_reset,
 292         .xstats_get_names = mlx5_xstats_get_names,
 293         .dev_infos_get = mlx5_dev_infos_get,
 294         .rx_descriptor_status = mlx5_rx_descriptor_status,
 295         .tx_descriptor_status = mlx5_tx_descriptor_status,
 296 };
 297
 298 /* Available operators in flow isolated mode. */
 299 const struct eth_dev_ops mlx5_dev_ops_isolate = {
 300         .dev_configure = mlx5_dev_configure,
 301         .dev_start = mlx5_dev_start,
 302         .dev_stop = mlx5_dev_stop,
 303         .dev_set_link_down = mlx5_set_link_down,
 304         .dev_set_link_up = mlx5_set_link_up,
 305         .dev_close = mlx5_dev_close,
 306         .link_update = mlx5_link_update,
 307         .stats_get = mlx5_stats_get,
 308         .stats_reset = mlx5_stats_reset,
 309         .xstats_get = mlx5_xstats_get,
 310         .xstats_reset = mlx5_xstats_reset,
 311         .xstats_get_names = mlx5_xstats_get_names,
 312         .dev_infos_get = mlx5_dev_infos_get,
 313         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
 314         .vlan_filter_set = mlx5_vlan_filter_set,
 315         .rx_queue_setup = mlx5_rx_queue_setup,
 316         .tx_queue_setup = mlx5_tx_queue_setup,
 317         .rx_queue_release = mlx5_rx_queue_release,
 318         .tx_queue_release = mlx5_tx_queue_release,
 319         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
 320         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
 321         .mac_addr_remove = mlx5_mac_addr_remove,
 322         .mac_addr_add = mlx5_mac_addr_add,
 323         .mac_addr_set = mlx5_mac_addr_set,
 324         .mtu_set = mlx5_dev_set_mtu,
 325         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
 326         .vlan_offload_set = mlx5_vlan_offload_set,
 327         .filter_ctrl = mlx5_dev_filter_ctrl,
 328         .rx_descriptor_status = mlx5_rx_descriptor_status,
 329         .tx_descriptor_status = mlx5_tx_descriptor_status,
 330         .rx_queue_intr_enable = mlx5_rx_intr_enable,
 331         .rx_queue_intr_disable = mlx5_rx_intr_disable,
 332         .is_removed = mlx5_is_removed,
 333 };
 334
 335 static struct {
 336         struct rte_pci_addr pci_addr; /* associated PCI address */
 337         uint32_t ports; /* physical ports bitfield. */
 338 } mlx5_dev[32];
 339
 340 /**
 341  * Get device index in mlx5_dev[] from PCI bus address.
 342  *
 343  * @param[in] pci_addr
 344  *   PCI bus address to look for.
 345  *
 346  * @return
 347  *   mlx5_dev[] index on success, -1 on failure.
 348  */
 349 static int
 350 mlx5_dev_idx(struct rte_pci_addr *pci_addr)
 351 {
 352         unsigned int i;
 353         int ret = -1;
 354
 355         assert(pci_addr != NULL);
 356         for (i = 0; (i != RTE_DIM(mlx5_dev)); ++i) {
 357                 if ((mlx5_dev[i].pci_addr.domain == pci_addr->domain) &&
 358                     (mlx5_dev[i].pci_addr.bus == pci_addr->bus) &&
 359                     (mlx5_dev[i].pci_addr.devid == pci_addr->devid) &&
 360                     (mlx5_dev[i].pci_addr.function == pci_addr->function))
 361                         return i;
 362                 if ((mlx5_dev[i].ports == 0) && (ret == -1))
 363                         ret = i;
 364         }
 365         return ret;
 366 }
 367
 368 /**
 369  * Verify and store value for device argument.
 370  *
 371  * @param[in] key
 372  *   Key argument to verify.
 373  * @param[in] val
 374  *   Value associated with key.
 375  * @param opaque
 376  *   User data.
 377  *
 378  * @return
 379  *   0 on success, a negative errno value otherwise and rte_errno is set.
 380  */
 381 static int
 382 mlx5_args_check(const char *key, const char *val, void *opaque)
 383 {
 384         struct mlx5_dev_config *config = opaque;
 385         unsigned long tmp;
 386
 387         errno = 0;
 388         tmp = strtoul(val, NULL, 0);
 389         if (errno) {
 390                 rte_errno = errno;
 391                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
 392                 return -rte_errno;
 393         }
 394         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
 395                 config->cqe_comp = !!tmp;
 396         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
 397                 config->txq_inline = tmp;
 398         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
 399                 config->txqs_inline = tmp;
 400         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
 401                 config->mps = !!tmp ? config->mps : 0;
 402         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
 403                 config->mpw_hdr_dseg = !!tmp;
 404         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
 405                 config->inline_max_packet_sz = tmp;
 406         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
 407                 config->tx_vec_en = !!tmp;
 408         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
 409                 config->rx_vec_en = !!tmp;
 410         } else {
 411                 DRV_LOG(WARNING, "%s: unknown parameter", key);
 412                 rte_errno = EINVAL;
 413                 return -rte_errno;
 414         }
 415         return 0;
 416 }
 417
 418 /**
 419  * Parse device parameters.
 420  *
 421  * @param config
 422  *   Pointer to device configuration structure.
 423  * @param devargs
 424  *   Device arguments structure.
 425  *
 426  * @return
 427  *   0 on success, a negative errno value otherwise and rte_errno is set.
 428  */
 429 static int
 430 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
 431 {
 432         const char **params = (const char *[]){
 433                 MLX5_RXQ_CQE_COMP_EN,
 434                 MLX5_TXQ_INLINE,
 435                 MLX5_TXQS_MIN_INLINE,
 436                 MLX5_TXQ_MPW_EN,
 437                 MLX5_TXQ_MPW_HDR_DSEG_EN,
 438                 MLX5_TXQ_MAX_INLINE_LEN,
 439                 MLX5_TX_VEC_EN,
 440                 MLX5_RX_VEC_EN,
 441                 NULL,
 442         };
 443         struct rte_kvargs *kvlist;
 444         int ret = 0;
 445         int i;
 446
 447         if (devargs == NULL)
 448                 return 0;
 449         /* Following UGLY cast is done to pass checkpatch. */
 450         kvlist = rte_kvargs_parse(devargs->args, params);
 451         if (kvlist == NULL)
 452                 return 0;
 453         /* Process parameters. */
 454         for (i = 0; (params[i] != NULL); ++i) {
 455                 if (rte_kvargs_count(kvlist, params[i])) {
 456                         ret = rte_kvargs_process(kvlist, params[i],
 457                                                  mlx5_args_check, config);
 458                         if (ret) {
 459                                 rte_errno = EINVAL;
 460                                 rte_kvargs_free(kvlist);
 461                                 return -rte_errno;
 462                         }
 463                 }
 464         }
 465         rte_kvargs_free(kvlist);
 466         return 0;
 467 }
 468
 469 static struct rte_pci_driver mlx5_driver;
 470
 471 /*
 472  * Reserved UAR address space for TXQ UAR(hw doorbell) mapping, process
 473  * local resource used by both primary and secondary to avoid duplicate
 474  * reservation.
 475  * The space has to be available on both primary and secondary process,
 476  * TXQ UAR maps to this area using fixed mmap w/o double check.
 477  */
 478 static void *uar_base;
 479
 480 /**
 481  * Reserve UAR address space for primary process.
 482  *
 483  * @param[in] dev
 484  *   Pointer to Ethernet device.
 485  *
 486  * @return
 487  *   0 on success, a negative errno value otherwise and rte_errno is set.
 488  */
 489 static int
 490 mlx5_uar_init_primary(struct rte_eth_dev *dev)
 491 {
 492         struct priv *priv = dev->data->dev_private;
 493         void *addr = (void *)0;
 494         int i;
 495         const struct rte_mem_config *mcfg;
 496
 497         if (uar_base) { /* UAR address space mapped. */
 498                 priv->uar_base = uar_base;
 499                 return 0;
 500         }
 501         /* find out lower bound of hugepage segments */
 502         mcfg = rte_eal_get_configuration()->mem_config;
 503         for (i = 0; i < RTE_MAX_MEMSEG && mcfg->memseg[i].addr; i++) {
 504                 if (addr)
 505                         addr = RTE_MIN(addr, mcfg->memseg[i].addr);
 506                 else
 507                         addr = mcfg->memseg[i].addr;
 508         }
 509         /* keep distance to hugepages to minimize potential conflicts. */
 510         addr = RTE_PTR_SUB(addr, MLX5_UAR_OFFSET + MLX5_UAR_SIZE);
 511         /* anonymous mmap, no real memory consumption. */
 512         addr = mmap(addr, MLX5_UAR_SIZE,
 513                     PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
 514         if (addr == MAP_FAILED) {
 515                 DRV_LOG(ERR,
 516                         "port %u failed to reserve UAR address space, please"
 517                         " adjust MLX5_UAR_SIZE or try --base-virtaddr",
 518                         dev->data->port_id);
 519                 rte_errno = ENOMEM;
 520                 return -rte_errno;
 521         }
 522         /* Accept either same addr or a new addr returned from mmap if target
 523          * range occupied.
 524          */
 525         DRV_LOG(INFO, "port %u reserved UAR address space: %p",
 526                 dev->data->port_id, addr);
 527         priv->uar_base = addr; /* for primary and secondary UAR re-mmap. */
 528         uar_base = addr; /* process local, don't reserve again. */
 529         return 0;
 530 }
 531
 532 /**
 533  * Reserve UAR address space for secondary process, align with
 534  * primary process.
 535  *
 536  * @param[in] dev
 537  *   Pointer to Ethernet device.
 538  *
 539  * @return
 540  *   0 on success, a negative errno value otherwise and rte_errno is set.
 541  */
 542 static int
 543 mlx5_uar_init_secondary(struct rte_eth_dev *dev)
 544 {
 545         struct priv *priv = dev->data->dev_private;
 546         void *addr;
 547
 548         assert(priv->uar_base);
 549         if (uar_base) { /* already reserved. */
 550                 assert(uar_base == priv->uar_base);
 551                 return 0;
 552         }
 553         /* anonymous mmap, no real memory consumption. */
 554         addr = mmap(priv->uar_base, MLX5_UAR_SIZE,
 555                     PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
 556         if (addr == MAP_FAILED) {
 557                 DRV_LOG(ERR, "port %u UAR mmap failed: %p size: %llu",
 558                         dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE);
 559                 rte_errno = ENXIO;
 560                 return -rte_errno;
 561         }
 562         if (priv->uar_base != addr) {
 563                 DRV_LOG(ERR,
 564                         "port %u UAR address %p size %llu occupied, please"
 565                         " adjust MLX5_UAR_OFFSET or try EAL parameter"
 566                         " --base-virtaddr",
 567                         dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE);
 568                 rte_errno = ENXIO;
 569                 return -rte_errno;
 570         }
 571         uar_base = addr; /* process local, don't reserve again */
 572         DRV_LOG(INFO, "port %u reserved UAR address space: %p",
 573                 dev->data->port_id, addr);
 574         return 0;
 575 }
 576
 577 /**
 578  * DPDK callback to register a PCI device.
 579  *
 580  * This function creates an Ethernet device for each port of a given
 581  * PCI device.
 582  *
 583  * @param[in] pci_drv
 584  *   PCI driver structure (mlx5_driver).
 585  * @param[in] pci_dev
 586  *   PCI device information.
 587  *
 588  * @return
 589  *   0 on success, a negative errno value otherwise and rte_errno is set.
 590  */
 591 static int
 592 mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 593                struct rte_pci_device *pci_dev)
 594 {
 595         struct ibv_device **list = NULL;
 596         struct ibv_device *ibv_dev;
 597         int err = 0;
 598         struct ibv_context *attr_ctx = NULL;
 599         struct ibv_device_attr_ex device_attr;
 600         unsigned int mps;
 601         unsigned int cqe_comp;
 602         unsigned int tunnel_en = 0;
 603         int idx;
 604         int i;
 605         struct mlx5dv_context attrs_out = {0};
 606 #ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT
 607         struct ibv_counter_set_description cs_desc;
 608 #endif
 609
 610         assert(pci_drv == &mlx5_driver);
 611         /* Get mlx5_dev[] index. */
 612         idx = mlx5_dev_idx(&pci_dev->addr);
 613         if (idx == -1) {
 614                 DRV_LOG(ERR, "this driver cannot support any more adapters");
 615                 err = ENOMEM;
 616                 goto error;
 617         }
 618         DRV_LOG(DEBUG, "using driver device index %d", idx);
 619         /* Save PCI address. */
 620         mlx5_dev[idx].pci_addr = pci_dev->addr;
 621         list = mlx5_glue->get_device_list(&i);
 622         if (list == NULL) {
 623                 assert(errno);
 624                 err = errno;
 625                 if (errno == ENOSYS)
 626                         DRV_LOG(ERR,
 627                                 "cannot list devices, is ib_uverbs loaded?");
 628                 goto error;
 629         }
 630         assert(i >= 0);
 631         /*
 632          * For each listed device, check related sysfs entry against
 633          * the provided PCI ID.
 634          */
 635         while (i != 0) {
 636                 struct rte_pci_addr pci_addr;
 637
 638                 --i;
 639                 DRV_LOG(DEBUG, "checking device \"%s\"", list[i]->name);
 640                 if (mlx5_ibv_device_to_pci_addr(list[i], &pci_addr))
 641                         continue;
 642                 if ((pci_dev->addr.domain != pci_addr.domain) ||
 643                     (pci_dev->addr.bus != pci_addr.bus) ||
 644                     (pci_dev->addr.devid != pci_addr.devid) ||
 645                     (pci_dev->addr.function != pci_addr.function))
 646                         continue;
 647                 DRV_LOG(INFO, "PCI information matches, using device \"%s\"",
 648                         list[i]->name);
 649                 attr_ctx = mlx5_glue->open_device(list[i]);
 650                 rte_errno = errno;
 651                 err = rte_errno;
 652                 break;
 653         }
 654         if (attr_ctx == NULL) {
 655                 mlx5_glue->free_device_list(list);
 656                 switch (err) {
 657                 case 0:
 658                         DRV_LOG(ERR,
 659                                 "cannot access device, is mlx5_ib loaded?");
 660                         err = ENODEV;
 661                         goto error;
 662                 case EINVAL:
 663                         DRV_LOG(ERR,
 664                                 "cannot use device, are drivers up to date?");
 665                         goto error;
 666                 }
 667         }
 668         ibv_dev = list[i];
 669         DRV_LOG(DEBUG, "device opened");
 670         /*
 671          * Multi-packet send is supported by ConnectX-4 Lx PF as well
 672          * as all ConnectX-5 devices.
 673          */
 674 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
 675         attrs_out.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS;
 676 #endif
 677         mlx5_glue->dv_query_device(attr_ctx, &attrs_out);
 678         if (attrs_out.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
 679                 if (attrs_out.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) {
 680                         DRV_LOG(DEBUG, "enhanced MPW is supported");
 681                         mps = MLX5_MPW_ENHANCED;
 682                 } else {
 683                         DRV_LOG(DEBUG, "MPW is supported");
 684                         mps = MLX5_MPW;
 685                 }
 686         } else {
 687                 DRV_LOG(DEBUG, "MPW isn't supported");
 688                 mps = MLX5_MPW_DISABLED;
 689         }
 690         if (RTE_CACHE_LINE_SIZE == 128 &&
 691             !(attrs_out.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP))
 692                 cqe_comp = 0;
 693         else
 694                 cqe_comp = 1;
 695 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
 696         if (attrs_out.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) {
 697                 tunnel_en = ((attrs_out.tunnel_offloads_caps &
 698                               MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) &&
 699                              (attrs_out.tunnel_offloads_caps &
 700                               MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE));
 701         }
 702         DRV_LOG(DEBUG, "tunnel offloading is %ssupported",
 703                 tunnel_en ? "" : "not ");
 704 #else
 705         DRV_LOG(WARNING,
 706                 "tunnel offloading disabled due to old OFED/rdma-core version");
 707 #endif
 708         if (mlx5_glue->query_device_ex(attr_ctx, NULL, &device_attr)) {
 709                 err = errno;
 710                 goto error;
 711         }
 712         DRV_LOG(INFO, "%u port(s) detected",
 713                 device_attr.orig_attr.phys_port_cnt);
 714         for (i = 0; i < device_attr.orig_attr.phys_port_cnt; i++) {
 715                 char name[RTE_ETH_NAME_MAX_LEN];
 716                 int len;
 717                 uint32_t port = i + 1; /* ports are indexed from one */
 718                 uint32_t test = (1 << i);
 719                 struct ibv_context *ctx = NULL;
 720                 struct ibv_port_attr port_attr;
 721                 struct ibv_pd *pd = NULL;
 722                 struct priv *priv = NULL;
 723                 struct rte_eth_dev *eth_dev = NULL;
 724                 struct ibv_device_attr_ex device_attr_ex;
 725                 struct ether_addr mac;
 726                 struct ibv_device_attr_ex device_attr;
 727                 struct mlx5_dev_config config = {
 728                         .cqe_comp = cqe_comp,
 729                         .mps = mps,
 730                         .tunnel_en = tunnel_en,
 731                         .tx_vec_en = 1,
 732                         .rx_vec_en = 1,
 733                         .mpw_hdr_dseg = 0,
 734                         .txq_inline = MLX5_ARG_UNSET,
 735                         .txqs_inline = MLX5_ARG_UNSET,
 736                         .inline_max_packet_sz = MLX5_ARG_UNSET,
 737                 };
 738
 739                 len = snprintf(name, sizeof(name), PCI_PRI_FMT,
 740                          pci_dev->addr.domain, pci_dev->addr.bus,
 741                          pci_dev->addr.devid, pci_dev->addr.function);
 742                 if (device_attr.orig_attr.phys_port_cnt > 1)
 743                         snprintf(name + len, sizeof(name), " port %u", i);
 744                 mlx5_dev[idx].ports |= test;
 745                 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
 746                         eth_dev = rte_eth_dev_attach_secondary(name);
 747                         if (eth_dev == NULL) {
 748                                 DRV_LOG(ERR, "can not attach rte ethdev");
 749                                 rte_errno = ENOMEM;
 750                                 err = rte_errno;
 751                                 goto error;
 752                         }
 753                         eth_dev->device = &pci_dev->device;
 754                         eth_dev->dev_ops = &mlx5_dev_sec_ops;
 755                         err = mlx5_uar_init_secondary(eth_dev);
 756                         if (err)
 757                                 goto error;
 758                         /* Receive command fd from primary process */
 759                         err = mlx5_socket_connect(eth_dev);
 760                         if (err)
 761                                 goto error;
 762                         /* Remap UAR for Tx queues. */
 763                         err = mlx5_tx_uar_remap(eth_dev, err);
 764                         if (err)
 765                                 goto error;
 766                         /*
 767                          * Ethdev pointer is still required as input since
 768                          * the primary device is not accessible from the
 769                          * secondary process.
 770                          */
 771                         eth_dev->rx_pkt_burst =
 772                                 mlx5_select_rx_function(eth_dev);
 773                         eth_dev->tx_pkt_burst =
 774                                 mlx5_select_tx_function(eth_dev);
 775                         continue;
 776                 }
 777                 DRV_LOG(DEBUG, "using port %u (%08" PRIx32 ")", port, test);
 778                 ctx = mlx5_glue->open_device(ibv_dev);
 779                 if (ctx == NULL) {
 780                         err = ENODEV;
 781                         goto port_error;
 782                 }
 783                 mlx5_glue->query_device_ex(ctx, NULL, &device_attr);
 784                 /* Check port status. */
 785                 err = mlx5_glue->query_port(ctx, port, &port_attr);
 786                 if (err) {
 787                         DRV_LOG(ERR, "port query failed: %s", strerror(err));
 788                         goto port_error;
 789                 }
 790                 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
 791                         DRV_LOG(ERR,
 792                                 "port %d is not configured in Ethernet mode",
 793                                 port);
 794                         err = EINVAL;
 795                         goto port_error;
 796                 }
 797                 if (port_attr.state != IBV_PORT_ACTIVE)
 798                         DRV_LOG(DEBUG, "port %d is not active: \"%s\" (%d)",
 799                                 port,
 800                                 mlx5_glue->port_state_str(port_attr.state),
 801                                 port_attr.state);
 802                 /* Allocate protection domain. */
 803                 pd = mlx5_glue->alloc_pd(ctx);
 804                 if (pd == NULL) {
 805                         DRV_LOG(ERR, "PD allocation failure");
 806                         err = ENOMEM;
 807                         goto port_error;
 808                 }
 809                 mlx5_dev[idx].ports |= test;
 810                 /* from rte_ethdev.c */
 811                 priv = rte_zmalloc("ethdev private structure",
 812                                    sizeof(*priv),
 813                                    RTE_CACHE_LINE_SIZE);
 814                 if (priv == NULL) {
 815                         DRV_LOG(ERR, "priv allocation failure");
 816                         err = ENOMEM;
 817                         goto port_error;
 818                 }
 819                 priv->ctx = ctx;
 820                 strncpy(priv->ibdev_path, priv->ctx->device->ibdev_path,
 821                         sizeof(priv->ibdev_path));
 822                 priv->device_attr = device_attr;
 823                 priv->port = port;
 824                 priv->pd = pd;
 825                 priv->mtu = ETHER_MTU;
 826                 err = mlx5_args(&config, pci_dev->device.devargs);
 827                 if (err) {
 828                         DRV_LOG(ERR, "failed to process device arguments: %s",
 829                                 strerror(err));
 830                         goto port_error;
 831                 }
 832                 if (mlx5_glue->query_device_ex(ctx, NULL, &device_attr_ex)) {
 833                         DRV_LOG(ERR, "ibv_query_device_ex() failed");
 834                         err = errno;
 835                         goto port_error;
 836                 }
 837                 config.hw_csum = !!(device_attr_ex.device_cap_flags_ex &
 838                                     IBV_DEVICE_RAW_IP_CSUM);
 839                 DRV_LOG(DEBUG, "checksum offloading is %ssupported",
 840                         (config.hw_csum ? "" : "not "));
 841 #ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT
 842                 config.flow_counter_en = !!(device_attr.max_counter_sets);
 843                 mlx5_glue->describe_counter_set(ctx, 0, &cs_desc);
 844                 DRV_LOG(DEBUG,
 845                         "counter type = %d, num of cs = %ld, attributes = %d",
 846                         cs_desc.counter_type, cs_desc.num_of_cs,
 847                         cs_desc.attributes);
 848 #endif
 849                 config.ind_table_max_size =
 850                         device_attr_ex.rss_caps.max_rwq_indirection_table_size;
 851                 /* Remove this check once DPDK supports larger/variable
 852                  * indirection tables. */
 853                 if (config.ind_table_max_size >
 854                                 (unsigned int)ETH_RSS_RETA_SIZE_512)
 855                         config.ind_table_max_size = ETH_RSS_RETA_SIZE_512;
 856                 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u",
 857                         config.ind_table_max_size);
 858                 config.hw_vlan_strip = !!(device_attr_ex.raw_packet_caps &
 859                                          IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
 860                 DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
 861                         (config.hw_vlan_strip ? "" : "not "));
 862
 863                 config.hw_fcs_strip = !!(device_attr_ex.raw_packet_caps &
 864                                          IBV_RAW_PACKET_CAP_SCATTER_FCS);
 865                 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported",
 866                         (config.hw_fcs_strip ? "" : "not "));
 867
 868 #ifdef HAVE_IBV_WQ_FLAG_RX_END_PADDING
 869                 config.hw_padding = !!device_attr_ex.rx_pad_end_addr_align;
 870 #endif
 871                 DRV_LOG(DEBUG,
 872                         "hardware Rx end alignment padding is %ssupported",
 873                         (config.hw_padding ? "" : "not "));
 874                 config.tso = ((device_attr_ex.tso_caps.max_tso > 0) &&
 875                               (device_attr_ex.tso_caps.supported_qpts &
 876                               (1 << IBV_QPT_RAW_PACKET)));
 877                 if (config.tso)
 878                         config.tso_max_payload_sz =
 879                                         device_attr_ex.tso_caps.max_tso;
 880                 if (config.mps && !mps) {
 881                         DRV_LOG(ERR,
 882                                 "multi-packet send not supported on this device"
 883                                 " (" MLX5_TXQ_MPW_EN ")");
 884                         err = ENOTSUP;
 885                         goto port_error;
 886                 }
 887                 DRV_LOG(INFO, "%s MPS is %s",
 888                         config.mps == MLX5_MPW_ENHANCED ? "enhanced " : "",
 889                         config.mps != MLX5_MPW_DISABLED ? "enabled" :
 890                         "disabled");
 891                 if (config.cqe_comp && !cqe_comp) {
 892                         DRV_LOG(WARNING, "Rx CQE compression isn't supported");
 893                         config.cqe_comp = 0;
 894                 }
 895                 eth_dev = rte_eth_dev_allocate(name);
 896                 if (eth_dev == NULL) {
 897                         DRV_LOG(ERR, "can not allocate rte ethdev");
 898                         err = ENOMEM;
 899                         goto port_error;
 900                 }
 901                 eth_dev->data->dev_private = priv;
 902                 priv->dev = eth_dev;
 903                 eth_dev->data->mac_addrs = priv->mac;
 904                 eth_dev->device = &pci_dev->device;
 905                 rte_eth_copy_pci_info(eth_dev, pci_dev);
 906                 eth_dev->device->driver = &mlx5_driver.driver;
 907                 err = mlx5_uar_init_primary(eth_dev);
 908                 if (err)
 909                         goto port_error;
 910                 /* Configure the first MAC address by default. */
 911                 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) {
 912                         DRV_LOG(ERR,
 913                                 "port %u cannot get MAC address, is mlx5_en"
 914                                 " loaded? (errno: %s)",
 915                                 eth_dev->data->port_id, strerror(errno));
 916                         err = ENODEV;
 917                         goto port_error;
 918                 }
 919                 DRV_LOG(INFO,
 920                         "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x",
 921                         eth_dev->data->port_id,
 922                         mac.addr_bytes[0], mac.addr_bytes[1],
 923                         mac.addr_bytes[2], mac.addr_bytes[3],
 924                         mac.addr_bytes[4], mac.addr_bytes[5]);
 925 #ifndef NDEBUG
 926                 {
 927                         char ifname[IF_NAMESIZE];
 928
 929                         if (mlx5_get_ifname(eth_dev, &ifname) == 0)
 930                                 DRV_LOG(DEBUG, "port %u ifname is \"%s\"",
 931                                         eth_dev->data->port_id, ifname);
 932                         else
 933                                 DRV_LOG(DEBUG, "port %u ifname is unknown",
 934                                         eth_dev->data->port_id);
 935                 }
 936 #endif
 937                 /* Get actual MTU if possible. */
 938                 err = mlx5_get_mtu(eth_dev, &priv->mtu);
 939                 if (err)
 940                         goto port_error;
 941                 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id,
 942                         priv->mtu);
 943                 /*
 944                  * Initialize burst functions to prevent crashes before link-up.
 945                  */
 946                 eth_dev->rx_pkt_burst = removed_rx_burst;
 947                 eth_dev->tx_pkt_burst = removed_tx_burst;
 948                 eth_dev->dev_ops = &mlx5_dev_ops;
 949                 /* Register MAC address. */
 950                 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
 951                 TAILQ_INIT(&priv->flows);
 952                 TAILQ_INIT(&priv->ctrl_flows);
 953                 /* Hint libmlx5 to use PMD allocator for data plane resources */
 954                 struct mlx5dv_ctx_allocators alctr = {
 955                         .alloc = &mlx5_alloc_verbs_buf,
 956                         .free = &mlx5_free_verbs_buf,
 957                         .data = priv,
 958                 };
 959                 mlx5_glue->dv_set_context_attr(ctx,
 960                                                MLX5DV_CTX_ATTR_BUF_ALLOCATORS,
 961                                                (void *)((uintptr_t)&alctr));
 962                 /* Bring Ethernet device up. */
 963                 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up",
 964                         eth_dev->data->port_id);
 965                 mlx5_set_flags(eth_dev, ~IFF_UP, IFF_UP);
 966                 /* Store device configuration on private structure. */
 967                 priv->config = config;
 968                 continue;
 969 port_error:
 970                 if (priv)
 971                         rte_free(priv);
 972                 if (pd)
 973                         claim_zero(mlx5_glue->dealloc_pd(pd));
 974                 if (ctx)
 975                         claim_zero(mlx5_glue->close_device(ctx));
 976                 break;
 977         }
 978         /*
 979          * XXX if something went wrong in the loop above, there is a resource
 980          * leak (ctx, pd, priv, dpdk ethdev) but we can do nothing about it as
 981          * long as the dpdk does not provide a way to deallocate a ethdev and a
 982          * way to enumerate the registered ethdevs to free the previous ones.
 983          */
 984         /* no port found, complain */
 985         if (!mlx5_dev[idx].ports) {
 986                 rte_errno = ENODEV;
 987                 err = rte_errno;
 988         }
 989 error:
 990         if (attr_ctx)
 991                 claim_zero(mlx5_glue->close_device(attr_ctx));
 992         if (list)
 993                 mlx5_glue->free_device_list(list);
 994         if (err) {
 995                 rte_errno = err;
 996                 return -rte_errno;
 997         }
 998         return 0;
 999 }
1000
1001 static const struct rte_pci_id mlx5_pci_id_map[] = {
1002         {
1003                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1004                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
1005         },
1006         {
1007                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1008                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
1009         },
1010         {
1011                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1012                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
1013         },
1014         {
1015                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1016                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
1017         },
1018         {
1019                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1020                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
1021         },
1022         {
1023                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1024                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
1025         },
1026         {
1027                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1028                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
1029         },
1030         {
1031                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1032                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
1033         },
1034         {
1035                 .vendor_id = 0
1036         }
1037 };
1038
1039 static struct rte_pci_driver mlx5_driver = {
1040         .driver = {
1041                 .name = MLX5_DRIVER_NAME
1042         },
1043         .id_table = mlx5_pci_id_map,
1044         .probe = mlx5_pci_probe,
1045         .drv_flags = RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV,
1046 };
1047
1048 #ifdef RTE_LIBRTE_MLX5_DLOPEN_DEPS
1049
1050 /**
1051  * Suffix RTE_EAL_PMD_PATH with "-glue".
1052  *
1053  * This function performs a sanity check on RTE_EAL_PMD_PATH before
1054  * suffixing its last component.
1055  *
1056  * @param buf[out]
1057  *   Output buffer, should be large enough otherwise NULL is returned.
1058  * @param size
1059  *   Size of @p out.
1060  *
1061  * @return
1062  *   Pointer to @p buf or @p NULL in case suffix cannot be appended.
1063  */
1064 static char *
1065 mlx5_glue_path(char *buf, size_t size)
1066 {
1067         static const char *const bad[] = { "/", ".", "..", NULL };
1068         const char *path = RTE_EAL_PMD_PATH;
1069         size_t len = strlen(path);
1070         size_t off;
1071         int i;
1072
1073         while (len && path[len - 1] == '/')
1074                 --len;
1075         for (off = len; off && path[off - 1] != '/'; --off)
1076                 ;
1077         for (i = 0; bad[i]; ++i)
1078                 if (!strncmp(path + off, bad[i], (int)(len - off)))
1079                         goto error;
1080         i = snprintf(buf, size, "%.*s-glue", (int)len, path);
1081         if (i == -1 || (size_t)i >= size)
1082                 goto error;
1083         return buf;
1084 error:
1085         DRV_LOG(ERR,
1086                 "unable to append \"-glue\" to last component of"
1087                 " RTE_EAL_PMD_PATH (\"" RTE_EAL_PMD_PATH "\"),"
1088                 " please re-configure DPDK");
1089         return NULL;
1090 }
1091
1092 /**
1093  * Initialization routine for run-time dependency on rdma-core.
1094  */
1095 static int
1096 mlx5_glue_init(void)
1097 {
1098         char glue_path[sizeof(RTE_EAL_PMD_PATH) - 1 + sizeof("-glue")];
1099         const char *path[] = {
1100                 /*
1101                  * A basic security check is necessary before trusting
1102                  * MLX5_GLUE_PATH, which may override RTE_EAL_PMD_PATH.
1103                  */
1104                 (geteuid() == getuid() && getegid() == getgid() ?
1105                  getenv("MLX5_GLUE_PATH") : NULL),
1106                 /*
1107                  * When RTE_EAL_PMD_PATH is set, use its glue-suffixed
1108                  * variant, otherwise let dlopen() look up libraries on its
1109                  * own.
1110                  */
1111                 (*RTE_EAL_PMD_PATH ?
1112                  mlx5_glue_path(glue_path, sizeof(glue_path)) : ""),
1113         };
1114         unsigned int i = 0;
1115         void *handle = NULL;
1116         void **sym;
1117         const char *dlmsg;
1118
1119         while (!handle && i != RTE_DIM(path)) {
1120                 const char *end;
1121                 size_t len;
1122                 int ret;
1123
1124                 if (!path[i]) {
1125                         ++i;
1126                         continue;
1127                 }
1128                 end = strpbrk(path[i], ":;");
1129                 if (!end)
1130                         end = path[i] + strlen(path[i]);
1131                 len = end - path[i];
1132                 ret = 0;
1133                 do {
1134                         char name[ret + 1];
1135
1136                         ret = snprintf(name, sizeof(name), "%.*s%s" MLX5_GLUE,
1137                                        (int)len, path[i],
1138                                        (!len || *(end - 1) == '/') ? "" : "/");
1139                         if (ret == -1)
1140                                 break;
1141                         if (sizeof(name) != (size_t)ret + 1)
1142                                 continue;
1143                         DRV_LOG(DEBUG, "looking for rdma-core glue as \"%s\"",
1144                                 name);
1145                         handle = dlopen(name, RTLD_LAZY);
1146                         break;
1147                 } while (1);
1148                 path[i] = end + 1;
1149                 if (!*end)
1150                         ++i;
1151         }
1152         if (!handle) {
1153                 rte_errno = EINVAL;
1154                 dlmsg = dlerror();
1155                 if (dlmsg)
1156                         DRV_LOG(WARNING, "cannot load glue library: %s", dlmsg);
1157                 goto glue_error;
1158         }
1159         sym = dlsym(handle, "mlx5_glue");
1160         if (!sym || !*sym) {
1161                 rte_errno = EINVAL;
1162                 dlmsg = dlerror();
1163                 if (dlmsg)
1164                         DRV_LOG(ERR, "cannot resolve glue symbol: %s", dlmsg);
1165                 goto glue_error;
1166         }
1167         mlx5_glue = *sym;
1168         return 0;
1169 glue_error:
1170         if (handle)
1171                 dlclose(handle);
1172         DRV_LOG(WARNING,
1173                 "cannot initialize PMD due to missing run-time dependency on"
1174                 " rdma-core libraries (libibverbs, libmlx5)");
1175         return -rte_errno;
1176 }
1177
1178 #endif
1179
1180 /**
1181  * Driver initialization routine.
1182  */
1183 RTE_INIT(rte_mlx5_pmd_init);
1184 static void
1185 rte_mlx5_pmd_init(void)
1186 {
1187         /* Build the static table for ptype conversion. */
1188         mlx5_set_ptype_table();
1189         /*
1190          * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use
1191          * huge pages. Calling ibv_fork_init() during init allows
1192          * applications to use fork() safely for purposes other than
1193          * using this PMD, which is not supported in forked processes.
1194          */
1195         setenv("RDMAV_HUGEPAGES_SAFE", "1", 1);
1196         /* Match the size of Rx completion entry to the size of a cacheline. */
1197         if (RTE_CACHE_LINE_SIZE == 128)
1198                 setenv("MLX5_CQE_SIZE", "128", 0);
1199 #ifdef RTE_LIBRTE_MLX5_DLOPEN_DEPS
1200         if (mlx5_glue_init())
1201                 return;
1202         assert(mlx5_glue);
1203 #endif
1204 #ifndef NDEBUG
1205         /* Glue structure must not contain any NULL pointers. */
1206         {
1207                 unsigned int i;
1208
1209                 for (i = 0; i != sizeof(*mlx5_glue) / sizeof(void *); ++i)
1210                         assert(((const void *const *)mlx5_glue)[i]);
1211         }
1212 #endif
1213         if (strcmp(mlx5_glue->version, MLX5_GLUE_VERSION)) {
1214                 DRV_LOG(ERR,
1215                         "rdma-core glue \"%s\" mismatch: \"%s\" is required",
1216                         mlx5_glue->version, MLX5_GLUE_VERSION);
1217                 return;
1218         }
1219         mlx5_glue->fork_init();
1220         rte_pci_register(&mlx5_driver);
1221 }
1222
1223 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
1224 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
1225 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");
1226
1227 /** Initialize driver log type. */
1228 RTE_INIT(vdev_netvsc_init_log)
1229 {
1230         mlx5_logtype = rte_log_register("pmd.net.mlx5");
1231         if (mlx5_logtype >= 0)
1232                 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE);
1233 }